1 # script for stm32l4x family
4 # stm32l4 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32l4x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 40kB (Available RAM in smallest device STM32L412)
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0xa000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0351
31 # Section 44.6.3 - corresponds to Cortex-M4 r0p1
32 set _CPUTAPID 0x4ba00477
34 set _CPUTAPID 0x2ba01477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
41 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
44 jtag newtap $_CHIPNAME bs -irlen 5
47 set _TARGETNAME $_CHIPNAME.cpu
48 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
50 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
52 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
53 flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
55 if { [info exists QUADSPI] && $QUADSPI } {
56 set a [llength [flash list]]
57 set _QSPINAME $_CHIPNAME.qspi
58 flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
60 if { [info exists OCTOSPI1] && $OCTOSPI1 } {
61 set a [llength [flash list]]
62 set _OCTOSPINAME1 $_CHIPNAME.octospi1
63 flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
65 if { [info exists OCTOSPI2] && $OCTOSPI2 } {
66 set b [llength [flash list]]
67 set _OCTOSPINAME2 $_CHIPNAME.octospi2
68 flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_TARGETNAME 0xA0001400
72 # Common knowledges tells JTAG speed should be <= F_CPU/6.
73 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
76 # Note that there is a pretty wide band where things are
77 # more or less stable, see http://openocd.zylin.com/#/c/3366/
80 adapter srst delay 100
85 reset_config srst_nogate
88 # if srst is not fitted use SYSRESETREQ to
89 # perform a soft reset
90 cortex_m reset_config sysresetreq
93 proc proc_post_enable {_chipname} {
94 targets $_chipname.cpu
96 if { [$_chipname.tpiu cget -protocol] eq "sync" } {
97 switch [$_chipname.tpiu cget -port-width] {
99 mmw 0xE0042004 0x00000060 0x000000c0
100 mmw 0x48001020 0x00000000 0x0000ff00
101 mmw 0x48001000 0x000000a0 0x000000f0
102 mmw 0x48001008 0x000000f0 0x00000000
105 mmw 0xE0042004 0x000000a0 0x000000c0
106 mmw 0x48001020 0x00000000 0x000fff00
107 mmw 0x48001000 0x000002a0 0x000003f0
108 mmw 0x48001008 0x000003f0 0x00000000
111 mmw 0xE0042004 0x000000e0 0x000000c0
112 mmw 0x48001020 0x00000000 0x0fffff00
113 mmw 0x48001000 0x00002aa0 0x00003ff0
114 mmw 0x48001008 0x00003ff0 0x00000000
118 mmw 0xE0042004 0x00000020 0x000000c0
122 $_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
124 $_TARGETNAME configure -event reset-init {
125 # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
126 # Use MSI 24 MHz clock, compliant even with VOS == 2.
127 # 3 WS compliant with VOS == 2 and 24 MHz.
128 mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
129 mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
130 # Boost JTAG frequency
134 $_TARGETNAME configure -event reset-start {
135 # Reset clock is MSI (4 MHz)
139 $_TARGETNAME configure -event examine-end {
140 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
141 mmw 0xE0042004 0x00000007 0
143 # Stop watchdog counters during halt
144 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
145 mmw 0xE0042008 0x00001800 0