1 # SPDX-License-Identifier: GPL-2.0-or-later
7 source [find target/swj-dp.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
15 if { [info exists CPUTAPID] } {
16 set _CPU_TAPID $CPUTAPID
18 set _CPU_TAPID 0x4BA00477
22 set _CPU_DAP_ID $_CPU_TAPID
24 set _CPU_DAP_ID 0x2ba01477
27 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
28 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
30 set _TARGETNAME $_CHIPNAME.cpu
31 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
33 if { [info exists WORKAREASIZE] } {
34 set _WORKAREASIZE $WORKAREASIZE
36 set _WORKAREASIZE 0x2000
39 $_TARGETNAME configure -work-area-phys [expr {0x20000000 - $_WORKAREASIZE / 2}] \
40 -work-area-size $_WORKAREASIZE -work-area-backup 0
42 source [find mem_helper.tcl]
44 $_TARGETNAME configure -event reset-init {
45 # Configure Target Device (PSoC 5LP Device Programming Specification 5.2)
47 set PANTHER_DBG_CFG 0x4008000C
48 set PANTHER_DBG_CFG_BYPASS [expr {1 << 1}]
49 mmw $PANTHER_DBG_CFG $PANTHER_DBG_CFG_BYPASS 0
51 set PM_ACT_CFG0 0x400043A0
54 set FASTCLK_IMO_CR 0x40004200
55 set FASTCLK_IMO_CR_F_RANGE_2 [expr {2 << 0}]
56 set FASTCLK_IMO_CR_F_RANGE_MASK [expr {7 << 0}]
57 mmw $FASTCLK_IMO_CR $FASTCLK_IMO_CR_F_RANGE_2 $FASTCLK_IMO_CR_F_RANGE_MASK
60 set _FLASHNAME $_CHIPNAME.flash
61 flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
62 flash bank $_CHIPNAME.eeprom psoc5lp_eeprom 0x40008000 0 0 0 $_TARGETNAME
63 flash bank $_CHIPNAME.nvl psoc5lp_nvl 0 0 0 0 $_TARGETNAME
66 cortex_m reset_config sysresetreq