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   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
   5 #
   6
   7 adapter speed 500
   8
   9 if { [info exists CHIPNAME] } {
  10         set _CHIPNAME $CHIPNAME
  11 } else {
  12         set _CHIPNAME lpc4370
  13 }
  14
  15 #
  16 # M4 JTAG mode TAP
  17 #
  18 if { [info exists M4_JTAG_TAPID] } {
  19         set _M4_JTAG_TAPID $M4_JTAG_TAPID
  20 } else {
  21         set _M4_JTAG_TAPID 0x4ba00477
  22 }
  23
  24 #
  25 # M4 SWD mode TAP
  26 #
  27 if { [info exists M4_SWD_TAPID] } {
  28         set _M4_SWD_TAPID $M4_SWD_TAPID
  29 } else {
  30         set _M4_SWD_TAPID 0x2ba01477
  31 }
  32
  33 source [find target/swj-dp.tcl]
  34
  35 if { [using_jtag] } {
  36         set _M4_TAPID $_M4_JTAG_TAPID
  37 } else {
  38         set _M4_TAPID $_M4_SWD_TAPID
  39 }
  40
  41 #
  42 # M0 TAP
  43 #
  44 if { [info exists M0_JTAG_TAPID] } {
  45         set _M0_JTAG_TAPID $M0_JTAG_TAPID
  46 } else {
  47         set _M0_JTAG_TAPID 0x0ba01477
  48 }
  49
  50 swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
  51                                 -expected-id $_M4_TAPID
  52 dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
  53 target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
  54
  55 # LPC4370 has 96+32 KB contiguous SRAM
  56 if { [info exists WORKAREASIZE] } {
  57         set _WORKAREASIZE $WORKAREASIZE
  58 } else {
  59         set _WORKAREASIZE 0x20000
  60 }
  61 $_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
  62                         -work-area-size $_WORKAREASIZE -work-area-backup 0
  63
  64 if { [using_jtag] } {
  65         jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
  66                                         -expected-id $_M0_JTAG_TAPID
  67         jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
  68                                         -expected-id $_M0_JTAG_TAPID
  69
  70         dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
  71         dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
  72         target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
  73         target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
  74
  75         # 32+8+32 KB SRAM
  76         $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
  77                                    -work-area-size 0x92000 -work-area-backup 0
  78
  79         # 16+2 KB M0 subsystem SRAM
  80         $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
  81                                    -work-area-size 0x4800 -work-area-backup 0
  82
  83         # Default to the Cortex-M4
  84         targets $_CHIPNAME.m4
  85 }
  86
  87 if { ![using_hla] } {
  88         cortex_m reset_config vectreset
  89 }