1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
10 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
11 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
14 # SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
15 # We will configure work area assuming 8-KB bank size in SRAM bank 1.
16 # Also SRAM start addresses defaults to secure mode alias.
17 # These values can be overridden as per board configuration
20 global _WORKAREASIZE_CPU0
21 if { [info exists WORKAREASIZE_CPU0] } {
22 set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
24 set _WORKAREASIZE_CPU0 0x1000
27 global _WORKAREAADDR_CPU0
28 if { [info exists WORKAREAADDR_CPU0] } {
29 set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
31 set _WORKAREAADDR_CPU0 0x30008000
35 # Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
36 # Core 0 is the boot core and will always be configured.
39 target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
41 ${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
43 ${TARGET}.CPU0 cortex_m reset_config sysresetreq
46 # Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
47 # Core 1 is optional and locked at boot until core 0 unlocks it.
50 if { $_ENABLE_CPU1 } {
51 global _WORKAREASIZE_CPU1
52 if { [info exists WORKAREASIZE_CPU1] } {
53 set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
55 set _WORKAREASIZE_CPU1 0x1000
58 global _WORKAREAADDR_CPU1
59 if { [info exists WORKAREAADDR_CPU1] } {
60 set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
62 set _WORKAREAADDR_CPU1 0x30009000
65 target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
67 ${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
69 ${TARGET}.CPU1 cortex_m reset_config vectreset
72 # Make sure the default target is the boot core
73 targets ${TARGET}.CPU0