1 source [find target/icepick.cfg]
2 source [find mem_helper.tcl]
4 ###############################################################################
6 ###############################################################################
7 set PRCM_BASE_ADDR 0x44df0000
8 set REVISION_PRM [expr {$PRCM_BASE_ADDR + 0x0000}]
9 set PRM_IRQSTATUS_MPU [expr {$PRCM_BASE_ADDR + 0x0004}]
10 set PRM_IRQENABLE_MPU [expr {$PRCM_BASE_ADDR + 0x0008}]
11 set PRM_IRQSTATUS_M3 [expr {$PRCM_BASE_ADDR + 0x000c}]
12 set PRM_IRQENABLE_M3 [expr {$PRCM_BASE_ADDR + 0x0010}]
13 set PM_MPU_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0300}]
14 set PM_MPU_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0304}]
15 set RM_MPU_RSTST [expr {$PRCM_BASE_ADDR + 0x0314}]
16 set RM_MPU_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0324}]
17 set PM_GFX_PWRSTCTRL [expr {$PRCM_BASE_ADDR + 0x0400}]
18 set PM_GFX_PWRSTST [expr {$PRCM_BASE_ADDR + 0x0404}]
19 set RM_GFX_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x0410}]
20 set RM_GFX_RSTST [expr {$PRCM_BASE_ADDR + 0x0414}]
21 set RM_GFX_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0424}]
22 set RM_RTC_CONTEXT [expr {$PRCM_BASE_ADDR + 0x0524}]
23 set RM_WKUP_RSTCTRL [expr {$PRCM_BASE_ADDR + 0x2010}]
24 set RM_WKUP_RSTST [expr {$PRCM_BASE_ADDR + 0x2014}]
25 set CM_L3_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2800}]
26 set CM_WKUP_DEBUGSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2820}]
27 set CM_L3S_TSC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2900}]
28 set CM_WKUP_ADC_TSC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2920}]
29 set CM_L4_WKUP_AON_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2a00}]
30 set CM_WKUP_L4WKUP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a20}]
31 set CM_WKUP_WKUP_M3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a28}]
32 set CM_WKUP_SYNCTIMER_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a30}]
33 set CM_WKUP_CLKDIV32K_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a38}]
34 set CM_WKUP_USBPHY0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a40}]
35 set CM_WKUP_USBPHY1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2a48}]
36 set CM_WKUP_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x2b00}]
37 set CM_WKUP_TIMER0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b20}]
38 set CM_WKUP_TIMER1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b28}]
39 set CM_WKUP_WDT0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b30}]
40 set CM_WKUP_WDT1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b38}]
41 set CM_WKUP_I2C0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b40}]
42 set CM_WKUP_UART0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b48}]
43 set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b50}]
44 set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b58}]
45 set CM_WKUP_CONTROL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b60}]
46 set CM_WKUP_GPIO0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x2b68}]
47 set CM_CLKMODE_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d20}]
48 set CM_IDLEST_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d24}]
49 set CM_CLKSEL_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d2c}]
50 set CM_DIV_M4_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d38}]
51 set CM_DIV_M5_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d3c}]
52 set CM_DIV_M6_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d40}]
53 set CM_SSC_DELTAMSTEP_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d48}]
54 set CM_SSC_MODFREQDIV_DPLL_CORE [expr {$PRCM_BASE_ADDR + 0x2d4c}]
55 set CM_CLKMODE_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d60}]
56 set CM_IDLEST_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d64}]
57 set CM_CLKSEL_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d6c}]
58 set CM_DIV_M2_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d70}]
59 set CM_SSC_DELTAMSTEP_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d88}]
60 set CM_SSC_MODFREQDIV_DPLL_MPU [expr {$PRCM_BASE_ADDR + 0x2d8c}]
61 set CM_CLKMODE_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da0}]
62 set CM_IDLEST_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2da4}]
63 set CM_CLKSEL_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dac}]
64 set CM_DIV_M2_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db0}]
65 set CM_DIV_M4_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2db8}]
66 set CM_SSC_DELTAMSTEP_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dc8}]
67 set CM_SSC_MODFREQDIV_DPLL_DDR [expr {$PRCM_BASE_ADDR + 0x2dcc}]
68 set CM_CLKMODE_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de0}]
69 set CM_IDLEST_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2de4}]
70 set CM_CLKSEL_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2dec}]
71 set CM_DIV_M2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2df0}]
72 set CM_CLKSEL2_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e04}]
73 set CM_SSC_DELTAMSTEP_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e08}]
74 set CM_SSC_MODFREQDIV_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e0c}]
75 set CM_CLKDCOLDO_DPLL_PER [expr {$PRCM_BASE_ADDR + 0x2e14}]
76 set CM_CLKMODE_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e20}]
77 set CM_IDLEST_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e24}]
78 set CM_CLKSEL_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e2c}]
79 set CM_DIV_M2_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e30}]
80 set CM_SSC_DELTAMSTEP_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e48}]
81 set CM_SSC_MODFREQDIV_DPLL_DISP [expr {$PRCM_BASE_ADDR + 0x2e4c}]
82 set CM_CLKMODE_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e60}]
83 set CM_IDLEST_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e64}]
84 set CM_CLKSEL_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e6c}]
85 set CM_DIV_M2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e70}]
86 set CM_CLKSEL2_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e84}]
87 set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e88}]
88 set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr {$PRCM_BASE_ADDR + 0x2e8c}]
89 set CM_SHADOW_FREQ_CONFIG1 [expr {$PRCM_BASE_ADDR + 0x2fa0}]
90 set CM_SHADOW_FREQ_CONFIG2 [expr {$PRCM_BASE_ADDR + 0x2fa4}]
91 set CM_CLKOUT1_CTRL [expr {$PRCM_BASE_ADDR + 0x4100}]
92 set CM_DLL_CTRL [expr {$PRCM_BASE_ADDR + 0x4104}]
93 set CM_CLKOUT2_CTRL [expr {$PRCM_BASE_ADDR + 0x4108}]
94 set CLKSEL_TIMER1MS_CLK [expr {$PRCM_BASE_ADDR + 0x4200}]
95 set CLKSEL_TIMER2_CLK [expr {$PRCM_BASE_ADDR + 0x4204}]
96 set CLKSEL_TIMER3_CLK [expr {$PRCM_BASE_ADDR + 0x4208}]
97 set CLKSEL_TIMER4_CLK [expr {$PRCM_BASE_ADDR + 0x420c}]
98 set CLKSEL_TIMER5_CLK [expr {$PRCM_BASE_ADDR + 0x4210}]
99 set CLKSEL_TIMER6_CLK [expr {$PRCM_BASE_ADDR + 0x4214}]
100 set CLKSEL_TIMER7_CLK [expr {$PRCM_BASE_ADDR + 0x4218}]
101 set CLKSEL_TIMER8_CLK [expr {$PRCM_BASE_ADDR + 0x421c}]
102 set CLKSEL_TIMER9_CLK [expr {$PRCM_BASE_ADDR + 0x4220}]
103 set CLKSEL_TIMER10_CLK [expr {$PRCM_BASE_ADDR + 0x4224}]
104 set CLKSEL_TIMER11_CLK [expr {$PRCM_BASE_ADDR + 0x4228}]
105 set CLKSEL_WDT1_CLK [expr {$PRCM_BASE_ADDR + 0x422c}]
106 set CLKSEL_SYNCTIMER_CLK [expr {$PRCM_BASE_ADDR + 0x4230}]
107 set CLKSEL_MAC_CLK [expr {$PRCM_BASE_ADDR + 0x4234}]
108 set CLKSEL_CPTS_RFT_CLK [expr {$PRCM_BASE_ADDR + 0x4238}]
109 set CLKSEL_GFX_FCLK [expr {$PRCM_BASE_ADDR + 0x423c}]
110 set CLKSEL_GPIO0_DBCLK [expr {$PRCM_BASE_ADDR + 0x4240}]
111 set CLKSEL_LCDC_PIXEL_CLK [expr {$PRCM_BASE_ADDR + 0x4244}]
112 set CLKSEL_ICSS_OCP_CLK [expr {$PRCM_BASE_ADDR + 0x4248}]
113 set CLKSEL_DLL_AGING_CLK [expr {$PRCM_BASE_ADDR + 0x4250}]
114 set CLKSEL_USBPHY32KHZ_GCLK [expr {$PRCM_BASE_ADDR + 0x4260}]
115 set CM_MPU_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8300}]
116 set CM_MPU_MPU_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8320}]
117 set CM_GFX_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8400}]
118 set CM_GFX_GFX_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8420}]
119 set CM_RTC_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8500}]
120 set CM_RTC_RTC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8520}]
121 set CM_PER_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8800}]
122 set CM_PER_L3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8820}]
123 set CM_PER_AES0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8828}]
124 set CM_PER_DES_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8830}]
125 set CM_PER_CRYPTODMA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8838}]
126 set CM_PER_L3_INSTR_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8840}]
127 set CM_PER_MSTR_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8848}]
128 set CM_PER_OCMCRAM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8850}]
129 set CM_PER_SHA0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8858}]
130 set CM_PER_SLV_EXPS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8860}]
131 set CM_PER_VPFE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8868}]
132 set CM_PER_VPFE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8870}]
133 set CM_PER_TPCC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8878}]
134 set CM_PER_TPTC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8880}]
135 set CM_PER_TPTC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8888}]
136 set CM_PER_TPTC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8890}]
137 set CM_PER_DLL_AGING_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8898}]
138 set CM_PER_L4HS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a0}]
139 set CM_PER_L4FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x88a8}]
140 set CM_PER_L3S_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8a00}]
141 set CM_PER_GPMC_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a20}]
142 set CM_PER_IEEE5000_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a28}]
143 set CM_PER_MCASP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a38}]
144 set CM_PER_MCASP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a40}]
145 set CM_PER_MMC2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a48}]
146 set CM_PER_QSPI_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a58}]
147 set CM_PER_USB_OTG_SS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a60}]
148 set CM_PER_USB_OTG_SS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8a68}]
149 set CM_PER_ICSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8b00}]
150 set CM_PER_ICSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8b20}]
151 set CM_PER_L4LS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8c00}]
152 set CM_PER_L4LS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c20}]
153 set CM_PER_DCAN0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c28}]
154 set CM_PER_DCAN1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c30}]
155 set CM_PER_EPWMSS0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c38}]
156 set CM_PER_EPWMSS1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c40}]
157 set CM_PER_EPWMSS2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c48}]
158 set CM_PER_EPWMSS3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c50}]
159 set CM_PER_EPWMSS4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c58}]
160 set CM_PER_EPWMSS5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c60}]
161 set CM_PER_ELM_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c68}]
162 set CM_PER_GPIO1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c78}]
163 set CM_PER_GPIO2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c80}]
164 set CM_PER_GPIO3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c88}]
165 set CM_PER_GPIO4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c90}]
166 set CM_PER_GPIO5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8c98}]
167 set CM_PER_HDQ1W_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca0}]
168 set CM_PER_I2C1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ca8}]
169 set CM_PER_I2C2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb0}]
170 set CM_PER_MAILBOX0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cb8}]
171 set CM_PER_MMC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc0}]
172 set CM_PER_MMC1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cc8}]
173 set CM_PER_PKA_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cd0}]
174 set CM_PER_RNG_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce0}]
175 set CM_PER_SPARE0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8ce8}]
176 set CM_PER_SPARE1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8cf0}]
177 set CM_PER_SPI0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d00}]
178 set CM_PER_SPI1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d08}]
179 set CM_PER_SPI2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d10}]
180 set CM_PER_SPI3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d18}]
181 set CM_PER_SPI4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d20}]
182 set CM_PER_SPINLOCK_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d28}]
183 set CM_PER_TIMER2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d30}]
184 set CM_PER_TIMER3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d38}]
185 set CM_PER_TIMER4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d40}]
186 set CM_PER_TIMER5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d48}]
187 set CM_PER_TIMER6_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d50}]
188 set CM_PER_TIMER7_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d58}]
189 set CM_PER_TIMER8_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d60}]
190 set CM_PER_TIMER9_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d68}]
191 set CM_PER_TIMER10_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d70}]
192 set CM_PER_TIMER11_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d78}]
193 set CM_PER_UART1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d80}]
194 set CM_PER_UART2_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d88}]
195 set CM_PER_UART3_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d90}]
196 set CM_PER_UART4_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8d98}]
197 set CM_PER_UART5_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8da0}]
198 set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8db8}]
199 set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8dc0}]
200 set CM_PER_EMIF_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x8f00}]
201 set CM_PER_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f20}]
202 set CM_PER_DLL_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f28}]
203 set CM_PER_EMIF_FW_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f30}]
204 set CM_PER_OTFA_EMIF_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x8f38}]
205 set CM_PER_DSS_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9200}]
206 set CM_PER_DSS_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9220}]
207 set CM_PER_CPSW_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9300}]
208 set CM_PER_CPGMAC0_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9320}]
209 set CM_PER_OCPWP_L3_CLKSTCTRL [expr {$PRCM_BASE_ADDR + 0x9400}]
210 set CM_PER_OCPWP_CLKCTRL [expr {$PRCM_BASE_ADDR + 0x9420}]
212 set CONTROL_BASE_ADDR 0x44e10000
213 set CONTROL_STATUS [expr {$CONTROL_BASE_ADDR + 0x0040}]
214 set DEVICE_ID [expr {$CONTROL_BASE_ADDR + 0x0600}]
215 set DEV_FEATURE [expr {$CONTROL_BASE_ADDR + 0x0604}]
216 set DEV_ATTRIBUTE [expr {$CONTROL_BASE_ADDR + 0x0610}]
217 set MAC_ID0_LO [expr {$CONTROL_BASE_ADDR + 0x0630}]
218 set MAC_ID0_HI [expr {$CONTROL_BASE_ADDR + 0x0634}]
219 set MAC_ID1_LO [expr {$CONTROL_BASE_ADDR + 0x0638}]
220 set MAC_ID1_HI [expr {$CONTROL_BASE_ADDR + 0x063c}]
221 set USB_VID_PID [expr {$CONTROL_BASE_ADDR + 0x07f4}]
222 set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr {$CONTROL_BASE_ADDR + 0x0964}]
223 set CONTROL_CONF_SPI4_CS0 [expr {$CONTROL_BASE_ADDR + 0x0a5c}]
224 set CONTROL_CONF_SPI2_SCLK [expr {$CONTROL_BASE_ADDR + 0x0a60}]
225 set CONTROL_CONF_SPI2_D0 [expr {$CONTROL_BASE_ADDR + 0x0a64}]
226 set CONTROL_CONF_XDMA_EVENT_INTR0 [expr {$CONTROL_BASE_ADDR + 0x0a70}]
227 set CONTROL_CONF_XDMA_EVENT_INTR1 [expr {$CONTROL_BASE_ADDR + 0x0a74}]
228 set CONTROL_CONF_GPMC_A0 [expr {$CONTROL_BASE_ADDR + 0x0840}]
229 set DDR_IO_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e04}]
230 set VTP_CTRL_REG [expr {$CONTROL_BASE_ADDR + 0x0e0c}]
231 set VREF_CTRL [expr {$CONTROL_BASE_ADDR + 0x0e14}]
232 set DDR_CKE_CTRL [expr {$CONTROL_BASE_ADDR + 0x131c}]
233 set DDR_ADDRCTRL_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1404}]
234 set DDR_ADDRCTRL_WD0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1408}]
235 set DDR_ADDRCTRL_WD1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x140c}]
236 set DDR_DATA0_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1440}]
237 set DDR_DATA1_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1444}]
238 set DDR_DATA2_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x1448}]
239 set DDR_DATA3_IOCTRL [expr {$CONTROL_BASE_ADDR + 0x144c}]
240 set EMIF_SDRAM_CONFIG_EXT [expr {$CONTROL_BASE_ADDR + 0x1460}]
241 set EMIF_SDRAM_STATUS_EXT [expr {$CONTROL_BASE_ADDR + 0x1464}]
243 set GPIO0_BASE_ADDR 0x44e07000
244 set GPIO0_SYSCONFIG [expr {$GPIO0_BASE_ADDR + 0x0010}]
245 set GPIO0_SYSSTATUS [expr {$GPIO0_BASE_ADDR + 0x0114}]
246 set GPIO0_CTRL [expr {$GPIO0_BASE_ADDR + 0x0130}]
247 set GPIO0_OE [expr {$GPIO0_BASE_ADDR + 0x0134}]
248 set GPIO0_CLEARDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0190}]
249 set GPIO0_SETDATAOUT [expr {$GPIO0_BASE_ADDR + 0x0194}]
251 set GPIO5_BASE_ADDR 0x48322000
252 set GPIO5_SYSCONFIG [expr {$GPIO5_BASE_ADDR + 0x0010}]
253 set GPIO5_SYSSTATUS [expr {$GPIO5_BASE_ADDR + 0x0114}]
254 set GPIO5_CTRL [expr {$GPIO5_BASE_ADDR + 0x0130}]
255 set GPIO5_OE [expr {$GPIO5_BASE_ADDR + 0x0134}]
256 set GPIO5_CLEARDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0190}]
257 set GPIO5_SETDATAOUT [expr {$GPIO5_BASE_ADDR + 0x0194}]
259 set GPIO1_BASE_ADDR 0x4804c000
260 set GPIO1_SYSCONFIG [expr {$GPIO1_BASE_ADDR + 0x0010}]
261 set GPIO1_SYSSTATUS [expr {$GPIO1_BASE_ADDR + 0x0114}]
262 set GPIO1_CTRL [expr {$GPIO1_BASE_ADDR + 0x0130}]
263 set GPIO1_OE [expr {$GPIO1_BASE_ADDR + 0x0134}]
264 set GPIO1_CLEARDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0190}]
265 set GPIO1_SETDATAOUT [expr {$GPIO1_BASE_ADDR + 0x0194}]
267 set EMIF_BASE_ADDR 0x4c000000
268 set EMIF_STATUS [expr {$EMIF_BASE_ADDR + 0x0004}]
269 set EMIF_SDRAM_CONFIG [expr {$EMIF_BASE_ADDR + 0x0008}]
270 set EMIF_SDRAM_CONFIG_2 [expr {$EMIF_BASE_ADDR + 0x000c}]
271 set EMIF_SDRAM_REF_CTRL [expr {$EMIF_BASE_ADDR + 0x0010}]
272 set EMIF_SDRAM_REF_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x0014}]
273 set EMIF_SDRAM_TIM_1 [expr {$EMIF_BASE_ADDR + 0x0018}]
274 set EMIF_SDRAM_TIM_1_SHDW [expr {$EMIF_BASE_ADDR + 0x001c}]
275 set EMIF_SDRAM_TIM_2 [expr {$EMIF_BASE_ADDR + 0x0020}]
276 set EMIF_SDRAM_TIM_2_SHDW [expr {$EMIF_BASE_ADDR + 0x0024}]
277 set EMIF_SDRAM_TIM_3 [expr {$EMIF_BASE_ADDR + 0x0028}]
278 set EMIF_SDRAM_TIM_3_SHDW [expr {$EMIF_BASE_ADDR + 0x002c}]
279 set EMIF_LPDDR2_NVM_TIM [expr {$EMIF_BASE_ADDR + 0x0030}]
280 set EMIF_LPDDR2_NVM_TIM_SHDW [expr {$EMIF_BASE_ADDR + 0x0034}]
281 set EMIF_PWR_MGMT_CTRL [expr {$EMIF_BASE_ADDR + 0x0038}]
282 set EMIF_PWR_MGMT_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x003c}]
283 set EMIF_LPDDR2_MODE_REG_DATA [expr {$EMIF_BASE_ADDR + 0x0040}]
284 set EMIF_LPDDR2_MODE_REG_CFG [expr {$EMIF_BASE_ADDR + 0x0050}]
285 set EMIF_OCP_CONFIG [expr {$EMIF_BASE_ADDR + 0x0054}]
286 set EMIF_OCP_CFG_VAL_1 [expr {$EMIF_BASE_ADDR + 0x0058}]
287 set EMIF_OCP_CFG_VAL_2 [expr {$EMIF_BASE_ADDR + 0x005c}]
288 set EMIF_IODFT_TLGC [expr {$EMIF_BASE_ADDR + 0x0060}]
289 set EMIF_IODFT_CTRL_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0064}]
290 set EMIF_IODFT_ADDR_MISR_RSLT [expr {$EMIF_BASE_ADDR + 0x0068}]
291 set EMIF_IODFT_DATA_MISR_RSLT_1 [expr {$EMIF_BASE_ADDR + 0x006c}]
292 set EMIF_IODFT_DATA_MISR_RSLT_2 [expr {$EMIF_BASE_ADDR + 0x0070}]
293 set EMIF_IODFT_DATA_MISR_RSLT_3 [expr {$EMIF_BASE_ADDR + 0x0074}]
294 set EMIF_PERF_CNT_1 [expr {$EMIF_BASE_ADDR + 0x0080}]
295 set EMIF_PERF_CNT_2 [expr {$EMIF_BASE_ADDR + 0x0084}]
296 set EMIF_PERF_CNT_CFG [expr {$EMIF_BASE_ADDR + 0x0088}]
297 set EMIF_PERF_CNT_SEL [expr {$EMIF_BASE_ADDR + 0x008c}]
298 set EMIF_PERF_CNT_TIM [expr {$EMIF_BASE_ADDR + 0x0090}]
299 set EMIF_MISC_REG [expr {$EMIF_BASE_ADDR + 0x0094}]
300 set EMIF_DLL_CALIB_CTRL [expr {$EMIF_BASE_ADDR + 0x0098}]
301 set EMIF_DLL_CALIB_CTRL_SHDW [expr {$EMIF_BASE_ADDR + 0x009c}]
302 set EMIF_IRQ_EOI [expr {$EMIF_BASE_ADDR + 0x00a0}]
303 set EMIF_IRQSTATUS_RAW_SYS [expr {$EMIF_BASE_ADDR + 0x00a4}]
304 set EMIF_IRQSTATUS_SYS [expr {$EMIF_BASE_ADDR + 0x00ac}]
305 set EMIF_IRQENABLE_SET_SYS [expr {$EMIF_BASE_ADDR + 0x00b4}]
306 set EMIF_IRQENABLE_CLR_SYS [expr {$EMIF_BASE_ADDR + 0x00bc}]
307 set EMIF_ZQ_CONFIG [expr {$EMIF_BASE_ADDR + 0x00c8}]
308 set EMIF_TEMP_ALERT_CONFIG [expr {$EMIF_BASE_ADDR + 0x00cc}]
309 set EMIF_OCP_ERR_LOG [expr {$EMIF_BASE_ADDR + 0x00d0}]
310 set EMIF_RDWR_LVL_RMP_WIN [expr {$EMIF_BASE_ADDR + 0x00d4}]
311 set EMIF_RDWR_LVL_RMP_CTRL [expr {$EMIF_BASE_ADDR + 0x00d8}]
312 set EMIF_RDWR_LVL_CTRL [expr {$EMIF_BASE_ADDR + 0x00dc}]
313 set EMIF_DDR_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x00e4}]
314 set EMIF_DDR_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x00e8}]
315 set EMIF_DDR_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x00ec}]
316 set EMIF_PRI_COS_MAP [expr {$EMIF_BASE_ADDR + 0x0100}]
317 set EMIF_CONNID_COS_1_MAP [expr {$EMIF_BASE_ADDR + 0x0104}]
318 set EMIF_CONNID_COS_2_MAP [expr {$EMIF_BASE_ADDR + 0x0108}]
319 set ECC_CTRL [expr {$EMIF_BASE_ADDR + 0x0110}]
320 set ECC_ADDR_RNG_1 [expr {$EMIF_BASE_ADDR + 0x0114}]
321 set ECC_ADDR_RNG_2 [expr {$EMIF_BASE_ADDR + 0x0118}]
322 set EMIF_RD_WR_EXEC_THRSH [expr {$EMIF_BASE_ADDR + 0x0120}]
323 set COS_CONFIG [expr {$EMIF_BASE_ADDR + 0x0124}]
325 set PHY_STATUS_1 [expr {$EMIF_BASE_ADDR + 0x0144}]
326 set PHY_STATUS_2 [expr {$EMIF_BASE_ADDR + 0x0148}]
327 set PHY_STATUS_3 [expr {$EMIF_BASE_ADDR + 0x014c}]
328 set PHY_STATUS_4 [expr {$EMIF_BASE_ADDR + 0x0150}]
329 set PHY_STATUS_5 [expr {$EMIF_BASE_ADDR + 0x0154}]
330 set PHY_STATUS_6 [expr {$EMIF_BASE_ADDR + 0x0158}]
331 set PHY_STATUS_7 [expr {$EMIF_BASE_ADDR + 0x015c}]
332 set PHY_STATUS_8 [expr {$EMIF_BASE_ADDR + 0x0160}]
333 set PHY_STATUS_9 [expr {$EMIF_BASE_ADDR + 0x0164}]
334 set PHY_STATUS_10 [expr {$EMIF_BASE_ADDR + 0x0168}]
335 set PHY_STATUS_11 [expr {$EMIF_BASE_ADDR + 0x016c}]
336 set PHY_STATUS_12 [expr {$EMIF_BASE_ADDR + 0x0170}]
337 set PHY_STATUS_13 [expr {$EMIF_BASE_ADDR + 0x0174}]
338 set PHY_STATUS_14 [expr {$EMIF_BASE_ADDR + 0x0178}]
339 set PHY_STATUS_15 [expr {$EMIF_BASE_ADDR + 0x017c}]
340 set PHY_STATUS_16 [expr {$EMIF_BASE_ADDR + 0x0180}]
341 set PHY_STATUS_17 [expr {$EMIF_BASE_ADDR + 0x0184}]
342 set PHY_STATUS_18 [expr {$EMIF_BASE_ADDR + 0x0188}]
343 set PHY_STATUS_19 [expr {$EMIF_BASE_ADDR + 0x018c}]
344 set PHY_STATUS_20 [expr {$EMIF_BASE_ADDR + 0x0190}]
345 set PHY_STATUS_21 [expr {$EMIF_BASE_ADDR + 0x0194}]
346 set PHY_STATUS_22 [expr {$EMIF_BASE_ADDR + 0x0198}]
347 set PHY_STATUS_23 [expr {$EMIF_BASE_ADDR + 0x019c}]
348 set PHY_STATUS_24 [expr {$EMIF_BASE_ADDR + 0x01a0}]
349 set PHY_STATUS_25 [expr {$EMIF_BASE_ADDR + 0x01a4}]
350 set PHY_STATUS_26 [expr {$EMIF_BASE_ADDR + 0x01a8}]
351 set PHY_STATUS_27 [expr {$EMIF_BASE_ADDR + 0x01ac}]
352 set PHY_STATUS_28 [expr {$EMIF_BASE_ADDR + 0x01b0}]
354 set EXT_PHY_CTRL_1 [expr {$EMIF_BASE_ADDR + 0x0200}]
355 set EXT_PHY_CTRL_1_SHDW [expr {$EMIF_BASE_ADDR + 0x0204}]
356 set EXT_PHY_CTRL_2 [expr {$EMIF_BASE_ADDR + 0x0208}]
357 set EXT_PHY_CTRL_2_SHDW [expr {$EMIF_BASE_ADDR + 0x020c}]
358 set EXT_PHY_CTRL_3 [expr {$EMIF_BASE_ADDR + 0x0210}]
359 set EXT_PHY_CTRL_3_SHDW [expr {$EMIF_BASE_ADDR + 0x0214}]
360 set EXT_PHY_CTRL_4 [expr {$EMIF_BASE_ADDR + 0x0218}]
361 set EXT_PHY_CTRL_4_SHDW [expr {$EMIF_BASE_ADDR + 0x021c}]
362 set EXT_PHY_CTRL_5 [expr {$EMIF_BASE_ADDR + 0x0220}]
363 set EXT_PHY_CTRL_5_SHDW [expr {$EMIF_BASE_ADDR + 0x0224}]
364 set EXT_PHY_CTRL_6 [expr {$EMIF_BASE_ADDR + 0x0228}]
365 set EXT_PHY_CTRL_6_SHDW [expr {$EMIF_BASE_ADDR + 0x022c}]
366 set EXT_PHY_CTRL_7 [expr {$EMIF_BASE_ADDR + 0x0230}]
367 set EXT_PHY_CTRL_7_SHDW [expr {$EMIF_BASE_ADDR + 0x0234}]
368 set EXT_PHY_CTRL_8 [expr {$EMIF_BASE_ADDR + 0x0238}]
369 set EXT_PHY_CTRL_8_SHDW [expr {$EMIF_BASE_ADDR + 0x023c}]
370 set EXT_PHY_CTRL_9 [expr {$EMIF_BASE_ADDR + 0x0240}]
371 set EXT_PHY_CTRL_9_SHDW [expr {$EMIF_BASE_ADDR + 0x0244}]
372 set EXT_PHY_CTRL_10 [expr {$EMIF_BASE_ADDR + 0x0248}]
373 set EXT_PHY_CTRL_10_SHDW [expr {$EMIF_BASE_ADDR + 0x024c}]
374 set EXT_PHY_CTRL_11 [expr {$EMIF_BASE_ADDR + 0x0250}]
375 set EXT_PHY_CTRL_11_SHDW [expr {$EMIF_BASE_ADDR + 0x0254}]
376 set EXT_PHY_CTRL_12 [expr {$EMIF_BASE_ADDR + 0x0258}]
377 set EXT_PHY_CTRL_12_SHDW [expr {$EMIF_BASE_ADDR + 0x025c}]
378 set EXT_PHY_CTRL_13 [expr {$EMIF_BASE_ADDR + 0x0260}]
379 set EXT_PHY_CTRL_13_SHDW [expr {$EMIF_BASE_ADDR + 0x0264}]
380 set EXT_PHY_CTRL_14 [expr {$EMIF_BASE_ADDR + 0x0268}]
381 set EXT_PHY_CTRL_14_SHDW [expr {$EMIF_BASE_ADDR + 0x026c}]
382 set EXT_PHY_CTRL_15 [expr {$EMIF_BASE_ADDR + 0x0270}]
383 set EXT_PHY_CTRL_15_SHDW [expr {$EMIF_BASE_ADDR + 0x0274}]
384 set EXT_PHY_CTRL_16 [expr {$EMIF_BASE_ADDR + 0x0278}]
385 set EXT_PHY_CTRL_16_SHDW [expr {$EMIF_BASE_ADDR + 0x027c}]
386 set EXT_PHY_CTRL_17 [expr {$EMIF_BASE_ADDR + 0x0280}]
387 set EXT_PHY_CTRL_17_SHDW [expr {$EMIF_BASE_ADDR + 0x0284}]
388 set EXT_PHY_CTRL_18 [expr {$EMIF_BASE_ADDR + 0x0288}]
389 set EXT_PHY_CTRL_18_SHDW [expr {$EMIF_BASE_ADDR + 0x028c}]
390 set EXT_PHY_CTRL_19 [expr {$EMIF_BASE_ADDR + 0x0290}]
391 set EXT_PHY_CTRL_19_SHDW [expr {$EMIF_BASE_ADDR + 0x0294}]
392 set EXT_PHY_CTRL_20 [expr {$EMIF_BASE_ADDR + 0x0298}]
393 set EXT_PHY_CTRL_20_SHDW [expr {$EMIF_BASE_ADDR + 0x029c}]
394 set EXT_PHY_CTRL_21 [expr {$EMIF_BASE_ADDR + 0x02a0}]
395 set EXT_PHY_CTRL_21_SHDW [expr {$EMIF_BASE_ADDR + 0x02a4}]
396 set EXT_PHY_CTRL_22 [expr {$EMIF_BASE_ADDR + 0x02a8}]
397 set EXT_PHY_CTRL_22_SHDW [expr {$EMIF_BASE_ADDR + 0x02ac}]
398 set EXT_PHY_CTRL_23 [expr {$EMIF_BASE_ADDR + 0x02b0}]
399 set EXT_PHY_CTRL_23_SHDW [expr {$EMIF_BASE_ADDR + 0x02b4}]
400 set EXT_PHY_CTRL_24 [expr {$EMIF_BASE_ADDR + 0x02b8}]
401 set EXT_PHY_CTRL_24_SHDW [expr {$EMIF_BASE_ADDR + 0x02bc}]
402 set EXT_PHY_CTRL_25 [expr {$EMIF_BASE_ADDR + 0x02c0}]
403 set EXT_PHY_CTRL_25_SHDW [expr {$EMIF_BASE_ADDR + 0x02c4}]
404 set EXT_PHY_CTRL_26 [expr {$EMIF_BASE_ADDR + 0x02c8}]
405 set EXT_PHY_CTRL_26_SHDW [expr {$EMIF_BASE_ADDR + 0x02cc}]
406 set EXT_PHY_CTRL_27 [expr {$EMIF_BASE_ADDR + 0x02d0}]
407 set EXT_PHY_CTRL_27_SHDW [expr {$EMIF_BASE_ADDR + 0x02d4}]
408 set EXT_PHY_CTRL_28 [expr {$EMIF_BASE_ADDR + 0x02d8}]
409 set EXT_PHY_CTRL_28_SHDW [expr {$EMIF_BASE_ADDR + 0x02dc}]
410 set EXT_PHY_CTRL_29 [expr {$EMIF_BASE_ADDR + 0x02e0}]
411 set EXT_PHY_CTRL_29_SHDW [expr {$EMIF_BASE_ADDR + 0x02e4}]
412 set EXT_PHY_CTRL_30 [expr {$EMIF_BASE_ADDR + 0x02e8}]
413 set EXT_PHY_CTRL_30_SHDW [expr {$EMIF_BASE_ADDR + 0x02ec}]
414 set EXT_PHY_CTRL_31 [expr {$EMIF_BASE_ADDR + 0x02f0}]
415 set EXT_PHY_CTRL_31_SHDW [expr {$EMIF_BASE_ADDR + 0x02f4}]
416 set EXT_PHY_CTRL_32 [expr {$EMIF_BASE_ADDR + 0x02f8}]
417 set EXT_PHY_CTRL_32_SHDW [expr {$EMIF_BASE_ADDR + 0x02fc}]
418 set EXT_PHY_CTRL_33 [expr {$EMIF_BASE_ADDR + 0x0300}]
419 set EXT_PHY_CTRL_33_SHDW [expr {$EMIF_BASE_ADDR + 0x0304}]
420 set EXT_PHY_CTRL_34 [expr {$EMIF_BASE_ADDR + 0x0308}]
421 set EXT_PHY_CTRL_34_SHDW [expr {$EMIF_BASE_ADDR + 0x030c}]
422 set EXT_PHY_CTRL_35 [expr {$EMIF_BASE_ADDR + 0x0310}]
423 set EXT_PHY_CTRL_35_SHDW [expr {$EMIF_BASE_ADDR + 0x0314}]
424 set EXT_PHY_CTRL_36 [expr {$EMIF_BASE_ADDR + 0x0318}]
425 set EXT_PHY_CTRL_36_SHDW [expr {$EMIF_BASE_ADDR + 0x031c}]
427 set WDT1_BASE_ADDR 0x44e35000
428 set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}]
429 set WDT1_WSPR [expr {$WDT1_BASE_ADDR + 0x0048}]
431 set RTC_BASE_ADDR 0x44e3e000
432 set RTC_KICK0R [expr {$RTC_BASE_ADDR + 0x6c}]
433 set RTC_KICK1R [expr {$RTC_BASE_ADDR + 0x70}]
436 if { [info exists CHIPNAME] } {
437 set _CHIPNAME $CHIPNAME
442 set JRC_MODULE icepick_d
443 set DEBUGSS_MODULE debugss
444 set M3_MODULE m3_wakeupss
446 set JRC_NAME $_CHIPNAME.$JRC_MODULE
447 set DEBUGSS_NAME $_CHIPNAME.$DEBUGSS_MODULE
448 set M3_NAME $_CHIPNAME.$M3_MODULE
449 set _TARGETNAME $_CHIPNAME.mpuss
454 if { [info exists M3_DAP_TAPID] } {
455 set _M3_DAP_TAPID $M3_DAP_TAPID
457 set _M3_DAP_TAPID 0x4b6b902f
459 jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
460 jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
461 dap create $M3_NAME.dap -chain-position $M3_NAME
466 if { [info exists DAP_TAPID] } {
467 set _DAP_TAPID $DAP_TAPID
469 set _DAP_TAPID 0x46b6902f
471 jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
472 jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
473 dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME
476 # ICEpick-D (JTAG route controller)
478 if { [info exists JRC_TAPID] } {
479 set _JRC_TAPID $JRC_TAPID
481 set _JRC_TAPID 0x0b98c02f
483 jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
484 jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
485 # some TCK tycles are required to activate the DEBUG power domain
486 jtag configure $JRC_NAME -event post-reset "runtest 100"
491 target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000
494 # SRAM: 256K at 0x4030.0000
495 $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
497 # Disables watchdog timer after reset otherwise board won't stay in
499 proc disable_watchdog { } {
501 global WDT1_W_PEND_WSPR
504 set curstate [$_TARGETNAME curstate]
506 if { [string compare $curstate halted] == 0 } {
507 set WDT_DISABLE_SEQ1 0xaaaa
508 set WDT_DISABLE_SEQ2 0x5555
510 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
512 # Empty body to make sure this executes as fast as possible.
513 # We don't want any delays here otherwise romcode might start
514 # executing and end up changing state of certain IPs.
515 while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
517 mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
518 while { [expr {[mrw $WDT1_W_PEND_WSPR] & 0x10}] } { }
523 return [ expr {($x + $y - 1) / $y} ]
526 proc device_type { } {
527 global CONTROL_STATUS
529 set tmp [ mrw $CONTROL_STATUS ]
530 set tmp [ expr {$tmp & 0x700} ]
531 set tmp [ expr {$tmp >> 8} ]
536 proc get_input_clock_frequency { } {
537 global CONTROL_STATUS
539 if { [ device_type ] != 3 } {
540 error "Unknown device type\n"
544 set freq [ mrw $CONTROL_STATUS ]
545 set freq [ expr {$freq & 0x00c00000} ]
546 set freq [ expr {$freq >> 22} ]
569 proc mpu_pll_config { CLKIN N M M2 } {
570 global CM_CLKMODE_DPLL_MPU
571 global CM_CLKSEL_DPLL_MPU
572 global CM_DIV_M2_DPLL_MPU
573 global CM_IDLEST_DPLL_MPU
575 set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
576 set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]
578 mww $CM_CLKMODE_DPLL_MPU 0x4
579 while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }
581 set clksel [ expr {$clksel & (~0x7ffff)} ]
582 set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
583 mww $CM_CLKSEL_DPLL_MPU $clksel
585 set div_m2 [ expr {$div_m2 & (~0x1f)} ]
586 set div_m2 [ expr {$div_m2 | $M2} ]
587 mww $CM_DIV_M2_DPLL_MPU $div_m2
589 mww $CM_CLKMODE_DPLL_MPU 0x7
590 while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }
592 echo "MPU DPLL locked"
595 proc core_pll_config { CLKIN N M M4 M5 M6 } {
596 global CM_CLKMODE_DPLL_CORE
597 global CM_CLKSEL_DPLL_CORE
598 global CM_DIV_M4_DPLL_CORE
599 global CM_DIV_M5_DPLL_CORE
600 global CM_DIV_M6_DPLL_CORE
601 global CM_IDLEST_DPLL_CORE
603 set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]
605 mww $CM_CLKMODE_DPLL_CORE 0x4
606 while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }
608 set clksel [ expr {$clksel & (~0x7ffff)} ]
609 set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
610 mww $CM_CLKSEL_DPLL_CORE $clksel
611 mww $CM_DIV_M4_DPLL_CORE $M4
612 mww $CM_DIV_M5_DPLL_CORE $M5
613 mww $CM_DIV_M6_DPLL_CORE $M6
615 mww $CM_CLKMODE_DPLL_CORE 0x7
616 while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }
618 echo "CORE DPLL locked"
621 proc per_pll_config { CLKIN N M M2 } {
622 global CM_CLKMODE_DPLL_PER
623 global CM_CLKSEL_DPLL_PER
624 global CM_DIV_M2_DPLL_PER
625 global CM_IDLEST_DPLL_PER
627 set x [ expr {$M * $CLKIN / 1000000} ]
628 set y [ expr {($N + 1) * 250} ]
629 set sd [ ceil $x $y ]
631 set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
632 set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]
634 mww $CM_CLKMODE_DPLL_PER 0x4
635 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }
637 set clksel [ expr {$clksel & (~0xff0fffff)} ]
638 set clksel [ expr {$clksel | ($M << 0x8) | $N} ]
639 set clksel [ expr {$clksel | ($sd << 24)} ]
640 mww $CM_CLKSEL_DPLL_PER $clksel
642 set div_m2 [ expr {0xffffff80 | $M2} ]
644 mww $CM_CLKMODE_DPLL_PER 0x7
645 while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }
647 echo "PER DPLL locked"
650 proc ddr_pll_config { CLKIN N M M2 M4 } {
651 global CM_CLKMODE_DPLL_DDR
652 global CM_CLKSEL_DPLL_DDR
653 global CM_DIV_M2_DPLL_DDR
654 global CM_DIV_M4_DPLL_DDR
655 global CM_IDLEST_DPLL_DDR
657 set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
658 set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]
660 mww $CM_CLKMODE_DPLL_DDR 0x4
661 while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }
663 set clksel [ expr {$clksel & (~0x7ffff)} ]
664 set clksel [ expr {$clksel | ($M << 8) | $N} ]
665 mww $CM_CLKSEL_DPLL_DDR $clksel
667 set div_m2 [ expr {($div_m2 & 0xffffffe0) | $M2} ]
668 mww $CM_DIV_M2_DPLL_DDR $div_m2
669 mww $CM_DIV_M4_DPLL_DDR $M4
671 mww $CM_CLKMODE_DPLL_DDR 0x7
672 while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }
674 echo "DDR DPLL Locked"
677 proc config_opp100 { } {
678 set CLKIN [ get_input_clock_frequency ]
680 if { $CLKIN == -1 } {
686 mpu_pll_config $CLKIN 0 25 1
687 core_pll_config $CLKIN 2 125 10 8 4
688 per_pll_config $CLKIN 9 400 5
689 ddr_pll_config $CLKIN 2 50 1 2
693 mpu_pll_config $CLKIN 0 24 1
694 core_pll_config $CLKIN 0 40 10 8 4
695 per_pll_config $CLKIN 9 384 5
696 ddr_pll_config $CLKIN 0 16 1 2
700 mpu_pll_config $CLKIN 12 300 1
701 core_pll_config $CLKIN 12 500 10 8 4
702 per_pll_config $CLKIN 12 480 5
703 ddr_pll_config $CLKIN 12 200 1 2
707 mpu_pll_config $CLKIN 3 125 1
708 core_pll_config $CLKIN 11 625 10 8 4
709 per_pll_config $CLKIN 7 400 5
710 ddr_pll_config $CLKIN 2 125 1 2
715 proc emif_prcm_clk_enable { } {
716 global CM_PER_EMIF_FW_CLKCTRL
717 global CM_PER_EMIF_CLKCTRL
719 mww $CM_PER_EMIF_FW_CLKCTRL 0x02
720 mww $CM_PER_EMIF_CLKCTRL 0x02
722 while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
725 proc vtp_enable { } {
728 set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x40 }]
729 mww $VTP_CTRL_REG $vtp
731 set vtp [ expr {[ mrw $VTP_CTRL_REG ] & ~0x01 }]
732 mww $VTP_CTRL_REG $vtp
734 set vtp [ expr {[ mrw $VTP_CTRL_REG ] | 0x01 }]
735 mww $VTP_CTRL_REG $vtp
739 proc config_ddr_ioctrl { } {
740 global DDR_ADDRCTRL_IOCTRL
741 global DDR_ADDRCTRL_WD0_IOCTRL
742 global DDR_ADDRCTRL_WD1_IOCTRL
744 global DDR_DATA0_IOCTRL
745 global DDR_DATA1_IOCTRL
746 global DDR_DATA2_IOCTRL
747 global DDR_DATA3_IOCTRL
750 mww $DDR_ADDRCTRL_IOCTRL 0x84
751 mww $DDR_ADDRCTRL_WD0_IOCTRL 0x00
752 mww $DDR_ADDRCTRL_WD1_IOCTRL 0x00
753 mww $DDR_DATA0_IOCTRL 0x84
754 mww $DDR_DATA1_IOCTRL 0x84
755 mww $DDR_DATA2_IOCTRL 0x84
756 mww $DDR_DATA3_IOCTRL 0x84
758 mww $DDR_IO_CTRL 0x00
759 mww $DDR_CKE_CTRL 0x03
762 proc config_ddr_phy { } {
763 global EMIF_DDR_PHY_CTRL_1
764 global EMIF_DDR_PHY_CTRL_1_SHDW
766 global EXT_PHY_CTRL_1
767 global EXT_PHY_CTRL_1_SHDW
768 global EXT_PHY_CTRL_2
769 global EXT_PHY_CTRL_2_SHDW
770 global EXT_PHY_CTRL_3
771 global EXT_PHY_CTRL_3_SHDW
772 global EXT_PHY_CTRL_4
773 global EXT_PHY_CTRL_4_SHDW
774 global EXT_PHY_CTRL_5
775 global EXT_PHY_CTRL_5_SHDW
776 global EXT_PHY_CTRL_6
777 global EXT_PHY_CTRL_6_SHDW
778 global EXT_PHY_CTRL_7
779 global EXT_PHY_CTRL_7_SHDW
780 global EXT_PHY_CTRL_8
781 global EXT_PHY_CTRL_8_SHDW
782 global EXT_PHY_CTRL_9
783 global EXT_PHY_CTRL_9_SHDW
784 global EXT_PHY_CTRL_10
785 global EXT_PHY_CTRL_10_SHDW
786 global EXT_PHY_CTRL_11
787 global EXT_PHY_CTRL_11_SHDW
788 global EXT_PHY_CTRL_12
789 global EXT_PHY_CTRL_12_SHDW
790 global EXT_PHY_CTRL_13
791 global EXT_PHY_CTRL_13_SHDW
792 global EXT_PHY_CTRL_14
793 global EXT_PHY_CTRL_14_SHDW
794 global EXT_PHY_CTRL_15
795 global EXT_PHY_CTRL_15_SHDW
796 global EXT_PHY_CTRL_16
797 global EXT_PHY_CTRL_16_SHDW
798 global EXT_PHY_CTRL_17
799 global EXT_PHY_CTRL_17_SHDW
800 global EXT_PHY_CTRL_18
801 global EXT_PHY_CTRL_18_SHDW
802 global EXT_PHY_CTRL_19
803 global EXT_PHY_CTRL_19_SHDW
804 global EXT_PHY_CTRL_20
805 global EXT_PHY_CTRL_20_SHDW
806 global EXT_PHY_CTRL_21
807 global EXT_PHY_CTRL_21_SHDW
808 global EXT_PHY_CTRL_22
809 global EXT_PHY_CTRL_22_SHDW
810 global EXT_PHY_CTRL_23
811 global EXT_PHY_CTRL_23_SHDW
812 global EXT_PHY_CTRL_24
813 global EXT_PHY_CTRL_24_SHDW
814 global EXT_PHY_CTRL_25
815 global EXT_PHY_CTRL_25_SHDW
816 global EXT_PHY_CTRL_26
817 global EXT_PHY_CTRL_26_SHDW
818 global EXT_PHY_CTRL_27
819 global EXT_PHY_CTRL_27_SHDW
820 global EXT_PHY_CTRL_28
821 global EXT_PHY_CTRL_28_SHDW
822 global EXT_PHY_CTRL_29
823 global EXT_PHY_CTRL_29_SHDW
824 global EXT_PHY_CTRL_30
825 global EXT_PHY_CTRL_30_SHDW
826 global EXT_PHY_CTRL_31
827 global EXT_PHY_CTRL_31_SHDW
828 global EXT_PHY_CTRL_32
829 global EXT_PHY_CTRL_32_SHDW
830 global EXT_PHY_CTRL_33
831 global EXT_PHY_CTRL_33_SHDW
832 global EXT_PHY_CTRL_34
833 global EXT_PHY_CTRL_34_SHDW
834 global EXT_PHY_CTRL_35
835 global EXT_PHY_CTRL_35_SHDW
836 global EXT_PHY_CTRL_36
837 global EXT_PHY_CTRL_36_SHDW
839 mww $EMIF_DDR_PHY_CTRL_1 0x8009
840 mww $EMIF_DDR_PHY_CTRL_1_SHDW 0x8009
843 set gatelvl_init_ratio 0x20
844 set wr_dqs_slave_delay 0x60
845 set rd_dqs_slave_delay 0x60
847 set gatelvl_init_mode 0x01
848 set wr_data_slave_delay 0x80
849 set gatelvl_num_dq0 0x0f
850 set wrlvl_num_dq0 0x0f
852 mww $EXT_PHY_CTRL_1 [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
853 mww $EXT_PHY_CTRL_1_SHDW [ expr {($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio} ]
854 mww $EXT_PHY_CTRL_26 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
855 mww $EXT_PHY_CTRL_26_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
856 mww $EXT_PHY_CTRL_27 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
857 mww $EXT_PHY_CTRL_27_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
858 mww $EXT_PHY_CTRL_28 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
859 mww $EXT_PHY_CTRL_28_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
860 mww $EXT_PHY_CTRL_29 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
861 mww $EXT_PHY_CTRL_29_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
862 mww $EXT_PHY_CTRL_30 [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
863 mww $EXT_PHY_CTRL_30_SHDW [ expr {($gatelvl_init_ratio << 16) | $gatelvl_init_ratio} ]
864 mww $EXT_PHY_CTRL_31 0x00
865 mww $EXT_PHY_CTRL_31_SHDW 0x00
866 mww $EXT_PHY_CTRL_32 0x00
867 mww $EXT_PHY_CTRL_32_SHDW 0x00
868 mww $EXT_PHY_CTRL_33 0x00
869 mww $EXT_PHY_CTRL_33_SHDW 0x00
870 mww $EXT_PHY_CTRL_34 0x00
871 mww $EXT_PHY_CTRL_34_SHDW 0x00
872 mww $EXT_PHY_CTRL_35 0x00
873 mww $EXT_PHY_CTRL_35_SHDW 0x00
874 mww $EXT_PHY_CTRL_22 0x00
875 mww $EXT_PHY_CTRL_22_SHDW 0x00
876 mww $EXT_PHY_CTRL_23 [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ]
877 mww $EXT_PHY_CTRL_23_SHDW [ expr {($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay} ]
878 mww $EXT_PHY_CTRL_24 [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay} ]
879 mww $EXT_PHY_CTRL_24_SHDW [ expr {($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0} ]
880 mww $EXT_PHY_CTRL_25 [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
881 mww $EXT_PHY_CTRL_25_SHDW [ expr {($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset} ]
882 mww $EXT_PHY_CTRL_36 [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
883 mww $EXT_PHY_CTRL_36_SHDW [ expr {($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0} ]
886 proc config_ddr_timing { } {
887 global EMIF_SDRAM_TIM_1
888 global EMIF_SDRAM_TIM_2
889 global EMIF_SDRAM_TIM_3
890 global EMIF_SDRAM_TIM_1_SHDW
891 global EMIF_SDRAM_TIM_2_SHDW
892 global EMIF_SDRAM_TIM_3_SHDW
893 global EMIF_ZQ_CONFIG
895 mww $EMIF_SDRAM_TIM_1 0xeaaad4db
896 mww $EMIF_SDRAM_TIM_1_SHDW 0xeaaad4db
898 mww $EMIF_SDRAM_TIM_2 0x266b7fda
899 mww $EMIF_SDRAM_TIM_2_SHDW 0x266b7fda
901 mww $EMIF_SDRAM_TIM_3 0x107f8678
902 mww $EMIF_SDRAM_TIM_3_SHDW 0x107f8678
904 mww $EMIF_ZQ_CONFIG 0x50074be4
907 proc config_ddr_pm { } {
908 global EMIF_PWR_MGMT_CTRL
909 global EMIF_PWR_MGMT_CTRL_SHDW
910 global EMIF_DLL_CALIB_CTRL
911 global EMIF_DLL_CALIB_CTRL_SHDW
912 global EMIF_TEMP_ALERT_CONFIG
914 mww $EMIF_PWR_MGMT_CTRL 0x00
915 mww $EMIF_PWR_MGMT_CTRL_SHDW 0x00
916 mww $EMIF_DLL_CALIB_CTRL 0x00050000
917 mww $EMIF_DLL_CALIB_CTRL_SHDW 0x00050000
918 mww $EMIF_TEMP_ALERT_CONFIG 0x00
921 proc config_ddr_priority { } {
922 global EMIF_PRI_COS_MAP
923 global EMIF_CONNID_COS_1_MAP
924 global EMIF_CONNID_COS_2_MAP
925 global EMIF_RD_WR_EXEC_THRSH
928 mww $EMIF_PRI_COS_MAP 0x00
929 mww $EMIF_CONNID_COS_1_MAP 0x00
930 mww $EMIF_CONNID_COS_2_MAP 0x0
931 mww $EMIF_RD_WR_EXEC_THRSH 0x0405
932 mww $COS_CONFIG 0x00ffffff
935 proc config_ddr3 { SDRAM_CONFIG } {
937 global EMIF_IODFT_TLGC
938 global EMIF_RDWR_LVL_CTRL
939 global EMIF_RDWR_LVL_RMP_CTRL
940 global EMIF_SDRAM_CONFIG
941 global EMIF_SDRAM_CONFIG_EXT
942 global EMIF_SDRAM_REF_CTRL
943 global EMIF_SDRAM_REF_CTRL_SHDW
945 global EXT_PHY_CTRL_36
946 global EXT_PHY_CTRL_36_SHDW
951 set dll [ expr {[ mrw $CM_DLL_CTRL ] & ~0x01 }]
952 mww $CM_DLL_CTRL $dll
953 while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
957 mww $EMIF_SDRAM_CONFIG_EXT 0xc163
958 mww $EMIF_IODFT_TLGC 0x2011
959 mww $EMIF_IODFT_TLGC 0x2411
960 mww $EMIF_IODFT_TLGC 0x2011
961 mww $EMIF_SDRAM_REF_CTRL 0x80003000
965 mww $EMIF_IODFT_TLGC 0x2011
966 mww $EMIF_IODFT_TLGC 0x2411
967 mww $EMIF_IODFT_TLGC 0x2011
973 mww $EMIF_SDRAM_REF_CTRL 0x3000
974 mww $EMIF_SDRAM_CONFIG $SDRAM_CONFIG
976 mww $EMIF_SDRAM_REF_CTRL 0x0c30
977 mww $EMIF_SDRAM_REF_CTRL_SHDW 0x0c30
981 set tmp [ expr {[ mrw $EXT_PHY_CTRL_36 ] | 0x0100 }]
982 mww $EXT_PHY_CTRL_36 $tmp
983 mww $EXT_PHY_CTRL_36_SHDW $tmp
985 mww $EMIF_RDWR_LVL_RMP_CTRL 0x80000000
986 mww $EMIF_RDWR_LVL_CTRL 0x80000000
988 while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }
990 if { [ mrw $EMIF_STATUS ] & 0x70 } {
991 error "DDR3 Hardware Leveling incomplete!!!"
995 proc init_platform { SDRAM_CONFIG } {
997 config_ddr3 $SDRAM_CONFIG
1000 $_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
1001 $_TARGETNAME configure -event reset-end { disable_watchdog }
projects / fw / openocd / blob