1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # /* Peripheral and SRAM base address in the alias region */
4 set PERIPH_BB_BASE 0x42000000
5 set SRAM_BB_BASE 0x22000000
7 # /*Peripheral and SRAM base address in the bit-band region */
8 set SRAM_BASE 0x20000000
9 set PERIPH_BASE 0x40000000
11 # /*FSMC registers base address */
12 set FSMC_R_BASE 0xA0000000
14 # /*Peripheral memory map */
15 set APB1PERIPH_BASE [set PERIPH_BASE]
16 set APB2PERIPH_BASE [expr {$PERIPH_BASE + 0x10000}]
17 set AHBPERIPH_BASE [expr {$PERIPH_BASE + 0x20000}]
19 set TIM2_BASE [expr {$APB1PERIPH_BASE + 0x0000}]
20 set TIM3_BASE [expr {$APB1PERIPH_BASE + 0x0400}]
21 set TIM4_BASE [expr {$APB1PERIPH_BASE + 0x0800}]
22 set TIM5_BASE [expr {$APB1PERIPH_BASE + 0x0C00}]
23 set TIM6_BASE [expr {$APB1PERIPH_BASE + 0x1000}]
24 set TIM7_BASE [expr {$APB1PERIPH_BASE + 0x1400}]
25 set RTC_BASE [expr {$APB1PERIPH_BASE + 0x2800}]
26 set WWDG_BASE [expr {$APB1PERIPH_BASE + 0x2C00}]
27 set IWDG_BASE [expr {$APB1PERIPH_BASE + 0x3000}]
28 set SPI2_BASE [expr {$APB1PERIPH_BASE + 0x3800}]
29 set SPI3_BASE [expr {$APB1PERIPH_BASE + 0x3C00}]
30 set USART2_BASE [expr {$APB1PERIPH_BASE + 0x4400}]
31 set USART3_BASE [expr {$APB1PERIPH_BASE + 0x4800}]
32 set UART4_BASE [expr {$APB1PERIPH_BASE + 0x4C00}]
33 set UART5_BASE [expr {$APB1PERIPH_BASE + 0x5000}]
34 set I2C1_BASE [expr {$APB1PERIPH_BASE + 0x5400}]
35 set I2C2_BASE [expr {$APB1PERIPH_BASE + 0x5800}]
36 set CAN_BASE [expr {$APB1PERIPH_BASE + 0x6400}]
37 set BKP_BASE [expr {$APB1PERIPH_BASE + 0x6C00}]
38 set PWR_BASE [expr {$APB1PERIPH_BASE + 0x7000}]
39 set DAC_BASE [expr {$APB1PERIPH_BASE + 0x7400}]
41 set AFIO_BASE [expr {$APB2PERIPH_BASE + 0x0000}]
42 set EXTI_BASE [expr {$APB2PERIPH_BASE + 0x0400}]
43 set GPIOA_BASE [expr {$APB2PERIPH_BASE + 0x0800}]
44 set GPIOB_BASE [expr {$APB2PERIPH_BASE + 0x0C00}]
45 set GPIOC_BASE [expr {$APB2PERIPH_BASE + 0x1000}]
46 set GPIOD_BASE [expr {$APB2PERIPH_BASE + 0x1400}]
47 set GPIOE_BASE [expr {$APB2PERIPH_BASE + 0x1800}]
48 set GPIOF_BASE [expr {$APB2PERIPH_BASE + 0x1C00}]
49 set GPIOG_BASE [expr {$APB2PERIPH_BASE + 0x2000}]
50 set ADC1_BASE [expr {$APB2PERIPH_BASE + 0x2400}]
51 set ADC2_BASE [expr {$APB2PERIPH_BASE + 0x2800}]
52 set TIM1_BASE [expr {$APB2PERIPH_BASE + 0x2C00}]
53 set SPI1_BASE [expr {$APB2PERIPH_BASE + 0x3000}]
54 set TIM8_BASE [expr {$APB2PERIPH_BASE + 0x3400}]
55 set USART1_BASE [expr {$APB2PERIPH_BASE + 0x3800}]
56 set ADC3_BASE [expr {$APB2PERIPH_BASE + 0x3C00}]
58 set SDIO_BASE [expr {$PERIPH_BASE + 0x18000}]
60 set DMA1_BASE [expr {$AHBPERIPH_BASE + 0x0000}]
61 set DMA1_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0008}]
62 set DMA1_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x001C}]
63 set DMA1_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0030}]
64 set DMA1_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0044}]
65 set DMA1_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0058}]
66 set DMA1_Channel6_BASE [expr {$AHBPERIPH_BASE + 0x006C}]
67 set DMA1_Channel7_BASE [expr {$AHBPERIPH_BASE + 0x0080}]
68 set DMA2_BASE [expr {$AHBPERIPH_BASE + 0x0400}]
69 set DMA2_Channel1_BASE [expr {$AHBPERIPH_BASE + 0x0408}]
70 set DMA2_Channel2_BASE [expr {$AHBPERIPH_BASE + 0x041C}]
71 set DMA2_Channel3_BASE [expr {$AHBPERIPH_BASE + 0x0430}]
72 set DMA2_Channel4_BASE [expr {$AHBPERIPH_BASE + 0x0444}]
73 set DMA2_Channel5_BASE [expr {$AHBPERIPH_BASE + 0x0458}]
74 set RCC_BASE [expr {$AHBPERIPH_BASE + 0x1000}]
75 set CRC_BASE [expr {$AHBPERIPH_BASE + 0x3000}]
77 # /*Flash registers base address */
78 set FLASH_R_BASE [expr {$AHBPERIPH_BASE + 0x2000}]
79 # /*Flash Option Bytes base address */
80 set OB_BASE 0x1FFFF800
82 # /*FSMC Bankx registers base address */
83 set FSMC_Bank1_R_BASE [expr {$FSMC_R_BASE + 0x0000}]
84 set FSMC_Bank1E_R_BASE [expr {$FSMC_R_BASE + 0x0104}]
85 set FSMC_Bank2_R_BASE [expr {$FSMC_R_BASE + 0x0060}]
86 set FSMC_Bank3_R_BASE [expr {$FSMC_R_BASE + 0x0080}]
87 set FSMC_Bank4_R_BASE [expr {$FSMC_R_BASE + 0x00A0}]
89 # /*Debug MCU registers base address */
90 set DBGMCU_BASE 0xE0042000
92 # /*System Control Space memory map */
93 set SCS_BASE 0xE000E000
95 set SysTick_BASE [expr {$SCS_BASE + 0x0010}]
96 set NVIC_BASE [expr {$SCS_BASE + 0x0100}]
97 set SCB_BASE [expr {$SCS_BASE + 0x0D00}]