1 # SPDX-License-Identifier: GPL-2.0-or-later
3 set AT91_MATRIX_MCFG0 [expr {$AT91_MATRIX + 0x00}] ;# Master Configuration Register 0
4 set AT91_MATRIX_MCFG1 [expr {$AT91_MATRIX + 0x04}] ;# Master Configuration Register 1
5 set AT91_MATRIX_MCFG2 [expr {$AT91_MATRIX + 0x08}] ;# Master Configuration Register 2
6 set AT91_MATRIX_MCFG3 [expr {$AT91_MATRIX + 0x0C}] ;# Master Configuration Register 3
7 set AT91_MATRIX_MCFG4 [expr {$AT91_MATRIX + 0x10}] ;# Master Configuration Register 4
8 set AT91_MATRIX_MCFG5 [expr {$AT91_MATRIX + 0x14}] ;# Master Configuration Register 5
9 set AT91_MATRIX_MCFG6 [expr {$AT91_MATRIX + 0x18}] ;# Master Configuration Register 6
10 set AT91_MATRIX_MCFG7 [expr {$AT91_MATRIX + 0x1C}] ;# Master Configuration Register 7
11 set AT91_MATRIX_MCFG8 [expr {$AT91_MATRIX + 0x20}] ;# Master Configuration Register 8
12 set AT91_MATRIX_ULBT [expr {7 << 0}] ;# Undefined Length Burst Type
13 set AT91_MATRIX_ULBT_INFINITE [expr {0 << 0}]
14 set AT91_MATRIX_ULBT_SINGLE [expr {1 << 0}]
15 set AT91_MATRIX_ULBT_FOUR [expr {2 << 0}]
16 set AT91_MATRIX_ULBT_EIGHT [expr {3 << 0}]
17 set AT91_MATRIX_ULBT_SIXTEEN [expr {4 << 0}]
19 set AT91_MATRIX_SCFG0 [expr {$AT91_MATRIX + 0x40}] ;# Slave Configuration Register 0
20 set AT91_MATRIX_SCFG1 [expr {$AT91_MATRIX + 0x44}] ;# Slave Configuration Register 1
21 set AT91_MATRIX_SCFG2 [expr {$AT91_MATRIX + 0x48}] ;# Slave Configuration Register 2
22 set AT91_MATRIX_SCFG3 [expr {$AT91_MATRIX + 0x4C}] ;# Slave Configuration Register 3
23 set AT91_MATRIX_SCFG4 [expr {$AT91_MATRIX + 0x50}] ;# Slave Configuration Register 4
24 set AT91_MATRIX_SCFG5 [expr {$AT91_MATRIX + 0x54}] ;# Slave Configuration Register 5
25 set AT91_MATRIX_SCFG6 [expr {$AT91_MATRIX + 0x58}] ;# Slave Configuration Register 6
26 set AT91_MATRIX_SCFG7 [expr {$AT91_MATRIX + 0x5C}] ;# Slave Configuration Register 7
27 set AT91_MATRIX_SLOT_CYCLE [expr {0xff << 0}] ;# Maximum Number of Allowed Cycles for a Burst
28 set AT91_MATRIX_DEFMSTR_TYPE [expr {3 << 16}] ;# Default Master Type
29 set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr {0 << 16}]
30 set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr {1 << 16}]
31 set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr {2 << 16}]
32 set AT91_MATRIX_FIXED_DEFMSTR [expr {0xf << 18}] ;# Fixed Index of Default Master
33 set AT91_MATRIX_ARBT [expr {3 << 24}] ;# Arbitration Type
34 set AT91_MATRIX_ARBT_ROUND_ROBIN [expr {0 << 24}]
35 set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr {1 << 24}]
37 set AT91_MATRIX_PRAS0 [expr {$AT91_MATRIX + 0x80}] ;# Priority Register A for Slave 0
38 set AT91_MATRIX_PRBS0 [expr {$AT91_MATRIX + 0x84}] ;# Priority Register B for Slave 0
39 set AT91_MATRIX_PRAS1 [expr {$AT91_MATRIX + 0x88}] ;# Priority Register A for Slave 1
40 set AT91_MATRIX_PRBS1 [expr {$AT91_MATRIX + 0x8C}] ;# Priority Register B for Slave 1
41 set AT91_MATRIX_PRAS2 [expr {$AT91_MATRIX + 0x90}] ;# Priority Register A for Slave 2
42 set AT91_MATRIX_PRBS2 [expr {$AT91_MATRIX + 0x94}] ;# Priority Register B for Slave 2
43 set AT91_MATRIX_PRAS3 [expr {$AT91_MATRIX + 0x98}] ;# Priority Register A for Slave 3
44 set AT91_MATRIX_PRBS3 [expr {$AT91_MATRIX + 0x9C}] ;# Priority Register B for Slave 3
45 set AT91_MATRIX_PRAS4 [expr {$AT91_MATRIX + 0xA0}] ;# Priority Register A for Slave 4
46 set AT91_MATRIX_PRBS4 [expr {$AT91_MATRIX + 0xA4}] ;# Priority Register B for Slave 4
47 set AT91_MATRIX_PRAS5 [expr {$AT91_MATRIX + 0xA8}] ;# Priority Register A for Slave 5
48 set AT91_MATRIX_PRBS5 [expr {$AT91_MATRIX + 0xAC}] ;# Priority Register B for Slave 5
49 set AT91_MATRIX_PRAS6 [expr {$AT91_MATRIX + 0xB0}] ;# Priority Register A for Slave 6
50 set AT91_MATRIX_PRBS6 [expr {$AT91_MATRIX + 0xB4}] ;# Priority Register B for Slave 6
51 set AT91_MATRIX_PRAS7 [expr {$AT91_MATRIX + 0xB8}] ;# Priority Register A for Slave 7
52 set AT91_MATRIX_PRBS7 [expr {$AT91_MATRIX + 0xBC}] ;# Priority Register B for Slave 7
53 set AT91_MATRIX_M0PR [expr {3 << 0}] ;# Master 0 Priority
54 set AT91_MATRIX_M1PR [expr {3 << 4}] ;# Master 1 Priority
55 set AT91_MATRIX_M2PR [expr {3 << 8}] ;# Master 2 Priority
56 set AT91_MATRIX_M3PR [expr {3 << 12}] ;# Master 3 Priority
57 set AT91_MATRIX_M4PR [expr {3 << 16}] ;# Master 4 Priority
58 set AT91_MATRIX_M5PR [expr {3 << 20}] ;# Master 5 Priority
59 set AT91_MATRIX_M6PR [expr {3 << 24}] ;# Master 6 Priority
60 set AT91_MATRIX_M7PR [expr {3 << 28}] ;# Master 7 Priority
61 set AT91_MATRIX_M8PR [expr {3 << 0}] ;# Master 8 Priority (in Register B)
63 set AT91_MATRIX_MRCR [expr {$AT91_MATRIX + 0x100}] ;# Master Remap Control Register
64 set AT91_MATRIX_RCB0 [expr {1 << 0}] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
65 set AT91_MATRIX_RCB1 [expr {1 << 1}] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
66 set AT91_MATRIX_RCB2 [expr {1 << 2}]
67 set AT91_MATRIX_RCB3 [expr {1 << 3}]
68 set AT91_MATRIX_RCB4 [expr {1 << 4}]
69 set AT91_MATRIX_RCB5 [expr {1 << 5}]
70 set AT91_MATRIX_RCB6 [expr {1 << 6}]
71 set AT91_MATRIX_RCB7 [expr {1 << 7}]
72 set AT91_MATRIX_RCB8 [expr {1 << 8}]
74 set AT91_MATRIX_TCMR [expr {$AT91_MATRIX + 0x114}] ;# TCM Configuration Register
75 set AT91_MATRIX_ITCM_SIZE [expr {0xf << 0}] ;# Size of ITCM enabled memory block
76 set AT91_MATRIX_ITCM_0 [expr {0 << 0}]
77 set AT91_MATRIX_ITCM_16 [expr {5 << 0}]
78 set AT91_MATRIX_ITCM_32 [expr {6 << 0}]
79 set AT91_MATRIX_DTCM_SIZE [expr {0xf << 4}] ;# Size of DTCM enabled memory block
80 set AT91_MATRIX_DTCM_0 [expr {0 << 4}]
81 set AT91_MATRIX_DTCM_16 [expr {5 << 4}]
82 set AT91_MATRIX_DTCM_32 [expr {6 << 4}]
84 set AT91_MATRIX_EBI0CSA [expr {$AT91_MATRIX + 0x120}] ;# EBI0 Chip Select Assignment Register
85 set AT91_MATRIX_EBI0_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment
86 set AT91_MATRIX_EBI0_CS1A_SMC [expr {0 << 1}]
87 set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr {1 << 1}]
88 set AT91_MATRIX_EBI0_CS3A [expr {1 << 3}] ;# Chip Select 3 Assignmen
89 set AT91_MATRIX_EBI0_CS3A_SMC [expr {0 << 3}]
90 set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr {1 << 3}]
91 set AT91_MATRIX_EBI0_CS4A [expr {1 << 4}] ;# Chip Select 4 Assignment
92 set AT91_MATRIX_EBI0_CS4A_SMC [expr {0 << 4}]
93 set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr {1 << 4}]
94 set AT91_MATRIX_EBI0_CS5A [expr {1 << 5}] ;# Chip Select 5 Assignment
95 set AT91_MATRIX_EBI0_CS5A_SMC [expr {0 << 5}]
96 set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr {1 << 5}]
97 set AT91_MATRIX_EBI0_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration
98 set AT91_MATRIX_EBI0_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection
99 set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr {0 << 16}]
100 set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr {1 << 16}]
102 set AT91_MATRIX_EBI1CSA [expr {$AT91_MATRIX + 0x124}] ;# EBI1 Chip Select Assignment Register
103 set AT91_MATRIX_EBI1_CS1A [expr {1 << 1}] ;# Chip Select 1 Assignment
104 set AT91_MATRIX_EBI1_CS1A_SMC [expr {0 << 1}]
105 set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr {1 << 1}]
106 set AT91_MATRIX_EBI1_CS2A [expr {1 << 3}] ;# Chip Select 3 Assignment
107 set AT91_MATRIX_EBI1_CS2A_SMC [expr {0 << 3}]
108 set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr {1 << 3}]
109 set AT91_MATRIX_EBI1_DBPUC [expr {1 << 8}] ;# Data Bus Pull-up Configuration
110 set AT91_MATRIX_EBI1_VDDIOMSEL [expr {1 << 16}] ;# Memory voltage selection
111 set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr {0 << 16}]
112 set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr {1 << 16}]
projects / fw / openocd / blob