1 /***************************************************************************
2 * Generic Xtensa target API for OpenOCD *
3 * Copyright (C) 2016-2019 Espressif Systems Ltd. *
4 * Author: Angus Gratton gus@projectgus.com *
5 * Author: Jeroen Domburg <jeroen@espressif.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20 #ifndef OPENOCD_TARGET_XTENSA_REGS_H
21 #define OPENOCD_TARGET_XTENSA_REGS_H
95 XT_REG_IDX_WINDOWBASE,
96 XT_REG_IDX_WINDOWSTART,
100 XT_REG_IDX_THREADPTR,
102 XT_REG_IDX_SCOMPARE1,
128 XT_REG_IDX_IBREAKENABLE,
159 XT_REG_IDX_INTERRUPT,
162 XT_REG_IDX_INTENABLE,
165 XT_REG_IDX_DEBUGCAUSE,
169 XT_REG_IDX_ICOUNTLEVEL,
171 XT_REG_IDX_CCOMPARE0,
172 XT_REG_IDX_CCOMPARE1,
173 XT_REG_IDX_CCOMPARE2,
208 XT_REG_IDX_CS_ITCTRL,
209 XT_REG_IDX_CS_CLAIMSET,
210 XT_REG_IDX_CS_CLAIMCLR,
211 XT_REG_IDX_CS_LOCKACCESS,
212 XT_REG_IDX_CS_LOCKSTATUS,
213 XT_REG_IDX_CS_AUTHSTATUS,
214 XT_REG_IDX_FAULT_INFO,
216 XT_REG_IDX_TRAX_CTRL,
217 XT_REG_IDX_TRAX_STAT,
218 XT_REG_IDX_TRAX_DATA,
219 XT_REG_IDX_TRAX_ADDR,
220 XT_REG_IDX_TRAX_PCTRIGGER,
221 XT_REG_IDX_TRAX_PCMATCH,
222 XT_REG_IDX_TRAX_DELAY,
223 XT_REG_IDX_TRAX_MEMSTART,
224 XT_REG_IDX_TRAX_MEMEND,
234 XT_REG_IDX_OCD_DCRCLR,
235 XT_REG_IDX_OCD_DCRSET,
239 /* chip-specific user registers go after ISA-defined ones */
240 XT_USR_REG_START = XT_NUM_REGS
243 typedef uint32_t xtensa_reg_val_t;
245 enum xtensa_reg_type {
246 XT_REG_GENERAL = 0, /* General-purpose register; part of the windowed register set */
247 XT_REG_USER = 1, /* User register, needs RUR to read */
248 XT_REG_SPECIAL = 2, /* Special register, needs RSR to read */
249 XT_REG_DEBUG = 3, /* Register used for the debug interface. Don't mess with this. */
250 XT_REG_RELGEN = 4, /* Relative general address. Points to the absolute addresses plus the window
252 XT_REG_FR = 5, /* Floating-point register */
255 enum xtensa_reg_flags {
256 XT_REGF_NOREAD = 0x01, /* Register is write-only */
257 XT_REGF_COPROC0 = 0x02 /* Can't be read if coproc0 isn't enabled */
260 struct xtensa_reg_desc {
262 unsigned int reg_num; /* ISA register num (meaning depends on register type) */
263 enum xtensa_reg_type type;
264 enum xtensa_reg_flags flags;
267 struct xtensa_user_reg_desc {
269 /* ISA register num (meaning depends on register type) */
270 unsigned int reg_num;
271 enum xtensa_reg_flags flags;
273 const struct reg_arch_type *type;
276 extern const struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS];
278 #endif /* OPENOCD_TARGET_XTENSA_REGS_H */