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   1 /***************************************************************************
   2  *   Copyright (C) 2006, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2009 Michael Schwingen                                  *
   9  *   michael@schwingen.org                                                 *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  25  ***************************************************************************/
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "breakpoints.h"
  32 #include "xscale.h"
  33 #include "target_type.h"
  34 #include "arm_jtag.h"
  35 #include "arm_simulator.h"
  36 #include "arm_disassembler.h"
  37 #include <helper/time_support.h>
  38 #include "register.h"
  39 #include "image.h"
  40 #include "arm_opcodes.h"
  41 #include "armv4_5.h"
  42
  43 /*
  44  * Important XScale documents available as of October 2009 include:
  45  *
  46  *  Intel XScale® Core Developer’s Manual, January 2004
  47  *              Order Number: 273473-002
  48  *      This has a chapter detailing debug facilities, and punts some
  49  *      details to chip-specific microarchitecture documents.
  50  *
  51  *  Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
  52  *              Document Number: 273539-005
  53  *      Less detailed than the developer's manual, but summarizes those
  54  *      missing details (for most XScales) and gives LOTS of notes about
  55  *      debugger/handler interaction issues.  Presents a simpler reset
  56  *      and load-handler sequence than the arch doc.  (Note, OpenOCD
  57  *      doesn't currently support "Hot-Debug" as defined there.)
  58  *
  59  * Chip-specific microarchitecture documents may also be useful.
  60  */
  61
  62 /* forward declarations */
  63 static int xscale_resume(struct target *, int current,
  64         uint32_t address, int handle_breakpoints, int debug_execution);
  65 static int xscale_debug_entry(struct target *);
  66 static int xscale_restore_banked(struct target *);
  67 static int xscale_get_reg(struct reg *reg);
  68 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
  69 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
  70 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
  71 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
  72 static int xscale_read_trace(struct target *);
  73
  74 /* This XScale "debug handler" is loaded into the processor's
  75  * mini-ICache, which is 2K of code writable only via JTAG.
  76  *
  77  * FIXME  the OpenOCD "bin2char" utility currently doesn't handle
  78  * binary files cleanly.  It's string oriented, and terminates them
  79  * with a NUL character.  Better would be to generate the constants
  80  * and let other code decide names, scoping, and other housekeeping.
  81  */
  82 static  /* unsigned const char xscale_debug_handler[] = ... */
  83 #include "xscale_debug.h"
  84
  85 static char *const xscale_reg_list[] = {
  86         "XSCALE_MAINID",                /* 0 */
  87         "XSCALE_CACHETYPE",
  88         "XSCALE_CTRL",
  89         "XSCALE_AUXCTRL",
  90         "XSCALE_TTB",
  91         "XSCALE_DAC",
  92         "XSCALE_FSR",
  93         "XSCALE_FAR",
  94         "XSCALE_PID",
  95         "XSCALE_CPACCESS",
  96         "XSCALE_IBCR0",                 /* 10 */
  97         "XSCALE_IBCR1",
  98         "XSCALE_DBR0",
  99         "XSCALE_DBR1",
 100         "XSCALE_DBCON",
 101         "XSCALE_TBREG",
 102         "XSCALE_CHKPT0",
 103         "XSCALE_CHKPT1",
 104         "XSCALE_DCSR",
 105         "XSCALE_TX",
 106         "XSCALE_RX",                    /* 20 */
 107         "XSCALE_TXRXCTRL",
 108 };
 109
 110 static const struct xscale_reg xscale_reg_arch_info[] = {
 111         {XSCALE_MAINID, NULL},
 112         {XSCALE_CACHETYPE, NULL},
 113         {XSCALE_CTRL, NULL},
 114         {XSCALE_AUXCTRL, NULL},
 115         {XSCALE_TTB, NULL},
 116         {XSCALE_DAC, NULL},
 117         {XSCALE_FSR, NULL},
 118         {XSCALE_FAR, NULL},
 119         {XSCALE_PID, NULL},
 120         {XSCALE_CPACCESS, NULL},
 121         {XSCALE_IBCR0, NULL},
 122         {XSCALE_IBCR1, NULL},
 123         {XSCALE_DBR0, NULL},
 124         {XSCALE_DBR1, NULL},
 125         {XSCALE_DBCON, NULL},
 126         {XSCALE_TBREG, NULL},
 127         {XSCALE_CHKPT0, NULL},
 128         {XSCALE_CHKPT1, NULL},
 129         {XSCALE_DCSR, NULL},    /* DCSR accessed via JTAG or SW */
 130         {-1, NULL},     /* TX accessed via JTAG */
 131         {-1, NULL},     /* RX accessed via JTAG */
 132         {-1, NULL},     /* TXRXCTRL implicit access via JTAG */
 133 };
 134
 135 /* convenience wrapper to access XScale specific registers */
 136 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 137 {
 138         uint8_t buf[4];
 139
 140         buf_set_u32(buf, 0, 32, value);
 141
 142         return xscale_set_reg(reg, buf);
 143 }
 144
 145 static const char xscale_not[] = "target is not an XScale";
 146
 147 static int xscale_verify_pointer(struct command_context *cmd_ctx,
 148         struct xscale_common *xscale)
 149 {
 150         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
 151                 command_print(cmd_ctx, xscale_not);
 152                 return ERROR_TARGET_INVALID;
 153         }
 154         return ERROR_OK;
 155 }
 156
 157 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
 158 {
 159         assert(tap != NULL);
 160
 161         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
 162                 struct scan_field field;
 163                 uint8_t scratch[4];
 164
 165                 memset(&field, 0, sizeof field);
 166                 field.num_bits = tap->ir_length;
 167                 field.out_value = scratch;
 168                 buf_set_u32(scratch, 0, field.num_bits, new_instr);
 169
 170                 jtag_add_ir_scan(tap, &field, end_state);
 171         }
 172
 173         return ERROR_OK;
 174 }
 175
 176 static int xscale_read_dcsr(struct target *target)
 177 {
 178         struct xscale_common *xscale = target_to_xscale(target);
 179         int retval;
 180         struct scan_field fields[3];
 181         uint8_t field0 = 0x0;
 182         uint8_t field0_check_value = 0x2;
 183         uint8_t field0_check_mask = 0x7;
 184         uint8_t field2 = 0x0;
 185         uint8_t field2_check_value = 0x0;
 186         uint8_t field2_check_mask = 0x1;
 187
 188         xscale_jtag_set_instr(target->tap,
 189                 XSCALE_SELDCSR << xscale->xscale_variant,
 190                 TAP_DRPAUSE);
 191
 192         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 193         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 194
 195         memset(&fields, 0, sizeof fields);
 196
 197         fields[0].num_bits = 3;
 198         fields[0].out_value = &field0;
 199         uint8_t tmp;
 200         fields[0].in_value = &tmp;
 201
 202         fields[1].num_bits = 32;
 203         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 204
 205         fields[2].num_bits = 1;
 206         fields[2].out_value = &field2;
 207         uint8_t tmp2;
 208         fields[2].in_value = &tmp2;
 209
 210         jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 211
 212         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 213         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 214
 215         retval = jtag_execute_queue();
 216         if (retval != ERROR_OK) {
 217                 LOG_ERROR("JTAG error while reading DCSR");
 218                 return retval;
 219         }
 220
 221         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
 222         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
 223
 224         /* write the register with the value we just read
 225          * on this second pass, only the first bit of field0 is guaranteed to be 0)
 226          */
 227         field0_check_mask = 0x1;
 228         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 229         fields[1].in_value = NULL;
 230
 231         jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 232
 233         /* DANGER!!! this must be here. It will make sure that the arguments
 234          * to jtag_set_check_value() does not go out of scope! */
 235         return jtag_execute_queue();
 236 }
 237
 238
 239 static void xscale_getbuf(jtag_callback_data_t arg)
 240 {
 241         uint8_t *in = (uint8_t *)arg;
 242         *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
 243 }
 244
 245 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
 246 {
 247         if (num_words == 0)
 248                 return ERROR_COMMAND_SYNTAX_ERROR;
 249
 250         struct xscale_common *xscale = target_to_xscale(target);
 251         int retval = ERROR_OK;
 252         tap_state_t path[3];
 253         struct scan_field fields[3];
 254         uint8_t *field0 = malloc(num_words * 1);
 255         uint8_t field0_check_value = 0x2;
 256         uint8_t field0_check_mask = 0x6;
 257         uint32_t *field1 = malloc(num_words * 4);
 258         uint8_t field2_check_value = 0x0;
 259         uint8_t field2_check_mask = 0x1;
 260         int words_done = 0;
 261         int words_scheduled = 0;
 262         int i;
 263
 264         path[0] = TAP_DRSELECT;
 265         path[1] = TAP_DRCAPTURE;
 266         path[2] = TAP_DRSHIFT;
 267
 268         memset(&fields, 0, sizeof fields);
 269
 270         fields[0].num_bits = 3;
 271         uint8_t tmp;
 272         fields[0].in_value = &tmp;
 273         fields[0].check_value = &field0_check_value;
 274         fields[0].check_mask = &field0_check_mask;
 275
 276         fields[1].num_bits = 32;
 277
 278         fields[2].num_bits = 1;
 279         uint8_t tmp2;
 280         fields[2].in_value = &tmp2;
 281         fields[2].check_value = &field2_check_value;
 282         fields[2].check_mask = &field2_check_mask;
 283
 284         xscale_jtag_set_instr(target->tap,
 285                 XSCALE_DBGTX << xscale->xscale_variant,
 286                 TAP_IDLE);
 287         jtag_add_runtest(1, TAP_IDLE);  /* ensures that we're in the TAP_IDLE state as the above
 288                                          *could be a no-op */
 289
 290         /* repeat until all words have been collected */
 291         int attempts = 0;
 292         while (words_done < num_words) {
 293                 /* schedule reads */
 294                 words_scheduled = 0;
 295                 for (i = words_done; i < num_words; i++) {
 296                         fields[0].in_value = &field0[i];
 297
 298                         jtag_add_pathmove(3, path);
 299
 300                         fields[1].in_value = (uint8_t *)(field1 + i);
 301
 302                         jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
 303
 304                         jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
 305
 306                         words_scheduled++;
 307                 }
 308
 309                 retval = jtag_execute_queue();
 310                 if (retval != ERROR_OK) {
 311                         LOG_ERROR("JTAG error while receiving data from debug handler");
 312                         break;
 313                 }
 314
 315                 /* examine results */
 316                 for (i = words_done; i < num_words; i++) {
 317                         if (!(field0[i] & 1)) {
 318                                 /* move backwards if necessary */
 319                                 int j;
 320                                 for (j = i; j < num_words - 1; j++) {
 321                                         field0[j] = field0[j + 1];
 322                                         field1[j] = field1[j + 1];
 323                                 }
 324                                 words_scheduled--;
 325                         }
 326                 }
 327                 if (words_scheduled == 0) {
 328                         if (attempts++ == 1000) {
 329                                 LOG_ERROR(
 330                                         "Failed to receiving data from debug handler after 1000 attempts");
 331                                 retval = ERROR_TARGET_TIMEOUT;
 332                                 break;
 333                         }
 334                 }
 335
 336                 words_done += words_scheduled;
 337         }
 338
 339         for (i = 0; i < num_words; i++)
 340                 *(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32);
 341
 342         free(field1);
 343
 344         return retval;
 345 }
 346
 347 static int xscale_read_tx(struct target *target, int consume)
 348 {
 349         struct xscale_common *xscale = target_to_xscale(target);
 350         tap_state_t path[3];
 351         tap_state_t noconsume_path[6];
 352         int retval;
 353         struct timeval timeout, now;
 354         struct scan_field fields[3];
 355         uint8_t field0_in = 0x0;
 356         uint8_t field0_check_value = 0x2;
 357         uint8_t field0_check_mask = 0x6;
 358         uint8_t field2_check_value = 0x0;
 359         uint8_t field2_check_mask = 0x1;
 360
 361         xscale_jtag_set_instr(target->tap,
 362                 XSCALE_DBGTX << xscale->xscale_variant,
 363                 TAP_IDLE);
 364
 365         path[0] = TAP_DRSELECT;
 366         path[1] = TAP_DRCAPTURE;
 367         path[2] = TAP_DRSHIFT;
 368
 369         noconsume_path[0] = TAP_DRSELECT;
 370         noconsume_path[1] = TAP_DRCAPTURE;
 371         noconsume_path[2] = TAP_DREXIT1;
 372         noconsume_path[3] = TAP_DRPAUSE;
 373         noconsume_path[4] = TAP_DREXIT2;
 374         noconsume_path[5] = TAP_DRSHIFT;
 375
 376         memset(&fields, 0, sizeof fields);
 377
 378         fields[0].num_bits = 3;
 379         fields[0].in_value = &field0_in;
 380
 381         fields[1].num_bits = 32;
 382         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 383
 384         fields[2].num_bits = 1;
 385         uint8_t tmp;
 386         fields[2].in_value = &tmp;
 387
 388         gettimeofday(&timeout, NULL);
 389         timeval_add_time(&timeout, 1, 0);
 390
 391         for (;; ) {
 392                 /* if we want to consume the register content (i.e. clear TX_READY),
 393                  * we have to go straight from Capture-DR to Shift-DR
 394                  * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
 395                 */
 396                 if (consume)
 397                         jtag_add_pathmove(3, path);
 398                 else
 399                         jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
 400
 401                 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 402
 403                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 404                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 405
 406                 retval = jtag_execute_queue();
 407                 if (retval != ERROR_OK) {
 408                         LOG_ERROR("JTAG error while reading TX");
 409                         return ERROR_TARGET_TIMEOUT;
 410                 }
 411
 412                 gettimeofday(&now, NULL);
 413                 if ((now.tv_sec > timeout.tv_sec) ||
 414                         ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
 415                         LOG_ERROR("time out reading TX register");
 416                         return ERROR_TARGET_TIMEOUT;
 417                 }
 418                 if (!((!(field0_in & 1)) && consume))
 419                         goto done;
 420                 if (debug_level >= 3) {
 421                         LOG_DEBUG("waiting 100ms");
 422                         alive_sleep(100);       /* avoid flooding the logs */
 423                 } else
 424                         keep_alive();
 425         }
 426 done:
 427
 428         if (!(field0_in & 1))
 429                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 430
 431         return ERROR_OK;
 432 }
 433
 434 static int xscale_write_rx(struct target *target)
 435 {
 436         struct xscale_common *xscale = target_to_xscale(target);
 437         int retval;
 438         struct timeval timeout, now;
 439         struct scan_field fields[3];
 440         uint8_t field0_out = 0x0;
 441         uint8_t field0_in = 0x0;
 442         uint8_t field0_check_value = 0x2;
 443         uint8_t field0_check_mask = 0x6;
 444         uint8_t field2 = 0x0;
 445         uint8_t field2_check_value = 0x0;
 446         uint8_t field2_check_mask = 0x1;
 447
 448         xscale_jtag_set_instr(target->tap,
 449                 XSCALE_DBGRX << xscale->xscale_variant,
 450                 TAP_IDLE);
 451
 452         memset(&fields, 0, sizeof fields);
 453
 454         fields[0].num_bits = 3;
 455         fields[0].out_value = &field0_out;
 456         fields[0].in_value = &field0_in;
 457
 458         fields[1].num_bits = 32;
 459         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 460
 461         fields[2].num_bits = 1;
 462         fields[2].out_value = &field2;
 463         uint8_t tmp;
 464         fields[2].in_value = &tmp;
 465
 466         gettimeofday(&timeout, NULL);
 467         timeval_add_time(&timeout, 1, 0);
 468
 469         /* poll until rx_read is low */
 470         LOG_DEBUG("polling RX");
 471         for (;;) {
 472                 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 473
 474                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 475                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 476
 477                 retval = jtag_execute_queue();
 478                 if (retval != ERROR_OK) {
 479                         LOG_ERROR("JTAG error while writing RX");
 480                         return retval;
 481                 }
 482
 483                 gettimeofday(&now, NULL);
 484                 if ((now.tv_sec > timeout.tv_sec) ||
 485                         ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
 486                         LOG_ERROR("time out writing RX register");
 487                         return ERROR_TARGET_TIMEOUT;
 488                 }
 489                 if (!(field0_in & 1))
 490                         goto done;
 491                 if (debug_level >= 3) {
 492                         LOG_DEBUG("waiting 100ms");
 493                         alive_sleep(100);       /* avoid flooding the logs */
 494                 } else
 495                         keep_alive();
 496         }
 497 done:
 498
 499         /* set rx_valid */
 500         field2 = 0x1;
 501         jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 502
 503         retval = jtag_execute_queue();
 504         if (retval != ERROR_OK) {
 505                 LOG_ERROR("JTAG error while writing RX");
 506                 return retval;
 507         }
 508
 509         return ERROR_OK;
 510 }
 511
 512 /* send count elements of size byte to the debug handler */
 513 static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
 514 {
 515         struct xscale_common *xscale = target_to_xscale(target);
 516         int retval;
 517         int done_count = 0;
 518
 519         xscale_jtag_set_instr(target->tap,
 520                 XSCALE_DBGRX << xscale->xscale_variant,
 521                 TAP_IDLE);
 522
 523         static const uint8_t t0;
 524         uint8_t t1[4];
 525         static const uint8_t t2 = 1;
 526         struct scan_field fields[3] = {
 527                         { .num_bits = 3, .out_value = &t0 },
 528                         { .num_bits = 32, .out_value = t1 },
 529                         { .num_bits = 1, .out_value = &t2 },
 530         };
 531
 532         int endianness = target->endianness;
 533         while (done_count++ < count) {
 534                 uint32_t t;
 535
 536                 switch (size) {
 537                         case 4:
 538                                 if (endianness == TARGET_LITTLE_ENDIAN)
 539                                         t = le_to_h_u32(buffer);
 540                                 else
 541                                         t = be_to_h_u32(buffer);
 542                                 break;
 543                         case 2:
 544                                 if (endianness == TARGET_LITTLE_ENDIAN)
 545                                         t = le_to_h_u16(buffer);
 546                                 else
 547                                         t = be_to_h_u16(buffer);
 548                                 break;
 549                         case 1:
 550                                 t = buffer[0];
 551                                 break;
 552                         default:
 553                                 LOG_ERROR("BUG: size neither 4, 2 nor 1");
 554                                 return ERROR_COMMAND_SYNTAX_ERROR;
 555                 }
 556
 557                 buf_set_u32(t1, 0, 32, t);
 558
 559                 jtag_add_dr_scan(target->tap,
 560                         3,
 561                         fields,
 562                         TAP_IDLE);
 563                 buffer += size;
 564         }
 565
 566         retval = jtag_execute_queue();
 567         if (retval != ERROR_OK) {
 568                 LOG_ERROR("JTAG error while sending data to debug handler");
 569                 return retval;
 570         }
 571
 572         return ERROR_OK;
 573 }
 574
 575 static int xscale_send_u32(struct target *target, uint32_t value)
 576 {
 577         struct xscale_common *xscale = target_to_xscale(target);
 578
 579         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
 580         return xscale_write_rx(target);
 581 }
 582
 583 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
 584 {
 585         struct xscale_common *xscale = target_to_xscale(target);
 586         int retval;
 587         struct scan_field fields[3];
 588         uint8_t field0 = 0x0;
 589         uint8_t field0_check_value = 0x2;
 590         uint8_t field0_check_mask = 0x7;
 591         uint8_t field2 = 0x0;
 592         uint8_t field2_check_value = 0x0;
 593         uint8_t field2_check_mask = 0x1;
 594
 595         if (hold_rst != -1)
 596                 xscale->hold_rst = hold_rst;
 597
 598         if (ext_dbg_brk != -1)
 599                 xscale->external_debug_break = ext_dbg_brk;
 600
 601         xscale_jtag_set_instr(target->tap,
 602                 XSCALE_SELDCSR << xscale->xscale_variant,
 603                 TAP_IDLE);
 604
 605         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 606         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 607
 608         memset(&fields, 0, sizeof fields);
 609
 610         fields[0].num_bits = 3;
 611         fields[0].out_value = &field0;
 612         uint8_t tmp;
 613         fields[0].in_value = &tmp;
 614
 615         fields[1].num_bits = 32;
 616         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 617
 618         fields[2].num_bits = 1;
 619         fields[2].out_value = &field2;
 620         uint8_t tmp2;
 621         fields[2].in_value = &tmp2;
 622
 623         jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 624
 625         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 626         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 627
 628         retval = jtag_execute_queue();
 629         if (retval != ERROR_OK) {
 630                 LOG_ERROR("JTAG error while writing DCSR");
 631                 return retval;
 632         }
 633
 634         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = 0;
 635         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = 1;
 636
 637         return ERROR_OK;
 638 }
 639
 640 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
 641 static unsigned int parity(unsigned int v)
 642 {
 643         /* unsigned int ov = v; */
 644         v ^= v >> 16;
 645         v ^= v >> 8;
 646         v ^= v >> 4;
 647         v &= 0xf;
 648         /* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */
 649         return (0x6996 >> v) & 1;
 650 }
 651
 652 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
 653 {
 654         struct xscale_common *xscale = target_to_xscale(target);
 655         uint8_t packet[4];
 656         uint8_t cmd;
 657         int word;
 658         struct scan_field fields[2];
 659
 660         LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 661
 662         /* LDIC into IR */
 663         xscale_jtag_set_instr(target->tap,
 664                 XSCALE_LDIC << xscale->xscale_variant,
 665                 TAP_IDLE);
 666
 667         /* CMD is b011 to load a cacheline into the Mini ICache.
 668          * Loading into the main ICache is deprecated, and unused.
 669          * It's followed by three zero bits, and 27 address bits.
 670          */
 671         buf_set_u32(&cmd, 0, 6, 0x3);
 672
 673         /* virtual address of desired cache line */
 674         buf_set_u32(packet, 0, 27, va >> 5);
 675
 676         memset(&fields, 0, sizeof fields);
 677
 678         fields[0].num_bits = 6;
 679         fields[0].out_value = &cmd;
 680
 681         fields[1].num_bits = 27;
 682         fields[1].out_value = packet;
 683
 684         jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 685
 686         /* rest of packet is a cacheline: 8 instructions, with parity */
 687         fields[0].num_bits = 32;
 688         fields[0].out_value = packet;
 689
 690         fields[1].num_bits = 1;
 691         fields[1].out_value = &cmd;
 692
 693         for (word = 0; word < 8; word++) {
 694                 buf_set_u32(packet, 0, 32, buffer[word]);
 695
 696                 uint32_t value;
 697                 memcpy(&value, packet, sizeof(uint32_t));
 698                 cmd = parity(value);
 699
 700                 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 701         }
 702
 703         return jtag_execute_queue();
 704 }
 705
 706 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 707 {
 708         struct xscale_common *xscale = target_to_xscale(target);
 709         uint8_t packet[4];
 710         uint8_t cmd;
 711         struct scan_field fields[2];
 712
 713         xscale_jtag_set_instr(target->tap,
 714                 XSCALE_LDIC << xscale->xscale_variant,
 715                 TAP_IDLE);
 716
 717         /* CMD for invalidate IC line b000, bits [6:4] b000 */
 718         buf_set_u32(&cmd, 0, 6, 0x0);
 719
 720         /* virtual address of desired cache line */
 721         buf_set_u32(packet, 0, 27, va >> 5);
 722
 723         memset(&fields, 0, sizeof fields);
 724
 725         fields[0].num_bits = 6;
 726         fields[0].out_value = &cmd;
 727
 728         fields[1].num_bits = 27;
 729         fields[1].out_value = packet;
 730
 731         jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 732
 733         return ERROR_OK;
 734 }
 735
 736 static int xscale_update_vectors(struct target *target)
 737 {
 738         struct xscale_common *xscale = target_to_xscale(target);
 739         int i;
 740         int retval;
 741
 742         uint32_t low_reset_branch, high_reset_branch;
 743
 744         for (i = 1; i < 8; i++) {
 745                 /* if there's a static vector specified for this exception, override */
 746                 if (xscale->static_high_vectors_set & (1 << i))
 747                         xscale->high_vectors[i] = xscale->static_high_vectors[i];
 748                 else {
 749                         retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
 750                         if (retval == ERROR_TARGET_TIMEOUT)
 751                                 return retval;
 752                         if (retval != ERROR_OK) {
 753                                 /* Some of these reads will fail as part of normal execution */
 754                                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 755                         }
 756                 }
 757         }
 758
 759         for (i = 1; i < 8; i++) {
 760                 if (xscale->static_low_vectors_set & (1 << i))
 761                         xscale->low_vectors[i] = xscale->static_low_vectors[i];
 762                 else {
 763                         retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
 764                         if (retval == ERROR_TARGET_TIMEOUT)
 765                                 return retval;
 766                         if (retval != ERROR_OK) {
 767                                 /* Some of these reads will fail as part of normal execution */
 768                                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 769                         }
 770                 }
 771         }
 772
 773         /* calculate branches to debug handler */
 774         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
 775         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
 776
 777         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
 778         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
 779
 780         /* invalidate and load exception vectors in mini i-cache */
 781         xscale_invalidate_ic_line(target, 0x0);
 782         xscale_invalidate_ic_line(target, 0xffff0000);
 783
 784         xscale_load_ic(target, 0x0, xscale->low_vectors);
 785         xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
 786
 787         return ERROR_OK;
 788 }
 789
 790 static int xscale_arch_state(struct target *target)
 791 {
 792         struct xscale_common *xscale = target_to_xscale(target);
 793         struct arm *arm = &xscale->arm;
 794
 795         static const char *state[] = {
 796                 "disabled", "enabled"
 797         };
 798
 799         static const char *arch_dbg_reason[] = {
 800                 "", "\n(processor reset)", "\n(trace buffer full)"
 801         };
 802
 803         if (arm->common_magic != ARM_COMMON_MAGIC) {
 804                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 805                 return ERROR_COMMAND_SYNTAX_ERROR;
 806         }
 807
 808         arm_arch_state(target);
 809         LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 810                 state[xscale->armv4_5_mmu.mmu_enabled],
 811                 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 812                 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
 813                 arch_dbg_reason[xscale->arch_debug_reason]);
 814
 815         return ERROR_OK;
 816 }
 817
 818 static int xscale_poll(struct target *target)
 819 {
 820         int retval = ERROR_OK;
 821
 822         if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) {
 823                 enum target_state previous_state = target->state;
 824                 retval = xscale_read_tx(target, 0);
 825                 if (retval == ERROR_OK) {
 826
 827                         /* there's data to read from the tx register, we entered debug state */
 828                         target->state = TARGET_HALTED;
 829
 830                         /* process debug entry, fetching current mode regs */
 831                         retval = xscale_debug_entry(target);
 832                 } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 833                         LOG_USER("error while polling TX register, reset CPU");
 834                         /* here we "lie" so GDB won't get stuck and a reset can be perfomed */
 835                         target->state = TARGET_HALTED;
 836                 }
 837
 838                 /* debug_entry could have overwritten target state (i.e. immediate resume)
 839                  * don't signal event handlers in that case
 840                  */
 841                 if (target->state != TARGET_HALTED)
 842                         return ERROR_OK;
 843
 844                 /* if target was running, signal that we halted
 845                  * otherwise we reentered from debug execution */
 846                 if (previous_state == TARGET_RUNNING)
 847                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 848                 else
 849                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 850         }
 851
 852         return retval;
 853 }
 854
 855 static int xscale_debug_entry(struct target *target)
 856 {
 857         struct xscale_common *xscale = target_to_xscale(target);
 858         struct arm *arm = &xscale->arm;
 859         uint32_t pc;
 860         uint32_t buffer[10];
 861         unsigned i;
 862         int retval;
 863         uint32_t moe;
 864
 865         /* clear external dbg break (will be written on next DCSR read) */
 866         xscale->external_debug_break = 0;
 867         retval = xscale_read_dcsr(target);
 868         if (retval != ERROR_OK)
 869                 return retval;
 870
 871         /* get r0, pc, r1 to r7 and cpsr */
 872         retval = xscale_receive(target, buffer, 10);
 873         if (retval != ERROR_OK)
 874                 return retval;
 875
 876         /* move r0 from buffer to register cache */
 877         buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
 878         arm->core_cache->reg_list[0].dirty = 1;
 879         arm->core_cache->reg_list[0].valid = 1;
 880         LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 881
 882         /* move pc from buffer to register cache */
 883         buf_set_u32(arm->pc->value, 0, 32, buffer[1]);
 884         arm->pc->dirty = 1;
 885         arm->pc->valid = 1;
 886         LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
 887
 888         /* move data from buffer to register cache */
 889         for (i = 1; i <= 7; i++) {
 890                 buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
 891                 arm->core_cache->reg_list[i].dirty = 1;
 892                 arm->core_cache->reg_list[i].valid = 1;
 893                 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 894         }
 895
 896         arm_set_cpsr(arm, buffer[9]);
 897         LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 898
 899         if (!is_arm_mode(arm->core_mode)) {
 900                 target->state = TARGET_UNKNOWN;
 901                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
 902                 return ERROR_TARGET_FAILURE;
 903         }
 904         LOG_DEBUG("target entered debug state in %s mode",
 905                 arm_mode_name(arm->core_mode));
 906
 907         /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
 908         if (arm->spsr) {
 909                 xscale_receive(target, buffer, 8);
 910                 buf_set_u32(arm->spsr->value, 0, 32, buffer[7]);
 911                 arm->spsr->dirty = false;
 912                 arm->spsr->valid = true;
 913         } else {
 914                 /* r8 to r14, but no spsr */
 915                 xscale_receive(target, buffer, 7);
 916         }
 917
 918         /* move data from buffer to right banked register in cache */
 919         for (i = 8; i <= 14; i++) {
 920                 struct reg *r = arm_reg_current(arm, i);
 921
 922                 buf_set_u32(r->value, 0, 32, buffer[i - 8]);
 923                 r->dirty = false;
 924                 r->valid = true;
 925         }
 926
 927         /* mark xscale regs invalid to ensure they are retrieved from the
 928          * debug handler if requested  */
 929         for (i = 0; i < xscale->reg_cache->num_regs; i++)
 930                 xscale->reg_cache->reg_list[i].valid = 0;
 931
 932         /* examine debug reason */
 933         xscale_read_dcsr(target);
 934         moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
 935
 936         /* stored PC (for calculating fixup) */
 937         pc = buf_get_u32(arm->pc->value, 0, 32);
 938
 939         switch (moe) {
 940                 case 0x0:       /* Processor reset */
 941                         target->debug_reason = DBG_REASON_DBGRQ;
 942                         xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
 943                         pc -= 4;
 944                         break;
 945                 case 0x1:       /* Instruction breakpoint hit */
 946                         target->debug_reason = DBG_REASON_BREAKPOINT;
 947                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 948                         pc -= 4;
 949                         break;
 950                 case 0x2:       /* Data breakpoint hit */
 951                         target->debug_reason = DBG_REASON_WATCHPOINT;
 952                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 953                         pc -= 4;
 954                         break;
 955                 case 0x3:       /* BKPT instruction executed */
 956                         target->debug_reason = DBG_REASON_BREAKPOINT;
 957                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 958                         pc -= 4;
 959                         break;
 960                 case 0x4:       /* Ext. debug event */
 961                         target->debug_reason = DBG_REASON_DBGRQ;
 962                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 963                         pc -= 4;
 964                         break;
 965                 case 0x5:       /* Vector trap occured */
 966                         target->debug_reason = DBG_REASON_BREAKPOINT;
 967                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 968                         pc -= 4;
 969                         break;
 970                 case 0x6:       /* Trace buffer full break */
 971                         target->debug_reason = DBG_REASON_DBGRQ;
 972                         xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
 973                         pc -= 4;
 974                         break;
 975                 case 0x7:       /* Reserved (may flag Hot-Debug support) */
 976                 default:
 977                         LOG_ERROR("Method of Entry is 'Reserved'");
 978                         exit(-1);
 979                         break;
 980         }
 981
 982         /* apply PC fixup */
 983         buf_set_u32(arm->pc->value, 0, 32, pc);
 984
 985         /* on the first debug entry, identify cache type */
 986         if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) {
 987                 uint32_t cache_type_reg;
 988
 989                 /* read cp15 cache type register */
 990                 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
 991                 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value,
 992                                 0,
 993                                 32);
 994
 995                 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
 996         }
 997
 998         /* examine MMU and Cache settings
 999          * read cp15 control register */
1000         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
1001         xscale->cp15_control_reg =
1002                 buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
1003         xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
1004         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
1005                 (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
1006         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
1007                 (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1008
1009         /* tracing enabled, read collected trace data */
1010         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1011                 xscale_read_trace(target);
1012
1013                 /* Resume if entered debug due to buffer fill and we're still collecting
1014                  * trace data.  Note that a debug exception due to trace buffer full
1015                  * can only happen in fill mode. */
1016                 if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) {
1017                         if (--xscale->trace.fill_counter > 0)
1018                                 xscale_resume(target, 1, 0x0, 1, 0);
1019                 } else  /* entered debug for other reason; reset counter */
1020                         xscale->trace.fill_counter = 0;
1021         }
1022
1023         return ERROR_OK;
1024 }
1025
1026 static int xscale_halt(struct target *target)
1027 {
1028         struct xscale_common *xscale = target_to_xscale(target);
1029
1030         LOG_DEBUG("target->state: %s",
1031                 target_state_name(target));
1032
1033         if (target->state == TARGET_HALTED) {
1034                 LOG_DEBUG("target was already halted");
1035                 return ERROR_OK;
1036         } else if (target->state == TARGET_UNKNOWN) {
1037                 /* this must not happen for a xscale target */
1038                 LOG_ERROR("target was in unknown state when halt was requested");
1039                 return ERROR_TARGET_INVALID;
1040         } else if (target->state == TARGET_RESET)
1041                 LOG_DEBUG("target->state == TARGET_RESET");
1042         else {
1043                 /* assert external dbg break */
1044                 xscale->external_debug_break = 1;
1045                 xscale_read_dcsr(target);
1046
1047                 target->debug_reason = DBG_REASON_DBGRQ;
1048         }
1049
1050         return ERROR_OK;
1051 }
1052
1053 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1054 {
1055         struct xscale_common *xscale = target_to_xscale(target);
1056         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1057         int retval;
1058
1059         if (xscale->ibcr0_used) {
1060                 struct breakpoint *ibcr0_bp =
1061                         breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1062
1063                 if (ibcr0_bp)
1064                         xscale_unset_breakpoint(target, ibcr0_bp);
1065                 else {
1066                         LOG_ERROR(
1067                                 "BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1068                         exit(-1);
1069                 }
1070         }
1071
1072         retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1073         if (retval != ERROR_OK)
1074                 return retval;
1075
1076         return ERROR_OK;
1077 }
1078
1079 static int xscale_disable_single_step(struct target *target)
1080 {
1081         struct xscale_common *xscale = target_to_xscale(target);
1082         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1083         int retval;
1084
1085         retval = xscale_set_reg_u32(ibcr0, 0x0);
1086         if (retval != ERROR_OK)
1087                 return retval;
1088
1089         return ERROR_OK;
1090 }
1091
1092 static void xscale_enable_watchpoints(struct target *target)
1093 {
1094         struct watchpoint *watchpoint = target->watchpoints;
1095
1096         while (watchpoint) {
1097                 if (watchpoint->set == 0)
1098                         xscale_set_watchpoint(target, watchpoint);
1099                 watchpoint = watchpoint->next;
1100         }
1101 }
1102
1103 static void xscale_enable_breakpoints(struct target *target)
1104 {
1105         struct breakpoint *breakpoint = target->breakpoints;
1106
1107         /* set any pending breakpoints */
1108         while (breakpoint) {
1109                 if (breakpoint->set == 0)
1110                         xscale_set_breakpoint(target, breakpoint);
1111                 breakpoint = breakpoint->next;
1112         }
1113 }
1114
1115 static void xscale_free_trace_data(struct xscale_common *xscale)
1116 {
1117         struct xscale_trace_data *td = xscale->trace.data;
1118         while (td) {
1119                 struct xscale_trace_data *next_td = td->next;
1120                 if (td->entries)
1121                         free(td->entries);
1122                 free(td);
1123                 td = next_td;
1124         }
1125         xscale->trace.data = NULL;
1126 }
1127
1128 static int xscale_resume(struct target *target, int current,
1129         uint32_t address, int handle_breakpoints, int debug_execution)
1130 {
1131         struct xscale_common *xscale = target_to_xscale(target);
1132         struct arm *arm = &xscale->arm;
1133         uint32_t current_pc;
1134         int retval;
1135         int i;
1136
1137         LOG_DEBUG("-");
1138
1139         if (target->state != TARGET_HALTED) {
1140                 LOG_WARNING("target not halted");
1141                 return ERROR_TARGET_NOT_HALTED;
1142         }
1143
1144         if (!debug_execution)
1145                 target_free_all_working_areas(target);
1146
1147         /* update vector tables */
1148         retval = xscale_update_vectors(target);
1149         if (retval != ERROR_OK)
1150                 return retval;
1151
1152         /* current = 1: continue on current pc, otherwise continue at <address> */
1153         if (!current)
1154                 buf_set_u32(arm->pc->value, 0, 32, address);
1155
1156         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1157
1158         /* if we're at the reset vector, we have to simulate the branch */
1159         if (current_pc == 0x0) {
1160                 arm_simulate_step(target, NULL);
1161                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1162         }
1163
1164         /* the front-end may request us not to handle breakpoints */
1165         if (handle_breakpoints) {
1166                 struct breakpoint *breakpoint;
1167                 breakpoint = breakpoint_find(target,
1168                                 buf_get_u32(arm->pc->value, 0, 32));
1169                 if (breakpoint != NULL) {
1170                         uint32_t next_pc;
1171                         enum trace_mode saved_trace_mode;
1172
1173                         /* there's a breakpoint at the current PC, we have to step over it */
1174                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1175                         xscale_unset_breakpoint(target, breakpoint);
1176
1177                         /* calculate PC of next instruction */
1178                         retval = arm_simulate_step(target, &next_pc);
1179                         if (retval != ERROR_OK) {
1180                                 uint32_t current_opcode;
1181                                 target_read_u32(target, current_pc, &current_opcode);
1182                                 LOG_ERROR(
1183                                         "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
1184                                         current_opcode);
1185                         }
1186
1187                         LOG_DEBUG("enable single-step");
1188                         xscale_enable_single_step(target, next_pc);
1189
1190                         /* restore banked registers */
1191                         retval = xscale_restore_banked(target);
1192                         if (retval != ERROR_OK)
1193                                 return retval;
1194
1195                         /* send resume request */
1196                         xscale_send_u32(target, 0x30);
1197
1198                         /* send CPSR */
1199                         xscale_send_u32(target,
1200                                 buf_get_u32(arm->cpsr->value, 0, 32));
1201                         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1202                                 buf_get_u32(arm->cpsr->value, 0, 32));
1203
1204                         for (i = 7; i >= 0; i--) {
1205                                 /* send register */
1206                                 xscale_send_u32(target,
1207                                         buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1208                                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
1209                                         i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1210                         }
1211
1212                         /* send PC */
1213                         xscale_send_u32(target,
1214                                 buf_get_u32(arm->pc->value, 0, 32));
1215                         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1216                                 buf_get_u32(arm->pc->value, 0, 32));
1217
1218                         /* disable trace data collection in xscale_debug_entry() */
1219                         saved_trace_mode = xscale->trace.mode;
1220                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
1221
1222                         /* wait for and process debug entry */
1223                         xscale_debug_entry(target);
1224
1225                         /* re-enable trace buffer, if enabled previously */
1226                         xscale->trace.mode = saved_trace_mode;
1227
1228                         LOG_DEBUG("disable single-step");
1229                         xscale_disable_single_step(target);
1230
1231                         LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
1232                         xscale_set_breakpoint(target, breakpoint);
1233                 }
1234         }
1235
1236         /* enable any pending breakpoints and watchpoints */
1237         xscale_enable_breakpoints(target);
1238         xscale_enable_watchpoints(target);
1239
1240         /* restore banked registers */
1241         retval = xscale_restore_banked(target);
1242         if (retval != ERROR_OK)
1243                 return retval;
1244
1245         /* send resume request (command 0x30 or 0x31)
1246          * clean the trace buffer if it is to be enabled (0x62) */
1247         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1248                 if (xscale->trace.mode == XSCALE_TRACE_FILL) {
1249                         /* If trace enabled in fill mode and starting collection of new set
1250                              * of buffers, initialize buffer counter and free previous buffers */
1251                         if (xscale->trace.fill_counter == 0) {
1252                                 xscale->trace.fill_counter = xscale->trace.buffer_fill;
1253                                 xscale_free_trace_data(xscale);
1254                         }
1255                 } else  /* wrap mode; free previous buffer */
1256                         xscale_free_trace_data(xscale);
1257
1258                 xscale_send_u32(target, 0x62);
1259                 xscale_send_u32(target, 0x31);
1260         } else
1261                 xscale_send_u32(target, 0x30);
1262
1263         /* send CPSR */
1264         xscale_send_u32(target, buf_get_u32(arm->cpsr->value, 0, 32));
1265         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1266                 buf_get_u32(arm->cpsr->value, 0, 32));
1267
1268         for (i = 7; i >= 0; i--) {
1269                 /* send register */
1270                 xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1271                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
1272                         i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1273         }
1274
1275         /* send PC */
1276         xscale_send_u32(target, buf_get_u32(arm->pc->value, 0, 32));
1277         LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1278                 buf_get_u32(arm->pc->value, 0, 32));
1279
1280         target->debug_reason = DBG_REASON_NOTHALTED;
1281
1282         if (!debug_execution) {
1283                 /* registers are now invalid */
1284                 register_cache_invalidate(arm->core_cache);
1285                 target->state = TARGET_RUNNING;
1286                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1287         } else {
1288                 target->state = TARGET_DEBUG_RUNNING;
1289                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1290         }
1291
1292         LOG_DEBUG("target resumed");
1293
1294         return ERROR_OK;
1295 }
1296
1297 static int xscale_step_inner(struct target *target, int current,
1298         uint32_t address, int handle_breakpoints)
1299 {
1300         struct xscale_common *xscale = target_to_xscale(target);
1301         struct arm *arm = &xscale->arm;
1302         uint32_t next_pc;
1303         int retval;
1304         int i;
1305
1306         target->debug_reason = DBG_REASON_SINGLESTEP;
1307
1308         /* calculate PC of next instruction */
1309         retval = arm_simulate_step(target, &next_pc);
1310         if (retval != ERROR_OK) {
1311                 uint32_t current_opcode, current_pc;
1312                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1313
1314                 target_read_u32(target, current_pc, &current_opcode);
1315                 LOG_ERROR(
1316                         "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
1317                         current_opcode);
1318                 return retval;
1319         }
1320
1321         LOG_DEBUG("enable single-step");
1322         retval = xscale_enable_single_step(target, next_pc);
1323         if (retval != ERROR_OK)
1324                 return retval;
1325
1326         /* restore banked registers */
1327         retval = xscale_restore_banked(target);
1328         if (retval != ERROR_OK)
1329                 return retval;
1330
1331         /* send resume request (command 0x30 or 0x31)
1332          * clean the trace buffer if it is to be enabled (0x62) */
1333         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1334                 retval = xscale_send_u32(target, 0x62);
1335                 if (retval != ERROR_OK)
1336                         return retval;
1337                 retval = xscale_send_u32(target, 0x31);
1338                 if (retval != ERROR_OK)
1339                         return retval;
1340         } else {
1341                 retval = xscale_send_u32(target, 0x30);
1342                 if (retval != ERROR_OK)
1343                         return retval;
1344         }
1345
1346         /* send CPSR */
1347         retval = xscale_send_u32(target,
1348                         buf_get_u32(arm->cpsr->value, 0, 32));
1349         if (retval != ERROR_OK)
1350                 return retval;
1351         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1352                 buf_get_u32(arm->cpsr->value, 0, 32));
1353
1354         for (i = 7; i >= 0; i--) {
1355                 /* send register */
1356                 retval = xscale_send_u32(target,
1357                                 buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1358                 if (retval != ERROR_OK)
1359                         return retval;
1360                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
1361                         buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1362         }
1363
1364         /* send PC */
1365         retval = xscale_send_u32(target,
1366                         buf_get_u32(arm->pc->value, 0, 32));
1367         if (retval != ERROR_OK)
1368                 return retval;
1369         LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1370                 buf_get_u32(arm->pc->value, 0, 32));
1371
1372         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1373
1374         /* registers are now invalid */
1375         register_cache_invalidate(arm->core_cache);
1376
1377         /* wait for and process debug entry */
1378         retval = xscale_debug_entry(target);
1379         if (retval != ERROR_OK)
1380                 return retval;
1381
1382         LOG_DEBUG("disable single-step");
1383         retval = xscale_disable_single_step(target);
1384         if (retval != ERROR_OK)
1385                 return retval;
1386
1387         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1388
1389         return ERROR_OK;
1390 }
1391
1392 static int xscale_step(struct target *target, int current,
1393         uint32_t address, int handle_breakpoints)
1394 {
1395         struct arm *arm = target_to_arm(target);
1396         struct breakpoint *breakpoint = NULL;
1397
1398         uint32_t current_pc;
1399         int retval;
1400
1401         if (target->state != TARGET_HALTED) {
1402                 LOG_WARNING("target not halted");
1403                 return ERROR_TARGET_NOT_HALTED;
1404         }
1405
1406         /* current = 1: continue on current pc, otherwise continue at <address> */
1407         if (!current)
1408                 buf_set_u32(arm->pc->value, 0, 32, address);
1409
1410         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1411
1412         /* if we're at the reset vector, we have to simulate the step */
1413         if (current_pc == 0x0) {
1414                 retval = arm_simulate_step(target, NULL);
1415                 if (retval != ERROR_OK)
1416                         return retval;
1417                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1418                 LOG_DEBUG("current pc %" PRIx32, current_pc);
1419
1420                 target->debug_reason = DBG_REASON_SINGLESTEP;
1421                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1422
1423                 return ERROR_OK;
1424         }
1425
1426         /* the front-end may request us not to handle breakpoints */
1427         if (handle_breakpoints)
1428                 breakpoint = breakpoint_find(target,
1429                                 buf_get_u32(arm->pc->value, 0, 32));
1430         if (breakpoint != NULL) {
1431                 retval = xscale_unset_breakpoint(target, breakpoint);
1432                 if (retval != ERROR_OK)
1433                         return retval;
1434         }
1435
1436         retval = xscale_step_inner(target, current, address, handle_breakpoints);
1437         if (retval != ERROR_OK)
1438                 return retval;
1439
1440         if (breakpoint)
1441                 xscale_set_breakpoint(target, breakpoint);
1442
1443         LOG_DEBUG("target stepped");
1444
1445         return ERROR_OK;
1446
1447 }
1448
1449 static int xscale_assert_reset(struct target *target)
1450 {
1451         struct xscale_common *xscale = target_to_xscale(target);
1452
1453         LOG_DEBUG("target->state: %s",
1454                 target_state_name(target));
1455
1456         /* assert reset */
1457         jtag_add_reset(0, 1);
1458
1459         /* sleep 1ms, to be sure we fulfill any requirements */
1460         jtag_add_sleep(1000);
1461         jtag_execute_queue();
1462
1463         /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1464          * end up in T-L-R, which would reset JTAG
1465          */
1466         xscale_jtag_set_instr(target->tap,
1467                 XSCALE_SELDCSR << xscale->xscale_variant,
1468                 TAP_IDLE);
1469
1470         /* set Hold reset, Halt mode and Trap Reset */
1471         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1472         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1473         xscale_write_dcsr(target, 1, 0);
1474
1475         /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1476         xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
1477         jtag_execute_queue();
1478
1479         target->state = TARGET_RESET;
1480
1481         if (target->reset_halt) {
1482                 int retval = target_halt(target);
1483                 if (retval != ERROR_OK)
1484                         return retval;
1485         }
1486
1487         return ERROR_OK;
1488 }
1489
1490 static int xscale_deassert_reset(struct target *target)
1491 {
1492         struct xscale_common *xscale = target_to_xscale(target);
1493         struct breakpoint *breakpoint = target->breakpoints;
1494
1495         LOG_DEBUG("-");
1496
1497         xscale->ibcr_available = 2;
1498         xscale->ibcr0_used = 0;
1499         xscale->ibcr1_used = 0;
1500
1501         xscale->dbr_available = 2;
1502         xscale->dbr0_used = 0;
1503         xscale->dbr1_used = 0;
1504
1505         /* mark all hardware breakpoints as unset */
1506         while (breakpoint) {
1507                 if (breakpoint->type == BKPT_HARD)
1508                         breakpoint->set = 0;
1509                 breakpoint = breakpoint->next;
1510         }
1511
1512         xscale->trace.mode = XSCALE_TRACE_DISABLED;
1513         xscale_free_trace_data(xscale);
1514
1515         register_cache_invalidate(xscale->arm.core_cache);
1516
1517         /* FIXME mark hardware watchpoints got unset too.  Also,
1518          * at least some of the XScale registers are invalid...
1519          */
1520
1521         /*
1522          * REVISIT:  *assumes* we had a SRST+TRST reset so the mini-icache
1523          * contents got invalidated.  Safer to force that, so writing new
1524          * contents can't ever fail..
1525          */
1526         {
1527                 uint32_t address;
1528                 unsigned buf_cnt;
1529                 const uint8_t *buffer = xscale_debug_handler;
1530                 int retval;
1531
1532                 /* release SRST */
1533                 jtag_add_reset(0, 0);
1534
1535                 /* wait 300ms; 150 and 100ms were not enough */
1536                 jtag_add_sleep(300*1000);
1537
1538                 jtag_add_runtest(2030, TAP_IDLE);
1539                 jtag_execute_queue();
1540
1541                 /* set Hold reset, Halt mode and Trap Reset */
1542                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1543                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1544                 xscale_write_dcsr(target, 1, 0);
1545
1546                 /* Load the debug handler into the mini-icache.  Since
1547                  * it's using halt mode (not monitor mode), it runs in
1548                  * "Special Debug State" for access to registers, memory,
1549                  * coprocessors, trace data, etc.
1550                  */
1551                 address = xscale->handler_address;
1552                 for (unsigned binary_size = sizeof xscale_debug_handler - 1;
1553                         binary_size > 0;
1554                         binary_size -= buf_cnt, buffer += buf_cnt) {
1555                         uint32_t cache_line[8];
1556                         unsigned i;
1557
1558                         buf_cnt = binary_size;
1559                         if (buf_cnt > 32)
1560                                 buf_cnt = 32;
1561
1562                         for (i = 0; i < buf_cnt; i += 4) {
1563                                 /* convert LE buffer to host-endian uint32_t */
1564                                 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1565                         }
1566
1567                         for (; i < 32; i += 4)
1568                                 cache_line[i / 4] = 0xe1a08008;
1569
1570                         /* only load addresses other than the reset vectors */
1571                         if ((address % 0x400) != 0x0) {
1572                                 retval = xscale_load_ic(target, address,
1573                                                 cache_line);
1574                                 if (retval != ERROR_OK)
1575                                         return retval;
1576                         }
1577
1578                         address += buf_cnt;
1579                 }
1580                 ;
1581
1582                 retval = xscale_load_ic(target, 0x0,
1583                                 xscale->low_vectors);
1584                 if (retval != ERROR_OK)
1585                         return retval;
1586                 retval = xscale_load_ic(target, 0xffff0000,
1587                                 xscale->high_vectors);
1588                 if (retval != ERROR_OK)
1589                         return retval;
1590
1591                 jtag_add_runtest(30, TAP_IDLE);
1592
1593                 jtag_add_sleep(100000);
1594
1595                 /* set Hold reset, Halt mode and Trap Reset */
1596                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1597                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1598                 xscale_write_dcsr(target, 1, 0);
1599
1600                 /* clear Hold reset to let the target run (should enter debug handler) */
1601                 xscale_write_dcsr(target, 0, 1);
1602                 target->state = TARGET_RUNNING;
1603
1604                 if (!target->reset_halt) {
1605                         jtag_add_sleep(10000);
1606
1607                         /* we should have entered debug now */
1608                         xscale_debug_entry(target);
1609                         target->state = TARGET_HALTED;
1610
1611                         /* resume the target */
1612                         xscale_resume(target, 1, 0x0, 1, 0);
1613                 }
1614         }
1615
1616         return ERROR_OK;
1617 }
1618
1619 static int xscale_read_core_reg(struct target *target, struct reg *r,
1620         int num, enum arm_mode mode)
1621 {
1622         /** \todo add debug handler support for core register reads */
1623         LOG_ERROR("not implemented");
1624         return ERROR_OK;
1625 }
1626
1627 static int xscale_write_core_reg(struct target *target, struct reg *r,
1628         int num, enum arm_mode mode, uint32_t value)
1629 {
1630         /** \todo add debug handler support for core register writes */
1631         LOG_ERROR("not implemented");
1632         return ERROR_OK;
1633 }
1634
1635 static int xscale_full_context(struct target *target)
1636 {
1637         struct arm *arm = target_to_arm(target);
1638
1639         uint32_t *buffer;
1640
1641         int i, j;
1642
1643         LOG_DEBUG("-");
1644
1645         if (target->state != TARGET_HALTED) {
1646                 LOG_WARNING("target not halted");
1647                 return ERROR_TARGET_NOT_HALTED;
1648         }
1649
1650         buffer = malloc(4 * 8);
1651
1652         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1653          * we can't enter User mode on an XScale (unpredictable),
1654          * but User shares registers with SYS
1655          */
1656         for (i = 1; i < 7; i++) {
1657                 enum arm_mode mode = armv4_5_number_to_mode(i);
1658                 bool valid = true;
1659                 struct reg *r;
1660
1661                 if (mode == ARM_MODE_USR)
1662                         continue;
1663
1664                 /* check if there are invalid registers in the current mode
1665                  */
1666                 for (j = 0; valid && j <= 16; j++) {
1667                         if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
1668                                 mode, j).valid)
1669                                 valid = false;
1670                 }
1671                 if (valid)
1672                         continue;
1673
1674                 /* request banked registers */
1675                 xscale_send_u32(target, 0x0);
1676
1677                 /* send CPSR for desired bank mode */
1678                 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1679
1680                 /* get banked registers:  r8 to r14; and SPSR
1681                  * except in USR/SYS mode
1682                  */
1683                 if (mode != ARM_MODE_SYS) {
1684                         /* SPSR */
1685                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1686                                         mode, 16);
1687
1688                         xscale_receive(target, buffer, 8);
1689
1690                         buf_set_u32(r->value, 0, 32, buffer[7]);
1691                         r->dirty = false;
1692                         r->valid = true;
1693                 } else
1694                         xscale_receive(target, buffer, 7);
1695
1696                 /* move data from buffer to register cache */
1697                 for (j = 8; j <= 14; j++) {
1698                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1699                                         mode, j);
1700
1701                         buf_set_u32(r->value, 0, 32, buffer[j - 8]);
1702                         r->dirty = false;
1703                         r->valid = true;
1704                 }
1705         }
1706
1707         free(buffer);
1708
1709         return ERROR_OK;
1710 }
1711
1712 static int xscale_restore_banked(struct target *target)
1713 {
1714         struct arm *arm = target_to_arm(target);
1715
1716         int i, j;
1717
1718         if (target->state != TARGET_HALTED) {
1719                 LOG_WARNING("target not halted");
1720                 return ERROR_TARGET_NOT_HALTED;
1721         }
1722
1723         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1724          * and check if any banked registers need to be written.  Ignore
1725          * USR mode (number 0) in favor of SYS; we can't enter User mode on
1726          * an XScale (unpredictable), but they share all registers.
1727          */
1728         for (i = 1; i < 7; i++) {
1729                 enum arm_mode mode = armv4_5_number_to_mode(i);
1730                 struct reg *r;
1731
1732                 if (mode == ARM_MODE_USR)
1733                         continue;
1734
1735                 /* check if there are dirty registers in this mode */
1736                 for (j = 8; j <= 14; j++) {
1737                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
1738                                 mode, j).dirty)
1739                                 goto dirty;
1740                 }
1741
1742                 /* if not USR/SYS, check if the SPSR needs to be written */
1743                 if (mode != ARM_MODE_SYS) {
1744                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
1745                                 mode, 16).dirty)
1746                                 goto dirty;
1747                 }
1748
1749                 /* there's nothing to flush for this mode */
1750                 continue;
1751
1752 dirty:
1753                 /* command 0x1:  "send banked registers" */
1754                 xscale_send_u32(target, 0x1);
1755
1756                 /* send CPSR for desired mode */
1757                 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1758
1759                 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1760                  * but this protocol doesn't understand that nuance.
1761                  */
1762                 for (j = 8; j <= 14; j++) {
1763                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1764                                         mode, j);
1765                         xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1766                         r->dirty = false;
1767                 }
1768
1769                 /* send spsr if not in USR/SYS mode */
1770                 if (mode != ARM_MODE_SYS) {
1771                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1772                                         mode, 16);
1773                         xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1774                         r->dirty = false;
1775                 }
1776         }
1777
1778         return ERROR_OK;
1779 }
1780
1781 static int xscale_read_memory(struct target *target, uint32_t address,
1782         uint32_t size, uint32_t count, uint8_t *buffer)
1783 {
1784         struct xscale_common *xscale = target_to_xscale(target);
1785         uint32_t *buf32;
1786         uint32_t i;
1787         int retval;
1788
1789         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1790                 address,
1791                 size,
1792                 count);
1793
1794         if (target->state != TARGET_HALTED) {
1795                 LOG_WARNING("target not halted");
1796                 return ERROR_TARGET_NOT_HALTED;
1797         }
1798
1799         /* sanitize arguments */
1800         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1801                 return ERROR_COMMAND_SYNTAX_ERROR;
1802
1803         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1804                 return ERROR_TARGET_UNALIGNED_ACCESS;
1805
1806         /* send memory read request (command 0x1n, n: access size) */
1807         retval = xscale_send_u32(target, 0x10 | size);
1808         if (retval != ERROR_OK)
1809                 return retval;
1810
1811         /* send base address for read request */
1812         retval = xscale_send_u32(target, address);
1813         if (retval != ERROR_OK)
1814                 return retval;
1815
1816         /* send number of requested data words */
1817         retval = xscale_send_u32(target, count);
1818         if (retval != ERROR_OK)
1819                 return retval;
1820
1821         /* receive data from target (count times 32-bit words in host endianness) */
1822         buf32 = malloc(4 * count);
1823         retval = xscale_receive(target, buf32, count);
1824         if (retval != ERROR_OK) {
1825                 free(buf32);
1826                 return retval;
1827         }
1828
1829         /* extract data from host-endian buffer into byte stream */
1830         for (i = 0; i < count; i++) {
1831                 switch (size) {
1832                         case 4:
1833                                 target_buffer_set_u32(target, buffer, buf32[i]);
1834                                 buffer += 4;
1835                                 break;
1836                         case 2:
1837                                 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1838                                 buffer += 2;
1839                                 break;
1840                         case 1:
1841                                 *buffer++ = buf32[i] & 0xff;
1842                                 break;
1843                         default:
1844                                 LOG_ERROR("invalid read size");
1845                                 return ERROR_COMMAND_SYNTAX_ERROR;
1846                 }
1847         }
1848
1849         free(buf32);
1850
1851         /* examine DCSR, to see if Sticky Abort (SA) got set */
1852         retval = xscale_read_dcsr(target);
1853         if (retval != ERROR_OK)
1854                 return retval;
1855         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
1856                 /* clear SA bit */
1857                 retval = xscale_send_u32(target, 0x60);
1858                 if (retval != ERROR_OK)
1859                         return retval;
1860
1861                 return ERROR_TARGET_DATA_ABORT;
1862         }
1863
1864         return ERROR_OK;
1865 }
1866
1867 static int xscale_read_phys_memory(struct target *target, uint32_t address,
1868         uint32_t size, uint32_t count, uint8_t *buffer)
1869 {
1870         struct xscale_common *xscale = target_to_xscale(target);
1871
1872         /* with MMU inactive, there are only physical addresses */
1873         if (!xscale->armv4_5_mmu.mmu_enabled)
1874                 return xscale_read_memory(target, address, size, count, buffer);
1875
1876         /** \todo: provide a non-stub implementation of this routine. */
1877         LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
1878                 target_name(target), __func__);
1879         return ERROR_FAIL;
1880 }
1881
1882 static int xscale_write_memory(struct target *target, uint32_t address,
1883         uint32_t size, uint32_t count, const uint8_t *buffer)
1884 {
1885         struct xscale_common *xscale = target_to_xscale(target);
1886         int retval;
1887
1888         LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1889                 address,
1890                 size,
1891                 count);
1892
1893         if (target->state != TARGET_HALTED) {
1894                 LOG_WARNING("target not halted");
1895                 return ERROR_TARGET_NOT_HALTED;
1896         }
1897
1898         /* sanitize arguments */
1899         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1900                 return ERROR_COMMAND_SYNTAX_ERROR;
1901
1902         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1903                 return ERROR_TARGET_UNALIGNED_ACCESS;
1904
1905         /* send memory write request (command 0x2n, n: access size) */
1906         retval = xscale_send_u32(target, 0x20 | size);
1907         if (retval != ERROR_OK)
1908                 return retval;
1909
1910         /* send base address for read request */
1911         retval = xscale_send_u32(target, address);
1912         if (retval != ERROR_OK)
1913                 return retval;
1914
1915         /* send number of requested data words to be written*/
1916         retval = xscale_send_u32(target, count);
1917         if (retval != ERROR_OK)
1918                 return retval;
1919
1920         /* extract data from host-endian buffer into byte stream */
1921 #if 0
1922         for (i = 0; i < count; i++) {
1923                 switch (size) {
1924                         case 4:
1925                                 value = target_buffer_get_u32(target, buffer);
1926                                 xscale_send_u32(target, value);
1927                                 buffer += 4;
1928                                 break;
1929                         case 2:
1930                                 value = target_buffer_get_u16(target, buffer);
1931                                 xscale_send_u32(target, value);
1932                                 buffer += 2;
1933                                 break;
1934                         case 1:
1935                                 value = *buffer;
1936                                 xscale_send_u32(target, value);
1937                                 buffer += 1;
1938                                 break;
1939                         default:
1940                                 LOG_ERROR("should never get here");
1941                                 exit(-1);
1942                 }
1943         }
1944 #endif
1945         retval = xscale_send(target, buffer, count, size);
1946         if (retval != ERROR_OK)
1947                 return retval;
1948
1949         /* examine DCSR, to see if Sticky Abort (SA) got set */
1950         retval = xscale_read_dcsr(target);
1951         if (retval != ERROR_OK)
1952                 return retval;
1953         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
1954                 /* clear SA bit */
1955                 retval = xscale_send_u32(target, 0x60);
1956                 if (retval != ERROR_OK)
1957                         return retval;
1958
1959                 LOG_ERROR("data abort writing memory");
1960                 return ERROR_TARGET_DATA_ABORT;
1961         }
1962
1963         return ERROR_OK;
1964 }
1965
1966 static int xscale_write_phys_memory(struct target *target, uint32_t address,
1967         uint32_t size, uint32_t count, const uint8_t *buffer)
1968 {
1969         struct xscale_common *xscale = target_to_xscale(target);
1970
1971         /* with MMU inactive, there are only physical addresses */
1972         if (!xscale->armv4_5_mmu.mmu_enabled)
1973                 return xscale_write_memory(target, address, size, count, buffer);
1974
1975         /** \todo: provide a non-stub implementation of this routine. */
1976         LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
1977                 target_name(target), __func__);
1978         return ERROR_FAIL;
1979 }
1980
1981 static int xscale_get_ttb(struct target *target, uint32_t *result)
1982 {
1983         struct xscale_common *xscale = target_to_xscale(target);
1984         uint32_t ttb;
1985         int retval;
1986
1987         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
1988         if (retval != ERROR_OK)
1989                 return retval;
1990         ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
1991
1992         *result = ttb;
1993
1994         return ERROR_OK;
1995 }
1996
1997 static int xscale_disable_mmu_caches(struct target *target, int mmu,
1998         int d_u_cache, int i_cache)
1999 {
2000         struct xscale_common *xscale = target_to_xscale(target);
2001         uint32_t cp15_control;
2002         int retval;
2003
2004         /* read cp15 control register */
2005         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2006         if (retval != ERROR_OK)
2007                 return retval;
2008         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2009
2010         if (mmu)
2011                 cp15_control &= ~0x1U;
2012
2013         if (d_u_cache) {
2014                 /* clean DCache */
2015                 retval = xscale_send_u32(target, 0x50);
2016                 if (retval != ERROR_OK)
2017                         return retval;
2018                 retval = xscale_send_u32(target, xscale->cache_clean_address);
2019                 if (retval != ERROR_OK)
2020                         return retval;
2021
2022                 /* invalidate DCache */
2023                 retval = xscale_send_u32(target, 0x51);
2024                 if (retval != ERROR_OK)
2025                         return retval;
2026
2027                 cp15_control &= ~0x4U;
2028         }
2029
2030         if (i_cache) {
2031                 /* invalidate ICache */
2032                 retval = xscale_send_u32(target, 0x52);
2033                 if (retval != ERROR_OK)
2034                         return retval;
2035                 cp15_control &= ~0x1000U;
2036         }
2037
2038         /* write new cp15 control register */
2039         retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2040         if (retval != ERROR_OK)
2041                 return retval;
2042
2043         /* execute cpwait to ensure outstanding operations complete */
2044         retval = xscale_send_u32(target, 0x53);
2045         return retval;
2046 }
2047
2048 static int xscale_enable_mmu_caches(struct target *target, int mmu,
2049         int d_u_cache, int i_cache)
2050 {
2051         struct xscale_common *xscale = target_to_xscale(target);
2052         uint32_t cp15_control;
2053         int retval;
2054
2055         /* read cp15 control register */
2056         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2057         if (retval != ERROR_OK)
2058                 return retval;
2059         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2060
2061         if (mmu)
2062                 cp15_control |= 0x1U;
2063
2064         if (d_u_cache)
2065                 cp15_control |= 0x4U;
2066
2067         if (i_cache)
2068                 cp15_control |= 0x1000U;
2069
2070         /* write new cp15 control register */
2071         retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2072         if (retval != ERROR_OK)
2073                 return retval;
2074
2075         /* execute cpwait to ensure outstanding operations complete */
2076         retval = xscale_send_u32(target, 0x53);
2077         return retval;
2078 }
2079
2080 static int xscale_set_breakpoint(struct target *target,
2081         struct breakpoint *breakpoint)
2082 {
2083         int retval;
2084         struct xscale_common *xscale = target_to_xscale(target);
2085
2086         if (target->state != TARGET_HALTED) {
2087                 LOG_WARNING("target not halted");
2088                 return ERROR_TARGET_NOT_HALTED;
2089         }
2090
2091         if (breakpoint->set) {
2092                 LOG_WARNING("breakpoint already set");
2093                 return ERROR_OK;
2094         }
2095
2096         if (breakpoint->type == BKPT_HARD) {
2097                 uint32_t value = breakpoint->address | 1;
2098                 if (!xscale->ibcr0_used) {
2099                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2100                         xscale->ibcr0_used = 1;
2101                         breakpoint->set = 1;    /* breakpoint set on first breakpoint register */
2102                 } else if (!xscale->ibcr1_used) {
2103                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2104                         xscale->ibcr1_used = 1;
2105                         breakpoint->set = 2;    /* breakpoint set on second breakpoint register */
2106                 } else {/* bug: availability previously verified in xscale_add_breakpoint() */
2107                         LOG_ERROR("BUG: no hardware comparator available");
2108                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2109                 }
2110         } else if (breakpoint->type == BKPT_SOFT) {
2111                 if (breakpoint->length == 4) {
2112                         /* keep the original instruction in target endianness */
2113                         retval = target_read_memory(target, breakpoint->address, 4, 1,
2114                                         breakpoint->orig_instr);
2115                         if (retval != ERROR_OK)
2116                                 return retval;
2117                         /* write the bkpt instruction in target endianness
2118                          *(arm7_9->arm_bkpt is host endian) */
2119                         retval = target_write_u32(target, breakpoint->address,
2120                                         xscale->arm_bkpt);
2121                         if (retval != ERROR_OK)
2122                                 return retval;
2123                 } else {
2124                         /* keep the original instruction in target endianness */
2125                         retval = target_read_memory(target, breakpoint->address, 2, 1,
2126                                         breakpoint->orig_instr);
2127                         if (retval != ERROR_OK)
2128                                 return retval;
2129                         /* write the bkpt instruction in target endianness
2130                          *(arm7_9->arm_bkpt is host endian) */
2131                         retval = target_write_u16(target, breakpoint->address,
2132                                         xscale->thumb_bkpt);
2133                         if (retval != ERROR_OK)
2134                                 return retval;
2135                 }
2136                 breakpoint->set = 1;
2137
2138                 xscale_send_u32(target, 0x50);  /* clean dcache */
2139                 xscale_send_u32(target, xscale->cache_clean_address);
2140                 xscale_send_u32(target, 0x51);  /* invalidate dcache */
2141                 xscale_send_u32(target, 0x52);  /* invalidate icache and flush fetch buffers */
2142         }
2143
2144         return ERROR_OK;
2145 }
2146
2147 static int xscale_add_breakpoint(struct target *target,
2148         struct breakpoint *breakpoint)
2149 {
2150         struct xscale_common *xscale = target_to_xscale(target);
2151
2152         if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) {
2153                 LOG_ERROR("no breakpoint unit available for hardware breakpoint");
2154                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2155         }
2156
2157         if ((breakpoint->length != 2) && (breakpoint->length != 4)) {
2158                 LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2159                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2160         }
2161
2162         if (breakpoint->type == BKPT_HARD)
2163                 xscale->ibcr_available--;
2164
2165         return xscale_set_breakpoint(target, breakpoint);
2166 }
2167
2168 static int xscale_unset_breakpoint(struct target *target,
2169         struct breakpoint *breakpoint)
2170 {
2171         int retval;
2172         struct xscale_common *xscale = target_to_xscale(target);
2173
2174         if (target->state != TARGET_HALTED) {
2175                 LOG_WARNING("target not halted");
2176                 return ERROR_TARGET_NOT_HALTED;
2177         }
2178
2179         if (!breakpoint->set) {
2180                 LOG_WARNING("breakpoint not set");
2181                 return ERROR_OK;
2182         }
2183
2184         if (breakpoint->type == BKPT_HARD) {
2185                 if (breakpoint->set == 1) {
2186                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2187                         xscale->ibcr0_used = 0;
2188                 } else if (breakpoint->set == 2) {
2189                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2190                         xscale->ibcr1_used = 0;
2191                 }
2192                 breakpoint->set = 0;
2193         } else {
2194                 /* restore original instruction (kept in target endianness) */
2195                 if (breakpoint->length == 4) {
2196                         retval = target_write_memory(target, breakpoint->address, 4, 1,
2197                                         breakpoint->orig_instr);
2198                         if (retval != ERROR_OK)
2199                                 return retval;
2200                 } else {
2201                         retval = target_write_memory(target, breakpoint->address, 2, 1,
2202                                         breakpoint->orig_instr);
2203                         if (retval != ERROR_OK)
2204                                 return retval;
2205                 }
2206                 breakpoint->set = 0;
2207
2208                 xscale_send_u32(target, 0x50);  /* clean dcache */
2209                 xscale_send_u32(target, xscale->cache_clean_address);
2210                 xscale_send_u32(target, 0x51);  /* invalidate dcache */
2211                 xscale_send_u32(target, 0x52);  /* invalidate icache and flush fetch buffers */
2212         }
2213
2214         return ERROR_OK;
2215 }
2216
2217 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2218 {
2219         struct xscale_common *xscale = target_to_xscale(target);
2220
2221         if (target->state != TARGET_HALTED) {
2222                 LOG_ERROR("target not halted");
2223                 return ERROR_TARGET_NOT_HALTED;
2224         }
2225
2226         if (breakpoint->set)
2227                 xscale_unset_breakpoint(target, breakpoint);
2228
2229         if (breakpoint->type == BKPT_HARD)
2230                 xscale->ibcr_available++;
2231
2232         return ERROR_OK;
2233 }
2234
2235 static int xscale_set_watchpoint(struct target *target,
2236         struct watchpoint *watchpoint)
2237 {
2238         struct xscale_common *xscale = target_to_xscale(target);
2239         uint32_t enable = 0;
2240         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2241         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2242
2243         if (target->state != TARGET_HALTED) {
2244                 LOG_ERROR("target not halted");
2245                 return ERROR_TARGET_NOT_HALTED;
2246         }
2247
2248         switch (watchpoint->rw) {
2249                 case WPT_READ:
2250                         enable = 0x3;
2251                         break;
2252                 case WPT_ACCESS:
2253                         enable = 0x2;
2254                         break;
2255                 case WPT_WRITE:
2256                         enable = 0x1;
2257                         break;
2258                 default:
2259                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2260         }
2261
2262         /* For watchpoint across more than one word, both DBR registers must
2263            be enlisted, with the second used as a mask. */
2264         if (watchpoint->length > 4) {
2265                 if (xscale->dbr0_used || xscale->dbr1_used) {
2266                         LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2267                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2268                 }
2269
2270                 /* Write mask value to DBR1, based on the length argument.
2271                  * Address bits ignored by the comparator are those set in mask. */
2272                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
2273                         watchpoint->length - 1);
2274                 xscale->dbr1_used = 1;
2275                 enable |= 0x100;                /* DBCON[M] */
2276         }
2277
2278         if (!xscale->dbr0_used) {
2279                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2280                 dbcon_value |= enable;
2281                 xscale_set_reg_u32(dbcon, dbcon_value);
2282                 watchpoint->set = 1;
2283                 xscale->dbr0_used = 1;
2284         } else if (!xscale->dbr1_used) {
2285                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2286                 dbcon_value |= enable << 2;
2287                 xscale_set_reg_u32(dbcon, dbcon_value);
2288                 watchpoint->set = 2;
2289                 xscale->dbr1_used = 1;
2290         } else {
2291                 LOG_ERROR("BUG: no hardware comparator available");
2292                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2293         }
2294
2295         return ERROR_OK;
2296 }
2297
2298 static int xscale_add_watchpoint(struct target *target,
2299         struct watchpoint *watchpoint)
2300 {
2301         struct xscale_common *xscale = target_to_xscale(target);
2302
2303         if (xscale->dbr_available < 1) {
2304                 LOG_ERROR("no more watchpoint registers available");
2305                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2306         }
2307
2308         if (watchpoint->value)
2309                 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2310
2311         /* check that length is a power of two */
2312         for (uint32_t len = watchpoint->length; len != 1; len /= 2) {
2313                 if (len % 2) {
2314                         LOG_ERROR("xscale requires that watchpoint length is a power of two");
2315                         return ERROR_COMMAND_ARGUMENT_INVALID;
2316                 }
2317         }
2318
2319         if (watchpoint->length == 4) {  /* single word watchpoint */
2320                 xscale->dbr_available--;/* one DBR reg used */
2321                 return ERROR_OK;
2322         }
2323
2324         /* watchpoints across multiple words require both DBR registers */
2325         if (xscale->dbr_available < 2) {
2326                 LOG_ERROR("insufficient watchpoint registers available");
2327                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2328         }
2329
2330         if (watchpoint->length > watchpoint->address) {
2331                 LOG_ERROR("xscale does not support watchpoints with length "
2332                         "greater than address");
2333                 return ERROR_COMMAND_ARGUMENT_INVALID;
2334         }
2335
2336         xscale->dbr_available = 0;
2337         return ERROR_OK;
2338 }
2339
2340 static int xscale_unset_watchpoint(struct target *target,
2341         struct watchpoint *watchpoint)
2342 {
2343         struct xscale_common *xscale = target_to_xscale(target);
2344         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2345         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2346
2347         if (target->state != TARGET_HALTED) {
2348                 LOG_WARNING("target not halted");
2349                 return ERROR_TARGET_NOT_HALTED;
2350         }
2351
2352         if (!watchpoint->set) {
2353                 LOG_WARNING("breakpoint not set");
2354                 return ERROR_OK;
2355         }
2356
2357         if (watchpoint->set == 1) {
2358                 if (watchpoint->length > 4) {
2359                         dbcon_value &= ~0x103;  /* clear DBCON[M] as well */
2360                         xscale->dbr1_used = 0;  /* DBR1 was used for mask */
2361                 } else
2362                         dbcon_value &= ~0x3;
2363
2364                 xscale_set_reg_u32(dbcon, dbcon_value);
2365                 xscale->dbr0_used = 0;
2366         } else if (watchpoint->set == 2) {
2367                 dbcon_value &= ~0xc;
2368                 xscale_set_reg_u32(dbcon, dbcon_value);
2369                 xscale->dbr1_used = 0;
2370         }
2371         watchpoint->set = 0;
2372
2373         return ERROR_OK;
2374 }
2375
2376 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2377 {
2378         struct xscale_common *xscale = target_to_xscale(target);
2379
2380         if (target->state != TARGET_HALTED) {
2381                 LOG_ERROR("target not halted");
2382                 return ERROR_TARGET_NOT_HALTED;
2383         }
2384
2385         if (watchpoint->set)
2386                 xscale_unset_watchpoint(target, watchpoint);
2387
2388         if (watchpoint->length > 4)
2389                 xscale->dbr_available++;/* both DBR regs now available */
2390
2391         xscale->dbr_available++;
2392
2393         return ERROR_OK;
2394 }
2395
2396 static int xscale_get_reg(struct reg *reg)
2397 {
2398         struct xscale_reg *arch_info = reg->arch_info;
2399         struct target *target = arch_info->target;
2400         struct xscale_common *xscale = target_to_xscale(target);
2401
2402         /* DCSR, TX and RX are accessible via JTAG */
2403         if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2404                 return xscale_read_dcsr(arch_info->target);
2405         else if (strcmp(reg->name, "XSCALE_TX") == 0) {
2406                 /* 1 = consume register content */
2407                 return xscale_read_tx(arch_info->target, 1);
2408         } else if (strcmp(reg->name, "XSCALE_RX") == 0) {
2409                 /* can't read from RX register (host -> debug handler) */
2410                 return ERROR_OK;
2411         } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
2412                 /* can't (explicitly) read from TXRXCTRL register */
2413                 return ERROR_OK;
2414         } else {/* Other DBG registers have to be transfered by the debug handler
2415                  * send CP read request (command 0x40) */
2416                 xscale_send_u32(target, 0x40);
2417
2418                 /* send CP register number */
2419                 xscale_send_u32(target, arch_info->dbg_handler_number);
2420
2421                 /* read register value */
2422                 xscale_read_tx(target, 1);
2423                 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2424
2425                 reg->dirty = 0;
2426                 reg->valid = 1;
2427         }
2428
2429         return ERROR_OK;
2430 }
2431
2432 static int xscale_set_reg(struct reg *reg, uint8_t *buf)
2433 {
2434         struct xscale_reg *arch_info = reg->arch_info;
2435         struct target *target = arch_info->target;
2436         struct xscale_common *xscale = target_to_xscale(target);
2437         uint32_t value = buf_get_u32(buf, 0, 32);
2438
2439         /* DCSR, TX and RX are accessible via JTAG */
2440         if (strcmp(reg->name, "XSCALE_DCSR") == 0) {
2441                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2442                 return xscale_write_dcsr(arch_info->target, -1, -1);
2443         } else if (strcmp(reg->name, "XSCALE_RX") == 0) {
2444                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2445                 return xscale_write_rx(arch_info->target);
2446         } else if (strcmp(reg->name, "XSCALE_TX") == 0) {
2447                 /* can't write to TX register (debug-handler -> host) */
2448                 return ERROR_OK;
2449         } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
2450                 /* can't (explicitly) write to TXRXCTRL register */
2451                 return ERROR_OK;
2452         } else {/* Other DBG registers have to be transfered by the debug handler
2453                  * send CP write request (command 0x41) */
2454                 xscale_send_u32(target, 0x41);
2455
2456                 /* send CP register number */
2457                 xscale_send_u32(target, arch_info->dbg_handler_number);
2458
2459                 /* send CP register value */
2460                 xscale_send_u32(target, value);
2461                 buf_set_u32(reg->value, 0, 32, value);
2462         }
2463
2464         return ERROR_OK;
2465 }
2466
2467 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2468 {
2469         struct xscale_common *xscale = target_to_xscale(target);
2470         struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2471         struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2472
2473         /* send CP write request (command 0x41) */
2474         xscale_send_u32(target, 0x41);
2475
2476         /* send CP register number */
2477         xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2478
2479         /* send CP register value */
2480         xscale_send_u32(target, value);
2481         buf_set_u32(dcsr->value, 0, 32, value);
2482
2483         return ERROR_OK;
2484 }
2485
2486 static int xscale_read_trace(struct target *target)
2487 {
2488         struct xscale_common *xscale = target_to_xscale(target);
2489         struct arm *arm = &xscale->arm;
2490         struct xscale_trace_data **trace_data_p;
2491
2492         /* 258 words from debug handler
2493          * 256 trace buffer entries
2494          * 2 checkpoint addresses
2495          */
2496         uint32_t trace_buffer[258];
2497         int is_address[256];
2498         int i, j;
2499         unsigned int num_checkpoints = 0;
2500
2501         if (target->state != TARGET_HALTED) {
2502                 LOG_WARNING("target must be stopped to read trace data");
2503                 return ERROR_TARGET_NOT_HALTED;
2504         }
2505
2506         /* send read trace buffer command (command 0x61) */
2507         xscale_send_u32(target, 0x61);
2508
2509         /* receive trace buffer content */
2510         xscale_receive(target, trace_buffer, 258);
2511
2512         /* parse buffer backwards to identify address entries */
2513         for (i = 255; i >= 0; i--) {
2514                 /* also count number of checkpointed entries */
2515                 if ((trace_buffer[i] & 0xe0) == 0xc0)
2516                         num_checkpoints++;
2517
2518                 is_address[i] = 0;
2519                 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2520                         ((trace_buffer[i] & 0xf0) == 0xd0)) {
2521                         if (i > 0)
2522                                 is_address[--i] = 1;
2523                         if (i > 0)
2524                                 is_address[--i] = 1;
2525                         if (i > 0)
2526                                 is_address[--i] = 1;
2527                         if (i > 0)
2528                                 is_address[--i] = 1;
2529                 }
2530         }
2531
2532
2533         /* search first non-zero entry that is not part of an address */
2534         for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2535                 ;
2536
2537         if (j == 256) {
2538                 LOG_DEBUG("no trace data collected");
2539                 return ERROR_XSCALE_NO_TRACE_DATA;
2540         }
2541
2542         /* account for possible partial address at buffer start (wrap mode only) */
2543         if (is_address[0]) {    /* first entry is address; complete set of 4? */
2544                 i = 1;
2545                 while (i < 4)
2546                         if (!is_address[i++])
2547                                 break;
2548                 if (i < 4)
2549                         j += i;         /* partial address; can't use it */
2550         }
2551
2552         /* if first valid entry is indirect branch, can't use that either (no address) */
2553         if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2554                 j++;
2555
2556         /* walk linked list to terminating entry */
2557         for (trace_data_p = &xscale->trace.data; *trace_data_p;
2558                 trace_data_p = &(*trace_data_p)->next)
2559                 ;
2560
2561         *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2562         (*trace_data_p)->next = NULL;
2563         (*trace_data_p)->chkpt0 = trace_buffer[256];
2564         (*trace_data_p)->chkpt1 = trace_buffer[257];
2565         (*trace_data_p)->last_instruction = buf_get_u32(arm->pc->value, 0, 32);
2566         (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2567         (*trace_data_p)->depth = 256 - j;
2568         (*trace_data_p)->num_checkpoints = num_checkpoints;
2569
2570         for (i = j; i < 256; i++) {
2571                 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2572                 if (is_address[i])
2573                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2574                 else
2575                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2576         }
2577
2578         return ERROR_OK;
2579 }
2580
2581 static int xscale_read_instruction(struct target *target, uint32_t pc,
2582         struct arm_instruction *instruction)
2583 {
2584         struct xscale_common *const xscale = target_to_xscale(target);
2585         int i;
2586         int section = -1;
2587         size_t size_read;
2588         uint32_t opcode;
2589         int retval;
2590
2591         if (!xscale->trace.image)
2592                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2593
2594         /* search for the section the current instruction belongs to */
2595         for (i = 0; i < xscale->trace.image->num_sections; i++) {
2596                 if ((xscale->trace.image->sections[i].base_address <= pc) &&
2597                         (xscale->trace.image->sections[i].base_address +
2598                         xscale->trace.image->sections[i].size > pc)) {
2599                         section = i;
2600                         break;
2601                 }
2602         }
2603
2604         if (section == -1) {
2605                 /* current instruction couldn't be found in the image */
2606                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2607         }
2608
2609         if (xscale->trace.core_state == ARM_STATE_ARM) {
2610                 uint8_t buf[4];
2611                 retval = image_read_section(xscale->trace.image, section,
2612                                 pc - xscale->trace.image->sections[section].base_address,
2613                                 4, buf, &size_read);
2614                 if (retval != ERROR_OK) {
2615                         LOG_ERROR("error while reading instruction");
2616                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2617                 }
2618                 opcode = target_buffer_get_u32(target, buf);
2619                 arm_evaluate_opcode(opcode, pc, instruction);
2620         } else if (xscale->trace.core_state == ARM_STATE_THUMB) {
2621                 uint8_t buf[2];
2622                 retval = image_read_section(xscale->trace.image, section,
2623                                 pc - xscale->trace.image->sections[section].base_address,
2624                                 2, buf, &size_read);
2625                 if (retval != ERROR_OK) {
2626                         LOG_ERROR("error while reading instruction");
2627                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2628                 }
2629                 opcode = target_buffer_get_u16(target, buf);
2630                 thumb_evaluate_opcode(opcode, pc, instruction);
2631         } else {
2632                 LOG_ERROR("BUG: unknown core state encountered");
2633                 exit(-1);
2634         }
2635
2636         return ERROR_OK;
2637 }
2638
2639 /* Extract address encoded into trace data.
2640  * Write result to address referenced by argument 'target', or 0 if incomplete.  */
2641 static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
2642         int i, uint32_t *target)
2643 {
2644         /* if there are less than four entries prior to the indirect branch message
2645          * we can't extract the address */
2646         if (i < 4)
2647                 *target = 0;
2648         else {
2649                 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2650                         (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2651         }
2652 }
2653
2654 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
2655         struct arm_instruction *instruction,
2656         struct command_context *cmd_ctx)
2657 {
2658         int retval = xscale_read_instruction(target, pc, instruction);
2659         if (retval == ERROR_OK)
2660                 command_print(cmd_ctx, "%s", instruction->text);
2661         else
2662                 command_print(cmd_ctx, "0x%8.8" PRIx32 "\t<not found in image>", pc);
2663 }
2664
2665 static int xscale_analyze_trace(struct target *target, struct command_context *cmd_ctx)
2666 {
2667         struct xscale_common *xscale = target_to_xscale(target);
2668         struct xscale_trace_data *trace_data = xscale->trace.data;
2669         int i, retval;
2670         uint32_t breakpoint_pc;
2671         struct arm_instruction instruction;
2672         uint32_t current_pc = 0;/* initialized when address determined */
2673
2674         if (!xscale->trace.image)
2675                 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2676
2677         /* loop for each trace buffer that was loaded from target */
2678         while (trace_data) {
2679                 int chkpt = 0;  /* incremented as checkpointed entries found */
2680                 int j;
2681
2682                 /* FIXME: set this to correct mode when trace buffer is first enabled */
2683                 xscale->trace.core_state = ARM_STATE_ARM;
2684
2685                 /* loop for each entry in this trace buffer */
2686                 for (i = 0; i < trace_data->depth; i++) {
2687                         int exception = 0;
2688                         uint32_t chkpt_reg = 0x0;
2689                         uint32_t branch_target = 0;
2690                         int count;
2691
2692                         /* trace entry type is upper nybble of 'message byte' */
2693                         int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
2694
2695                         /* Target addresses of indirect branches are written into buffer
2696                          * before the message byte representing the branch. Skip past it */
2697                         if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2698                                 continue;
2699
2700                         switch (trace_msg_type) {
2701                                 case 0: /* Exceptions */
2702                                 case 1:
2703                                 case 2:
2704                                 case 3:
2705                                 case 4:
2706                                 case 5:
2707                                 case 6:
2708                                 case 7:
2709                                         exception = (trace_data->entries[i].data & 0x70) >> 4;
2710
2711                                         /* FIXME: vector table may be at ffff0000 */
2712                                         branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
2713                                         break;
2714
2715                                 case 8: /* Direct Branch */
2716                                         break;
2717
2718                                 case 9: /* Indirect Branch */
2719                                         xscale_branch_address(trace_data, i, &branch_target);
2720                                         break;
2721
2722                                 case 13:        /* Checkpointed Indirect Branch */
2723                                         xscale_branch_address(trace_data, i, &branch_target);
2724                                         if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2725                                                 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
2726                                                                                  *oldest */
2727                                         else
2728                                                 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
2729                                                                                  *newest */
2730
2731                                         chkpt++;
2732                                         break;
2733
2734                                 case 12:        /* Checkpointed Direct Branch */
2735                                         if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2736                                                 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
2737                                                                                  *oldest */
2738                                         else
2739                                                 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
2740                                                                                  *newest */
2741
2742                                         /* if no current_pc, checkpoint will be starting point */
2743                                         if (current_pc == 0)
2744                                                 branch_target = chkpt_reg;
2745
2746                                         chkpt++;
2747                                         break;
2748
2749                                 case 15:/* Roll-over */
2750                                         break;
2751
2752                                 default:/* Reserved */
2753                                         LOG_WARNING("trace is suspect: invalid trace message byte");
2754                                         continue;
2755
2756                         }
2757
2758                         /* If we don't have the current_pc yet, but we did get the branch target
2759                          * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2760                          * then we can start displaying instructions at the next iteration, with
2761                          * branch_target as the starting point.
2762                          */
2763                         if (current_pc == 0) {
2764                                 current_pc = branch_target;     /* remains 0 unless branch_target *obtained */
2765                                 continue;
2766                         }
2767
2768                         /* We have current_pc.  Read and display the instructions from the image.
2769                          * First, display count instructions (lower nybble of message byte). */
2770                         count = trace_data->entries[i].data & 0x0f;
2771                         for (j = 0; j < count; j++) {
2772                                 xscale_display_instruction(target, current_pc, &instruction,
2773                                         cmd_ctx);
2774                                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2775                         }
2776
2777                         /* An additional instruction is implicitly added to count for
2778                          * rollover and some exceptions: undef, swi, prefetch abort. */
2779                         if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) {
2780                                 xscale_display_instruction(target, current_pc, &instruction,
2781                                         cmd_ctx);
2782                                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2783                         }
2784
2785                         if (trace_msg_type == 15)       /* rollover */
2786                                 continue;
2787
2788                         if (exception) {
2789                                 command_print(cmd_ctx, "--- exception %i ---", exception);
2790                                 continue;
2791                         }
2792
2793                         /* not exception or rollover; next instruction is a branch and is
2794                          * not included in the count */
2795                         xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2796
2797                         /* for direct branches, extract branch destination from instruction */
2798                         if ((trace_msg_type == 8) || (trace_msg_type == 12)) {
2799                                 retval = xscale_read_instruction(target, current_pc, &instruction);
2800                                 if (retval == ERROR_OK)
2801                                         current_pc = instruction.info.b_bl_bx_blx.target_address;
2802                                 else
2803                                         current_pc = 0; /* branch destination unknown */
2804
2805                                 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2806                                 if (trace_msg_type == 12) {
2807                                         if (current_pc == 0)
2808                                                 current_pc = chkpt_reg;
2809                                         else if (current_pc != chkpt_reg)       /* sanity check */
2810                                                 LOG_WARNING("trace is suspect: checkpoint register "
2811                                                         "inconsistent with adddress from image");
2812                                 }
2813
2814                                 if (current_pc == 0)
2815                                         command_print(cmd_ctx, "address unknown");
2816
2817                                 continue;
2818                         }
2819
2820                         /* indirect branch; the branch destination was read from trace buffer */
2821                         if ((trace_msg_type == 9) || (trace_msg_type == 13)) {
2822                                 current_pc = branch_target;
2823
2824                                 /* sanity check (checkpoint reg is redundant) */
2825                                 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2826                                         LOG_WARNING("trace is suspect: checkpoint register "
2827                                                 "inconsistent with address from trace buffer");
2828                         }
2829
2830                 }       /* END: for (i = 0; i < trace_data->depth; i++) */
2831
2832                 breakpoint_pc = trace_data->last_instruction;   /* used below */
2833                 trace_data = trace_data->next;
2834
2835         }       /* END: while (trace_data) */
2836
2837         /* Finally... display all instructions up to the value of the pc when the
2838          * debug break occurred (saved when trace data was collected from target).
2839          * This is necessary because the trace only records execution branches and 16
2840          * consecutive instructions (rollovers), so last few typically missed.
2841          */
2842         if (current_pc == 0)
2843                 return ERROR_OK;/* current_pc was never found */
2844
2845         /* how many instructions remaining? */
2846         int gap_count = (breakpoint_pc - current_pc) /
2847                 (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
2848
2849         /* should never be negative or over 16, but verify */
2850         if (gap_count < 0 || gap_count > 16) {
2851                 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2852                 return ERROR_OK;/* bail; large number or negative value no good */
2853         }
2854
2855         /* display remaining instructions */
2856         for (i = 0; i < gap_count; i++) {
2857                 xscale_display_instruction(target, current_pc, &instruction, cmd_ctx);
2858                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2859         }
2860
2861         return ERROR_OK;
2862 }
2863
2864 static const struct reg_arch_type xscale_reg_type = {
2865         .get = xscale_get_reg,
2866         .set = xscale_set_reg,
2867 };
2868
2869 static void xscale_build_reg_cache(struct target *target)
2870 {
2871         struct xscale_common *xscale = target_to_xscale(target);
2872         struct arm *arm = &xscale->arm;
2873         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2874         struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2875         int i;
2876         int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
2877
2878         (*cache_p) = arm_build_reg_cache(target, arm);
2879
2880         (*cache_p)->next = malloc(sizeof(struct reg_cache));
2881         cache_p = &(*cache_p)->next;
2882
2883         /* fill in values for the xscale reg cache */
2884         (*cache_p)->name = "XScale registers";
2885         (*cache_p)->next = NULL;
2886         (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
2887         (*cache_p)->num_regs = num_regs;
2888
2889         for (i = 0; i < num_regs; i++) {
2890                 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2891                 (*cache_p)->reg_list[i].value = calloc(4, 1);
2892                 (*cache_p)->reg_list[i].dirty = 0;
2893                 (*cache_p)->reg_list[i].valid = 0;
2894                 (*cache_p)->reg_list[i].size = 32;
2895                 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2896                 (*cache_p)->reg_list[i].type = &xscale_reg_type;
2897                 arch_info[i] = xscale_reg_arch_info[i];
2898                 arch_info[i].target = target;
2899         }
2900
2901         xscale->reg_cache = (*cache_p);
2902 }
2903
2904 static int xscale_init_target(struct command_context *cmd_ctx,
2905         struct target *target)
2906 {
2907         xscale_build_reg_cache(target);
2908         return ERROR_OK;
2909 }
2910
2911 static int xscale_init_arch_info(struct target *target,
2912         struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
2913 {
2914         struct arm *arm;
2915         uint32_t high_reset_branch, low_reset_branch;
2916         int i;
2917
2918         arm = &xscale->arm;
2919
2920         /* store architecture specfic data */
2921         xscale->common_magic = XSCALE_COMMON_MAGIC;
2922
2923         /* we don't really *need* a variant param ... */
2924         if (variant) {
2925                 int ir_length = 0;
2926
2927                 if (strcmp(variant, "pxa250") == 0
2928                         || strcmp(variant, "pxa255") == 0
2929                         || strcmp(variant, "pxa26x") == 0)
2930                         ir_length = 5;
2931                 else if (strcmp(variant, "pxa27x") == 0
2932                         || strcmp(variant, "ixp42x") == 0
2933                         || strcmp(variant, "ixp45x") == 0
2934                         || strcmp(variant, "ixp46x") == 0)
2935                         ir_length = 7;
2936                 else if (strcmp(variant, "pxa3xx") == 0)
2937                         ir_length = 11;
2938                 else
2939                         LOG_WARNING("%s: unrecognized variant %s",
2940                                 tap->dotted_name, variant);
2941
2942                 if (ir_length && ir_length != tap->ir_length) {
2943                         LOG_WARNING("%s: IR length for %s is %d; fixing",
2944                                 tap->dotted_name, variant, ir_length);
2945                         tap->ir_length = ir_length;
2946                 }
2947         }
2948
2949         /* PXA3xx shifts the JTAG instructions */
2950         if (tap->ir_length == 11)
2951                 xscale->xscale_variant = XSCALE_PXA3XX;
2952         else
2953                 xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
2954
2955         /* the debug handler isn't installed (and thus not running) at this time */
2956         xscale->handler_address = 0xfe000800;
2957
2958         /* clear the vectors we keep locally for reference */
2959         memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
2960         memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
2961
2962         /* no user-specified vectors have been configured yet */
2963         xscale->static_low_vectors_set = 0x0;
2964         xscale->static_high_vectors_set = 0x0;
2965
2966         /* calculate branches to debug handler */
2967         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
2968         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
2969
2970         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
2971         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
2972
2973         for (i = 1; i <= 7; i++) {
2974                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2975                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2976         }
2977
2978         /* 64kB aligned region used for DCache cleaning */
2979         xscale->cache_clean_address = 0xfffe0000;
2980
2981         xscale->hold_rst = 0;
2982         xscale->external_debug_break = 0;
2983
2984         xscale->ibcr_available = 2;
2985         xscale->ibcr0_used = 0;
2986         xscale->ibcr1_used = 0;
2987
2988         xscale->dbr_available = 2;
2989         xscale->dbr0_used = 0;
2990         xscale->dbr1_used = 0;
2991
2992         LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
2993                 target_name(target));
2994
2995         xscale->arm_bkpt = ARMV5_BKPT(0x0);
2996         xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
2997
2998         xscale->vector_catch = 0x1;
2999
3000         xscale->trace.data = NULL;
3001         xscale->trace.image = NULL;
3002         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3003         xscale->trace.buffer_fill = 0;
3004         xscale->trace.fill_counter = 0;
3005
3006         /* prepare ARMv4/5 specific information */
3007         arm->arch_info = xscale;
3008         arm->core_type = ARM_MODE_ANY;
3009         arm->read_core_reg = xscale_read_core_reg;
3010         arm->write_core_reg = xscale_write_core_reg;
3011         arm->full_context = xscale_full_context;
3012
3013         arm_init_arch_info(target, arm);
3014
3015         xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3016         xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3017         xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3018         xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3019         xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3020         xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3021         xscale->armv4_5_mmu.has_tiny_pages = 1;
3022         xscale->armv4_5_mmu.mmu_enabled = 0;
3023
3024         return ERROR_OK;
3025 }
3026
3027 static int xscale_target_create(struct target *target, Jim_Interp *interp)
3028 {
3029         struct xscale_common *xscale;
3030
3031         if (sizeof xscale_debug_handler - 1 > 0x800) {
3032                 LOG_ERROR("debug_handler.bin: larger than 2kb");
3033                 return ERROR_FAIL;
3034         }
3035
3036         xscale = calloc(1, sizeof(*xscale));
3037         if (!xscale)
3038                 return ERROR_FAIL;
3039
3040         return xscale_init_arch_info(target, xscale, target->tap,
3041                         target->variant);
3042 }
3043
3044 COMMAND_HANDLER(xscale_handle_debug_handler_command)
3045 {
3046         struct target *target = NULL;
3047         struct xscale_common *xscale;
3048         int retval;
3049         uint32_t handler_address;
3050
3051         if (CMD_ARGC < 2)
3052                 return ERROR_COMMAND_SYNTAX_ERROR;
3053
3054         target = get_target(CMD_ARGV[0]);
3055         if (target == NULL) {
3056                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3057                 return ERROR_FAIL;
3058         }
3059
3060         xscale = target_to_xscale(target);
3061         retval = xscale_verify_pointer(CMD_CTX, xscale);
3062         if (retval != ERROR_OK)
3063                 return retval;
3064
3065         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
3066
3067         if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3068                 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3069                 xscale->handler_address = handler_address;
3070         else {
3071                 LOG_ERROR(
3072                         "xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3073                 return ERROR_FAIL;
3074         }
3075
3076         return ERROR_OK;
3077 }
3078
3079 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3080 {
3081         struct target *target = NULL;
3082         struct xscale_common *xscale;
3083         int retval;
3084         uint32_t cache_clean_address;
3085
3086         if (CMD_ARGC < 2)
3087                 return ERROR_COMMAND_SYNTAX_ERROR;
3088
3089         target = get_target(CMD_ARGV[0]);
3090         if (target == NULL) {
3091                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3092                 return ERROR_FAIL;
3093         }
3094         xscale = target_to_xscale(target);
3095         retval = xscale_verify_pointer(CMD_CTX, xscale);
3096         if (retval != ERROR_OK)
3097                 return retval;
3098
3099         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
3100
3101         if (cache_clean_address & 0xffff)
3102                 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3103         else
3104                 xscale->cache_clean_address = cache_clean_address;
3105
3106         return ERROR_OK;
3107 }
3108
3109 COMMAND_HANDLER(xscale_handle_cache_info_command)
3110 {
3111         struct target *target = get_current_target(CMD_CTX);
3112         struct xscale_common *xscale = target_to_xscale(target);
3113         int retval;
3114
3115         retval = xscale_verify_pointer(CMD_CTX, xscale);
3116         if (retval != ERROR_OK)
3117                 return retval;
3118
3119         return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
3120 }
3121
3122 static int xscale_virt2phys(struct target *target,
3123         uint32_t virtual, uint32_t *physical)
3124 {
3125         struct xscale_common *xscale = target_to_xscale(target);
3126         uint32_t cb;
3127
3128         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3129                 LOG_ERROR(xscale_not);
3130                 return ERROR_TARGET_INVALID;
3131         }
3132
3133         uint32_t ret;
3134         int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
3135                         virtual, &cb, &ret);
3136         if (retval != ERROR_OK)
3137                 return retval;
3138         *physical = ret;
3139         return ERROR_OK;
3140 }
3141
3142 static int xscale_mmu(struct target *target, int *enabled)
3143 {
3144         struct xscale_common *xscale = target_to_xscale(target);
3145
3146         if (target->state != TARGET_HALTED) {
3147                 LOG_ERROR("Target not halted");
3148                 return ERROR_TARGET_INVALID;
3149         }
3150         *enabled = xscale->armv4_5_mmu.mmu_enabled;
3151         return ERROR_OK;
3152 }
3153
3154 COMMAND_HANDLER(xscale_handle_mmu_command)
3155 {
3156         struct target *target = get_current_target(CMD_CTX);
3157         struct xscale_common *xscale = target_to_xscale(target);
3158         int retval;
3159
3160         retval = xscale_verify_pointer(CMD_CTX, xscale);
3161         if (retval != ERROR_OK)
3162                 return retval;
3163
3164         if (target->state != TARGET_HALTED) {
3165                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3166                 return ERROR_OK;
3167         }
3168
3169         if (CMD_ARGC >= 1) {
3170                 bool enable;
3171                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3172                 if (enable)
3173                         xscale_enable_mmu_caches(target, 1, 0, 0);
3174                 else
3175                         xscale_disable_mmu_caches(target, 1, 0, 0);
3176                 xscale->armv4_5_mmu.mmu_enabled = enable;
3177         }
3178
3179         command_print(CMD_CTX, "mmu %s",
3180                 (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3181
3182         return ERROR_OK;
3183 }
3184
3185 COMMAND_HANDLER(xscale_handle_idcache_command)
3186 {
3187         struct target *target = get_current_target(CMD_CTX);
3188         struct xscale_common *xscale = target_to_xscale(target);
3189
3190         int retval = xscale_verify_pointer(CMD_CTX, xscale);
3191         if (retval != ERROR_OK)
3192                 return retval;
3193
3194         if (target->state != TARGET_HALTED) {
3195                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3196                 return ERROR_OK;
3197         }
3198
3199         bool icache = false;
3200         if (strcmp(CMD_NAME, "icache") == 0)
3201                 icache = true;
3202         if (CMD_ARGC >= 1) {
3203                 bool enable;
3204                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3205                 if (icache) {
3206                         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
3207                         if (enable)
3208                                 xscale_enable_mmu_caches(target, 0, 0, 1);
3209                         else
3210                                 xscale_disable_mmu_caches(target, 0, 0, 1);
3211                 } else {
3212                         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
3213                         if (enable)
3214                                 xscale_enable_mmu_caches(target, 0, 1, 0);
3215                         else
3216                                 xscale_disable_mmu_caches(target, 0, 1, 0);
3217                 }
3218         }
3219
3220         bool enabled = icache ?
3221                 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
3222                 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
3223         const char *msg = enabled ? "enabled" : "disabled";
3224         command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
3225
3226         return ERROR_OK;
3227 }
3228
3229 static const struct {
3230         char name[15];
3231         unsigned mask;
3232 } vec_ids[] = {
3233         { "fiq",                DCSR_TF, },
3234         { "irq",                DCSR_TI, },
3235         { "dabt",               DCSR_TD, },
3236         { "pabt",               DCSR_TA, },
3237         { "swi",                DCSR_TS, },
3238         { "undef",              DCSR_TU, },
3239         { "reset",              DCSR_TR, },
3240 };
3241
3242 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3243 {
3244         struct target *target = get_current_target(CMD_CTX);
3245         struct xscale_common *xscale = target_to_xscale(target);
3246         int retval;
3247         uint32_t dcsr_value;
3248         uint32_t catch = 0;
3249         struct reg *dcsr_reg = &xscale->reg_cache->reg_list[XSCALE_DCSR];
3250
3251         retval = xscale_verify_pointer(CMD_CTX, xscale);
3252         if (retval != ERROR_OK)
3253                 return retval;
3254
3255         dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
3256         if (CMD_ARGC > 0) {
3257                 if (CMD_ARGC == 1) {
3258                         if (strcmp(CMD_ARGV[0], "all") == 0) {
3259                                 catch = DCSR_TRAP_MASK;
3260                                 CMD_ARGC--;
3261                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
3262                                 catch = 0;
3263                                 CMD_ARGC--;
3264                         }
3265                 }
3266                 while (CMD_ARGC-- > 0) {
3267                         unsigned i;
3268                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
3269                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name))
3270                                         continue;
3271                                 catch |= vec_ids[i].mask;
3272                                 break;
3273                         }
3274                         if (i == ARRAY_SIZE(vec_ids)) {
3275                                 LOG_ERROR("No vector '%s'", CMD_ARGV[CMD_ARGC]);
3276                                 return ERROR_COMMAND_SYNTAX_ERROR;
3277                         }
3278                 }
3279                 *(uint32_t *)(dcsr_reg->value) &= ~DCSR_TRAP_MASK;
3280                 *(uint32_t *)(dcsr_reg->value) |= catch;
3281                 xscale_write_dcsr(target, -1, -1);
3282         }
3283
3284         dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
3285         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
3286                 command_print(CMD_CTX, "%15s: %s", vec_ids[i].name,
3287                         (dcsr_value & vec_ids[i].mask) ? "catch" : "ignore");
3288         }
3289
3290         return ERROR_OK;
3291 }
3292
3293
3294 COMMAND_HANDLER(xscale_handle_vector_table_command)
3295 {
3296         struct target *target = get_current_target(CMD_CTX);
3297         struct xscale_common *xscale = target_to_xscale(target);
3298         int err = 0;
3299         int retval;
3300
3301         retval = xscale_verify_pointer(CMD_CTX, xscale);
3302         if (retval != ERROR_OK)
3303                 return retval;
3304
3305         if (CMD_ARGC == 0) {    /* print current settings */
3306                 int idx;
3307
3308                 command_print(CMD_CTX, "active user-set static vectors:");
3309                 for (idx = 1; idx < 8; idx++)
3310                         if (xscale->static_low_vectors_set & (1 << idx))
3311                                 command_print(CMD_CTX,
3312                                         "low  %d: 0x%" PRIx32,
3313                                         idx,
3314                                         xscale->static_low_vectors[idx]);
3315                 for (idx = 1; idx < 8; idx++)
3316                         if (xscale->static_high_vectors_set & (1 << idx))
3317                                 command_print(CMD_CTX,
3318                                         "high %d: 0x%" PRIx32,
3319                                         idx,
3320                                         xscale->static_high_vectors[idx]);
3321                 return ERROR_OK;
3322         }
3323
3324         if (CMD_ARGC != 3)
3325                 err = 1;
3326         else {
3327                 int idx;
3328                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
3329                 uint32_t vec;
3330                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
3331
3332                 if (idx < 1 || idx >= 8)
3333                         err = 1;
3334
3335                 if (!err && strcmp(CMD_ARGV[0], "low") == 0) {
3336                         xscale->static_low_vectors_set |= (1<<idx);
3337                         xscale->static_low_vectors[idx] = vec;
3338                 } else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) {
3339                         xscale->static_high_vectors_set |= (1<<idx);
3340                         xscale->static_high_vectors[idx] = vec;
3341                 } else
3342                         err = 1;
3343         }
3344
3345         if (err)
3346                 return ERROR_COMMAND_SYNTAX_ERROR;
3347
3348         return ERROR_OK;
3349 }
3350
3351
3352 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3353 {
3354         struct target *target = get_current_target(CMD_CTX);
3355         struct xscale_common *xscale = target_to_xscale(target);
3356         uint32_t dcsr_value;
3357         int retval;
3358
3359         retval = xscale_verify_pointer(CMD_CTX, xscale);
3360         if (retval != ERROR_OK)
3361                 return retval;
3362
3363         if (target->state != TARGET_HALTED) {
3364                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3365                 return ERROR_OK;
3366         }
3367
3368         if (CMD_ARGC >= 1) {
3369                 if (strcmp("enable", CMD_ARGV[0]) == 0)
3370                         xscale->trace.mode = XSCALE_TRACE_WRAP; /* default */
3371                 else if (strcmp("disable", CMD_ARGV[0]) == 0)
3372                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3373                 else
3374                         return ERROR_COMMAND_SYNTAX_ERROR;
3375         }
3376
3377         if (CMD_ARGC >= 2 && xscale->trace.mode != XSCALE_TRACE_DISABLED) {
3378                 if (strcmp("fill", CMD_ARGV[1]) == 0) {
3379                         int buffcount = 1;              /* default */
3380                         if (CMD_ARGC >= 3)
3381                                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount);
3382                         if (buffcount < 1) {            /* invalid */
3383                                 command_print(CMD_CTX, "fill buffer count must be > 0");
3384                                 xscale->trace.mode = XSCALE_TRACE_DISABLED;
3385                                 return ERROR_COMMAND_SYNTAX_ERROR;
3386                         }
3387                         xscale->trace.buffer_fill = buffcount;
3388                         xscale->trace.mode = XSCALE_TRACE_FILL;
3389                 } else if (strcmp("wrap", CMD_ARGV[1]) == 0)
3390                         xscale->trace.mode = XSCALE_TRACE_WRAP;
3391                 else {
3392                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3393                         return ERROR_COMMAND_SYNTAX_ERROR;
3394                 }
3395         }
3396
3397         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
3398                 char fill_string[12];
3399                 sprintf(fill_string, "fill %d", xscale->trace.buffer_fill);
3400                 command_print(CMD_CTX, "trace buffer enabled (%s)",
3401                         (xscale->trace.mode == XSCALE_TRACE_FILL)
3402                         ? fill_string : "wrap");
3403         } else
3404                 command_print(CMD_CTX, "trace buffer disabled");
3405
3406         dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3407         if (xscale->trace.mode == XSCALE_TRACE_FILL)
3408                 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3409         else
3410                 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3411
3412         return ERROR_OK;
3413 }
3414
3415 COMMAND_HANDLER(xscale_handle_trace_image_command)
3416 {
3417         struct target *target = get_current_target(CMD_CTX);
3418         struct xscale_common *xscale = target_to_xscale(target);
3419         int retval;
3420
3421         if (CMD_ARGC < 1)
3422                 return ERROR_COMMAND_SYNTAX_ERROR;
3423
3424         retval = xscale_verify_pointer(CMD_CTX, xscale);
3425         if (retval != ERROR_OK)
3426                 return retval;
3427
3428         if (xscale->trace.image) {
3429                 image_close(xscale->trace.image);
3430                 free(xscale->trace.image);
3431                 command_print(CMD_CTX, "previously loaded image found and closed");
3432         }
3433
3434         xscale->trace.image = malloc(sizeof(struct image));
3435         xscale->trace.image->base_address_set = 0;
3436         xscale->trace.image->start_address_set = 0;
3437
3438         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3439         if (CMD_ARGC >= 2) {
3440                 xscale->trace.image->base_address_set = 1;
3441                 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
3442         } else
3443                 xscale->trace.image->base_address_set = 0;
3444
3445         if (image_open(xscale->trace.image, CMD_ARGV[0],
3446                 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
3447                 free(xscale->trace.image);
3448                 xscale->trace.image = NULL;
3449                 return ERROR_OK;
3450         }
3451
3452         return ERROR_OK;
3453 }
3454
3455 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3456 {
3457         struct target *target = get_current_target(CMD_CTX);
3458         struct xscale_common *xscale = target_to_xscale(target);
3459         struct xscale_trace_data *trace_data;
3460         struct fileio file;
3461         int retval;
3462
3463         retval = xscale_verify_pointer(CMD_CTX, xscale);
3464         if (retval != ERROR_OK)
3465                 return retval;
3466
3467         if (target->state != TARGET_HALTED) {
3468                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3469                 return ERROR_OK;
3470         }
3471
3472         if (CMD_ARGC < 1)
3473                 return ERROR_COMMAND_SYNTAX_ERROR;
3474
3475         trace_data = xscale->trace.data;
3476
3477         if (!trace_data) {
3478                 command_print(CMD_CTX, "no trace data collected");
3479                 return ERROR_OK;
3480         }
3481
3482         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3483                 return ERROR_OK;
3484
3485         while (trace_data) {
3486                 int i;
3487
3488                 fileio_write_u32(&file, trace_data->chkpt0);
3489                 fileio_write_u32(&file, trace_data->chkpt1);
3490                 fileio_write_u32(&file, trace_data->last_instruction);
3491                 fileio_write_u32(&file, trace_data->depth);
3492
3493                 for (i = 0; i < trace_data->depth; i++)
3494                         fileio_write_u32(&file, trace_data->entries[i].data |
3495                                 ((trace_data->entries[i].type & 0xffff) << 16));
3496
3497                 trace_data = trace_data->next;
3498         }
3499
3500         fileio_close(&file);
3501
3502         return ERROR_OK;
3503 }
3504
3505 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3506 {
3507         struct target *target = get_current_target(CMD_CTX);
3508         struct xscale_common *xscale = target_to_xscale(target);
3509         int retval;
3510
3511         retval = xscale_verify_pointer(CMD_CTX, xscale);
3512         if (retval != ERROR_OK)
3513                 return retval;
3514
3515         xscale_analyze_trace(target, CMD_CTX);
3516
3517         return ERROR_OK;
3518 }
3519
3520 COMMAND_HANDLER(xscale_handle_cp15)
3521 {
3522         struct target *target = get_current_target(CMD_CTX);
3523         struct xscale_common *xscale = target_to_xscale(target);
3524         int retval;
3525
3526         retval = xscale_verify_pointer(CMD_CTX, xscale);
3527         if (retval != ERROR_OK)
3528                 return retval;
3529
3530         if (target->state != TARGET_HALTED) {
3531                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
3532                 return ERROR_OK;
3533         }
3534         uint32_t reg_no = 0;
3535         struct reg *reg = NULL;
3536         if (CMD_ARGC > 0) {
3537                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
3538                 /*translate from xscale cp15 register no to openocd register*/
3539                 switch (reg_no) {
3540                         case 0:
3541                                 reg_no = XSCALE_MAINID;
3542                                 break;
3543                         case 1:
3544                                 reg_no = XSCALE_CTRL;
3545                                 break;
3546                         case 2:
3547                                 reg_no = XSCALE_TTB;
3548                                 break;
3549                         case 3:
3550                                 reg_no = XSCALE_DAC;
3551                                 break;
3552                         case 5:
3553                                 reg_no = XSCALE_FSR;
3554                                 break;
3555                         case 6:
3556                                 reg_no = XSCALE_FAR;
3557                                 break;
3558                         case 13:
3559                                 reg_no = XSCALE_PID;
3560                                 break;
3561                         case 15:
3562                                 reg_no = XSCALE_CPACCESS;
3563                                 break;
3564                         default:
3565                                 command_print(CMD_CTX, "invalid register number");
3566                                 return ERROR_COMMAND_SYNTAX_ERROR;
3567                 }
3568                 reg = &xscale->reg_cache->reg_list[reg_no];
3569
3570         }
3571         if (CMD_ARGC == 1) {
3572                 uint32_t value;
3573
3574                 /* read cp15 control register */
3575                 xscale_get_reg(reg);
3576                 value = buf_get_u32(reg->value, 0, 32);
3577                 command_print(CMD_CTX, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
3578                         value);
3579         } else if (CMD_ARGC == 2) {
3580                 uint32_t value;
3581                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
3582
3583                 /* send CP write request (command 0x41) */
3584                 xscale_send_u32(target, 0x41);
3585
3586                 /* send CP register number */
3587                 xscale_send_u32(target, reg_no);
3588
3589                 /* send CP register value */
3590                 xscale_send_u32(target, value);
3591
3592                 /* execute cpwait to ensure outstanding operations complete */
3593                 xscale_send_u32(target, 0x53);
3594         } else
3595                 return ERROR_COMMAND_SYNTAX_ERROR;
3596
3597         return ERROR_OK;
3598 }
3599
3600 static const struct command_registration xscale_exec_command_handlers[] = {
3601         {
3602                 .name = "cache_info",
3603                 .handler = xscale_handle_cache_info_command,
3604                 .mode = COMMAND_EXEC,
3605                 .help = "display information about CPU caches",
3606         },
3607         {
3608                 .name = "mmu",
3609                 .handler = xscale_handle_mmu_command,
3610                 .mode = COMMAND_EXEC,
3611                 .help = "enable or disable the MMU",
3612                 .usage = "['enable'|'disable']",
3613         },
3614         {
3615                 .name = "icache",
3616                 .handler = xscale_handle_idcache_command,
3617                 .mode = COMMAND_EXEC,
3618                 .help = "display ICache state, optionally enabling or "
3619                         "disabling it",
3620                 .usage = "['enable'|'disable']",
3621         },
3622         {
3623                 .name = "dcache",
3624                 .handler = xscale_handle_idcache_command,
3625                 .mode = COMMAND_EXEC,
3626                 .help = "display DCache state, optionally enabling or "
3627                         "disabling it",
3628                 .usage = "['enable'|'disable']",
3629         },
3630         {
3631                 .name = "vector_catch",
3632                 .handler = xscale_handle_vector_catch_command,
3633                 .mode = COMMAND_EXEC,
3634                 .help = "set or display mask of vectors "
3635                         "that should trigger debug entry",
3636                 .usage = "['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']",
3637         },
3638         {
3639                 .name = "vector_table",
3640                 .handler = xscale_handle_vector_table_command,
3641                 .mode = COMMAND_EXEC,
3642                 .help = "set vector table entry in mini-ICache, "
3643                         "or display current tables",
3644                 .usage = "[('high'|'low') index code]",
3645         },
3646         {
3647                 .name = "trace_buffer",
3648                 .handler = xscale_handle_trace_buffer_command,
3649                 .mode = COMMAND_EXEC,
3650                 .help = "display trace buffer status, enable or disable "
3651                         "tracing, and optionally reconfigure trace mode",
3652                 .usage = "['enable'|'disable' ['fill' [number]|'wrap']]",
3653         },
3654         {
3655                 .name = "dump_trace",
3656                 .handler = xscale_handle_dump_trace_command,
3657                 .mode = COMMAND_EXEC,
3658                 .help = "dump content of trace buffer to file",
3659                 .usage = "filename",
3660         },
3661         {
3662                 .name = "analyze_trace",
3663                 .handler = xscale_handle_analyze_trace_buffer_command,
3664                 .mode = COMMAND_EXEC,
3665                 .help = "analyze content of trace buffer",
3666                 .usage = "",
3667         },
3668         {
3669                 .name = "trace_image",
3670                 .handler = xscale_handle_trace_image_command,
3671                 .mode = COMMAND_EXEC,
3672                 .help = "load image from file to address (default 0)",
3673                 .usage = "filename [offset [filetype]]",
3674         },
3675         {
3676                 .name = "cp15",
3677                 .handler = xscale_handle_cp15,
3678                 .mode = COMMAND_EXEC,
3679                 .help = "Read or write coprocessor 15 register.",
3680                 .usage = "register [value]",
3681         },
3682         COMMAND_REGISTRATION_DONE
3683 };
3684 static const struct command_registration xscale_any_command_handlers[] = {
3685         {
3686                 .name = "debug_handler",
3687                 .handler = xscale_handle_debug_handler_command,
3688                 .mode = COMMAND_ANY,
3689                 .help = "Change address used for debug handler.",
3690                 .usage = "<target> <address>",
3691         },
3692         {
3693                 .name = "cache_clean_address",
3694                 .handler = xscale_handle_cache_clean_address_command,
3695                 .mode = COMMAND_ANY,
3696                 .help = "Change address used for cleaning data cache.",
3697                 .usage = "address",
3698         },
3699         {
3700                 .chain = xscale_exec_command_handlers,
3701         },
3702         COMMAND_REGISTRATION_DONE
3703 };
3704 static const struct command_registration xscale_command_handlers[] = {
3705         {
3706                 .chain = arm_command_handlers,
3707         },
3708         {
3709                 .name = "xscale",
3710                 .mode = COMMAND_ANY,
3711                 .help = "xscale command group",
3712                 .usage = "",
3713                 .chain = xscale_any_command_handlers,
3714         },
3715         COMMAND_REGISTRATION_DONE
3716 };
3717
3718 struct target_type xscale_target = {
3719         .name = "xscale",
3720
3721         .poll = xscale_poll,
3722         .arch_state = xscale_arch_state,
3723
3724         .halt = xscale_halt,
3725         .resume = xscale_resume,
3726         .step = xscale_step,
3727
3728         .assert_reset = xscale_assert_reset,
3729         .deassert_reset = xscale_deassert_reset,
3730
3731         /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3732         .get_gdb_reg_list = arm_get_gdb_reg_list,
3733
3734         .read_memory = xscale_read_memory,
3735         .read_phys_memory = xscale_read_phys_memory,
3736         .write_memory = xscale_write_memory,
3737         .write_phys_memory = xscale_write_phys_memory,
3738
3739         .checksum_memory = arm_checksum_memory,
3740         .blank_check_memory = arm_blank_check_memory,
3741
3742         .run_algorithm = armv4_5_run_algorithm,
3743
3744         .add_breakpoint = xscale_add_breakpoint,
3745         .remove_breakpoint = xscale_remove_breakpoint,
3746         .add_watchpoint = xscale_add_watchpoint,
3747         .remove_watchpoint = xscale_remove_watchpoint,
3748
3749         .commands = xscale_command_handlers,
3750         .target_create = xscale_target_create,
3751         .init_target = xscale_init_target,
3752
3753         .virt2phys = xscale_virt2phys,
3754         .mmu = xscale_mmu
3755 };