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   1 /***************************************************************************
   2  *   Copyright (C) 2006, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   Copyright (C) 2009 Michael Schwingen                                  *
   9  *   michael@schwingen.org                                                 *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  23  ***************************************************************************/
  24
  25 #ifdef HAVE_CONFIG_H
  26 #include "config.h"
  27 #endif
  28
  29 #include "breakpoints.h"
  30 #include "xscale.h"
  31 #include "target_type.h"
  32 #include "arm_jtag.h"
  33 #include "arm_simulator.h"
  34 #include "arm_disassembler.h"
  35 #include <helper/time_support.h>
  36 #include "register.h"
  37 #include "image.h"
  38 #include "arm_opcodes.h"
  39 #include "armv4_5.h"
  40
  41 /*
  42  * Important XScale documents available as of October 2009 include:
  43  *
  44  *  Intel XScale® Core Developer’s Manual, January 2004
  45  *              Order Number: 273473-002
  46  *      This has a chapter detailing debug facilities, and punts some
  47  *      details to chip-specific microarchitecture documents.
  48  *
  49  *  Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
  50  *              Document Number: 273539-005
  51  *      Less detailed than the developer's manual, but summarizes those
  52  *      missing details (for most XScales) and gives LOTS of notes about
  53  *      debugger/handler interaction issues.  Presents a simpler reset
  54  *      and load-handler sequence than the arch doc.  (Note, OpenOCD
  55  *      doesn't currently support "Hot-Debug" as defined there.)
  56  *
  57  * Chip-specific microarchitecture documents may also be useful.
  58  */
  59
  60 /* forward declarations */
  61 static int xscale_resume(struct target *, int current,
  62         target_addr_t address, int handle_breakpoints, int debug_execution);
  63 static int xscale_debug_entry(struct target *);
  64 static int xscale_restore_banked(struct target *);
  65 static int xscale_get_reg(struct reg *reg);
  66 static int xscale_set_reg(struct reg *reg, uint8_t *buf);
  67 static int xscale_set_breakpoint(struct target *, struct breakpoint *);
  68 static int xscale_set_watchpoint(struct target *, struct watchpoint *);
  69 static int xscale_unset_breakpoint(struct target *, struct breakpoint *);
  70 static int xscale_read_trace(struct target *);
  71
  72 /* This XScale "debug handler" is loaded into the processor's
  73  * mini-ICache, which is 2K of code writable only via JTAG.
  74  */
  75 static const uint8_t xscale_debug_handler[] = {
  76 #include "../../contrib/loaders/debug/xscale/debug_handler.inc"
  77 };
  78
  79 static const char *const xscale_reg_list[] = {
  80         "XSCALE_MAINID",                /* 0 */
  81         "XSCALE_CACHETYPE",
  82         "XSCALE_CTRL",
  83         "XSCALE_AUXCTRL",
  84         "XSCALE_TTB",
  85         "XSCALE_DAC",
  86         "XSCALE_FSR",
  87         "XSCALE_FAR",
  88         "XSCALE_PID",
  89         "XSCALE_CPACCESS",
  90         "XSCALE_IBCR0",                 /* 10 */
  91         "XSCALE_IBCR1",
  92         "XSCALE_DBR0",
  93         "XSCALE_DBR1",
  94         "XSCALE_DBCON",
  95         "XSCALE_TBREG",
  96         "XSCALE_CHKPT0",
  97         "XSCALE_CHKPT1",
  98         "XSCALE_DCSR",
  99         "XSCALE_TX",
 100         "XSCALE_RX",                    /* 20 */
 101         "XSCALE_TXRXCTRL",
 102 };
 103
 104 static const struct xscale_reg xscale_reg_arch_info[] = {
 105         {XSCALE_MAINID, NULL},
 106         {XSCALE_CACHETYPE, NULL},
 107         {XSCALE_CTRL, NULL},
 108         {XSCALE_AUXCTRL, NULL},
 109         {XSCALE_TTB, NULL},
 110         {XSCALE_DAC, NULL},
 111         {XSCALE_FSR, NULL},
 112         {XSCALE_FAR, NULL},
 113         {XSCALE_PID, NULL},
 114         {XSCALE_CPACCESS, NULL},
 115         {XSCALE_IBCR0, NULL},
 116         {XSCALE_IBCR1, NULL},
 117         {XSCALE_DBR0, NULL},
 118         {XSCALE_DBR1, NULL},
 119         {XSCALE_DBCON, NULL},
 120         {XSCALE_TBREG, NULL},
 121         {XSCALE_CHKPT0, NULL},
 122         {XSCALE_CHKPT1, NULL},
 123         {XSCALE_DCSR, NULL},    /* DCSR accessed via JTAG or SW */
 124         {-1, NULL},     /* TX accessed via JTAG */
 125         {-1, NULL},     /* RX accessed via JTAG */
 126         {-1, NULL},     /* TXRXCTRL implicit access via JTAG */
 127 };
 128
 129 /* convenience wrapper to access XScale specific registers */
 130 static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
 131 {
 132         uint8_t buf[4] = { 0 };
 133
 134         buf_set_u32(buf, 0, 32, value);
 135
 136         return xscale_set_reg(reg, buf);
 137 }
 138
 139 static const char xscale_not[] = "target is not an XScale";
 140
 141 static int xscale_verify_pointer(struct command_invocation *cmd,
 142         struct xscale_common *xscale)
 143 {
 144         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
 145                 command_print(cmd, xscale_not);
 146                 return ERROR_TARGET_INVALID;
 147         }
 148         return ERROR_OK;
 149 }
 150
 151 static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
 152 {
 153         assert(tap);
 154
 155         if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
 156                 struct scan_field field;
 157                 uint8_t scratch[4] = { 0 };
 158
 159                 memset(&field, 0, sizeof(field));
 160                 field.num_bits = tap->ir_length;
 161                 field.out_value = scratch;
 162                 buf_set_u32(scratch, 0, field.num_bits, new_instr);
 163
 164                 jtag_add_ir_scan(tap, &field, end_state);
 165         }
 166
 167         return ERROR_OK;
 168 }
 169
 170 static int xscale_read_dcsr(struct target *target)
 171 {
 172         struct xscale_common *xscale = target_to_xscale(target);
 173         int retval;
 174         struct scan_field fields[3];
 175         uint8_t field0 = 0x0;
 176         uint8_t field0_check_value = 0x2;
 177         uint8_t field0_check_mask = 0x7;
 178         uint8_t field2 = 0x0;
 179         uint8_t field2_check_value = 0x0;
 180         uint8_t field2_check_mask = 0x1;
 181
 182         xscale_jtag_set_instr(target->tap,
 183                 XSCALE_SELDCSR << xscale->xscale_variant,
 184                 TAP_DRPAUSE);
 185
 186         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 187         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 188
 189         memset(&fields, 0, sizeof(fields));
 190
 191         fields[0].num_bits = 3;
 192         fields[0].out_value = &field0;
 193         uint8_t tmp;
 194         fields[0].in_value = &tmp;
 195
 196         fields[1].num_bits = 32;
 197         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 198
 199         fields[2].num_bits = 1;
 200         fields[2].out_value = &field2;
 201         uint8_t tmp2;
 202         fields[2].in_value = &tmp2;
 203
 204         jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 205
 206         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 207         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 208
 209         retval = jtag_execute_queue();
 210         if (retval != ERROR_OK) {
 211                 LOG_ERROR("JTAG error while reading DCSR");
 212                 return retval;
 213         }
 214
 215         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
 216         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
 217
 218         /* write the register with the value we just read
 219          * on this second pass, only the first bit of field0 is guaranteed to be 0)
 220          */
 221         field0_check_mask = 0x1;
 222         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 223         fields[1].in_value = NULL;
 224
 225         jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 226
 227         /* DANGER!!! this must be here. It will make sure that the arguments
 228          * to jtag_set_check_value() does not go out of scope! */
 229         return jtag_execute_queue();
 230 }
 231
 232
 233 static void xscale_getbuf(jtag_callback_data_t arg)
 234 {
 235         uint8_t *in = (uint8_t *)arg;
 236         *((uint32_t *)arg) = buf_get_u32(in, 0, 32);
 237 }
 238
 239 static int xscale_receive(struct target *target, uint32_t *buffer, int num_words)
 240 {
 241         if (num_words == 0)
 242                 return ERROR_COMMAND_SYNTAX_ERROR;
 243
 244         struct xscale_common *xscale = target_to_xscale(target);
 245         int retval = ERROR_OK;
 246         tap_state_t path[3];
 247         struct scan_field fields[3];
 248         uint8_t *field0 = malloc(num_words * 1);
 249         uint8_t field0_check_value = 0x2;
 250         uint8_t field0_check_mask = 0x6;
 251         uint32_t *field1 = malloc(num_words * 4);
 252         uint8_t field2_check_value = 0x0;
 253         uint8_t field2_check_mask = 0x1;
 254         int words_done = 0;
 255         int words_scheduled = 0;
 256         int i;
 257
 258         path[0] = TAP_DRSELECT;
 259         path[1] = TAP_DRCAPTURE;
 260         path[2] = TAP_DRSHIFT;
 261
 262         memset(&fields, 0, sizeof(fields));
 263
 264         fields[0].num_bits = 3;
 265         uint8_t tmp;
 266         fields[0].in_value = &tmp;
 267         fields[0].check_value = &field0_check_value;
 268         fields[0].check_mask = &field0_check_mask;
 269
 270         fields[1].num_bits = 32;
 271
 272         fields[2].num_bits = 1;
 273         uint8_t tmp2;
 274         fields[2].in_value = &tmp2;
 275         fields[2].check_value = &field2_check_value;
 276         fields[2].check_mask = &field2_check_mask;
 277
 278         xscale_jtag_set_instr(target->tap,
 279                 XSCALE_DBGTX << xscale->xscale_variant,
 280                 TAP_IDLE);
 281         jtag_add_runtest(1, TAP_IDLE);  /* ensures that we're in the TAP_IDLE state as the above
 282                                          *could be a no-op */
 283
 284         /* repeat until all words have been collected */
 285         int attempts = 0;
 286         while (words_done < num_words) {
 287                 /* schedule reads */
 288                 words_scheduled = 0;
 289                 for (i = words_done; i < num_words; i++) {
 290                         fields[0].in_value = &field0[i];
 291
 292                         jtag_add_pathmove(3, path);
 293
 294                         fields[1].in_value = (uint8_t *)(field1 + i);
 295
 296                         jtag_add_dr_scan_check(target->tap, 3, fields, TAP_IDLE);
 297
 298                         jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
 299
 300                         words_scheduled++;
 301                 }
 302
 303                 retval = jtag_execute_queue();
 304                 if (retval != ERROR_OK) {
 305                         LOG_ERROR("JTAG error while receiving data from debug handler");
 306                         break;
 307                 }
 308
 309                 /* examine results */
 310                 for (i = words_done; i < num_words; i++) {
 311                         if (!(field0[i] & 1)) {
 312                                 /* move backwards if necessary */
 313                                 int j;
 314                                 for (j = i; j < num_words - 1; j++) {
 315                                         field0[j] = field0[j + 1];
 316                                         field1[j] = field1[j + 1];
 317                                 }
 318                                 words_scheduled--;
 319                         }
 320                 }
 321                 if (words_scheduled == 0) {
 322                         if (attempts++ == 1000) {
 323                                 LOG_ERROR(
 324                                         "Failed to receiving data from debug handler after 1000 attempts");
 325                                 retval = ERROR_TARGET_TIMEOUT;
 326                                 break;
 327                         }
 328                 }
 329
 330                 words_done += words_scheduled;
 331         }
 332
 333         for (i = 0; i < num_words; i++)
 334                 *(buffer++) = buf_get_u32((uint8_t *)&field1[i], 0, 32);
 335
 336         free(field1);
 337
 338         return retval;
 339 }
 340
 341 static int xscale_read_tx(struct target *target, int consume)
 342 {
 343         struct xscale_common *xscale = target_to_xscale(target);
 344         tap_state_t path[3];
 345         tap_state_t noconsume_path[6];
 346         int retval;
 347         struct timeval timeout, now;
 348         struct scan_field fields[3];
 349         uint8_t field0_in = 0x0;
 350         uint8_t field0_check_value = 0x2;
 351         uint8_t field0_check_mask = 0x6;
 352         uint8_t field2_check_value = 0x0;
 353         uint8_t field2_check_mask = 0x1;
 354
 355         xscale_jtag_set_instr(target->tap,
 356                 XSCALE_DBGTX << xscale->xscale_variant,
 357                 TAP_IDLE);
 358
 359         path[0] = TAP_DRSELECT;
 360         path[1] = TAP_DRCAPTURE;
 361         path[2] = TAP_DRSHIFT;
 362
 363         noconsume_path[0] = TAP_DRSELECT;
 364         noconsume_path[1] = TAP_DRCAPTURE;
 365         noconsume_path[2] = TAP_DREXIT1;
 366         noconsume_path[3] = TAP_DRPAUSE;
 367         noconsume_path[4] = TAP_DREXIT2;
 368         noconsume_path[5] = TAP_DRSHIFT;
 369
 370         memset(&fields, 0, sizeof(fields));
 371
 372         fields[0].num_bits = 3;
 373         fields[0].in_value = &field0_in;
 374
 375         fields[1].num_bits = 32;
 376         fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 377
 378         fields[2].num_bits = 1;
 379         uint8_t tmp;
 380         fields[2].in_value = &tmp;
 381
 382         gettimeofday(&timeout, NULL);
 383         timeval_add_time(&timeout, 1, 0);
 384
 385         for (;; ) {
 386                 /* if we want to consume the register content (i.e. clear TX_READY),
 387                  * we have to go straight from Capture-DR to Shift-DR
 388                  * otherwise, we go from Capture-DR to Exit1-DR to Pause-DR
 389                 */
 390                 if (consume)
 391                         jtag_add_pathmove(3, path);
 392                 else
 393                         jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
 394
 395                 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 396
 397                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 398                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 399
 400                 retval = jtag_execute_queue();
 401                 if (retval != ERROR_OK) {
 402                         LOG_ERROR("JTAG error while reading TX");
 403                         return ERROR_TARGET_TIMEOUT;
 404                 }
 405
 406                 gettimeofday(&now, NULL);
 407                 if (timeval_compare(&now, &timeout) > 0) {
 408                         LOG_ERROR("time out reading TX register");
 409                         return ERROR_TARGET_TIMEOUT;
 410                 }
 411                 if (!((!(field0_in & 1)) && consume))
 412                         goto done;
 413                 if (debug_level >= 3) {
 414                         LOG_DEBUG("waiting 100ms");
 415                         alive_sleep(100);       /* avoid flooding the logs */
 416                 } else
 417                         keep_alive();
 418         }
 419 done:
 420
 421         if (!(field0_in & 1))
 422                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 423
 424         return ERROR_OK;
 425 }
 426
 427 static int xscale_write_rx(struct target *target)
 428 {
 429         struct xscale_common *xscale = target_to_xscale(target);
 430         int retval;
 431         struct timeval timeout, now;
 432         struct scan_field fields[3];
 433         uint8_t field0_out = 0x0;
 434         uint8_t field0_in = 0x0;
 435         uint8_t field0_check_value = 0x2;
 436         uint8_t field0_check_mask = 0x6;
 437         uint8_t field2 = 0x0;
 438         uint8_t field2_check_value = 0x0;
 439         uint8_t field2_check_mask = 0x1;
 440
 441         xscale_jtag_set_instr(target->tap,
 442                 XSCALE_DBGRX << xscale->xscale_variant,
 443                 TAP_IDLE);
 444
 445         memset(&fields, 0, sizeof(fields));
 446
 447         fields[0].num_bits = 3;
 448         fields[0].out_value = &field0_out;
 449         fields[0].in_value = &field0_in;
 450
 451         fields[1].num_bits = 32;
 452         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 453
 454         fields[2].num_bits = 1;
 455         fields[2].out_value = &field2;
 456         uint8_t tmp;
 457         fields[2].in_value = &tmp;
 458
 459         gettimeofday(&timeout, NULL);
 460         timeval_add_time(&timeout, 1, 0);
 461
 462         /* poll until rx_read is low */
 463         LOG_DEBUG("polling RX");
 464         for (;;) {
 465                 jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 466
 467                 jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 468                 jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 469
 470                 retval = jtag_execute_queue();
 471                 if (retval != ERROR_OK) {
 472                         LOG_ERROR("JTAG error while writing RX");
 473                         return retval;
 474                 }
 475
 476                 gettimeofday(&now, NULL);
 477                 if ((now.tv_sec > timeout.tv_sec) ||
 478                         ((now.tv_sec == timeout.tv_sec) && (now.tv_usec > timeout.tv_usec))) {
 479                         LOG_ERROR("time out writing RX register");
 480                         return ERROR_TARGET_TIMEOUT;
 481                 }
 482                 if (!(field0_in & 1))
 483                         goto done;
 484                 if (debug_level >= 3) {
 485                         LOG_DEBUG("waiting 100ms");
 486                         alive_sleep(100);       /* avoid flooding the logs */
 487                 } else
 488                         keep_alive();
 489         }
 490 done:
 491
 492         /* set rx_valid */
 493         field2 = 0x1;
 494         jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 495
 496         retval = jtag_execute_queue();
 497         if (retval != ERROR_OK) {
 498                 LOG_ERROR("JTAG error while writing RX");
 499                 return retval;
 500         }
 501
 502         return ERROR_OK;
 503 }
 504
 505 /* send count elements of size byte to the debug handler */
 506 static int xscale_send(struct target *target, const uint8_t *buffer, int count, int size)
 507 {
 508         struct xscale_common *xscale = target_to_xscale(target);
 509         int retval;
 510         int done_count = 0;
 511
 512         xscale_jtag_set_instr(target->tap,
 513                 XSCALE_DBGRX << xscale->xscale_variant,
 514                 TAP_IDLE);
 515
 516         static const uint8_t t0;
 517         uint8_t t1[4] = { 0 };
 518         static const uint8_t t2 = 1;
 519         struct scan_field fields[3] = {
 520                         { .num_bits = 3, .out_value = &t0 },
 521                         { .num_bits = 32, .out_value = t1 },
 522                         { .num_bits = 1, .out_value = &t2 },
 523         };
 524
 525         int endianness = target->endianness;
 526         while (done_count++ < count) {
 527                 uint32_t t;
 528
 529                 switch (size) {
 530                         case 4:
 531                                 if (endianness == TARGET_LITTLE_ENDIAN)
 532                                         t = le_to_h_u32(buffer);
 533                                 else
 534                                         t = be_to_h_u32(buffer);
 535                                 break;
 536                         case 2:
 537                                 if (endianness == TARGET_LITTLE_ENDIAN)
 538                                         t = le_to_h_u16(buffer);
 539                                 else
 540                                         t = be_to_h_u16(buffer);
 541                                 break;
 542                         case 1:
 543                                 t = buffer[0];
 544                                 break;
 545                         default:
 546                                 LOG_ERROR("BUG: size neither 4, 2 nor 1");
 547                                 return ERROR_COMMAND_SYNTAX_ERROR;
 548                 }
 549
 550                 buf_set_u32(t1, 0, 32, t);
 551
 552                 jtag_add_dr_scan(target->tap,
 553                         3,
 554                         fields,
 555                         TAP_IDLE);
 556                 buffer += size;
 557         }
 558
 559         retval = jtag_execute_queue();
 560         if (retval != ERROR_OK) {
 561                 LOG_ERROR("JTAG error while sending data to debug handler");
 562                 return retval;
 563         }
 564
 565         return ERROR_OK;
 566 }
 567
 568 static int xscale_send_u32(struct target *target, uint32_t value)
 569 {
 570         struct xscale_common *xscale = target_to_xscale(target);
 571
 572         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
 573         return xscale_write_rx(target);
 574 }
 575
 576 static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_brk)
 577 {
 578         struct xscale_common *xscale = target_to_xscale(target);
 579         int retval;
 580         struct scan_field fields[3];
 581         uint8_t field0 = 0x0;
 582         uint8_t field0_check_value = 0x2;
 583         uint8_t field0_check_mask = 0x7;
 584         uint8_t field2 = 0x0;
 585         uint8_t field2_check_value = 0x0;
 586         uint8_t field2_check_mask = 0x1;
 587
 588         if (hold_rst != -1)
 589                 xscale->hold_rst = hold_rst;
 590
 591         if (ext_dbg_brk != -1)
 592                 xscale->external_debug_break = ext_dbg_brk;
 593
 594         xscale_jtag_set_instr(target->tap,
 595                 XSCALE_SELDCSR << xscale->xscale_variant,
 596                 TAP_IDLE);
 597
 598         buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 599         buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 600
 601         memset(&fields, 0, sizeof(fields));
 602
 603         fields[0].num_bits = 3;
 604         fields[0].out_value = &field0;
 605         uint8_t tmp;
 606         fields[0].in_value = &tmp;
 607
 608         fields[1].num_bits = 32;
 609         fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 610
 611         fields[2].num_bits = 1;
 612         fields[2].out_value = &field2;
 613         uint8_t tmp2;
 614         fields[2].in_value = &tmp2;
 615
 616         jtag_add_dr_scan(target->tap, 3, fields, TAP_IDLE);
 617
 618         jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
 619         jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
 620
 621         retval = jtag_execute_queue();
 622         if (retval != ERROR_OK) {
 623                 LOG_ERROR("JTAG error while writing DCSR");
 624                 return retval;
 625         }
 626
 627         xscale->reg_cache->reg_list[XSCALE_DCSR].dirty = false;
 628         xscale->reg_cache->reg_list[XSCALE_DCSR].valid = true;
 629
 630         return ERROR_OK;
 631 }
 632
 633 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
 634 static unsigned int parity(unsigned int v)
 635 {
 636         /* unsigned int ov = v; */
 637         v ^= v >> 16;
 638         v ^= v >> 8;
 639         v ^= v >> 4;
 640         v &= 0xf;
 641         /* LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1); */
 642         return (0x6996 >> v) & 1;
 643 }
 644
 645 static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
 646 {
 647         struct xscale_common *xscale = target_to_xscale(target);
 648         uint8_t packet[4] = { 0 };
 649         uint8_t cmd = 0;
 650         int word;
 651         struct scan_field fields[2];
 652
 653         LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 654
 655         /* LDIC into IR */
 656         xscale_jtag_set_instr(target->tap,
 657                 XSCALE_LDIC << xscale->xscale_variant,
 658                 TAP_IDLE);
 659
 660         /* CMD is b011 to load a cacheline into the Mini ICache.
 661          * Loading into the main ICache is deprecated, and unused.
 662          * It's followed by three zero bits, and 27 address bits.
 663          */
 664         buf_set_u32(&cmd, 0, 6, 0x3);
 665
 666         /* virtual address of desired cache line */
 667         buf_set_u32(packet, 0, 27, va >> 5);
 668
 669         memset(&fields, 0, sizeof(fields));
 670
 671         fields[0].num_bits = 6;
 672         fields[0].out_value = &cmd;
 673
 674         fields[1].num_bits = 27;
 675         fields[1].out_value = packet;
 676
 677         jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 678
 679         /* rest of packet is a cacheline: 8 instructions, with parity */
 680         fields[0].num_bits = 32;
 681         fields[0].out_value = packet;
 682
 683         fields[1].num_bits = 1;
 684         fields[1].out_value = &cmd;
 685
 686         for (word = 0; word < 8; word++) {
 687                 buf_set_u32(packet, 0, 32, buffer[word]);
 688
 689                 uint32_t value;
 690                 memcpy(&value, packet, sizeof(uint32_t));
 691                 cmd = parity(value);
 692
 693                 jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 694         }
 695
 696         return jtag_execute_queue();
 697 }
 698
 699 static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 700 {
 701         struct xscale_common *xscale = target_to_xscale(target);
 702         uint8_t packet[4] = { 0 };
 703         uint8_t cmd = 0;
 704         struct scan_field fields[2];
 705
 706         xscale_jtag_set_instr(target->tap,
 707                 XSCALE_LDIC << xscale->xscale_variant,
 708                 TAP_IDLE);
 709
 710         /* CMD for invalidate IC line b000, bits [6:4] b000 */
 711         buf_set_u32(&cmd, 0, 6, 0x0);
 712
 713         /* virtual address of desired cache line */
 714         buf_set_u32(packet, 0, 27, va >> 5);
 715
 716         memset(&fields, 0, sizeof(fields));
 717
 718         fields[0].num_bits = 6;
 719         fields[0].out_value = &cmd;
 720
 721         fields[1].num_bits = 27;
 722         fields[1].out_value = packet;
 723
 724         jtag_add_dr_scan(target->tap, 2, fields, TAP_IDLE);
 725
 726         return ERROR_OK;
 727 }
 728
 729 static int xscale_update_vectors(struct target *target)
 730 {
 731         struct xscale_common *xscale = target_to_xscale(target);
 732         int i;
 733         int retval;
 734
 735         uint32_t low_reset_branch, high_reset_branch;
 736
 737         for (i = 1; i < 8; i++) {
 738                 /* if there's a static vector specified for this exception, override */
 739                 if (xscale->static_high_vectors_set & (1 << i))
 740                         xscale->high_vectors[i] = xscale->static_high_vectors[i];
 741                 else {
 742                         retval = target_read_u32(target, 0xffff0000 + 4*i, &xscale->high_vectors[i]);
 743                         if (retval == ERROR_TARGET_TIMEOUT)
 744                                 return retval;
 745                         if (retval != ERROR_OK) {
 746                                 /* Some of these reads will fail as part of normal execution */
 747                                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 748                         }
 749                 }
 750         }
 751
 752         for (i = 1; i < 8; i++) {
 753                 if (xscale->static_low_vectors_set & (1 << i))
 754                         xscale->low_vectors[i] = xscale->static_low_vectors[i];
 755                 else {
 756                         retval = target_read_u32(target, 0x0 + 4*i, &xscale->low_vectors[i]);
 757                         if (retval == ERROR_TARGET_TIMEOUT)
 758                                 return retval;
 759                         if (retval != ERROR_OK) {
 760                                 /* Some of these reads will fail as part of normal execution */
 761                                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
 762                         }
 763                 }
 764         }
 765
 766         /* calculate branches to debug handler */
 767         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
 768         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
 769
 770         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
 771         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
 772
 773         /* invalidate and load exception vectors in mini i-cache */
 774         xscale_invalidate_ic_line(target, 0x0);
 775         xscale_invalidate_ic_line(target, 0xffff0000);
 776
 777         xscale_load_ic(target, 0x0, xscale->low_vectors);
 778         xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
 779
 780         return ERROR_OK;
 781 }
 782
 783 static int xscale_arch_state(struct target *target)
 784 {
 785         struct xscale_common *xscale = target_to_xscale(target);
 786         struct arm *arm = &xscale->arm;
 787
 788         static const char *state[] = {
 789                 "disabled", "enabled"
 790         };
 791
 792         static const char *arch_dbg_reason[] = {
 793                 "", "\n(processor reset)", "\n(trace buffer full)"
 794         };
 795
 796         if (arm->common_magic != ARM_COMMON_MAGIC) {
 797                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 798                 return ERROR_COMMAND_SYNTAX_ERROR;
 799         }
 800
 801         arm_arch_state(target);
 802         LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 803                 state[xscale->armv4_5_mmu.mmu_enabled],
 804                 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 805                 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
 806                 arch_dbg_reason[xscale->arch_debug_reason]);
 807
 808         return ERROR_OK;
 809 }
 810
 811 static int xscale_poll(struct target *target)
 812 {
 813         int retval = ERROR_OK;
 814
 815         if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING)) {
 816                 enum target_state previous_state = target->state;
 817                 retval = xscale_read_tx(target, 0);
 818                 if (retval == ERROR_OK) {
 819
 820                         /* there's data to read from the tx register, we entered debug state */
 821                         target->state = TARGET_HALTED;
 822
 823                         /* process debug entry, fetching current mode regs */
 824                         retval = xscale_debug_entry(target);
 825                 } else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 826                         LOG_USER("error while polling TX register, reset CPU");
 827                         /* here we "lie" so GDB won't get stuck and a reset can be performed */
 828                         target->state = TARGET_HALTED;
 829                 }
 830
 831                 /* debug_entry could have overwritten target state (i.e. immediate resume)
 832                  * don't signal event handlers in that case
 833                  */
 834                 if (target->state != TARGET_HALTED)
 835                         return ERROR_OK;
 836
 837                 /* if target was running, signal that we halted
 838                  * otherwise we reentered from debug execution */
 839                 if (previous_state == TARGET_RUNNING)
 840                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 841                 else
 842                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 843         }
 844
 845         return retval;
 846 }
 847
 848 static int xscale_debug_entry(struct target *target)
 849 {
 850         struct xscale_common *xscale = target_to_xscale(target);
 851         struct arm *arm = &xscale->arm;
 852         uint32_t pc;
 853         uint32_t buffer[10];
 854         unsigned i;
 855         int retval;
 856         uint32_t moe;
 857
 858         /* clear external dbg break (will be written on next DCSR read) */
 859         xscale->external_debug_break = 0;
 860         retval = xscale_read_dcsr(target);
 861         if (retval != ERROR_OK)
 862                 return retval;
 863
 864         /* get r0, pc, r1 to r7 and cpsr */
 865         retval = xscale_receive(target, buffer, 10);
 866         if (retval != ERROR_OK)
 867                 return retval;
 868
 869         /* move r0 from buffer to register cache */
 870         buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
 871         arm->core_cache->reg_list[0].dirty = true;
 872         arm->core_cache->reg_list[0].valid = true;
 873         LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 874
 875         /* move pc from buffer to register cache */
 876         buf_set_u32(arm->pc->value, 0, 32, buffer[1]);
 877         arm->pc->dirty = true;
 878         arm->pc->valid = true;
 879         LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
 880
 881         /* move data from buffer to register cache */
 882         for (i = 1; i <= 7; i++) {
 883                 buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
 884                 arm->core_cache->reg_list[i].dirty = true;
 885                 arm->core_cache->reg_list[i].valid = true;
 886                 LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
 887         }
 888
 889         arm_set_cpsr(arm, buffer[9]);
 890         LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
 891
 892         if (!is_arm_mode(arm->core_mode)) {
 893                 target->state = TARGET_UNKNOWN;
 894                 LOG_ERROR("cpsr contains invalid mode value - communication failure");
 895                 return ERROR_TARGET_FAILURE;
 896         }
 897         LOG_DEBUG("target entered debug state in %s mode",
 898                 arm_mode_name(arm->core_mode));
 899
 900         /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */
 901         if (arm->spsr) {
 902                 xscale_receive(target, buffer, 8);
 903                 buf_set_u32(arm->spsr->value, 0, 32, buffer[7]);
 904                 arm->spsr->dirty = false;
 905                 arm->spsr->valid = true;
 906         } else {
 907                 /* r8 to r14, but no spsr */
 908                 xscale_receive(target, buffer, 7);
 909         }
 910
 911         /* move data from buffer to right banked register in cache */
 912         for (i = 8; i <= 14; i++) {
 913                 struct reg *r = arm_reg_current(arm, i);
 914
 915                 buf_set_u32(r->value, 0, 32, buffer[i - 8]);
 916                 r->dirty = false;
 917                 r->valid = true;
 918         }
 919
 920         /* mark xscale regs invalid to ensure they are retrieved from the
 921          * debug handler if requested  */
 922         for (i = 0; i < xscale->reg_cache->num_regs; i++)
 923                 xscale->reg_cache->reg_list[i].valid = false;
 924
 925         /* examine debug reason */
 926         xscale_read_dcsr(target);
 927         moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3);
 928
 929         /* stored PC (for calculating fixup) */
 930         pc = buf_get_u32(arm->pc->value, 0, 32);
 931
 932         switch (moe) {
 933                 case 0x0:       /* Processor reset */
 934                         target->debug_reason = DBG_REASON_DBGRQ;
 935                         xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET;
 936                         pc -= 4;
 937                         break;
 938                 case 0x1:       /* Instruction breakpoint hit */
 939                         target->debug_reason = DBG_REASON_BREAKPOINT;
 940                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 941                         pc -= 4;
 942                         break;
 943                 case 0x2:       /* Data breakpoint hit */
 944                         target->debug_reason = DBG_REASON_WATCHPOINT;
 945                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 946                         pc -= 4;
 947                         break;
 948                 case 0x3:       /* BKPT instruction executed */
 949                         target->debug_reason = DBG_REASON_BREAKPOINT;
 950                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 951                         pc -= 4;
 952                         break;
 953                 case 0x4:       /* Ext. debug event */
 954                         target->debug_reason = DBG_REASON_DBGRQ;
 955                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 956                         pc -= 4;
 957                         break;
 958                 case 0x5:       /* Vector trap occurred */
 959                         target->debug_reason = DBG_REASON_BREAKPOINT;
 960                         xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 961                         pc -= 4;
 962                         break;
 963                 case 0x6:       /* Trace buffer full break */
 964                         target->debug_reason = DBG_REASON_DBGRQ;
 965                         xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
 966                         pc -= 4;
 967                         break;
 968                 case 0x7:       /* Reserved (may flag Hot-Debug support) */
 969                 default:
 970                         LOG_ERROR("Method of Entry is 'Reserved'");
 971                         exit(-1);
 972                         break;
 973         }
 974
 975         /* apply PC fixup */
 976         buf_set_u32(arm->pc->value, 0, 32, pc);
 977
 978         /* on the first debug entry, identify cache type */
 979         if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) {
 980                 uint32_t cache_type_reg;
 981
 982                 /* read cp15 cache type register */
 983                 xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CACHETYPE]);
 984                 cache_type_reg = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CACHETYPE].value,
 985                                 0,
 986                                 32);
 987
 988                 armv4_5_identify_cache(cache_type_reg, &xscale->armv4_5_mmu.armv4_5_cache);
 989         }
 990
 991         /* examine MMU and Cache settings
 992          * read cp15 control register */
 993         xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
 994         xscale->cp15_control_reg =
 995                 buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 996         xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
 997         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
 998                 (xscale->cp15_control_reg & 0x4U) ? 1 : 0;
 999         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
1000                 (xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
1001
1002         /* tracing enabled, read collected trace data */
1003         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1004                 xscale_read_trace(target);
1005
1006                 /* Resume if entered debug due to buffer fill and we're still collecting
1007                  * trace data.  Note that a debug exception due to trace buffer full
1008                  * can only happen in fill mode. */
1009                 if (xscale->arch_debug_reason == XSCALE_DBG_REASON_TB_FULL) {
1010                         if (--xscale->trace.fill_counter > 0)
1011                                 xscale_resume(target, 1, 0x0, 1, 0);
1012                 } else  /* entered debug for other reason; reset counter */
1013                         xscale->trace.fill_counter = 0;
1014         }
1015
1016         return ERROR_OK;
1017 }
1018
1019 static int xscale_halt(struct target *target)
1020 {
1021         struct xscale_common *xscale = target_to_xscale(target);
1022
1023         LOG_DEBUG("target->state: %s",
1024                 target_state_name(target));
1025
1026         if (target->state == TARGET_HALTED) {
1027                 LOG_DEBUG("target was already halted");
1028                 return ERROR_OK;
1029         } else if (target->state == TARGET_UNKNOWN) {
1030                 /* this must not happen for a xscale target */
1031                 LOG_ERROR("target was in unknown state when halt was requested");
1032                 return ERROR_TARGET_INVALID;
1033         } else if (target->state == TARGET_RESET)
1034                 LOG_DEBUG("target->state == TARGET_RESET");
1035         else {
1036                 /* assert external dbg break */
1037                 xscale->external_debug_break = 1;
1038                 xscale_read_dcsr(target);
1039
1040                 target->debug_reason = DBG_REASON_DBGRQ;
1041         }
1042
1043         return ERROR_OK;
1044 }
1045
1046 static int xscale_enable_single_step(struct target *target, uint32_t next_pc)
1047 {
1048         struct xscale_common *xscale = target_to_xscale(target);
1049         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1050         int retval;
1051
1052         if (xscale->ibcr0_used) {
1053                 struct breakpoint *ibcr0_bp =
1054                         breakpoint_find(target, buf_get_u32(ibcr0->value, 0, 32) & 0xfffffffe);
1055
1056                 if (ibcr0_bp)
1057                         xscale_unset_breakpoint(target, ibcr0_bp);
1058                 else {
1059                         LOG_ERROR(
1060                                 "BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
1061                         exit(-1);
1062                 }
1063         }
1064
1065         retval = xscale_set_reg_u32(ibcr0, next_pc | 0x1);
1066         if (retval != ERROR_OK)
1067                 return retval;
1068
1069         return ERROR_OK;
1070 }
1071
1072 static int xscale_disable_single_step(struct target *target)
1073 {
1074         struct xscale_common *xscale = target_to_xscale(target);
1075         struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
1076         int retval;
1077
1078         retval = xscale_set_reg_u32(ibcr0, 0x0);
1079         if (retval != ERROR_OK)
1080                 return retval;
1081
1082         return ERROR_OK;
1083 }
1084
1085 static void xscale_enable_watchpoints(struct target *target)
1086 {
1087         struct watchpoint *watchpoint = target->watchpoints;
1088
1089         while (watchpoint) {
1090                 if (!watchpoint->is_set)
1091                         xscale_set_watchpoint(target, watchpoint);
1092                 watchpoint = watchpoint->next;
1093         }
1094 }
1095
1096 static void xscale_enable_breakpoints(struct target *target)
1097 {
1098         struct breakpoint *breakpoint = target->breakpoints;
1099
1100         /* set any pending breakpoints */
1101         while (breakpoint) {
1102                 if (!breakpoint->is_set)
1103                         xscale_set_breakpoint(target, breakpoint);
1104                 breakpoint = breakpoint->next;
1105         }
1106 }
1107
1108 static void xscale_free_trace_data(struct xscale_common *xscale)
1109 {
1110         struct xscale_trace_data *td = xscale->trace.data;
1111         while (td) {
1112                 struct xscale_trace_data *next_td = td->next;
1113                 free(td->entries);
1114                 free(td);
1115                 td = next_td;
1116         }
1117         xscale->trace.data = NULL;
1118 }
1119
1120 static int xscale_resume(struct target *target, int current,
1121         target_addr_t address, int handle_breakpoints, int debug_execution)
1122 {
1123         struct xscale_common *xscale = target_to_xscale(target);
1124         struct arm *arm = &xscale->arm;
1125         uint32_t current_pc;
1126         int retval;
1127         int i;
1128
1129         LOG_DEBUG("-");
1130
1131         if (target->state != TARGET_HALTED) {
1132                 LOG_WARNING("target not halted");
1133                 return ERROR_TARGET_NOT_HALTED;
1134         }
1135
1136         if (!debug_execution)
1137                 target_free_all_working_areas(target);
1138
1139         /* update vector tables */
1140         retval = xscale_update_vectors(target);
1141         if (retval != ERROR_OK)
1142                 return retval;
1143
1144         /* current = 1: continue on current pc, otherwise continue at <address> */
1145         if (!current)
1146                 buf_set_u32(arm->pc->value, 0, 32, address);
1147
1148         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1149
1150         /* if we're at the reset vector, we have to simulate the branch */
1151         if (current_pc == 0x0) {
1152                 arm_simulate_step(target, NULL);
1153                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1154         }
1155
1156         /* the front-end may request us not to handle breakpoints */
1157         if (handle_breakpoints) {
1158                 struct breakpoint *breakpoint;
1159                 breakpoint = breakpoint_find(target,
1160                                 buf_get_u32(arm->pc->value, 0, 32));
1161                 if (breakpoint) {
1162                         uint32_t next_pc;
1163                         enum trace_mode saved_trace_mode;
1164
1165                         /* there's a breakpoint at the current PC, we have to step over it */
1166                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
1167                                 breakpoint->address);
1168                         xscale_unset_breakpoint(target, breakpoint);
1169
1170                         /* calculate PC of next instruction */
1171                         retval = arm_simulate_step(target, &next_pc);
1172                         if (retval != ERROR_OK) {
1173                                 uint32_t current_opcode;
1174                                 target_read_u32(target, current_pc, &current_opcode);
1175                                 LOG_ERROR(
1176                                         "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
1177                                         current_opcode);
1178                         }
1179
1180                         LOG_DEBUG("enable single-step");
1181                         xscale_enable_single_step(target, next_pc);
1182
1183                         /* restore banked registers */
1184                         retval = xscale_restore_banked(target);
1185                         if (retval != ERROR_OK)
1186                                 return retval;
1187
1188                         /* send resume request */
1189                         xscale_send_u32(target, 0x30);
1190
1191                         /* send CPSR */
1192                         xscale_send_u32(target,
1193                                 buf_get_u32(arm->cpsr->value, 0, 32));
1194                         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1195                                 buf_get_u32(arm->cpsr->value, 0, 32));
1196
1197                         for (i = 7; i >= 0; i--) {
1198                                 /* send register */
1199                                 xscale_send_u32(target,
1200                                         buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1201                                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
1202                                         i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1203                         }
1204
1205                         /* send PC */
1206                         xscale_send_u32(target,
1207                                 buf_get_u32(arm->pc->value, 0, 32));
1208                         LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
1209                                 buf_get_u32(arm->pc->value, 0, 32));
1210
1211                         /* disable trace data collection in xscale_debug_entry() */
1212                         saved_trace_mode = xscale->trace.mode;
1213                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
1214
1215                         /* wait for and process debug entry */
1216                         xscale_debug_entry(target);
1217
1218                         /* re-enable trace buffer, if enabled previously */
1219                         xscale->trace.mode = saved_trace_mode;
1220
1221                         LOG_DEBUG("disable single-step");
1222                         xscale_disable_single_step(target);
1223
1224                         LOG_DEBUG("set breakpoint at " TARGET_ADDR_FMT "",
1225                                 breakpoint->address);
1226                         xscale_set_breakpoint(target, breakpoint);
1227                 }
1228         }
1229
1230         /* enable any pending breakpoints and watchpoints */
1231         xscale_enable_breakpoints(target);
1232         xscale_enable_watchpoints(target);
1233
1234         /* restore banked registers */
1235         retval = xscale_restore_banked(target);
1236         if (retval != ERROR_OK)
1237                 return retval;
1238
1239         /* send resume request (command 0x30 or 0x31)
1240          * clean the trace buffer if it is to be enabled (0x62) */
1241         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1242                 if (xscale->trace.mode == XSCALE_TRACE_FILL) {
1243                         /* If trace enabled in fill mode and starting collection of new set
1244                              * of buffers, initialize buffer counter and free previous buffers */
1245                         if (xscale->trace.fill_counter == 0) {
1246                                 xscale->trace.fill_counter = xscale->trace.buffer_fill;
1247                                 xscale_free_trace_data(xscale);
1248                         }
1249                 } else  /* wrap mode; free previous buffer */
1250                         xscale_free_trace_data(xscale);
1251
1252                 xscale_send_u32(target, 0x62);
1253                 xscale_send_u32(target, 0x31);
1254         } else
1255                 xscale_send_u32(target, 0x30);
1256
1257         /* send CPSR */
1258         xscale_send_u32(target, buf_get_u32(arm->cpsr->value, 0, 32));
1259         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1260                 buf_get_u32(arm->cpsr->value, 0, 32));
1261
1262         for (i = 7; i >= 0; i--) {
1263                 /* send register */
1264                 xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1265                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
1266                         i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1267         }
1268
1269         /* send PC */
1270         xscale_send_u32(target, buf_get_u32(arm->pc->value, 0, 32));
1271         LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1272                 buf_get_u32(arm->pc->value, 0, 32));
1273
1274         target->debug_reason = DBG_REASON_NOTHALTED;
1275
1276         if (!debug_execution) {
1277                 /* registers are now invalid */
1278                 register_cache_invalidate(arm->core_cache);
1279                 target->state = TARGET_RUNNING;
1280                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1281         } else {
1282                 target->state = TARGET_DEBUG_RUNNING;
1283                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
1284         }
1285
1286         LOG_DEBUG("target resumed");
1287
1288         return ERROR_OK;
1289 }
1290
1291 static int xscale_step_inner(struct target *target, int current,
1292         uint32_t address, int handle_breakpoints)
1293 {
1294         struct xscale_common *xscale = target_to_xscale(target);
1295         struct arm *arm = &xscale->arm;
1296         uint32_t next_pc;
1297         int retval;
1298         int i;
1299
1300         target->debug_reason = DBG_REASON_SINGLESTEP;
1301
1302         /* calculate PC of next instruction */
1303         retval = arm_simulate_step(target, &next_pc);
1304         if (retval != ERROR_OK) {
1305                 uint32_t current_opcode, current_pc;
1306                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1307
1308                 target_read_u32(target, current_pc, &current_opcode);
1309                 LOG_ERROR(
1310                         "BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
1311                         current_opcode);
1312                 return retval;
1313         }
1314
1315         LOG_DEBUG("enable single-step");
1316         retval = xscale_enable_single_step(target, next_pc);
1317         if (retval != ERROR_OK)
1318                 return retval;
1319
1320         /* restore banked registers */
1321         retval = xscale_restore_banked(target);
1322         if (retval != ERROR_OK)
1323                 return retval;
1324
1325         /* send resume request (command 0x30 or 0x31)
1326          * clean the trace buffer if it is to be enabled (0x62) */
1327         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
1328                 retval = xscale_send_u32(target, 0x62);
1329                 if (retval != ERROR_OK)
1330                         return retval;
1331                 retval = xscale_send_u32(target, 0x31);
1332                 if (retval != ERROR_OK)
1333                         return retval;
1334         } else {
1335                 retval = xscale_send_u32(target, 0x30);
1336                 if (retval != ERROR_OK)
1337                         return retval;
1338         }
1339
1340         /* send CPSR */
1341         retval = xscale_send_u32(target,
1342                         buf_get_u32(arm->cpsr->value, 0, 32));
1343         if (retval != ERROR_OK)
1344                 return retval;
1345         LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
1346                 buf_get_u32(arm->cpsr->value, 0, 32));
1347
1348         for (i = 7; i >= 0; i--) {
1349                 /* send register */
1350                 retval = xscale_send_u32(target,
1351                                 buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1352                 if (retval != ERROR_OK)
1353                         return retval;
1354                 LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
1355                         buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
1356         }
1357
1358         /* send PC */
1359         retval = xscale_send_u32(target,
1360                         buf_get_u32(arm->pc->value, 0, 32));
1361         if (retval != ERROR_OK)
1362                 return retval;
1363         LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32,
1364                 buf_get_u32(arm->pc->value, 0, 32));
1365
1366         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1367
1368         /* registers are now invalid */
1369         register_cache_invalidate(arm->core_cache);
1370
1371         /* wait for and process debug entry */
1372         retval = xscale_debug_entry(target);
1373         if (retval != ERROR_OK)
1374                 return retval;
1375
1376         LOG_DEBUG("disable single-step");
1377         retval = xscale_disable_single_step(target);
1378         if (retval != ERROR_OK)
1379                 return retval;
1380
1381         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1382
1383         return ERROR_OK;
1384 }
1385
1386 static int xscale_step(struct target *target, int current,
1387         target_addr_t address, int handle_breakpoints)
1388 {
1389         struct arm *arm = target_to_arm(target);
1390         struct breakpoint *breakpoint = NULL;
1391
1392         uint32_t current_pc;
1393         int retval;
1394
1395         if (target->state != TARGET_HALTED) {
1396                 LOG_WARNING("target not halted");
1397                 return ERROR_TARGET_NOT_HALTED;
1398         }
1399
1400         /* current = 1: continue on current pc, otherwise continue at <address> */
1401         if (!current)
1402                 buf_set_u32(arm->pc->value, 0, 32, address);
1403
1404         current_pc = buf_get_u32(arm->pc->value, 0, 32);
1405
1406         /* if we're at the reset vector, we have to simulate the step */
1407         if (current_pc == 0x0) {
1408                 retval = arm_simulate_step(target, NULL);
1409                 if (retval != ERROR_OK)
1410                         return retval;
1411                 current_pc = buf_get_u32(arm->pc->value, 0, 32);
1412                 LOG_DEBUG("current pc %" PRIx32, current_pc);
1413
1414                 target->debug_reason = DBG_REASON_SINGLESTEP;
1415                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1416
1417                 return ERROR_OK;
1418         }
1419
1420         /* the front-end may request us not to handle breakpoints */
1421         if (handle_breakpoints)
1422                 breakpoint = breakpoint_find(target,
1423                                 buf_get_u32(arm->pc->value, 0, 32));
1424         if (breakpoint) {
1425                 retval = xscale_unset_breakpoint(target, breakpoint);
1426                 if (retval != ERROR_OK)
1427                         return retval;
1428         }
1429
1430         retval = xscale_step_inner(target, current, address, handle_breakpoints);
1431         if (retval != ERROR_OK)
1432                 return retval;
1433
1434         if (breakpoint)
1435                 xscale_set_breakpoint(target, breakpoint);
1436
1437         LOG_DEBUG("target stepped");
1438
1439         return ERROR_OK;
1440
1441 }
1442
1443 static int xscale_assert_reset(struct target *target)
1444 {
1445         struct xscale_common *xscale = target_to_xscale(target);
1446
1447         /* TODO: apply hw reset signal in not examined state */
1448         if (!(target_was_examined(target))) {
1449                 LOG_WARNING("Reset is not asserted because the target is not examined.");
1450                 LOG_WARNING("Use a reset button or power cycle the target.");
1451                 return ERROR_TARGET_NOT_EXAMINED;
1452         }
1453
1454         LOG_DEBUG("target->state: %s",
1455                 target_state_name(target));
1456
1457         /* assert reset */
1458         jtag_add_reset(0, 1);
1459
1460         /* sleep 1ms, to be sure we fulfill any requirements */
1461         jtag_add_sleep(1000);
1462         jtag_execute_queue();
1463
1464         /* select DCSR instruction (set endstate to R-T-I to ensure we don't
1465          * end up in T-L-R, which would reset JTAG
1466          */
1467         xscale_jtag_set_instr(target->tap,
1468                 XSCALE_SELDCSR << xscale->xscale_variant,
1469                 TAP_IDLE);
1470
1471         /* set Hold reset, Halt mode and Trap Reset */
1472         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1473         buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1474         xscale_write_dcsr(target, 1, 0);
1475
1476         /* select BYPASS, because having DCSR selected caused problems on the PXA27x */
1477         xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
1478         jtag_execute_queue();
1479
1480         target->state = TARGET_RESET;
1481
1482         if (target->reset_halt) {
1483                 int retval = target_halt(target);
1484                 if (retval != ERROR_OK)
1485                         return retval;
1486         }
1487
1488         return ERROR_OK;
1489 }
1490
1491 static int xscale_deassert_reset(struct target *target)
1492 {
1493         struct xscale_common *xscale = target_to_xscale(target);
1494         struct breakpoint *breakpoint = target->breakpoints;
1495
1496         LOG_DEBUG("-");
1497
1498         xscale->ibcr_available = 2;
1499         xscale->ibcr0_used = 0;
1500         xscale->ibcr1_used = 0;
1501
1502         xscale->dbr_available = 2;
1503         xscale->dbr0_used = 0;
1504         xscale->dbr1_used = 0;
1505
1506         /* mark all hardware breakpoints as unset */
1507         while (breakpoint) {
1508                 if (breakpoint->type == BKPT_HARD)
1509                         breakpoint->is_set = false;
1510                 breakpoint = breakpoint->next;
1511         }
1512
1513         xscale->trace.mode = XSCALE_TRACE_DISABLED;
1514         xscale_free_trace_data(xscale);
1515
1516         register_cache_invalidate(xscale->arm.core_cache);
1517
1518         /* FIXME mark hardware watchpoints got unset too.  Also,
1519          * at least some of the XScale registers are invalid...
1520          */
1521
1522         /*
1523          * REVISIT:  *assumes* we had a SRST+TRST reset so the mini-icache
1524          * contents got invalidated.  Safer to force that, so writing new
1525          * contents can't ever fail..
1526          */
1527         {
1528                 uint32_t address;
1529                 unsigned buf_cnt;
1530                 const uint8_t *buffer = xscale_debug_handler;
1531                 int retval;
1532
1533                 /* release SRST */
1534                 jtag_add_reset(0, 0);
1535
1536                 /* wait 300ms; 150 and 100ms were not enough */
1537                 jtag_add_sleep(300*1000);
1538
1539                 jtag_add_runtest(2030, TAP_IDLE);
1540                 jtag_execute_queue();
1541
1542                 /* set Hold reset, Halt mode and Trap Reset */
1543                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1544                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1545                 xscale_write_dcsr(target, 1, 0);
1546
1547                 /* Load the debug handler into the mini-icache.  Since
1548                  * it's using halt mode (not monitor mode), it runs in
1549                  * "Special Debug State" for access to registers, memory,
1550                  * coprocessors, trace data, etc.
1551                  */
1552                 address = xscale->handler_address;
1553                 for (unsigned binary_size = sizeof(xscale_debug_handler);
1554                         binary_size > 0;
1555                         binary_size -= buf_cnt, buffer += buf_cnt) {
1556                         uint32_t cache_line[8];
1557                         unsigned i;
1558
1559                         buf_cnt = binary_size;
1560                         if (buf_cnt > 32)
1561                                 buf_cnt = 32;
1562
1563                         for (i = 0; i < buf_cnt; i += 4) {
1564                                 /* convert LE buffer to host-endian uint32_t */
1565                                 cache_line[i / 4] = le_to_h_u32(&buffer[i]);
1566                         }
1567
1568                         for (; i < 32; i += 4)
1569                                 cache_line[i / 4] = 0xe1a08008;
1570
1571                         /* only load addresses other than the reset vectors */
1572                         if ((address % 0x400) != 0x0) {
1573                                 retval = xscale_load_ic(target, address,
1574                                                 cache_line);
1575                                 if (retval != ERROR_OK)
1576                                         return retval;
1577                         }
1578
1579                         address += buf_cnt;
1580                 }
1581
1582                 retval = xscale_load_ic(target, 0x0,
1583                                 xscale->low_vectors);
1584                 if (retval != ERROR_OK)
1585                         return retval;
1586                 retval = xscale_load_ic(target, 0xffff0000,
1587                                 xscale->high_vectors);
1588                 if (retval != ERROR_OK)
1589                         return retval;
1590
1591                 jtag_add_runtest(30, TAP_IDLE);
1592
1593                 jtag_add_sleep(100000);
1594
1595                 /* set Hold reset, Halt mode and Trap Reset */
1596                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
1597                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
1598                 xscale_write_dcsr(target, 1, 0);
1599
1600                 /* clear Hold reset to let the target run (should enter debug handler) */
1601                 xscale_write_dcsr(target, 0, 1);
1602                 target->state = TARGET_RUNNING;
1603
1604                 if (!target->reset_halt) {
1605                         jtag_add_sleep(10000);
1606
1607                         /* we should have entered debug now */
1608                         xscale_debug_entry(target);
1609                         target->state = TARGET_HALTED;
1610
1611                         /* resume the target */
1612                         xscale_resume(target, 1, 0x0, 1, 0);
1613                 }
1614         }
1615
1616         return ERROR_OK;
1617 }
1618
1619 static int xscale_read_core_reg(struct target *target, struct reg *r,
1620         int num, enum arm_mode mode)
1621 {
1622         /** \todo add debug handler support for core register reads */
1623         LOG_ERROR("not implemented");
1624         return ERROR_OK;
1625 }
1626
1627 static int xscale_write_core_reg(struct target *target, struct reg *r,
1628         int num, enum arm_mode mode, uint8_t *value)
1629 {
1630         /** \todo add debug handler support for core register writes */
1631         LOG_ERROR("not implemented");
1632         return ERROR_OK;
1633 }
1634
1635 static int xscale_full_context(struct target *target)
1636 {
1637         struct arm *arm = target_to_arm(target);
1638
1639         uint32_t *buffer;
1640
1641         int i, j;
1642
1643         LOG_DEBUG("-");
1644
1645         if (target->state != TARGET_HALTED) {
1646                 LOG_WARNING("target not halted");
1647                 return ERROR_TARGET_NOT_HALTED;
1648         }
1649
1650         buffer = malloc(4 * 8);
1651
1652         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1653          * we can't enter User mode on an XScale (unpredictable),
1654          * but User shares registers with SYS
1655          */
1656         for (i = 1; i < 7; i++) {
1657                 enum arm_mode mode = armv4_5_number_to_mode(i);
1658                 bool valid = true;
1659                 struct reg *r;
1660
1661                 if (mode == ARM_MODE_USR)
1662                         continue;
1663
1664                 /* check if there are invalid registers in the current mode
1665                  */
1666                 for (j = 0; valid && j <= 16; j++) {
1667                         if (!ARMV4_5_CORE_REG_MODE(arm->core_cache,
1668                                 mode, j).valid)
1669                                 valid = false;
1670                 }
1671                 if (valid)
1672                         continue;
1673
1674                 /* request banked registers */
1675                 xscale_send_u32(target, 0x0);
1676
1677                 /* send CPSR for desired bank mode */
1678                 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1679
1680                 /* get banked registers:  r8 to r14; and SPSR
1681                  * except in USR/SYS mode
1682                  */
1683                 if (mode != ARM_MODE_SYS) {
1684                         /* SPSR */
1685                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1686                                         mode, 16);
1687
1688                         xscale_receive(target, buffer, 8);
1689
1690                         buf_set_u32(r->value, 0, 32, buffer[7]);
1691                         r->dirty = false;
1692                         r->valid = true;
1693                 } else
1694                         xscale_receive(target, buffer, 7);
1695
1696                 /* move data from buffer to register cache */
1697                 for (j = 8; j <= 14; j++) {
1698                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1699                                         mode, j);
1700
1701                         buf_set_u32(r->value, 0, 32, buffer[j - 8]);
1702                         r->dirty = false;
1703                         r->valid = true;
1704                 }
1705         }
1706
1707         free(buffer);
1708
1709         return ERROR_OK;
1710 }
1711
1712 static int xscale_restore_banked(struct target *target)
1713 {
1714         struct arm *arm = target_to_arm(target);
1715
1716         int i, j;
1717
1718         if (target->state != TARGET_HALTED) {
1719                 LOG_WARNING("target not halted");
1720                 return ERROR_TARGET_NOT_HALTED;
1721         }
1722
1723         /* iterate through processor modes (FIQ, IRQ, SVC, ABT, UND and SYS)
1724          * and check if any banked registers need to be written.  Ignore
1725          * USR mode (number 0) in favor of SYS; we can't enter User mode on
1726          * an XScale (unpredictable), but they share all registers.
1727          */
1728         for (i = 1; i < 7; i++) {
1729                 enum arm_mode mode = armv4_5_number_to_mode(i);
1730                 struct reg *r;
1731
1732                 if (mode == ARM_MODE_USR)
1733                         continue;
1734
1735                 /* check if there are dirty registers in this mode */
1736                 for (j = 8; j <= 14; j++) {
1737                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
1738                                 mode, j).dirty)
1739                                 goto dirty;
1740                 }
1741
1742                 /* if not USR/SYS, check if the SPSR needs to be written */
1743                 if (mode != ARM_MODE_SYS) {
1744                         if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
1745                                 mode, 16).dirty)
1746                                 goto dirty;
1747                 }
1748
1749                 /* there's nothing to flush for this mode */
1750                 continue;
1751
1752 dirty:
1753                 /* command 0x1:  "send banked registers" */
1754                 xscale_send_u32(target, 0x1);
1755
1756                 /* send CPSR for desired mode */
1757                 xscale_send_u32(target, mode | 0xc0 /* I/F bits */);
1758
1759                 /* send r8 to r14/lr ... only FIQ needs more than r13..r14,
1760                  * but this protocol doesn't understand that nuance.
1761                  */
1762                 for (j = 8; j <= 14; j++) {
1763                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1764                                         mode, j);
1765                         xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1766                         r->dirty = false;
1767                 }
1768
1769                 /* send spsr if not in USR/SYS mode */
1770                 if (mode != ARM_MODE_SYS) {
1771                         r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1772                                         mode, 16);
1773                         xscale_send_u32(target, buf_get_u32(r->value, 0, 32));
1774                         r->dirty = false;
1775                 }
1776         }
1777
1778         return ERROR_OK;
1779 }
1780
1781 static int xscale_read_memory(struct target *target, target_addr_t address,
1782         uint32_t size, uint32_t count, uint8_t *buffer)
1783 {
1784         struct xscale_common *xscale = target_to_xscale(target);
1785         uint32_t *buf32;
1786         uint32_t i;
1787         int retval;
1788
1789         LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1790                 address,
1791                 size,
1792                 count);
1793
1794         if (target->state != TARGET_HALTED) {
1795                 LOG_WARNING("target not halted");
1796                 return ERROR_TARGET_NOT_HALTED;
1797         }
1798
1799         /* sanitize arguments */
1800         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1801                 return ERROR_COMMAND_SYNTAX_ERROR;
1802
1803         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1804                 return ERROR_TARGET_UNALIGNED_ACCESS;
1805
1806         /* send memory read request (command 0x1n, n: access size) */
1807         retval = xscale_send_u32(target, 0x10 | size);
1808         if (retval != ERROR_OK)
1809                 return retval;
1810
1811         /* send base address for read request */
1812         retval = xscale_send_u32(target, address);
1813         if (retval != ERROR_OK)
1814                 return retval;
1815
1816         /* send number of requested data words */
1817         retval = xscale_send_u32(target, count);
1818         if (retval != ERROR_OK)
1819                 return retval;
1820
1821         /* receive data from target (count times 32-bit words in host endianness) */
1822         buf32 = malloc(4 * count);
1823         retval = xscale_receive(target, buf32, count);
1824         if (retval != ERROR_OK) {
1825                 free(buf32);
1826                 return retval;
1827         }
1828
1829         /* extract data from host-endian buffer into byte stream */
1830         for (i = 0; i < count; i++) {
1831                 switch (size) {
1832                         case 4:
1833                                 target_buffer_set_u32(target, buffer, buf32[i]);
1834                                 buffer += 4;
1835                                 break;
1836                         case 2:
1837                                 target_buffer_set_u16(target, buffer, buf32[i] & 0xffff);
1838                                 buffer += 2;
1839                                 break;
1840                         case 1:
1841                                 *buffer++ = buf32[i] & 0xff;
1842                                 break;
1843                         default:
1844                                 LOG_ERROR("invalid read size");
1845                                 return ERROR_COMMAND_SYNTAX_ERROR;
1846                 }
1847         }
1848
1849         free(buf32);
1850
1851         /* examine DCSR, to see if Sticky Abort (SA) got set */
1852         retval = xscale_read_dcsr(target);
1853         if (retval != ERROR_OK)
1854                 return retval;
1855         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
1856                 /* clear SA bit */
1857                 retval = xscale_send_u32(target, 0x60);
1858                 if (retval != ERROR_OK)
1859                         return retval;
1860
1861                 return ERROR_TARGET_DATA_ABORT;
1862         }
1863
1864         return ERROR_OK;
1865 }
1866
1867 static int xscale_read_phys_memory(struct target *target, target_addr_t address,
1868         uint32_t size, uint32_t count, uint8_t *buffer)
1869 {
1870         struct xscale_common *xscale = target_to_xscale(target);
1871
1872         /* with MMU inactive, there are only physical addresses */
1873         if (!xscale->armv4_5_mmu.mmu_enabled)
1874                 return xscale_read_memory(target, address, size, count, buffer);
1875
1876         /** \todo: provide a non-stub implementation of this routine. */
1877         LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
1878                 target_name(target), __func__);
1879         return ERROR_FAIL;
1880 }
1881
1882 static int xscale_write_memory(struct target *target, target_addr_t address,
1883         uint32_t size, uint32_t count, const uint8_t *buffer)
1884 {
1885         struct xscale_common *xscale = target_to_xscale(target);
1886         int retval;
1887
1888         LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
1889                 address,
1890                 size,
1891                 count);
1892
1893         if (target->state != TARGET_HALTED) {
1894                 LOG_WARNING("target not halted");
1895                 return ERROR_TARGET_NOT_HALTED;
1896         }
1897
1898         /* sanitize arguments */
1899         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1900                 return ERROR_COMMAND_SYNTAX_ERROR;
1901
1902         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1903                 return ERROR_TARGET_UNALIGNED_ACCESS;
1904
1905         /* send memory write request (command 0x2n, n: access size) */
1906         retval = xscale_send_u32(target, 0x20 | size);
1907         if (retval != ERROR_OK)
1908                 return retval;
1909
1910         /* send base address for read request */
1911         retval = xscale_send_u32(target, address);
1912         if (retval != ERROR_OK)
1913                 return retval;
1914
1915         /* send number of requested data words to be written*/
1916         retval = xscale_send_u32(target, count);
1917         if (retval != ERROR_OK)
1918                 return retval;
1919
1920         /* extract data from host-endian buffer into byte stream */
1921 #if 0
1922         for (i = 0; i < count; i++) {
1923                 switch (size) {
1924                         case 4:
1925                                 value = target_buffer_get_u32(target, buffer);
1926                                 xscale_send_u32(target, value);
1927                                 buffer += 4;
1928                                 break;
1929                         case 2:
1930                                 value = target_buffer_get_u16(target, buffer);
1931                                 xscale_send_u32(target, value);
1932                                 buffer += 2;
1933                                 break;
1934                         case 1:
1935                                 value = *buffer;
1936                                 xscale_send_u32(target, value);
1937                                 buffer += 1;
1938                                 break;
1939                         default:
1940                                 LOG_ERROR("should never get here");
1941                                 exit(-1);
1942                 }
1943         }
1944 #endif
1945         retval = xscale_send(target, buffer, count, size);
1946         if (retval != ERROR_OK)
1947                 return retval;
1948
1949         /* examine DCSR, to see if Sticky Abort (SA) got set */
1950         retval = xscale_read_dcsr(target);
1951         if (retval != ERROR_OK)
1952                 return retval;
1953         if (buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 5, 1) == 1) {
1954                 /* clear SA bit */
1955                 retval = xscale_send_u32(target, 0x60);
1956                 if (retval != ERROR_OK)
1957                         return retval;
1958
1959                 LOG_ERROR("data abort writing memory");
1960                 return ERROR_TARGET_DATA_ABORT;
1961         }
1962
1963         return ERROR_OK;
1964 }
1965
1966 static int xscale_write_phys_memory(struct target *target, target_addr_t address,
1967         uint32_t size, uint32_t count, const uint8_t *buffer)
1968 {
1969         struct xscale_common *xscale = target_to_xscale(target);
1970
1971         /* with MMU inactive, there are only physical addresses */
1972         if (!xscale->armv4_5_mmu.mmu_enabled)
1973                 return xscale_write_memory(target, address, size, count, buffer);
1974
1975         /** \todo: provide a non-stub implementation of this routine. */
1976         LOG_ERROR("%s: %s is not implemented.  Disable MMU?",
1977                 target_name(target), __func__);
1978         return ERROR_FAIL;
1979 }
1980
1981 static int xscale_get_ttb(struct target *target, uint32_t *result)
1982 {
1983         struct xscale_common *xscale = target_to_xscale(target);
1984         uint32_t ttb;
1985         int retval;
1986
1987         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_TTB]);
1988         if (retval != ERROR_OK)
1989                 return retval;
1990         ttb = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_TTB].value, 0, 32);
1991
1992         *result = ttb;
1993
1994         return ERROR_OK;
1995 }
1996
1997 static int xscale_disable_mmu_caches(struct target *target, int mmu,
1998         int d_u_cache, int i_cache)
1999 {
2000         struct xscale_common *xscale = target_to_xscale(target);
2001         uint32_t cp15_control;
2002         int retval;
2003
2004         /* read cp15 control register */
2005         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2006         if (retval != ERROR_OK)
2007                 return retval;
2008         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2009
2010         if (mmu)
2011                 cp15_control &= ~0x1U;
2012
2013         if (d_u_cache) {
2014                 /* clean DCache */
2015                 retval = xscale_send_u32(target, 0x50);
2016                 if (retval != ERROR_OK)
2017                         return retval;
2018                 retval = xscale_send_u32(target, xscale->cache_clean_address);
2019                 if (retval != ERROR_OK)
2020                         return retval;
2021
2022                 /* invalidate DCache */
2023                 retval = xscale_send_u32(target, 0x51);
2024                 if (retval != ERROR_OK)
2025                         return retval;
2026
2027                 cp15_control &= ~0x4U;
2028         }
2029
2030         if (i_cache) {
2031                 /* invalidate ICache */
2032                 retval = xscale_send_u32(target, 0x52);
2033                 if (retval != ERROR_OK)
2034                         return retval;
2035                 cp15_control &= ~0x1000U;
2036         }
2037
2038         /* write new cp15 control register */
2039         retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2040         if (retval != ERROR_OK)
2041                 return retval;
2042
2043         /* execute cpwait to ensure outstanding operations complete */
2044         retval = xscale_send_u32(target, 0x53);
2045         return retval;
2046 }
2047
2048 static int xscale_enable_mmu_caches(struct target *target, int mmu,
2049         int d_u_cache, int i_cache)
2050 {
2051         struct xscale_common *xscale = target_to_xscale(target);
2052         uint32_t cp15_control;
2053         int retval;
2054
2055         /* read cp15 control register */
2056         retval = xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
2057         if (retval != ERROR_OK)
2058                 return retval;
2059         cp15_control = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
2060
2061         if (mmu)
2062                 cp15_control |= 0x1U;
2063
2064         if (d_u_cache)
2065                 cp15_control |= 0x4U;
2066
2067         if (i_cache)
2068                 cp15_control |= 0x1000U;
2069
2070         /* write new cp15 control register */
2071         retval = xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_CTRL], cp15_control);
2072         if (retval != ERROR_OK)
2073                 return retval;
2074
2075         /* execute cpwait to ensure outstanding operations complete */
2076         retval = xscale_send_u32(target, 0x53);
2077         return retval;
2078 }
2079
2080 static int xscale_set_breakpoint(struct target *target,
2081         struct breakpoint *breakpoint)
2082 {
2083         int retval;
2084         struct xscale_common *xscale = target_to_xscale(target);
2085
2086         if (target->state != TARGET_HALTED) {
2087                 LOG_WARNING("target not halted");
2088                 return ERROR_TARGET_NOT_HALTED;
2089         }
2090
2091         if (breakpoint->is_set) {
2092                 LOG_WARNING("breakpoint already set");
2093                 return ERROR_OK;
2094         }
2095
2096         if (breakpoint->type == BKPT_HARD) {
2097                 uint32_t value = breakpoint->address | 1;
2098                 if (!xscale->ibcr0_used) {
2099                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], value);
2100                         xscale->ibcr0_used = 1;
2101                         /* breakpoint set on first breakpoint register */
2102                         breakpoint_hw_set(breakpoint, 0);
2103                 } else if (!xscale->ibcr1_used) {
2104                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], value);
2105                         xscale->ibcr1_used = 1;
2106                         /* breakpoint set on second breakpoint register */
2107                         breakpoint_hw_set(breakpoint, 1);
2108                 } else {/* bug: availability previously verified in xscale_add_breakpoint() */
2109                         LOG_ERROR("BUG: no hardware comparator available");
2110                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2111                 }
2112         } else if (breakpoint->type == BKPT_SOFT) {
2113                 if (breakpoint->length == 4) {
2114                         /* keep the original instruction in target endianness */
2115                         retval = target_read_memory(target, breakpoint->address, 4, 1,
2116                                         breakpoint->orig_instr);
2117                         if (retval != ERROR_OK)
2118                                 return retval;
2119                         /* write the bkpt instruction in target endianness
2120                          *(arm7_9->arm_bkpt is host endian) */
2121                         retval = target_write_u32(target, breakpoint->address,
2122                                         xscale->arm_bkpt);
2123                         if (retval != ERROR_OK)
2124                                 return retval;
2125                 } else {
2126                         /* keep the original instruction in target endianness */
2127                         retval = target_read_memory(target, breakpoint->address, 2, 1,
2128                                         breakpoint->orig_instr);
2129                         if (retval != ERROR_OK)
2130                                 return retval;
2131                         /* write the bkpt instruction in target endianness
2132                          *(arm7_9->arm_bkpt is host endian) */
2133                         retval = target_write_u16(target, breakpoint->address,
2134                                         xscale->thumb_bkpt);
2135                         if (retval != ERROR_OK)
2136                                 return retval;
2137                 }
2138                 breakpoint->is_set = true;
2139
2140                 xscale_send_u32(target, 0x50);  /* clean dcache */
2141                 xscale_send_u32(target, xscale->cache_clean_address);
2142                 xscale_send_u32(target, 0x51);  /* invalidate dcache */
2143                 xscale_send_u32(target, 0x52);  /* invalidate icache and flush fetch buffers */
2144         }
2145
2146         return ERROR_OK;
2147 }
2148
2149 static int xscale_add_breakpoint(struct target *target,
2150         struct breakpoint *breakpoint)
2151 {
2152         struct xscale_common *xscale = target_to_xscale(target);
2153
2154         if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1)) {
2155                 LOG_ERROR("no breakpoint unit available for hardware breakpoint");
2156                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2157         }
2158
2159         if ((breakpoint->length != 2) && (breakpoint->length != 4)) {
2160                 LOG_ERROR("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
2161                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2162         }
2163
2164         if (breakpoint->type == BKPT_HARD)
2165                 xscale->ibcr_available--;
2166
2167         return xscale_set_breakpoint(target, breakpoint);
2168 }
2169
2170 static int xscale_unset_breakpoint(struct target *target,
2171         struct breakpoint *breakpoint)
2172 {
2173         int retval;
2174         struct xscale_common *xscale = target_to_xscale(target);
2175
2176         if (target->state != TARGET_HALTED) {
2177                 LOG_WARNING("target not halted");
2178                 return ERROR_TARGET_NOT_HALTED;
2179         }
2180
2181         if (!breakpoint->is_set) {
2182                 LOG_WARNING("breakpoint not set");
2183                 return ERROR_OK;
2184         }
2185
2186         if (breakpoint->type == BKPT_HARD) {
2187                 if (breakpoint->number == 0) {
2188                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR0], 0x0);
2189                         xscale->ibcr0_used = 0;
2190                 } else if (breakpoint->number == 1) {
2191                         xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_IBCR1], 0x0);
2192                         xscale->ibcr1_used = 0;
2193                 }
2194                 breakpoint->is_set = false;
2195         } else {
2196                 /* restore original instruction (kept in target endianness) */
2197                 if (breakpoint->length == 4) {
2198                         retval = target_write_memory(target, breakpoint->address, 4, 1,
2199                                         breakpoint->orig_instr);
2200                         if (retval != ERROR_OK)
2201                                 return retval;
2202                 } else {
2203                         retval = target_write_memory(target, breakpoint->address, 2, 1,
2204                                         breakpoint->orig_instr);
2205                         if (retval != ERROR_OK)
2206                                 return retval;
2207                 }
2208                 breakpoint->is_set = false;
2209
2210                 xscale_send_u32(target, 0x50);  /* clean dcache */
2211                 xscale_send_u32(target, xscale->cache_clean_address);
2212                 xscale_send_u32(target, 0x51);  /* invalidate dcache */
2213                 xscale_send_u32(target, 0x52);  /* invalidate icache and flush fetch buffers */
2214         }
2215
2216         return ERROR_OK;
2217 }
2218
2219 static int xscale_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
2220 {
2221         struct xscale_common *xscale = target_to_xscale(target);
2222
2223         if (target->state != TARGET_HALTED) {
2224                 LOG_ERROR("target not halted");
2225                 return ERROR_TARGET_NOT_HALTED;
2226         }
2227
2228         if (breakpoint->is_set)
2229                 xscale_unset_breakpoint(target, breakpoint);
2230
2231         if (breakpoint->type == BKPT_HARD)
2232                 xscale->ibcr_available++;
2233
2234         return ERROR_OK;
2235 }
2236
2237 static int xscale_set_watchpoint(struct target *target,
2238         struct watchpoint *watchpoint)
2239 {
2240         struct xscale_common *xscale = target_to_xscale(target);
2241         uint32_t enable = 0;
2242         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2243         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2244
2245         if (target->state != TARGET_HALTED) {
2246                 LOG_ERROR("target not halted");
2247                 return ERROR_TARGET_NOT_HALTED;
2248         }
2249
2250         switch (watchpoint->rw) {
2251                 case WPT_READ:
2252                         enable = 0x3;
2253                         break;
2254                 case WPT_ACCESS:
2255                         enable = 0x2;
2256                         break;
2257                 case WPT_WRITE:
2258                         enable = 0x1;
2259                         break;
2260                 default:
2261                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
2262         }
2263
2264         /* For watchpoint across more than one word, both DBR registers must
2265            be enlisted, with the second used as a mask. */
2266         if (watchpoint->length > 4) {
2267                 if (xscale->dbr0_used || xscale->dbr1_used) {
2268                         LOG_ERROR("BUG: sufficient hardware comparators unavailable");
2269                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2270                 }
2271
2272                 /* Write mask value to DBR1, based on the length argument.
2273                  * Address bits ignored by the comparator are those set in mask. */
2274                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1],
2275                         watchpoint->length - 1);
2276                 xscale->dbr1_used = 1;
2277                 enable |= 0x100;                /* DBCON[M] */
2278         }
2279
2280         if (!xscale->dbr0_used) {
2281                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR0], watchpoint->address);
2282                 dbcon_value |= enable;
2283                 xscale_set_reg_u32(dbcon, dbcon_value);
2284                 watchpoint_set(watchpoint, 0);
2285                 xscale->dbr0_used = 1;
2286         } else if (!xscale->dbr1_used) {
2287                 xscale_set_reg_u32(&xscale->reg_cache->reg_list[XSCALE_DBR1], watchpoint->address);
2288                 dbcon_value |= enable << 2;
2289                 xscale_set_reg_u32(dbcon, dbcon_value);
2290                 watchpoint_set(watchpoint, 1);
2291                 xscale->dbr1_used = 1;
2292         } else {
2293                 LOG_ERROR("BUG: no hardware comparator available");
2294                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2295         }
2296
2297         return ERROR_OK;
2298 }
2299
2300 static int xscale_add_watchpoint(struct target *target,
2301         struct watchpoint *watchpoint)
2302 {
2303         struct xscale_common *xscale = target_to_xscale(target);
2304
2305         if (xscale->dbr_available < 1) {
2306                 LOG_ERROR("no more watchpoint registers available");
2307                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2308         }
2309
2310         if (watchpoint->value)
2311                 LOG_WARNING("xscale does not support value, mask arguments; ignoring");
2312
2313         /* check that length is a power of two */
2314         for (uint32_t len = watchpoint->length; len != 1; len /= 2) {
2315                 if (len % 2) {
2316                         LOG_ERROR("xscale requires that watchpoint length is a power of two");
2317                         return ERROR_COMMAND_ARGUMENT_INVALID;
2318                 }
2319         }
2320
2321         if (watchpoint->length == 4) {  /* single word watchpoint */
2322                 xscale->dbr_available--;/* one DBR reg used */
2323                 return ERROR_OK;
2324         }
2325
2326         /* watchpoints across multiple words require both DBR registers */
2327         if (xscale->dbr_available < 2) {
2328                 LOG_ERROR("insufficient watchpoint registers available");
2329                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
2330         }
2331
2332         if (watchpoint->length > watchpoint->address) {
2333                 LOG_ERROR("xscale does not support watchpoints with length "
2334                         "greater than address");
2335                 return ERROR_COMMAND_ARGUMENT_INVALID;
2336         }
2337
2338         xscale->dbr_available = 0;
2339         return ERROR_OK;
2340 }
2341
2342 static int xscale_unset_watchpoint(struct target *target,
2343         struct watchpoint *watchpoint)
2344 {
2345         struct xscale_common *xscale = target_to_xscale(target);
2346         struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
2347         uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
2348
2349         if (target->state != TARGET_HALTED) {
2350                 LOG_WARNING("target not halted");
2351                 return ERROR_TARGET_NOT_HALTED;
2352         }
2353
2354         if (!watchpoint->is_set) {
2355                 LOG_WARNING("breakpoint not set");
2356                 return ERROR_OK;
2357         }
2358
2359         if (watchpoint->number == 0) {
2360                 if (watchpoint->length > 4) {
2361                         dbcon_value &= ~0x103;  /* clear DBCON[M] as well */
2362                         xscale->dbr1_used = 0;  /* DBR1 was used for mask */
2363                 } else
2364                         dbcon_value &= ~0x3;
2365
2366                 xscale_set_reg_u32(dbcon, dbcon_value);
2367                 xscale->dbr0_used = 0;
2368         } else if (watchpoint->number == 1) {
2369                 dbcon_value &= ~0xc;
2370                 xscale_set_reg_u32(dbcon, dbcon_value);
2371                 xscale->dbr1_used = 0;
2372         }
2373         watchpoint->is_set = false;
2374
2375         return ERROR_OK;
2376 }
2377
2378 static int xscale_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
2379 {
2380         struct xscale_common *xscale = target_to_xscale(target);
2381
2382         if (target->state != TARGET_HALTED) {
2383                 LOG_ERROR("target not halted");
2384                 return ERROR_TARGET_NOT_HALTED;
2385         }
2386
2387         if (watchpoint->is_set)
2388                 xscale_unset_watchpoint(target, watchpoint);
2389
2390         if (watchpoint->length > 4)
2391                 xscale->dbr_available++;/* both DBR regs now available */
2392
2393         xscale->dbr_available++;
2394
2395         return ERROR_OK;
2396 }
2397
2398 static int xscale_get_reg(struct reg *reg)
2399 {
2400         struct xscale_reg *arch_info = reg->arch_info;
2401         struct target *target = arch_info->target;
2402         struct xscale_common *xscale = target_to_xscale(target);
2403
2404         /* DCSR, TX and RX are accessible via JTAG */
2405         if (strcmp(reg->name, "XSCALE_DCSR") == 0)
2406                 return xscale_read_dcsr(arch_info->target);
2407         else if (strcmp(reg->name, "XSCALE_TX") == 0) {
2408                 /* 1 = consume register content */
2409                 return xscale_read_tx(arch_info->target, 1);
2410         } else if (strcmp(reg->name, "XSCALE_RX") == 0) {
2411                 /* can't read from RX register (host -> debug handler) */
2412                 return ERROR_OK;
2413         } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
2414                 /* can't (explicitly) read from TXRXCTRL register */
2415                 return ERROR_OK;
2416         } else {/* Other DBG registers have to be transferred by the debug handler
2417                  * send CP read request (command 0x40) */
2418                 xscale_send_u32(target, 0x40);
2419
2420                 /* send CP register number */
2421                 xscale_send_u32(target, arch_info->dbg_handler_number);
2422
2423                 /* read register value */
2424                 xscale_read_tx(target, 1);
2425                 buf_cpy(xscale->reg_cache->reg_list[XSCALE_TX].value, reg->value, 32);
2426
2427                 reg->dirty = false;
2428                 reg->valid = true;
2429         }
2430
2431         return ERROR_OK;
2432 }
2433
2434 static int xscale_set_reg(struct reg *reg, uint8_t *buf)
2435 {
2436         struct xscale_reg *arch_info = reg->arch_info;
2437         struct target *target = arch_info->target;
2438         struct xscale_common *xscale = target_to_xscale(target);
2439         uint32_t value = buf_get_u32(buf, 0, 32);
2440
2441         /* DCSR, TX and RX are accessible via JTAG */
2442         if (strcmp(reg->name, "XSCALE_DCSR") == 0) {
2443                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32, value);
2444                 return xscale_write_dcsr(arch_info->target, -1, -1);
2445         } else if (strcmp(reg->name, "XSCALE_RX") == 0) {
2446                 buf_set_u32(xscale->reg_cache->reg_list[XSCALE_RX].value, 0, 32, value);
2447                 return xscale_write_rx(arch_info->target);
2448         } else if (strcmp(reg->name, "XSCALE_TX") == 0) {
2449                 /* can't write to TX register (debug-handler -> host) */
2450                 return ERROR_OK;
2451         } else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
2452                 /* can't (explicitly) write to TXRXCTRL register */
2453                 return ERROR_OK;
2454         } else {/* Other DBG registers have to be transferred by the debug handler
2455                  * send CP write request (command 0x41) */
2456                 xscale_send_u32(target, 0x41);
2457
2458                 /* send CP register number */
2459                 xscale_send_u32(target, arch_info->dbg_handler_number);
2460
2461                 /* send CP register value */
2462                 xscale_send_u32(target, value);
2463                 buf_set_u32(reg->value, 0, 32, value);
2464         }
2465
2466         return ERROR_OK;
2467 }
2468
2469 static int xscale_write_dcsr_sw(struct target *target, uint32_t value)
2470 {
2471         struct xscale_common *xscale = target_to_xscale(target);
2472         struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
2473         struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
2474
2475         /* send CP write request (command 0x41) */
2476         xscale_send_u32(target, 0x41);
2477
2478         /* send CP register number */
2479         xscale_send_u32(target, dcsr_arch_info->dbg_handler_number);
2480
2481         /* send CP register value */
2482         xscale_send_u32(target, value);
2483         buf_set_u32(dcsr->value, 0, 32, value);
2484
2485         return ERROR_OK;
2486 }
2487
2488 static int xscale_read_trace(struct target *target)
2489 {
2490         struct xscale_common *xscale = target_to_xscale(target);
2491         struct arm *arm = &xscale->arm;
2492         struct xscale_trace_data **trace_data_p;
2493
2494         /* 258 words from debug handler
2495          * 256 trace buffer entries
2496          * 2 checkpoint addresses
2497          */
2498         uint32_t trace_buffer[258];
2499         int is_address[256];
2500         int i, j;
2501         unsigned int num_checkpoints = 0;
2502
2503         if (target->state != TARGET_HALTED) {
2504                 LOG_WARNING("target must be stopped to read trace data");
2505                 return ERROR_TARGET_NOT_HALTED;
2506         }
2507
2508         /* send read trace buffer command (command 0x61) */
2509         xscale_send_u32(target, 0x61);
2510
2511         /* receive trace buffer content */
2512         xscale_receive(target, trace_buffer, 258);
2513
2514         /* parse buffer backwards to identify address entries */
2515         for (i = 255; i >= 0; i--) {
2516                 /* also count number of checkpointed entries */
2517                 if ((trace_buffer[i] & 0xe0) == 0xc0)
2518                         num_checkpoints++;
2519
2520                 is_address[i] = 0;
2521                 if (((trace_buffer[i] & 0xf0) == 0x90) ||
2522                         ((trace_buffer[i] & 0xf0) == 0xd0)) {
2523                         if (i > 0)
2524                                 is_address[--i] = 1;
2525                         if (i > 0)
2526                                 is_address[--i] = 1;
2527                         if (i > 0)
2528                                 is_address[--i] = 1;
2529                         if (i > 0)
2530                                 is_address[--i] = 1;
2531                 }
2532         }
2533
2534
2535         /* search first non-zero entry that is not part of an address */
2536         for (j = 0; (j < 256) && (trace_buffer[j] == 0) && (!is_address[j]); j++)
2537                 ;
2538
2539         if (j == 256) {
2540                 LOG_DEBUG("no trace data collected");
2541                 return ERROR_XSCALE_NO_TRACE_DATA;
2542         }
2543
2544         /* account for possible partial address at buffer start (wrap mode only) */
2545         if (is_address[0]) {    /* first entry is address; complete set of 4? */
2546                 i = 1;
2547                 while (i < 4)
2548                         if (!is_address[i++])
2549                                 break;
2550                 if (i < 4)
2551                         j += i;         /* partial address; can't use it */
2552         }
2553
2554         /* if first valid entry is indirect branch, can't use that either (no address) */
2555         if (((trace_buffer[j] & 0xf0) == 0x90) || ((trace_buffer[j] & 0xf0) == 0xd0))
2556                 j++;
2557
2558         /* walk linked list to terminating entry */
2559         for (trace_data_p = &xscale->trace.data; *trace_data_p;
2560                 trace_data_p = &(*trace_data_p)->next)
2561                 ;
2562
2563         *trace_data_p = malloc(sizeof(struct xscale_trace_data));
2564         (*trace_data_p)->next = NULL;
2565         (*trace_data_p)->chkpt0 = trace_buffer[256];
2566         (*trace_data_p)->chkpt1 = trace_buffer[257];
2567         (*trace_data_p)->last_instruction = buf_get_u32(arm->pc->value, 0, 32);
2568         (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j));
2569         (*trace_data_p)->depth = 256 - j;
2570         (*trace_data_p)->num_checkpoints = num_checkpoints;
2571
2572         for (i = j; i < 256; i++) {
2573                 (*trace_data_p)->entries[i - j].data = trace_buffer[i];
2574                 if (is_address[i])
2575                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_ADDRESS;
2576                 else
2577                         (*trace_data_p)->entries[i - j].type = XSCALE_TRACE_MESSAGE;
2578         }
2579
2580         return ERROR_OK;
2581 }
2582
2583 static int xscale_read_instruction(struct target *target, uint32_t pc,
2584         struct arm_instruction *instruction)
2585 {
2586         struct xscale_common *const xscale = target_to_xscale(target);
2587         int section = -1;
2588         size_t size_read;
2589         uint32_t opcode;
2590         int retval;
2591
2592         if (!xscale->trace.image)
2593                 return ERROR_TRACE_IMAGE_UNAVAILABLE;
2594
2595         /* search for the section the current instruction belongs to */
2596         for (unsigned int i = 0; i < xscale->trace.image->num_sections; i++) {
2597                 if ((xscale->trace.image->sections[i].base_address <= pc) &&
2598                         (xscale->trace.image->sections[i].base_address +
2599                         xscale->trace.image->sections[i].size > pc)) {
2600                         section = i;
2601                         break;
2602                 }
2603         }
2604
2605         if (section == -1) {
2606                 /* current instruction couldn't be found in the image */
2607                 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2608         }
2609
2610         if (xscale->trace.core_state == ARM_STATE_ARM) {
2611                 uint8_t buf[4];
2612                 retval = image_read_section(xscale->trace.image, section,
2613                                 pc - xscale->trace.image->sections[section].base_address,
2614                                 4, buf, &size_read);
2615                 if (retval != ERROR_OK) {
2616                         LOG_ERROR("error while reading instruction");
2617                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2618                 }
2619                 opcode = target_buffer_get_u32(target, buf);
2620                 arm_evaluate_opcode(opcode, pc, instruction);
2621         } else if (xscale->trace.core_state == ARM_STATE_THUMB) {
2622                 uint8_t buf[2];
2623                 retval = image_read_section(xscale->trace.image, section,
2624                                 pc - xscale->trace.image->sections[section].base_address,
2625                                 2, buf, &size_read);
2626                 if (retval != ERROR_OK) {
2627                         LOG_ERROR("error while reading instruction");
2628                         return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
2629                 }
2630                 opcode = target_buffer_get_u16(target, buf);
2631                 thumb_evaluate_opcode(opcode, pc, instruction);
2632         } else {
2633                 LOG_ERROR("BUG: unknown core state encountered");
2634                 exit(-1);
2635         }
2636
2637         return ERROR_OK;
2638 }
2639
2640 /* Extract address encoded into trace data.
2641  * Write result to address referenced by argument 'target', or 0 if incomplete.  */
2642 static inline void xscale_branch_address(struct xscale_trace_data *trace_data,
2643         int i, uint32_t *target)
2644 {
2645         /* if there are less than four entries prior to the indirect branch message
2646          * we can't extract the address */
2647         if (i < 4)
2648                 *target = 0;
2649         else {
2650                 *target = (trace_data->entries[i-1].data) | (trace_data->entries[i-2].data << 8) |
2651                         (trace_data->entries[i-3].data << 16) | (trace_data->entries[i-4].data << 24);
2652         }
2653 }
2654
2655 static inline void xscale_display_instruction(struct target *target, uint32_t pc,
2656         struct arm_instruction *instruction,
2657         struct command_invocation *cmd)
2658 {
2659         int retval = xscale_read_instruction(target, pc, instruction);
2660         if (retval == ERROR_OK)
2661                 command_print(cmd, "%s", instruction->text);
2662         else
2663                 command_print(cmd, "0x%8.8" PRIx32 "\t<not found in image>", pc);
2664 }
2665
2666 static int xscale_analyze_trace(struct target *target, struct command_invocation *cmd)
2667 {
2668         struct xscale_common *xscale = target_to_xscale(target);
2669         struct xscale_trace_data *trace_data = xscale->trace.data;
2670         int i, retval;
2671         uint32_t breakpoint_pc = 0;
2672         struct arm_instruction instruction;
2673         uint32_t current_pc = 0;/* initialized when address determined */
2674
2675         if (!xscale->trace.image)
2676                 LOG_WARNING("No trace image loaded; use 'xscale trace_image'");
2677
2678         /* loop for each trace buffer that was loaded from target */
2679         while (trace_data) {
2680                 int chkpt = 0;  /* incremented as checkpointed entries found */
2681                 int j;
2682
2683                 /* FIXME: set this to correct mode when trace buffer is first enabled */
2684                 xscale->trace.core_state = ARM_STATE_ARM;
2685
2686                 /* loop for each entry in this trace buffer */
2687                 for (i = 0; i < trace_data->depth; i++) {
2688                         int exception = 0;
2689                         uint32_t chkpt_reg = 0x0;
2690                         uint32_t branch_target = 0;
2691                         int count;
2692
2693                         /* trace entry type is upper nybble of 'message byte' */
2694                         int trace_msg_type = (trace_data->entries[i].data & 0xf0) >> 4;
2695
2696                         /* Target addresses of indirect branches are written into buffer
2697                          * before the message byte representing the branch. Skip past it */
2698                         if (trace_data->entries[i].type == XSCALE_TRACE_ADDRESS)
2699                                 continue;
2700
2701                         switch (trace_msg_type) {
2702                                 case 0: /* Exceptions */
2703                                 case 1:
2704                                 case 2:
2705                                 case 3:
2706                                 case 4:
2707                                 case 5:
2708                                 case 6:
2709                                 case 7:
2710                                         exception = (trace_data->entries[i].data & 0x70) >> 4;
2711
2712                                         /* FIXME: vector table may be at ffff0000 */
2713                                         branch_target = (trace_data->entries[i].data & 0xf0) >> 2;
2714                                         break;
2715
2716                                 case 8: /* Direct Branch */
2717                                         break;
2718
2719                                 case 9: /* Indirect Branch */
2720                                         xscale_branch_address(trace_data, i, &branch_target);
2721                                         break;
2722
2723                                 case 13:        /* Checkpointed Indirect Branch */
2724                                         xscale_branch_address(trace_data, i, &branch_target);
2725                                         if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2726                                                 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
2727                                                                                  *oldest */
2728                                         else
2729                                                 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
2730                                                                                  *newest */
2731
2732                                         chkpt++;
2733                                         break;
2734
2735                                 case 12:        /* Checkpointed Direct Branch */
2736                                         if ((trace_data->num_checkpoints == 2) && (chkpt == 0))
2737                                                 chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is
2738                                                                                  *oldest */
2739                                         else
2740                                                 chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and
2741                                                                                  *newest */
2742
2743                                         /* if no current_pc, checkpoint will be starting point */
2744                                         if (current_pc == 0)
2745                                                 branch_target = chkpt_reg;
2746
2747                                         chkpt++;
2748                                         break;
2749
2750                                 case 15:/* Roll-over */
2751                                         break;
2752
2753                                 default:/* Reserved */
2754                                         LOG_WARNING("trace is suspect: invalid trace message byte");
2755                                         continue;
2756
2757                         }
2758
2759                         /* If we don't have the current_pc yet, but we did get the branch target
2760                          * (either from the trace buffer on indirect branch, or from a checkpoint reg),
2761                          * then we can start displaying instructions at the next iteration, with
2762                          * branch_target as the starting point.
2763                          */
2764                         if (current_pc == 0) {
2765                                 current_pc = branch_target;     /* remains 0 unless branch_target *obtained */
2766                                 continue;
2767                         }
2768
2769                         /* We have current_pc.  Read and display the instructions from the image.
2770                          * First, display count instructions (lower nybble of message byte). */
2771                         count = trace_data->entries[i].data & 0x0f;
2772                         for (j = 0; j < count; j++) {
2773                                 xscale_display_instruction(target, current_pc, &instruction,
2774                                         cmd);
2775                                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2776                         }
2777
2778                         /* An additional instruction is implicitly added to count for
2779                          * rollover and some exceptions: undef, swi, prefetch abort. */
2780                         if ((trace_msg_type == 15) || (exception > 0 && exception < 4)) {
2781                                 xscale_display_instruction(target, current_pc, &instruction,
2782                                         cmd);
2783                                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2784                         }
2785
2786                         if (trace_msg_type == 15)       /* rollover */
2787                                 continue;
2788
2789                         if (exception) {
2790                                 command_print(cmd, "--- exception %i ---", exception);
2791                                 continue;
2792                         }
2793
2794                         /* not exception or rollover; next instruction is a branch and is
2795                          * not included in the count */
2796                         xscale_display_instruction(target, current_pc, &instruction, cmd);
2797
2798                         /* for direct branches, extract branch destination from instruction */
2799                         if ((trace_msg_type == 8) || (trace_msg_type == 12)) {
2800                                 retval = xscale_read_instruction(target, current_pc, &instruction);
2801                                 if (retval == ERROR_OK)
2802                                         current_pc = instruction.info.b_bl_bx_blx.target_address;
2803                                 else
2804                                         current_pc = 0; /* branch destination unknown */
2805
2806                                 /* direct branch w/ checkpoint; can also get from checkpoint reg */
2807                                 if (trace_msg_type == 12) {
2808                                         if (current_pc == 0)
2809                                                 current_pc = chkpt_reg;
2810                                         else if (current_pc != chkpt_reg)       /* sanity check */
2811                                                 LOG_WARNING("trace is suspect: checkpoint register "
2812                                                         "inconsistent with address from image");
2813                                 }
2814
2815                                 if (current_pc == 0)
2816                                         command_print(cmd, "address unknown");
2817
2818                                 continue;
2819                         }
2820
2821                         /* indirect branch; the branch destination was read from trace buffer */
2822                         if ((trace_msg_type == 9) || (trace_msg_type == 13)) {
2823                                 current_pc = branch_target;
2824
2825                                 /* sanity check (checkpoint reg is redundant) */
2826                                 if ((trace_msg_type == 13) && (chkpt_reg != branch_target))
2827                                         LOG_WARNING("trace is suspect: checkpoint register "
2828                                                 "inconsistent with address from trace buffer");
2829                         }
2830
2831                 }       /* END: for (i = 0; i < trace_data->depth; i++) */
2832
2833                 breakpoint_pc = trace_data->last_instruction;   /* used below */
2834                 trace_data = trace_data->next;
2835
2836         }       /* END: while (trace_data) */
2837
2838         /* Finally... display all instructions up to the value of the pc when the
2839          * debug break occurred (saved when trace data was collected from target).
2840          * This is necessary because the trace only records execution branches and 16
2841          * consecutive instructions (rollovers), so last few typically missed.
2842          */
2843         if (current_pc == 0)
2844                 return ERROR_OK;/* current_pc was never found */
2845
2846         /* how many instructions remaining? */
2847         int gap_count = (breakpoint_pc - current_pc) /
2848                 (xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2);
2849
2850         /* should never be negative or over 16, but verify */
2851         if (gap_count < 0 || gap_count > 16) {
2852                 LOG_WARNING("trace is suspect: excessive gap at end of trace");
2853                 return ERROR_OK;/* bail; large number or negative value no good */
2854         }
2855
2856         /* display remaining instructions */
2857         for (i = 0; i < gap_count; i++) {
2858                 xscale_display_instruction(target, current_pc, &instruction, cmd);
2859                 current_pc += xscale->trace.core_state == ARM_STATE_ARM ? 4 : 2;
2860         }
2861
2862         return ERROR_OK;
2863 }
2864
2865 static const struct reg_arch_type xscale_reg_type = {
2866         .get = xscale_get_reg,
2867         .set = xscale_set_reg,
2868 };
2869
2870 static void xscale_build_reg_cache(struct target *target)
2871 {
2872         struct xscale_common *xscale = target_to_xscale(target);
2873         struct arm *arm = &xscale->arm;
2874         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
2875         struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info));
2876         int i;
2877         int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
2878
2879         (*cache_p) = arm_build_reg_cache(target, arm);
2880
2881         (*cache_p)->next = malloc(sizeof(struct reg_cache));
2882         cache_p = &(*cache_p)->next;
2883
2884         /* fill in values for the xscale reg cache */
2885         (*cache_p)->name = "XScale registers";
2886         (*cache_p)->next = NULL;
2887         (*cache_p)->reg_list = calloc(num_regs, sizeof(struct reg));
2888         (*cache_p)->num_regs = num_regs;
2889
2890         for (i = 0; i < num_regs; i++) {
2891                 (*cache_p)->reg_list[i].name = xscale_reg_list[i];
2892                 (*cache_p)->reg_list[i].value = calloc(4, 1);
2893                 (*cache_p)->reg_list[i].dirty = false;
2894                 (*cache_p)->reg_list[i].valid = false;
2895                 (*cache_p)->reg_list[i].size = 32;
2896                 (*cache_p)->reg_list[i].arch_info = &arch_info[i];
2897                 (*cache_p)->reg_list[i].type = &xscale_reg_type;
2898                 (*cache_p)->reg_list[i].exist = true;
2899                 arch_info[i] = xscale_reg_arch_info[i];
2900                 arch_info[i].target = target;
2901         }
2902
2903         xscale->reg_cache = (*cache_p);
2904 }
2905
2906 static void xscale_free_reg_cache(struct target *target)
2907 {
2908         struct xscale_common *xscale = target_to_xscale(target);
2909         struct reg_cache *cache = xscale->reg_cache;
2910
2911         for (unsigned int i = 0; i < ARRAY_SIZE(xscale_reg_arch_info); i++)
2912                 free(cache->reg_list[i].value);
2913
2914         free(cache->reg_list[0].arch_info);
2915         free(cache->reg_list);
2916         free(cache);
2917
2918         arm_free_reg_cache(&xscale->arm);
2919 }
2920
2921 static int xscale_init_target(struct command_context *cmd_ctx,
2922         struct target *target)
2923 {
2924         xscale_build_reg_cache(target);
2925         return ERROR_OK;
2926 }
2927
2928 static void xscale_deinit_target(struct target *target)
2929 {
2930         struct xscale_common *xscale = target_to_xscale(target);
2931
2932         xscale_free_reg_cache(target);
2933         free(xscale);
2934 }
2935
2936 static int xscale_init_arch_info(struct target *target,
2937         struct xscale_common *xscale, struct jtag_tap *tap)
2938 {
2939         struct arm *arm;
2940         uint32_t high_reset_branch, low_reset_branch;
2941         int i;
2942
2943         arm = &xscale->arm;
2944
2945         /* store architecture specific data */
2946         xscale->common_magic = XSCALE_COMMON_MAGIC;
2947
2948         /* PXA3xx with 11 bit IR shifts the JTAG instructions */
2949         if (tap->ir_length == 11)
2950                 xscale->xscale_variant = XSCALE_PXA3XX;
2951         else
2952                 xscale->xscale_variant = XSCALE_IXP4XX_PXA2XX;
2953
2954         /* the debug handler isn't installed (and thus not running) at this time */
2955         xscale->handler_address = 0xfe000800;
2956
2957         /* clear the vectors we keep locally for reference */
2958         memset(xscale->low_vectors, 0, sizeof(xscale->low_vectors));
2959         memset(xscale->high_vectors, 0, sizeof(xscale->high_vectors));
2960
2961         /* no user-specified vectors have been configured yet */
2962         xscale->static_low_vectors_set = 0x0;
2963         xscale->static_high_vectors_set = 0x0;
2964
2965         /* calculate branches to debug handler */
2966         low_reset_branch = (xscale->handler_address + 0x20 - 0x0 - 0x8) >> 2;
2967         high_reset_branch = (xscale->handler_address + 0x20 - 0xffff0000 - 0x8) >> 2;
2968
2969         xscale->low_vectors[0] = ARMV4_5_B((low_reset_branch & 0xffffff), 0);
2970         xscale->high_vectors[0] = ARMV4_5_B((high_reset_branch & 0xffffff), 0);
2971
2972         for (i = 1; i <= 7; i++) {
2973                 xscale->low_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2974                 xscale->high_vectors[i] = ARMV4_5_B(0xfffffe, 0);
2975         }
2976
2977         /* 64kB aligned region used for DCache cleaning */
2978         xscale->cache_clean_address = 0xfffe0000;
2979
2980         xscale->hold_rst = 0;
2981         xscale->external_debug_break = 0;
2982
2983         xscale->ibcr_available = 2;
2984         xscale->ibcr0_used = 0;
2985         xscale->ibcr1_used = 0;
2986
2987         xscale->dbr_available = 2;
2988         xscale->dbr0_used = 0;
2989         xscale->dbr1_used = 0;
2990
2991         LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
2992                 target_name(target));
2993
2994         xscale->arm_bkpt = ARMV5_BKPT(0x0);
2995         xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
2996
2997         xscale->vector_catch = 0x1;
2998
2999         xscale->trace.data = NULL;
3000         xscale->trace.image = NULL;
3001         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3002         xscale->trace.buffer_fill = 0;
3003         xscale->trace.fill_counter = 0;
3004
3005         /* prepare ARMv4/5 specific information */
3006         arm->arch_info = xscale;
3007         arm->core_type = ARM_CORE_TYPE_STD;
3008         arm->read_core_reg = xscale_read_core_reg;
3009         arm->write_core_reg = xscale_write_core_reg;
3010         arm->full_context = xscale_full_context;
3011
3012         arm_init_arch_info(target, arm);
3013
3014         xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
3015         xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
3016         xscale->armv4_5_mmu.read_memory = xscale_read_memory;
3017         xscale->armv4_5_mmu.write_memory = xscale_write_memory;
3018         xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
3019         xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
3020         xscale->armv4_5_mmu.has_tiny_pages = 1;
3021         xscale->armv4_5_mmu.mmu_enabled = 0;
3022
3023         return ERROR_OK;
3024 }
3025
3026 static int xscale_target_create(struct target *target, Jim_Interp *interp)
3027 {
3028         struct xscale_common *xscale;
3029
3030         if (sizeof(xscale_debug_handler) > 0x800) {
3031                 LOG_ERROR("debug_handler.bin: larger than 2kb");
3032                 return ERROR_FAIL;
3033         }
3034
3035         xscale = calloc(1, sizeof(*xscale));
3036         if (!xscale)
3037                 return ERROR_FAIL;
3038
3039         return xscale_init_arch_info(target, xscale, target->tap);
3040 }
3041
3042 COMMAND_HANDLER(xscale_handle_debug_handler_command)
3043 {
3044         struct target *target = NULL;
3045         struct xscale_common *xscale;
3046         int retval;
3047         uint32_t handler_address;
3048
3049         if (CMD_ARGC < 2)
3050                 return ERROR_COMMAND_SYNTAX_ERROR;
3051
3052         target = get_target(CMD_ARGV[0]);
3053         if (!target) {
3054                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3055                 return ERROR_FAIL;
3056         }
3057
3058         xscale = target_to_xscale(target);
3059         retval = xscale_verify_pointer(CMD, xscale);
3060         if (retval != ERROR_OK)
3061                 return retval;
3062
3063         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], handler_address);
3064
3065         if (((handler_address >= 0x800) && (handler_address <= 0x1fef800)) ||
3066                 ((handler_address >= 0xfe000800) && (handler_address <= 0xfffff800)))
3067                 xscale->handler_address = handler_address;
3068         else {
3069                 LOG_ERROR(
3070                         "xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
3071                 return ERROR_FAIL;
3072         }
3073
3074         return ERROR_OK;
3075 }
3076
3077 COMMAND_HANDLER(xscale_handle_cache_clean_address_command)
3078 {
3079         struct target *target = NULL;
3080         struct xscale_common *xscale;
3081         int retval;
3082         uint32_t cache_clean_address;
3083
3084         if (CMD_ARGC < 2)
3085                 return ERROR_COMMAND_SYNTAX_ERROR;
3086
3087         target = get_target(CMD_ARGV[0]);
3088         if (!target) {
3089                 LOG_ERROR("target '%s' not defined", CMD_ARGV[0]);
3090                 return ERROR_FAIL;
3091         }
3092         xscale = target_to_xscale(target);
3093         retval = xscale_verify_pointer(CMD, xscale);
3094         if (retval != ERROR_OK)
3095                 return retval;
3096
3097         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cache_clean_address);
3098
3099         if (cache_clean_address & 0xffff)
3100                 LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
3101         else
3102                 xscale->cache_clean_address = cache_clean_address;
3103
3104         return ERROR_OK;
3105 }
3106
3107 COMMAND_HANDLER(xscale_handle_cache_info_command)
3108 {
3109         struct target *target = get_current_target(CMD_CTX);
3110         struct xscale_common *xscale = target_to_xscale(target);
3111         int retval;
3112
3113         retval = xscale_verify_pointer(CMD, xscale);
3114         if (retval != ERROR_OK)
3115                 return retval;
3116
3117         return armv4_5_handle_cache_info_command(CMD, &xscale->armv4_5_mmu.armv4_5_cache);
3118 }
3119
3120 static int xscale_virt2phys(struct target *target,
3121         target_addr_t virtual, target_addr_t *physical)
3122 {
3123         struct xscale_common *xscale = target_to_xscale(target);
3124         uint32_t cb;
3125
3126         if (xscale->common_magic != XSCALE_COMMON_MAGIC) {
3127                 LOG_ERROR(xscale_not);
3128                 return ERROR_TARGET_INVALID;
3129         }
3130
3131         uint32_t ret;
3132         int retval = armv4_5_mmu_translate_va(target, &xscale->armv4_5_mmu,
3133                         virtual, &cb, &ret);
3134         if (retval != ERROR_OK)
3135                 return retval;
3136         *physical = ret;
3137         return ERROR_OK;
3138 }
3139
3140 static int xscale_mmu(struct target *target, int *enabled)
3141 {
3142         struct xscale_common *xscale = target_to_xscale(target);
3143
3144         if (target->state != TARGET_HALTED) {
3145                 LOG_ERROR("Target not halted");
3146                 return ERROR_TARGET_INVALID;
3147         }
3148         *enabled = xscale->armv4_5_mmu.mmu_enabled;
3149         return ERROR_OK;
3150 }
3151
3152 COMMAND_HANDLER(xscale_handle_mmu_command)
3153 {
3154         struct target *target = get_current_target(CMD_CTX);
3155         struct xscale_common *xscale = target_to_xscale(target);
3156         int retval;
3157
3158         retval = xscale_verify_pointer(CMD, xscale);
3159         if (retval != ERROR_OK)
3160                 return retval;
3161
3162         if (target->state != TARGET_HALTED) {
3163                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
3164                 return ERROR_OK;
3165         }
3166
3167         if (CMD_ARGC >= 1) {
3168                 bool enable;
3169                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3170                 if (enable)
3171                         xscale_enable_mmu_caches(target, 1, 0, 0);
3172                 else
3173                         xscale_disable_mmu_caches(target, 1, 0, 0);
3174                 xscale->armv4_5_mmu.mmu_enabled = enable;
3175         }
3176
3177         command_print(CMD, "mmu %s",
3178                 (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
3179
3180         return ERROR_OK;
3181 }
3182
3183 COMMAND_HANDLER(xscale_handle_idcache_command)
3184 {
3185         struct target *target = get_current_target(CMD_CTX);
3186         struct xscale_common *xscale = target_to_xscale(target);
3187
3188         int retval = xscale_verify_pointer(CMD, xscale);
3189         if (retval != ERROR_OK)
3190                 return retval;
3191
3192         if (target->state != TARGET_HALTED) {
3193                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
3194                 return ERROR_OK;
3195         }
3196
3197         bool icache = false;
3198         if (strcmp(CMD_NAME, "icache") == 0)
3199                 icache = true;
3200         if (CMD_ARGC >= 1) {
3201                 bool enable;
3202                 COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
3203                 if (icache) {
3204                         xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
3205                         if (enable)
3206                                 xscale_enable_mmu_caches(target, 0, 0, 1);
3207                         else
3208                                 xscale_disable_mmu_caches(target, 0, 0, 1);
3209                 } else {
3210                         xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
3211                         if (enable)
3212                                 xscale_enable_mmu_caches(target, 0, 1, 0);
3213                         else
3214                                 xscale_disable_mmu_caches(target, 0, 1, 0);
3215                 }
3216         }
3217
3218         bool enabled = icache ?
3219                 xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
3220                 xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
3221         const char *msg = enabled ? "enabled" : "disabled";
3222         command_print(CMD, "%s %s", CMD_NAME, msg);
3223
3224         return ERROR_OK;
3225 }
3226
3227 static const struct {
3228         char name[15];
3229         unsigned mask;
3230 } vec_ids[] = {
3231         { "fiq",                DCSR_TF, },
3232         { "irq",                DCSR_TI, },
3233         { "dabt",               DCSR_TD, },
3234         { "pabt",               DCSR_TA, },
3235         { "swi",                DCSR_TS, },
3236         { "undef",              DCSR_TU, },
3237         { "reset",              DCSR_TR, },
3238 };
3239
3240 COMMAND_HANDLER(xscale_handle_vector_catch_command)
3241 {
3242         struct target *target = get_current_target(CMD_CTX);
3243         struct xscale_common *xscale = target_to_xscale(target);
3244         int retval;
3245         uint32_t dcsr_value;
3246         uint32_t catch = 0;
3247         struct reg *dcsr_reg = &xscale->reg_cache->reg_list[XSCALE_DCSR];
3248
3249         retval = xscale_verify_pointer(CMD, xscale);
3250         if (retval != ERROR_OK)
3251                 return retval;
3252
3253         if (CMD_ARGC > 0) {
3254                 if (CMD_ARGC == 1) {
3255                         if (strcmp(CMD_ARGV[0], "all") == 0) {
3256                                 catch = DCSR_TRAP_MASK;
3257                                 CMD_ARGC--;
3258                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
3259                                 catch = 0;
3260                                 CMD_ARGC--;
3261                         }
3262                 }
3263                 while (CMD_ARGC-- > 0) {
3264                         unsigned i;
3265                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
3266                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name))
3267                                         continue;
3268                                 catch |= vec_ids[i].mask;
3269                                 break;
3270                         }
3271                         if (i == ARRAY_SIZE(vec_ids)) {
3272                                 LOG_ERROR("No vector '%s'", CMD_ARGV[CMD_ARGC]);
3273                                 return ERROR_COMMAND_SYNTAX_ERROR;
3274                         }
3275                 }
3276                 buf_set_u32(dcsr_reg->value, 0, 32,
3277                                 (buf_get_u32(dcsr_reg->value, 0, 32) & ~DCSR_TRAP_MASK) | catch);
3278                 xscale_write_dcsr(target, -1, -1);
3279         }
3280
3281         dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
3282         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
3283                 command_print(CMD, "%15s: %s", vec_ids[i].name,
3284                         (dcsr_value & vec_ids[i].mask) ? "catch" : "ignore");
3285         }
3286
3287         return ERROR_OK;
3288 }
3289
3290
3291 COMMAND_HANDLER(xscale_handle_vector_table_command)
3292 {
3293         struct target *target = get_current_target(CMD_CTX);
3294         struct xscale_common *xscale = target_to_xscale(target);
3295         int err = 0;
3296         int retval;
3297
3298         retval = xscale_verify_pointer(CMD, xscale);
3299         if (retval != ERROR_OK)
3300                 return retval;
3301
3302         if (CMD_ARGC == 0) {    /* print current settings */
3303                 int idx;
3304
3305                 command_print(CMD, "active user-set static vectors:");
3306                 for (idx = 1; idx < 8; idx++)
3307                         if (xscale->static_low_vectors_set & (1 << idx))
3308                                 command_print(CMD,
3309                                         "low  %d: 0x%" PRIx32,
3310                                         idx,
3311                                         xscale->static_low_vectors[idx]);
3312                 for (idx = 1; idx < 8; idx++)
3313                         if (xscale->static_high_vectors_set & (1 << idx))
3314                                 command_print(CMD,
3315                                         "high %d: 0x%" PRIx32,
3316                                         idx,
3317                                         xscale->static_high_vectors[idx]);
3318                 return ERROR_OK;
3319         }
3320
3321         if (CMD_ARGC != 3)
3322                 err = 1;
3323         else {
3324                 int idx;
3325                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], idx);
3326                 uint32_t vec;
3327                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], vec);
3328
3329                 if (idx < 1 || idx >= 8)
3330                         err = 1;
3331
3332                 if (!err && strcmp(CMD_ARGV[0], "low") == 0) {
3333                         xscale->static_low_vectors_set |= (1<<idx);
3334                         xscale->static_low_vectors[idx] = vec;
3335                 } else if (!err && (strcmp(CMD_ARGV[0], "high") == 0)) {
3336                         xscale->static_high_vectors_set |= (1<<idx);
3337                         xscale->static_high_vectors[idx] = vec;
3338                 } else
3339                         err = 1;
3340         }
3341
3342         if (err)
3343                 return ERROR_COMMAND_SYNTAX_ERROR;
3344
3345         return ERROR_OK;
3346 }
3347
3348
3349 COMMAND_HANDLER(xscale_handle_trace_buffer_command)
3350 {
3351         struct target *target = get_current_target(CMD_CTX);
3352         struct xscale_common *xscale = target_to_xscale(target);
3353         uint32_t dcsr_value;
3354         int retval;
3355
3356         retval = xscale_verify_pointer(CMD, xscale);
3357         if (retval != ERROR_OK)
3358                 return retval;
3359
3360         if (target->state != TARGET_HALTED) {
3361                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
3362                 return ERROR_OK;
3363         }
3364
3365         if (CMD_ARGC >= 1) {
3366                 if (strcmp("enable", CMD_ARGV[0]) == 0)
3367                         xscale->trace.mode = XSCALE_TRACE_WRAP; /* default */
3368                 else if (strcmp("disable", CMD_ARGV[0]) == 0)
3369                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3370                 else
3371                         return ERROR_COMMAND_SYNTAX_ERROR;
3372         }
3373
3374         if (CMD_ARGC >= 2 && xscale->trace.mode != XSCALE_TRACE_DISABLED) {
3375                 if (strcmp("fill", CMD_ARGV[1]) == 0) {
3376                         int buffcount = 1;              /* default */
3377                         if (CMD_ARGC >= 3)
3378                                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], buffcount);
3379                         if (buffcount < 1) {            /* invalid */
3380                                 command_print(CMD, "fill buffer count must be > 0");
3381                                 xscale->trace.mode = XSCALE_TRACE_DISABLED;
3382                                 return ERROR_COMMAND_SYNTAX_ERROR;
3383                         }
3384                         xscale->trace.buffer_fill = buffcount;
3385                         xscale->trace.mode = XSCALE_TRACE_FILL;
3386                 } else if (strcmp("wrap", CMD_ARGV[1]) == 0)
3387                         xscale->trace.mode = XSCALE_TRACE_WRAP;
3388                 else {
3389                         xscale->trace.mode = XSCALE_TRACE_DISABLED;
3390                         return ERROR_COMMAND_SYNTAX_ERROR;
3391                 }
3392         }
3393
3394         if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {
3395                 char fill_string[12];
3396                 sprintf(fill_string, "fill %d", xscale->trace.buffer_fill);
3397                 command_print(CMD, "trace buffer enabled (%s)",
3398                         (xscale->trace.mode == XSCALE_TRACE_FILL)
3399                         ? fill_string : "wrap");
3400         } else
3401                 command_print(CMD, "trace buffer disabled");
3402
3403         dcsr_value = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 0, 32);
3404         if (xscale->trace.mode == XSCALE_TRACE_FILL)
3405                 xscale_write_dcsr_sw(target, (dcsr_value & 0xfffffffc) | 2);
3406         else
3407                 xscale_write_dcsr_sw(target, dcsr_value & 0xfffffffc);
3408
3409         return ERROR_OK;
3410 }
3411
3412 COMMAND_HANDLER(xscale_handle_trace_image_command)
3413 {
3414         struct target *target = get_current_target(CMD_CTX);
3415         struct xscale_common *xscale = target_to_xscale(target);
3416         int retval;
3417
3418         if (CMD_ARGC < 1)
3419                 return ERROR_COMMAND_SYNTAX_ERROR;
3420
3421         retval = xscale_verify_pointer(CMD, xscale);
3422         if (retval != ERROR_OK)
3423                 return retval;
3424
3425         if (xscale->trace.image) {
3426                 image_close(xscale->trace.image);
3427                 free(xscale->trace.image);
3428                 command_print(CMD, "previously loaded image found and closed");
3429         }
3430
3431         xscale->trace.image = malloc(sizeof(struct image));
3432         xscale->trace.image->base_address_set = false;
3433         xscale->trace.image->start_address_set = false;
3434
3435         /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
3436         if (CMD_ARGC >= 2) {
3437                 xscale->trace.image->base_address_set = true;
3438                 COMMAND_PARSE_NUMBER(llong, CMD_ARGV[1], xscale->trace.image->base_address);
3439         } else
3440                 xscale->trace.image->base_address_set = false;
3441
3442         if (image_open(xscale->trace.image, CMD_ARGV[0],
3443                 (CMD_ARGC >= 3) ? CMD_ARGV[2] : NULL) != ERROR_OK) {
3444                 free(xscale->trace.image);
3445                 xscale->trace.image = NULL;
3446                 return ERROR_OK;
3447         }
3448
3449         return ERROR_OK;
3450 }
3451
3452 COMMAND_HANDLER(xscale_handle_dump_trace_command)
3453 {
3454         struct target *target = get_current_target(CMD_CTX);
3455         struct xscale_common *xscale = target_to_xscale(target);
3456         struct xscale_trace_data *trace_data;
3457         struct fileio *file;
3458         int retval;
3459
3460         retval = xscale_verify_pointer(CMD, xscale);
3461         if (retval != ERROR_OK)
3462                 return retval;
3463
3464         if (target->state != TARGET_HALTED) {
3465                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
3466                 return ERROR_OK;
3467         }
3468
3469         if (CMD_ARGC < 1)
3470                 return ERROR_COMMAND_SYNTAX_ERROR;
3471
3472         trace_data = xscale->trace.data;
3473
3474         if (!trace_data) {
3475                 command_print(CMD, "no trace data collected");
3476                 return ERROR_OK;
3477         }
3478
3479         if (fileio_open(&file, CMD_ARGV[0], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
3480                 return ERROR_OK;
3481
3482         while (trace_data) {
3483                 int i;
3484
3485                 fileio_write_u32(file, trace_data->chkpt0);
3486                 fileio_write_u32(file, trace_data->chkpt1);
3487                 fileio_write_u32(file, trace_data->last_instruction);
3488                 fileio_write_u32(file, trace_data->depth);
3489
3490                 for (i = 0; i < trace_data->depth; i++)
3491                         fileio_write_u32(file, trace_data->entries[i].data |
3492                                 ((trace_data->entries[i].type & 0xffff) << 16));
3493
3494                 trace_data = trace_data->next;
3495         }
3496
3497         fileio_close(file);
3498
3499         return ERROR_OK;
3500 }
3501
3502 COMMAND_HANDLER(xscale_handle_analyze_trace_buffer_command)
3503 {
3504         struct target *target = get_current_target(CMD_CTX);
3505         struct xscale_common *xscale = target_to_xscale(target);
3506         int retval;
3507
3508         retval = xscale_verify_pointer(CMD, xscale);
3509         if (retval != ERROR_OK)
3510                 return retval;
3511
3512         xscale_analyze_trace(target, CMD);
3513
3514         return ERROR_OK;
3515 }
3516
3517 COMMAND_HANDLER(xscale_handle_cp15)
3518 {
3519         struct target *target = get_current_target(CMD_CTX);
3520         struct xscale_common *xscale = target_to_xscale(target);
3521         int retval;
3522
3523         retval = xscale_verify_pointer(CMD, xscale);
3524         if (retval != ERROR_OK)
3525                 return retval;
3526
3527         if (target->state != TARGET_HALTED) {
3528                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
3529                 return ERROR_OK;
3530         }
3531         uint32_t reg_no = 0;
3532         struct reg *reg = NULL;
3533         if (CMD_ARGC > 0) {
3534                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no);
3535                 /*translate from xscale cp15 register no to openocd register*/
3536                 switch (reg_no) {
3537                         case 0:
3538                                 reg_no = XSCALE_MAINID;
3539                                 break;
3540                         case 1:
3541                                 reg_no = XSCALE_CTRL;
3542                                 break;
3543                         case 2:
3544                                 reg_no = XSCALE_TTB;
3545                                 break;
3546                         case 3:
3547                                 reg_no = XSCALE_DAC;
3548                                 break;
3549                         case 5:
3550                                 reg_no = XSCALE_FSR;
3551                                 break;
3552                         case 6:
3553                                 reg_no = XSCALE_FAR;
3554                                 break;
3555                         case 13:
3556                                 reg_no = XSCALE_PID;
3557                                 break;
3558                         case 15:
3559                                 reg_no = XSCALE_CPACCESS;
3560                                 break;
3561                         default:
3562                                 command_print(CMD, "invalid register number");
3563                                 return ERROR_COMMAND_SYNTAX_ERROR;
3564                 }
3565                 reg = &xscale->reg_cache->reg_list[reg_no];
3566
3567         }
3568         if (CMD_ARGC == 1) {
3569                 uint32_t value;
3570
3571                 /* read cp15 control register */
3572                 xscale_get_reg(reg);
3573                 value = buf_get_u32(reg->value, 0, 32);
3574                 command_print(CMD, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
3575                         value);
3576         } else if (CMD_ARGC == 2) {
3577                 uint32_t value;
3578                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
3579
3580                 /* send CP write request (command 0x41) */
3581                 xscale_send_u32(target, 0x41);
3582
3583                 /* send CP register number */
3584                 xscale_send_u32(target, reg_no);
3585
3586                 /* send CP register value */
3587                 xscale_send_u32(target, value);
3588
3589                 /* execute cpwait to ensure outstanding operations complete */
3590                 xscale_send_u32(target, 0x53);
3591         } else
3592                 return ERROR_COMMAND_SYNTAX_ERROR;
3593
3594         return ERROR_OK;
3595 }
3596
3597 static const struct command_registration xscale_exec_command_handlers[] = {
3598         {
3599                 .name = "cache_info",
3600                 .handler = xscale_handle_cache_info_command,
3601                 .mode = COMMAND_EXEC,
3602                 .help = "display information about CPU caches",
3603                 .usage = "",
3604         },
3605         {
3606                 .name = "mmu",
3607                 .handler = xscale_handle_mmu_command,
3608                 .mode = COMMAND_EXEC,
3609                 .help = "enable or disable the MMU",
3610                 .usage = "['enable'|'disable']",
3611         },
3612         {
3613                 .name = "icache",
3614                 .handler = xscale_handle_idcache_command,
3615                 .mode = COMMAND_EXEC,
3616                 .help = "display ICache state, optionally enabling or "
3617                         "disabling it",
3618                 .usage = "['enable'|'disable']",
3619         },
3620         {
3621                 .name = "dcache",
3622                 .handler = xscale_handle_idcache_command,
3623                 .mode = COMMAND_EXEC,
3624                 .help = "display DCache state, optionally enabling or "
3625                         "disabling it",
3626                 .usage = "['enable'|'disable']",
3627         },
3628         {
3629                 .name = "vector_catch",
3630                 .handler = xscale_handle_vector_catch_command,
3631                 .mode = COMMAND_EXEC,
3632                 .help = "set or display mask of vectors "
3633                         "that should trigger debug entry",
3634                 .usage = "['all'|'none'|'fiq'|'irq'|'dabt'|'pabt'|'swi'|'undef'|'reset']",
3635         },
3636         {
3637                 .name = "vector_table",
3638                 .handler = xscale_handle_vector_table_command,
3639                 .mode = COMMAND_EXEC,
3640                 .help = "set vector table entry in mini-ICache, "
3641                         "or display current tables",
3642                 .usage = "[('high'|'low') index code]",
3643         },
3644         {
3645                 .name = "trace_buffer",
3646                 .handler = xscale_handle_trace_buffer_command,
3647                 .mode = COMMAND_EXEC,
3648                 .help = "display trace buffer status, enable or disable "
3649                         "tracing, and optionally reconfigure trace mode",
3650                 .usage = "['enable'|'disable' ['fill' [number]|'wrap']]",
3651         },
3652         {
3653                 .name = "dump_trace",
3654                 .handler = xscale_handle_dump_trace_command,
3655                 .mode = COMMAND_EXEC,
3656                 .help = "dump content of trace buffer to file",
3657                 .usage = "filename",
3658         },
3659         {
3660                 .name = "analyze_trace",
3661                 .handler = xscale_handle_analyze_trace_buffer_command,
3662                 .mode = COMMAND_EXEC,
3663                 .help = "analyze content of trace buffer",
3664                 .usage = "",
3665         },
3666         {
3667                 .name = "trace_image",
3668                 .handler = xscale_handle_trace_image_command,
3669                 .mode = COMMAND_EXEC,
3670                 .help = "load image from file to address (default 0)",
3671                 .usage = "filename [offset [filetype]]",
3672         },
3673         {
3674                 .name = "cp15",
3675                 .handler = xscale_handle_cp15,
3676                 .mode = COMMAND_EXEC,
3677                 .help = "Read or write coprocessor 15 register.",
3678                 .usage = "register [value]",
3679         },
3680         COMMAND_REGISTRATION_DONE
3681 };
3682 static const struct command_registration xscale_any_command_handlers[] = {
3683         {
3684                 .name = "debug_handler",
3685                 .handler = xscale_handle_debug_handler_command,
3686                 .mode = COMMAND_ANY,
3687                 .help = "Change address used for debug handler.",
3688                 .usage = "<target> <address>",
3689         },
3690         {
3691                 .name = "cache_clean_address",
3692                 .handler = xscale_handle_cache_clean_address_command,
3693                 .mode = COMMAND_ANY,
3694                 .help = "Change address used for cleaning data cache.",
3695                 .usage = "address",
3696         },
3697         {
3698                 .chain = xscale_exec_command_handlers,
3699         },
3700         COMMAND_REGISTRATION_DONE
3701 };
3702 static const struct command_registration xscale_command_handlers[] = {
3703         {
3704                 .chain = arm_command_handlers,
3705         },
3706         {
3707                 .name = "xscale",
3708                 .mode = COMMAND_ANY,
3709                 .help = "xscale command group",
3710                 .usage = "",
3711                 .chain = xscale_any_command_handlers,
3712         },
3713         COMMAND_REGISTRATION_DONE
3714 };
3715
3716 struct target_type xscale_target = {
3717         .name = "xscale",
3718
3719         .poll = xscale_poll,
3720         .arch_state = xscale_arch_state,
3721
3722         .halt = xscale_halt,
3723         .resume = xscale_resume,
3724         .step = xscale_step,
3725
3726         .assert_reset = xscale_assert_reset,
3727         .deassert_reset = xscale_deassert_reset,
3728
3729         /* REVISIT on some cores, allow exporting iwmmxt registers ... */
3730         .get_gdb_arch = arm_get_gdb_arch,
3731         .get_gdb_reg_list = arm_get_gdb_reg_list,
3732
3733         .read_memory = xscale_read_memory,
3734         .read_phys_memory = xscale_read_phys_memory,
3735         .write_memory = xscale_write_memory,
3736         .write_phys_memory = xscale_write_phys_memory,
3737
3738         .checksum_memory = arm_checksum_memory,
3739         .blank_check_memory = arm_blank_check_memory,
3740
3741         .run_algorithm = armv4_5_run_algorithm,
3742
3743         .add_breakpoint = xscale_add_breakpoint,
3744         .remove_breakpoint = xscale_remove_breakpoint,
3745         .add_watchpoint = xscale_add_watchpoint,
3746         .remove_watchpoint = xscale_remove_watchpoint,
3747
3748         .commands = xscale_command_handlers,
3749         .target_create = xscale_target_create,
3750         .init_target = xscale_init_target,
3751         .deinit_target = xscale_deinit_target,
3752
3753         .virt2phys = xscale_virt2phys,
3754         .mmu = xscale_mmu
3755 };