1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include "jtag/jtag.h"
12 #include "target/register.h"
13 #include "target/semihosting_common.h"
14 #include <helper/command.h>
16 #define RISCV_COMMON_MAGIC 0x52495356U
18 /* The register cache is statically allocated. */
19 #define RISCV_MAX_HARTS 1024
20 #define RISCV_MAX_REGISTERS 5000
21 #define RISCV_MAX_TRIGGERS 32
22 #define RISCV_MAX_HWBPS 16
24 #define DEFAULT_COMMAND_TIMEOUT_SEC 2
25 #define DEFAULT_RESET_TIMEOUT_SEC 30
27 #define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
28 #define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
29 #define RISCV_PGSHIFT 12
31 # define PG_MAX_LEVEL 4
33 #define RISCV_NUM_MEM_ACCESS_METHODS 3
35 extern struct target_type riscv011_target;
36 extern struct target_type riscv013_target;
39 * Definitions shared by code supporting all RISC-V versions.
41 typedef uint64_t riscv_reg_t;
42 typedef uint32_t riscv_insn_t;
43 typedef uint64_t riscv_addr_t;
45 enum riscv_mem_access_method {
46 RISCV_MEM_ACCESS_UNSPECIFIED,
47 RISCV_MEM_ACCESS_PROGBUF,
48 RISCV_MEM_ACCESS_SYSBUS,
49 RISCV_MEM_ACCESS_ABSTRACT
52 enum riscv_halt_reason {
54 RISCV_HALT_BREAKPOINT,
55 RISCV_HALT_SINGLESTEP,
63 struct target *target;
64 unsigned custom_number;
67 #define RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE 0x80
68 #define RISCV_SAMPLE_BUF_TIMESTAMP_AFTER 0x81
69 struct riscv_sample_buf {
79 target_addr_t address;
82 } riscv_sample_config_t;
85 struct list_head list;
91 unsigned int common_magic;
95 struct command_context *cmd_ctx;
96 void *version_specific;
98 /* The hart that is currently being debugged. Note that this is
99 * different than the hartid that the RTOS is expected to use. This
100 * one will change all the time, it's more of a global argument to
101 * every function than an actual */
104 /* Single buffer that contains all register names, instead of calling
105 * malloc for each register. Needs to be freed when reg_list is freed. */
108 /* It's possible that each core has a different supported ISA set. */
111 /* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
114 /* The number of triggers per hart. */
115 unsigned int trigger_count;
117 /* For each physical trigger, contains -1 if the hwbp is available, or the
118 * unique_id of the breakpoint/watchpoint that is using it.
119 * Note that in RTOS mode the triggers are the same across all harts the
120 * target controls, while otherwise only a single hart is controlled. */
121 int trigger_unique_id[RISCV_MAX_HWBPS];
123 /* The number of entries in the debug buffer. */
124 int debug_buffer_size;
126 /* This hart contains an implicit ebreak at the end of the program buffer. */
129 bool triggers_enumerated;
131 /* Decremented every scan, and when it reaches 0 we clear the learned
132 * delays, causing them to be relearned. Used for testing. */
133 int reset_delays_wait;
135 /* This target has been prepped and is ready to step/resume. */
137 /* This target was selected using hasel. */
140 /* Helper functions that target the various RISC-V debug spec
141 * implementations. */
142 int (*get_register)(struct target *target, riscv_reg_t *value, int regid);
143 int (*set_register)(struct target *target, int regid, uint64_t value);
144 int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
145 int (*set_register_buf)(struct target *target, int regno,
147 int (*select_current_hart)(struct target *target);
148 bool (*is_halted)(struct target *target);
149 /* Resume this target, as well as every other prepped target that can be
150 * resumed near-simultaneously. Clear the prepped flag on any target that
152 int (*resume_go)(struct target *target);
153 int (*step_current_hart)(struct target *target);
154 int (*on_halt)(struct target *target);
155 /* Get this target as ready as possible to resume, without actually
157 int (*resume_prep)(struct target *target);
158 int (*halt_prep)(struct target *target);
159 int (*halt_go)(struct target *target);
160 int (*on_step)(struct target *target);
161 enum riscv_halt_reason (*halt_reason)(struct target *target);
162 int (*write_debug_buffer)(struct target *target, unsigned index,
164 riscv_insn_t (*read_debug_buffer)(struct target *target, unsigned index);
165 int (*execute_debug_buffer)(struct target *target);
166 int (*dmi_write_u64_bits)(struct target *target);
167 void (*fill_dmi_write_u64)(struct target *target, char *buf, int a, uint64_t d);
168 void (*fill_dmi_read_u64)(struct target *target, char *buf, int a);
169 void (*fill_dmi_nop_u64)(struct target *target, char *buf);
171 int (*authdata_read)(struct target *target, uint32_t *value, unsigned int index);
172 int (*authdata_write)(struct target *target, uint32_t value, unsigned int index);
174 int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
175 int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
177 int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address,
178 uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
180 int (*sample_memory)(struct target *target,
181 struct riscv_sample_buf *buf,
182 riscv_sample_config_t *config,
185 int (*read_memory)(struct target *target, target_addr_t address,
186 uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
188 /* How many harts are attached to the DM that this target is attached to? */
189 int (*hart_count)(struct target *target);
190 unsigned (*data_bits)(struct target *target);
192 COMMAND_HELPER((*print_info), struct target *target);
194 /* Storage for vector register types. */
195 struct reg_data_type_vector vector_uint8;
196 struct reg_data_type_vector vector_uint16;
197 struct reg_data_type_vector vector_uint32;
198 struct reg_data_type_vector vector_uint64;
199 struct reg_data_type_vector vector_uint128;
200 struct reg_data_type type_uint8_vector;
201 struct reg_data_type type_uint16_vector;
202 struct reg_data_type type_uint32_vector;
203 struct reg_data_type type_uint64_vector;
204 struct reg_data_type type_uint128_vector;
205 struct reg_data_type_union_field vector_fields[5];
206 struct reg_data_type_union vector_union;
207 struct reg_data_type type_vector;
209 /* Set when trigger registers are changed by the user. This indicates we eed
210 * to beware that we may hit a trigger that we didn't realize had been set. */
211 bool manual_hwbp_set;
213 /* Memory access methods to use, ordered by priority, highest to lowest. */
214 int mem_access_methods[RISCV_NUM_MEM_ACCESS_METHODS];
216 /* Different memory regions may need different methods but single configuration is applied
217 * for all. Following flags are used to warn only once about failing memory access method. */
218 bool mem_access_progbuf_warn;
219 bool mem_access_sysbus_warn;
220 bool mem_access_abstract_warn;
222 /* In addition to the ones in the standard spec, we'll also expose additional
223 * CSRs in this list. */
224 struct list_head expose_csr;
225 /* Same, but for custom registers.
226 * Custom registers are for non-standard extensions and use abstract register numbers
227 * from range 0xc000 ... 0xffff. */
228 struct list_head expose_custom;
230 riscv_sample_config_t sample_config;
231 struct riscv_sample_buf sample_buf;
234 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
238 uint8_t tunneled_dr_width;
239 struct scan_field tunneled_dr[4];
240 } riscv_bscan_tunneled_scan_context_t;
247 unsigned vpn_shift[PG_MAX_LEVEL];
248 unsigned vpn_mask[PG_MAX_LEVEL];
249 unsigned pte_ppn_shift[PG_MAX_LEVEL];
250 unsigned pte_ppn_mask[PG_MAX_LEVEL];
251 unsigned pa_ppn_shift[PG_MAX_LEVEL];
252 unsigned pa_ppn_mask[PG_MAX_LEVEL];
255 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
256 extern int riscv_command_timeout_sec;
258 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
259 extern int riscv_reset_timeout_sec;
261 extern bool riscv_enable_virtual;
262 extern bool riscv_ebreakm;
263 extern bool riscv_ebreaks;
264 extern bool riscv_ebreaku;
266 /* Everything needs the RISC-V specific info structure, so here's a nice macro
267 * that provides that. */
268 static inline struct riscv_info *riscv_info(const struct target *target) __attribute__((unused));
269 static inline struct riscv_info *riscv_info(const struct target *target)
271 assert(target->arch_info);
272 return target->arch_info;
274 #define RISCV_INFO(R) struct riscv_info *R = riscv_info(target);
276 static inline bool is_riscv(const struct riscv_info *riscv_info)
278 return riscv_info->common_magic == RISCV_COMMON_MAGIC;
281 extern struct scan_field select_dtmcontrol;
282 extern struct scan_field select_dbus;
283 extern struct scan_field select_idcode;
285 extern struct scan_field *bscan_tunneled_select_dmi;
286 extern uint32_t bscan_tunneled_select_dmi_num_fields;
287 typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
288 extern int bscan_tunnel_ir_width;
290 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
291 void select_dmi_via_bscan(struct target *target);
293 /*** OpenOCD Interface */
294 int riscv_openocd_poll(struct target *target);
296 int riscv_halt(struct target *target);
298 int riscv_openocd_step(
299 struct target *target,
301 target_addr_t address,
302 int handle_breakpoints
305 int riscv_openocd_assert_reset(struct target *target);
306 int riscv_openocd_deassert_reset(struct target *target);
308 /*** RISC-V Interface ***/
310 bool riscv_supports_extension(struct target *target, char letter);
312 /* Returns XLEN for the given (or current) hart. */
313 unsigned riscv_xlen(const struct target *target);
314 int riscv_xlen_of_hart(const struct target *target);
316 /* Sets the current hart, which is the hart that will actually be used when
317 * issuing debug commands. */
318 int riscv_set_current_hartid(struct target *target, int hartid);
319 int riscv_select_current_hart(struct target *target);
320 int riscv_current_hartid(const struct target *target);
322 /*** Support functions for the RISC-V 'RTOS', which provides multihart support
323 * without requiring multiple targets. */
325 /* Lists the number of harts in the system, which are assumed to be
326 * consecutive and start with mhartid=0. */
327 int riscv_count_harts(struct target *target);
329 /** Set register, updating the cache. */
330 int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
331 /** Get register, from the cache if it's in there. */
332 int riscv_get_register(struct target *target, riscv_reg_t *value,
335 /* Checks the state of the current hart -- "is_halted" checks the actual
336 * on-device register. */
337 bool riscv_is_halted(struct target *target);
339 /* These helper functions let the generic program interface get target-specific
341 size_t riscv_debug_buffer_size(struct target *target);
343 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index);
344 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn);
345 int riscv_execute_debug_buffer(struct target *target);
347 void riscv_fill_dmi_nop_u64(struct target *target, char *buf);
348 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d);
349 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a);
350 int riscv_dmi_write_u64_bits(struct target *target);
352 int riscv_enumerate_triggers(struct target *target);
354 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
355 int riscv_remove_watchpoint(struct target *target,
356 struct watchpoint *watchpoint);
358 int riscv_init_registers(struct target *target);
360 void riscv_semihosting_init(struct target *target);
362 enum semihosting_result riscv_semihosting(struct target *target, int *retval);
364 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
365 riscv_bscan_tunneled_scan_context_t *ctxt);
367 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);
368 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer);