git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <stdlib.h>
   5 #include <time.h>
   6
   7 #ifdef HAVE_CONFIG_H
   8 #include "config.h"
   9 #endif
  10
  11 #include <helper/log.h>
  12 #include <helper/time_support.h>
  13 #include "target/target.h"
  14 #include "target/algorithm.h"
  15 #include "target/target_type.h"
  16 #include <target/smp.h>
  17 #include "jtag/jtag.h"
  18 #include "target/register.h"
  19 #include "target/breakpoints.h"
  20 #include "riscv.h"
  21 #include "gdb_regs.h"
  22 #include "rtos/rtos.h"
  23 #include "debug_defines.h"
  24 #include <helper/bits.h>
  25
  26 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  27 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  28
  29 /* Constants for legacy SiFive hardware breakpoints. */
  30 #define CSR_BPCONTROL_X                 (1<<0)
  31 #define CSR_BPCONTROL_W                 (1<<1)
  32 #define CSR_BPCONTROL_R                 (1<<2)
  33 #define CSR_BPCONTROL_U                 (1<<3)
  34 #define CSR_BPCONTROL_S                 (1<<4)
  35 #define CSR_BPCONTROL_H                 (1<<5)
  36 #define CSR_BPCONTROL_M                 (1<<6)
  37 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  38 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  39
  40 #define DEBUG_ROM_START         0x800
  41 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  42 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  43 #define DEBUG_RAM_START         0x400
  44
  45 #define SETHALTNOT                              0x10c
  46
  47 /*** JTAG registers. ***/
  48
  49 #define DTMCONTROL                                      0x10
  50 #define DTMCONTROL_DBUS_RESET           (1<<16)
  51 #define DTMCONTROL_IDLE                         (7<<10)
  52 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  53 #define DTMCONTROL_VERSION                      (0xf)
  54
  55 #define DBUS                                            0x11
  56 #define DBUS_OP_START                           0
  57 #define DBUS_OP_SIZE                            2
  58 typedef enum {
  59         DBUS_OP_NOP = 0,
  60         DBUS_OP_READ = 1,
  61         DBUS_OP_WRITE = 2
  62 } dbus_op_t;
  63 typedef enum {
  64         DBUS_STATUS_SUCCESS = 0,
  65         DBUS_STATUS_FAILED = 2,
  66         DBUS_STATUS_BUSY = 3
  67 } dbus_status_t;
  68 #define DBUS_DATA_START                         2
  69 #define DBUS_DATA_SIZE                          34
  70 #define DBUS_ADDRESS_START                      36
  71
  72 typedef enum slot {
  73         SLOT0,
  74         SLOT1,
  75         SLOT_LAST,
  76 } slot_t;
  77
  78 /*** Debug Bus registers. ***/
  79
  80 #define DMCONTROL                               0x10
  81 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
  82 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
  83 #define DMCONTROL_BUSERROR              (7<<19)
  84 #define DMCONTROL_SERIAL                (3<<16)
  85 #define DMCONTROL_AUTOINCREMENT (1<<15)
  86 #define DMCONTROL_ACCESS                (7<<12)
  87 #define DMCONTROL_HARTID                (0x3ff<<2)
  88 #define DMCONTROL_NDRESET               (1<<1)
  89 #define DMCONTROL_FULLRESET             1
  90
  91 #define DMINFO                                  0x11
  92 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
  93 #define DMINFO_SERIALCOUNT              (0xf<<21)
  94 #define DMINFO_ACCESS128                (1<<20)
  95 #define DMINFO_ACCESS64                 (1<<19)
  96 #define DMINFO_ACCESS32                 (1<<18)
  97 #define DMINFO_ACCESS16                 (1<<17)
  98 #define DMINFO_ACCESS8                  (1<<16)
  99 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 100 #define DMINFO_AUTHENTICATED    (1<<5)
 101 #define DMINFO_AUTHBUSY                 (1<<4)
 102 #define DMINFO_AUTHTYPE                 (3<<2)
 103 #define DMINFO_VERSION                  3
 104
 105 /*** Info about the core being debugged. ***/
 106
 107 #define DBUS_ADDRESS_UNKNOWN    0xffff
 108
 109 #define MAX_HWBPS                       16
 110 #define DRAM_CACHE_SIZE         16
 111
 112 uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
 113 struct scan_field select_dtmcontrol = {
 114         .in_value = NULL,
 115         .out_value = ir_dtmcontrol
 116 };
 117 uint8_t ir_dbus[4] = {DBUS};
 118 struct scan_field select_dbus = {
 119         .in_value = NULL,
 120         .out_value = ir_dbus
 121 };
 122 uint8_t ir_idcode[4] = {0x1};
 123 struct scan_field select_idcode = {
 124         .in_value = NULL,
 125         .out_value = ir_idcode
 126 };
 127
 128 bscan_tunnel_type_t bscan_tunnel_type;
 129 int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
 130
 131 static const uint8_t bscan_zero[4] = {0};
 132 static const uint8_t bscan_one[4] = {1};
 133
 134 static uint8_t ir_user4[4];
 135 struct scan_field select_user4 = {
 136         .in_value = NULL,
 137         .out_value = ir_user4
 138 };
 139
 140
 141 static uint8_t bscan_tunneled_ir_width[4] = {5};  /* overridden by assignment in riscv_init_target */
 142 static struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
 143                 {
 144                         .num_bits = 3,
 145                         .out_value = bscan_zero,
 146                         .in_value = NULL,
 147                 },
 148                 {
 149                         .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
 150                         .out_value = ir_dbus,
 151                         .in_value = NULL,
 152                 },
 153                 {
 154                         .num_bits = 7,
 155                         .out_value = bscan_tunneled_ir_width,
 156                         .in_value = NULL,
 157                 },
 158                 {
 159                         .num_bits = 1,
 160                         .out_value = bscan_zero,
 161                         .in_value = NULL,
 162                 }
 163 };
 164
 165 static struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
 166                 {
 167                         .num_bits = 1,
 168                         .out_value = bscan_zero,
 169                         .in_value = NULL,
 170                 },
 171                 {
 172                         .num_bits = 7,
 173                         .out_value = bscan_tunneled_ir_width,
 174                         .in_value = NULL,
 175                 },
 176                 {
 177                         .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
 178                         .out_value = ir_dbus,
 179                         .in_value = NULL,
 180                 },
 181                 {
 182                         .num_bits = 3,
 183                         .out_value = bscan_zero,
 184                         .in_value = NULL,
 185                 }
 186 };
 187 static struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
 188 static uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
 189
 190 static struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
 191 static uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
 192
 193 struct trigger {
 194         uint64_t address;
 195         uint32_t length;
 196         uint64_t mask;
 197         uint64_t value;
 198         bool read, write, execute;
 199         int unique_id;
 200 };
 201
 202 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 203 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 204
 205 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 206 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 207
 208 static bool riscv_enable_virt2phys = true;
 209 bool riscv_ebreakm = true;
 210 bool riscv_ebreaks = true;
 211 bool riscv_ebreaku = true;
 212
 213 bool riscv_enable_virtual;
 214
 215 static enum {
 216         RO_NORMAL,
 217         RO_REVERSED
 218 } resume_order;
 219
 220 static const virt2phys_info_t sv32 = {
 221         .name = "Sv32",
 222         .va_bits = 32,
 223         .level = 2,
 224         .pte_shift = 2,
 225         .vpn_shift = {12, 22},
 226         .vpn_mask = {0x3ff, 0x3ff},
 227         .pte_ppn_shift = {10, 20},
 228         .pte_ppn_mask = {0x3ff, 0xfff},
 229         .pa_ppn_shift = {12, 22},
 230         .pa_ppn_mask = {0x3ff, 0xfff},
 231 };
 232
 233 static const virt2phys_info_t sv39 = {
 234         .name = "Sv39",
 235         .va_bits = 39,
 236         .level = 3,
 237         .pte_shift = 3,
 238         .vpn_shift = {12, 21, 30},
 239         .vpn_mask = {0x1ff, 0x1ff, 0x1ff},
 240         .pte_ppn_shift = {10, 19, 28},
 241         .pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 242         .pa_ppn_shift = {12, 21, 30},
 243         .pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 244 };
 245
 246 static const virt2phys_info_t sv48 = {
 247         .name = "Sv48",
 248         .va_bits = 48,
 249         .level = 4,
 250         .pte_shift = 3,
 251         .vpn_shift = {12, 21, 30, 39},
 252         .vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
 253         .pte_ppn_shift = {10, 19, 28, 37},
 254         .pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 255         .pa_ppn_shift = {12, 21, 30, 39},
 256         .pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 257 };
 258
 259 static void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before)
 260 {
 261         RISCV_INFO(r);
 262         uint32_t now = timeval_ms() & 0xffffffff;
 263         if (r->sample_buf.used + 5 < r->sample_buf.size) {
 264                 if (before)
 265                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE;
 266                 else
 267                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER;
 268                 r->sample_buf.buf[r->sample_buf.used++] = now & 0xff;
 269                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 8) & 0xff;
 270                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 16) & 0xff;
 271                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 24) & 0xff;
 272         }
 273 }
 274
 275 static int riscv_resume_go_all_harts(struct target *target);
 276
 277 void select_dmi_via_bscan(struct target *target)
 278 {
 279         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 280         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 281                 jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
 282                                                                                 bscan_tunnel_data_register_select_dmi, TAP_IDLE);
 283         else /* BSCAN_TUNNEL_NESTED_TAP */
 284                 jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
 285                                                                                 bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
 286 }
 287
 288 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
 289 {
 290         /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
 291         uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
 292         uint8_t tunneled_dr_width[4] = {32};
 293         uint8_t out_value[5] = {0};
 294         uint8_t in_value[5] = {0};
 295
 296         buf_set_u32(out_value, 0, 32, out);
 297         struct scan_field tunneled_ir[4] = {};
 298         struct scan_field tunneled_dr[4] = {};
 299
 300         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
 301                 tunneled_ir[0].num_bits = 3;
 302                 tunneled_ir[0].out_value = bscan_zero;
 303                 tunneled_ir[0].in_value = NULL;
 304                 tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
 305                 tunneled_ir[1].out_value = ir_dtmcontrol;
 306                 tunneled_ir[1].in_value = NULL;
 307                 tunneled_ir[2].num_bits = 7;
 308                 tunneled_ir[2].out_value = tunneled_ir_width;
 309                 tunneled_ir[2].in_value = NULL;
 310                 tunneled_ir[3].num_bits = 1;
 311                 tunneled_ir[3].out_value = bscan_zero;
 312                 tunneled_ir[3].in_value = NULL;
 313
 314                 tunneled_dr[0].num_bits = 3;
 315                 tunneled_dr[0].out_value = bscan_zero;
 316                 tunneled_dr[0].in_value = NULL;
 317                 tunneled_dr[1].num_bits = 32 + 1;
 318                 tunneled_dr[1].out_value = out_value;
 319                 tunneled_dr[1].in_value = in_value;
 320                 tunneled_dr[2].num_bits = 7;
 321                 tunneled_dr[2].out_value = tunneled_dr_width;
 322                 tunneled_dr[2].in_value = NULL;
 323                 tunneled_dr[3].num_bits = 1;
 324                 tunneled_dr[3].out_value = bscan_one;
 325                 tunneled_dr[3].in_value = NULL;
 326         } else {
 327                 /* BSCAN_TUNNEL_NESTED_TAP */
 328                 tunneled_ir[3].num_bits = 3;
 329                 tunneled_ir[3].out_value = bscan_zero;
 330                 tunneled_ir[3].in_value = NULL;
 331                 tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
 332                 tunneled_ir[2].out_value = ir_dtmcontrol;
 333                 tunneled_ir[1].in_value = NULL;
 334                 tunneled_ir[1].num_bits = 7;
 335                 tunneled_ir[1].out_value = tunneled_ir_width;
 336                 tunneled_ir[2].in_value = NULL;
 337                 tunneled_ir[0].num_bits = 1;
 338                 tunneled_ir[0].out_value = bscan_zero;
 339                 tunneled_ir[0].in_value = NULL;
 340
 341                 tunneled_dr[3].num_bits = 3;
 342                 tunneled_dr[3].out_value = bscan_zero;
 343                 tunneled_dr[3].in_value = NULL;
 344                 tunneled_dr[2].num_bits = 32 + 1;
 345                 tunneled_dr[2].out_value = out_value;
 346                 tunneled_dr[2].in_value = in_value;
 347                 tunneled_dr[1].num_bits = 7;
 348                 tunneled_dr[1].out_value = tunneled_dr_width;
 349                 tunneled_dr[1].in_value = NULL;
 350                 tunneled_dr[0].num_bits = 1;
 351                 tunneled_dr[0].out_value = bscan_one;
 352                 tunneled_dr[0].in_value = NULL;
 353         }
 354         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 355         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE);
 356         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE);
 357         select_dmi_via_bscan(target);
 358
 359         int retval = jtag_execute_queue();
 360         if (retval != ERROR_OK) {
 361                 LOG_ERROR("failed jtag scan: %d", retval);
 362                 return retval;
 363         }
 364         /* Note the starting offset is bit 1, not bit 0.  In BSCAN tunnel, there is a one-bit TCK skew between
 365            output and input */
 366         uint32_t in = buf_get_u32(in_value, 1, 32);
 367         LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
 368
 369         return in;
 370 }
 371
 372 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 373 {
 374         struct scan_field field;
 375         uint8_t in_value[4];
 376         uint8_t out_value[4] = { 0 };
 377
 378         if (bscan_tunnel_ir_width != 0)
 379                 return dtmcontrol_scan_via_bscan(target, out);
 380
 381
 382         buf_set_u32(out_value, 0, 32, out);
 383
 384         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 385
 386         field.num_bits = 32;
 387         field.out_value = out_value;
 388         field.in_value = in_value;
 389         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 390
 391         /* Always return to dbus. */
 392         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 393
 394         int retval = jtag_execute_queue();
 395         if (retval != ERROR_OK) {
 396                 LOG_ERROR("failed jtag scan: %d", retval);
 397                 return retval;
 398         }
 399
 400         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 401         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 402
 403         return in;
 404 }
 405
 406 static struct target_type *get_target_type(struct target *target)
 407 {
 408         if (!target->arch_info) {
 409                 LOG_ERROR("Target has not been initialized");
 410                 return NULL;
 411         }
 412
 413         RISCV_INFO(info);
 414         switch (info->dtm_version) {
 415                 case 0:
 416                         return &riscv011_target;
 417                 case 1:
 418                         return &riscv013_target;
 419                 default:
 420                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 421                         return NULL;
 422         }
 423 }
 424
 425 static int riscv_create_target(struct target *target, Jim_Interp *interp)
 426 {
 427         LOG_DEBUG("riscv_create_target()");
 428         target->arch_info = calloc(1, sizeof(struct riscv_info));
 429         if (!target->arch_info) {
 430                 LOG_ERROR("Failed to allocate RISC-V target structure.");
 431                 return ERROR_FAIL;
 432         }
 433         riscv_info_init(target, target->arch_info);
 434         return ERROR_OK;
 435 }
 436
 437 static int riscv_init_target(struct command_context *cmd_ctx,
 438                 struct target *target)
 439 {
 440         LOG_DEBUG("riscv_init_target()");
 441         RISCV_INFO(info);
 442         info->cmd_ctx = cmd_ctx;
 443
 444         select_dtmcontrol.num_bits = target->tap->ir_length;
 445         select_dbus.num_bits = target->tap->ir_length;
 446         select_idcode.num_bits = target->tap->ir_length;
 447
 448         if (bscan_tunnel_ir_width != 0) {
 449                 assert(target->tap->ir_length >= 6);
 450                 uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
 451                 ir_user4[0] = (uint8_t)ir_user4_raw;
 452                 ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8);
 453                 ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
 454                 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
 455                 select_user4.num_bits = target->tap->ir_length;
 456                 bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
 457                 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 458                         bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
 459                 else /* BSCAN_TUNNEL_NESTED_TAP */
 460                         bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
 461         }
 462
 463         riscv_semihosting_init(target);
 464
 465         target->debug_reason = DBG_REASON_DBGRQ;
 466
 467         return ERROR_OK;
 468 }
 469
 470 static void riscv_free_registers(struct target *target)
 471 {
 472         /* Free the shared structure use for most registers. */
 473         if (target->reg_cache) {
 474                 if (target->reg_cache->reg_list) {
 475                         free(target->reg_cache->reg_list[0].arch_info);
 476                         /* Free the ones we allocated separately. */
 477                         for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
 478                                 free(target->reg_cache->reg_list[i].arch_info);
 479                         for (unsigned int i = 0; i < target->reg_cache->num_regs; i++)
 480                                 free(target->reg_cache->reg_list[i].value);
 481                         free(target->reg_cache->reg_list);
 482                 }
 483                 free(target->reg_cache);
 484         }
 485 }
 486
 487 static void riscv_deinit_target(struct target *target)
 488 {
 489         LOG_DEBUG("riscv_deinit_target()");
 490
 491         struct riscv_info *info = target->arch_info;
 492         struct target_type *tt = get_target_type(target);
 493
 494         if (tt && info && info->version_specific)
 495                 tt->deinit_target(target);
 496
 497         riscv_free_registers(target);
 498
 499         if (!info)
 500                 return;
 501
 502         range_list_t *entry, *tmp;
 503         list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
 504                 free(entry->name);
 505                 free(entry);
 506         }
 507
 508         list_for_each_entry_safe(entry, tmp, &info->expose_custom, list) {
 509                 free(entry->name);
 510                 free(entry);
 511         }
 512
 513         free(info->reg_names);
 514         free(target->arch_info);
 515
 516         target->arch_info = NULL;
 517 }
 518
 519 static void trigger_from_breakpoint(struct trigger *trigger,
 520                 const struct breakpoint *breakpoint)
 521 {
 522         trigger->address = breakpoint->address;
 523         trigger->length = breakpoint->length;
 524         trigger->mask = ~0LL;
 525         trigger->read = false;
 526         trigger->write = false;
 527         trigger->execute = true;
 528         /* unique_id is unique across both breakpoints and watchpoints. */
 529         trigger->unique_id = breakpoint->unique_id;
 530 }
 531
 532 static int maybe_add_trigger_t1(struct target *target,
 533                 struct trigger *trigger, uint64_t tdata1)
 534 {
 535         RISCV_INFO(r);
 536
 537         const uint32_t bpcontrol_x = 1<<0;
 538         const uint32_t bpcontrol_w = 1<<1;
 539         const uint32_t bpcontrol_r = 1<<2;
 540         const uint32_t bpcontrol_u = 1<<3;
 541         const uint32_t bpcontrol_s = 1<<4;
 542         const uint32_t bpcontrol_h = 1<<5;
 543         const uint32_t bpcontrol_m = 1<<6;
 544         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 545         const uint32_t bpcontrol_bpaction = 0xff << 11;
 546
 547         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 548                 /* Trigger is already in use, presumably by user code. */
 549                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 550         }
 551
 552         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 553         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 554         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 555         tdata1 = set_field(tdata1, bpcontrol_u,
 556                         !!(r->misa & BIT('U' - 'A')));
 557         tdata1 = set_field(tdata1, bpcontrol_s,
 558                         !!(r->misa & BIT('S' - 'A')));
 559         tdata1 = set_field(tdata1, bpcontrol_h,
 560                         !!(r->misa & BIT('H' - 'A')));
 561         tdata1 |= bpcontrol_m;
 562         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 563         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 564
 565         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 566
 567         riscv_reg_t tdata1_rb;
 568         if (riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1) != ERROR_OK)
 569                 return ERROR_FAIL;
 570         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 571
 572         if (tdata1 != tdata1_rb) {
 573                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 574                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 575                                 tdata1, tdata1_rb);
 576                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 577                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 578         }
 579
 580         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 581
 582         return ERROR_OK;
 583 }
 584
 585 static int maybe_add_trigger_t2(struct target *target,
 586                 struct trigger *trigger, uint64_t tdata1)
 587 {
 588         RISCV_INFO(r);
 589
 590         /* tselect is already set */
 591         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 592                 /* Trigger is already in use, presumably by user code. */
 593                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 594         }
 595
 596         /* address/data match trigger */
 597         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 598         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 599                         MCONTROL_ACTION_DEBUG_MODE);
 600         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 601         tdata1 |= MCONTROL_M;
 602         if (r->misa & (1 << ('S' - 'A')))
 603                 tdata1 |= MCONTROL_S;
 604         if (r->misa & (1 << ('U' - 'A')))
 605                 tdata1 |= MCONTROL_U;
 606
 607         if (trigger->execute)
 608                 tdata1 |= MCONTROL_EXECUTE;
 609         if (trigger->read)
 610                 tdata1 |= MCONTROL_LOAD;
 611         if (trigger->write)
 612                 tdata1 |= MCONTROL_STORE;
 613
 614         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 615
 616         uint64_t tdata1_rb;
 617         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 618         if (result != ERROR_OK)
 619                 return result;
 620         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 621
 622         if (tdata1 != tdata1_rb) {
 623                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 624                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 625                                 tdata1, tdata1_rb);
 626                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 627                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 628         }
 629
 630         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 631
 632         return ERROR_OK;
 633 }
 634
 635 static int maybe_add_trigger_t6(struct target *target,
 636                 struct trigger *trigger, uint64_t tdata1)
 637 {
 638         RISCV_INFO(r);
 639
 640         /* tselect is already set */
 641         if (tdata1 & (CSR_MCONTROL6_EXECUTE | CSR_MCONTROL6_STORE | CSR_MCONTROL6_LOAD)) {
 642                 /* Trigger is already in use, presumably by user code. */
 643                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 644         }
 645
 646         /* address/data match trigger */
 647         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 648         tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION,
 649                         MCONTROL_ACTION_DEBUG_MODE);
 650         tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, MCONTROL_MATCH_EQUAL);
 651         tdata1 |= CSR_MCONTROL6_M;
 652         if (r->misa & (1 << ('H' - 'A')))
 653                 tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU;
 654         if (r->misa & (1 << ('S' - 'A')))
 655                 tdata1 |= CSR_MCONTROL6_S;
 656         if (r->misa & (1 << ('U' - 'A')))
 657                 tdata1 |= CSR_MCONTROL6_U;
 658
 659         if (trigger->execute)
 660                 tdata1 |= CSR_MCONTROL6_EXECUTE;
 661         if (trigger->read)
 662                 tdata1 |= CSR_MCONTROL6_LOAD;
 663         if (trigger->write)
 664                 tdata1 |= CSR_MCONTROL6_STORE;
 665
 666         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 667
 668         uint64_t tdata1_rb;
 669         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 670         if (result != ERROR_OK)
 671                 return result;
 672         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 673
 674         if (tdata1 != tdata1_rb) {
 675                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 676                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 677                                 tdata1, tdata1_rb);
 678                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 679                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 680         }
 681
 682         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 683
 684         return ERROR_OK;
 685 }
 686
 687 static int add_trigger(struct target *target, struct trigger *trigger)
 688 {
 689         RISCV_INFO(r);
 690
 691         if (riscv_enumerate_triggers(target) != ERROR_OK)
 692                 return ERROR_FAIL;
 693
 694         riscv_reg_t tselect;
 695         if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
 696                 return ERROR_FAIL;
 697
 698         unsigned int i;
 699         for (i = 0; i < r->trigger_count; i++) {
 700                 if (r->trigger_unique_id[i] != -1)
 701                         continue;
 702
 703                 riscv_set_register(target, GDB_REGNO_TSELECT, i);
 704
 705                 uint64_t tdata1;
 706                 int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
 707                 if (result != ERROR_OK)
 708                         return result;
 709                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 710
 711                 result = ERROR_OK;
 712                 switch (type) {
 713                         case 1:
 714                                 result = maybe_add_trigger_t1(target, trigger, tdata1);
 715                                 break;
 716                         case 2:
 717                                 result = maybe_add_trigger_t2(target, trigger, tdata1);
 718                                 break;
 719                         case 6:
 720                                 result = maybe_add_trigger_t6(target, trigger, tdata1);
 721                                 break;
 722                         default:
 723                                 LOG_DEBUG("trigger %d has unknown type %d", i, type);
 724                                 continue;
 725                 }
 726
 727                 if (result != ERROR_OK)
 728                         continue;
 729
 730                 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
 731                                 i, type, trigger->unique_id);
 732                 r->trigger_unique_id[i] = trigger->unique_id;
 733                 break;
 734         }
 735
 736         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 737
 738         if (i >= r->trigger_count) {
 739                 LOG_ERROR("Couldn't find an available hardware trigger.");
 740                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 741         }
 742
 743         return ERROR_OK;
 744 }
 745
 746 /**
 747  * Write one memory item of given "size". Use memory access of given "access_size".
 748  * Utilize read-modify-write, if needed.
 749  * */
 750 static int write_by_given_size(struct target *target, target_addr_t address,
 751                 uint32_t size, uint8_t *buffer, uint32_t access_size)
 752 {
 753         assert(size == 1 || size == 2 || size == 4 || size == 8);
 754         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 755
 756         if (access_size <= size && address % access_size == 0)
 757                 /* Can do the memory access directly without a helper buffer. */
 758                 return target_write_memory(target, address, access_size, size / access_size, buffer);
 759
 760         unsigned int offset_head = address % access_size;
 761         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 762         uint8_t helper_buf[n_blocks * access_size];
 763
 764         /* Read from memory */
 765         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 766                 return ERROR_FAIL;
 767
 768         /* Modify and write back */
 769         memcpy(helper_buf + offset_head, buffer, size);
 770         return target_write_memory(target, address - offset_head, access_size, n_blocks, helper_buf);
 771 }
 772
 773 /**
 774  * Read one memory item of given "size". Use memory access of given "access_size".
 775  * Read larger section of memory and pick out the required portion, if needed.
 776  * */
 777 static int read_by_given_size(struct target *target, target_addr_t address,
 778         uint32_t size, uint8_t *buffer, uint32_t access_size)
 779 {
 780         assert(size == 1 || size == 2 || size == 4 || size == 8);
 781         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 782
 783         if (access_size <= size && address % access_size == 0)
 784                 /* Can do the memory access directly without a helper buffer. */
 785                 return target_read_memory(target, address, access_size, size / access_size, buffer);
 786
 787         unsigned int offset_head = address % access_size;
 788         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 789         uint8_t helper_buf[n_blocks * access_size];
 790
 791         /* Read from memory */
 792         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 793                 return ERROR_FAIL;
 794
 795         /* Pick the requested portion from the buffer */
 796         memcpy(buffer, helper_buf + offset_head, size);
 797         return ERROR_OK;
 798 }
 799
 800 /**
 801  * Write one memory item using any memory access size that will work.
 802  * Utilize read-modify-write, if needed.
 803  * */
 804 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 805 {
 806         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 807
 808         /* Find access size that correspond to data size and the alignment. */
 809         unsigned int preferred_size = size;
 810         while (address % preferred_size != 0)
 811                 preferred_size /= 2;
 812
 813         /* First try the preferred (most natural) access size. */
 814         if (write_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 815                 return ERROR_OK;
 816
 817         /* On failure, try other access sizes.
 818            Minimize the number of accesses by trying first the largest size. */
 819         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 820                 if (access_size == preferred_size)
 821                         /* Already tried this size. */
 822                         continue;
 823
 824                 if (write_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 825                         return ERROR_OK;
 826         }
 827
 828         /* No access attempt succeeded. */
 829         return ERROR_FAIL;
 830 }
 831
 832 /**
 833  * Read one memory item using any memory access size that will work.
 834  * Read larger section of memory and pick out the required portion, if needed.
 835  * */
 836 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 837 {
 838         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 839
 840         /* Find access size that correspond to data size and the alignment. */
 841         unsigned int preferred_size = size;
 842         while (address % preferred_size != 0)
 843                 preferred_size /= 2;
 844
 845         /* First try the preferred (most natural) access size. */
 846         if (read_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 847                 return ERROR_OK;
 848
 849         /* On failure, try other access sizes.
 850            Minimize the number of accesses by trying first the largest size. */
 851         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 852                 if (access_size == preferred_size)
 853                         /* Already tried this size. */
 854                         continue;
 855
 856                 if (read_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 857                         return ERROR_OK;
 858         }
 859
 860         /* No access attempt succeeded. */
 861         return ERROR_FAIL;
 862 }
 863
 864 int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 865 {
 866         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
 867         assert(breakpoint);
 868         if (breakpoint->type == BKPT_SOFT) {
 869                 /** @todo check RVC for size/alignment */
 870                 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
 871                         LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
 872                         return ERROR_FAIL;
 873                 }
 874
 875                 if (0 != (breakpoint->address % 2)) {
 876                         LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
 877                         return ERROR_FAIL;
 878                 }
 879
 880                 /* Read the original instruction. */
 881                 if (riscv_read_by_any_size(
 882                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 883                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 884                                         breakpoint->address);
 885                         return ERROR_FAIL;
 886                 }
 887
 888                 uint8_t buff[4] = { 0 };
 889                 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
 890                 /* Write the ebreak instruction. */
 891                 if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
 892                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 893                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 894                         return ERROR_FAIL;
 895                 }
 896
 897         } else if (breakpoint->type == BKPT_HARD) {
 898                 struct trigger trigger;
 899                 trigger_from_breakpoint(&trigger, breakpoint);
 900                 int const result = add_trigger(target, &trigger);
 901                 if (result != ERROR_OK)
 902                         return result;
 903         } else {
 904                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 905                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 906         }
 907
 908         breakpoint->is_set = true;
 909         return ERROR_OK;
 910 }
 911
 912 static int remove_trigger(struct target *target, struct trigger *trigger)
 913 {
 914         RISCV_INFO(r);
 915
 916         if (riscv_enumerate_triggers(target) != ERROR_OK)
 917                 return ERROR_FAIL;
 918
 919         unsigned int i;
 920         for (i = 0; i < r->trigger_count; i++) {
 921                 if (r->trigger_unique_id[i] == trigger->unique_id)
 922                         break;
 923         }
 924         if (i >= r->trigger_count) {
 925                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 926                                 "trigger.");
 927                 return ERROR_FAIL;
 928         }
 929         LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
 930                         trigger->unique_id);
 931
 932         riscv_reg_t tselect;
 933         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
 934         if (result != ERROR_OK)
 935                 return result;
 936         riscv_set_register(target, GDB_REGNO_TSELECT, i);
 937         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 938         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 939         r->trigger_unique_id[i] = -1;
 940
 941         return ERROR_OK;
 942 }
 943
 944 int riscv_remove_breakpoint(struct target *target,
 945                 struct breakpoint *breakpoint)
 946 {
 947         if (breakpoint->type == BKPT_SOFT) {
 948                 /* Write the original instruction. */
 949                 if (riscv_write_by_any_size(
 950                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 951                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 952                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 953                         return ERROR_FAIL;
 954                 }
 955
 956         } else if (breakpoint->type == BKPT_HARD) {
 957                 struct trigger trigger;
 958                 trigger_from_breakpoint(&trigger, breakpoint);
 959                 int result = remove_trigger(target, &trigger);
 960                 if (result != ERROR_OK)
 961                         return result;
 962
 963         } else {
 964                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 965                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 966         }
 967
 968         breakpoint->is_set = false;
 969
 970         return ERROR_OK;
 971 }
 972
 973 static void trigger_from_watchpoint(struct trigger *trigger,
 974                 const struct watchpoint *watchpoint)
 975 {
 976         trigger->address = watchpoint->address;
 977         trigger->length = watchpoint->length;
 978         trigger->mask = watchpoint->mask;
 979         trigger->value = watchpoint->value;
 980         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 981         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 982         trigger->execute = false;
 983         /* unique_id is unique across both breakpoints and watchpoints. */
 984         trigger->unique_id = watchpoint->unique_id;
 985 }
 986
 987 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 988 {
 989         struct trigger trigger;
 990         trigger_from_watchpoint(&trigger, watchpoint);
 991
 992         int result = add_trigger(target, &trigger);
 993         if (result != ERROR_OK)
 994                 return result;
 995         watchpoint->is_set = true;
 996
 997         return ERROR_OK;
 998 }
 999
1000 int riscv_remove_watchpoint(struct target *target,
1001                 struct watchpoint *watchpoint)
1002 {
1003         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
1004
1005         struct trigger trigger;
1006         trigger_from_watchpoint(&trigger, watchpoint);
1007
1008         int result = remove_trigger(target, &trigger);
1009         if (result != ERROR_OK)
1010                 return result;
1011         watchpoint->is_set = false;
1012
1013         return ERROR_OK;
1014 }
1015
1016 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1017  * current halt.
1018  *
1019  * The GDB server uses this information to tell GDB what data address has
1020  * been hit, which enables GDB to print the hit variable along with its old
1021  * and new value. */
1022 int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1023 {
1024         struct watchpoint *wp = target->watchpoints;
1025
1026         LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
1027
1028         /*TODO instead of disassembling the instruction that we think caused the
1029          * trigger, check the hit bit of each watchpoint first. The hit bit is
1030          * simpler and more reliable to check but as it is optional and relatively
1031          * new, not all hardware will implement it  */
1032         riscv_reg_t dpc;
1033         riscv_get_register(target, &dpc, GDB_REGNO_DPC);
1034         const uint8_t length = 4;
1035         LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
1036
1037         /* fetch the instruction at dpc */
1038         uint8_t buffer[length];
1039         if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
1040                 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
1041                 return ERROR_FAIL;
1042         }
1043
1044         uint32_t instruction = 0;
1045
1046         for (int i = 0; i < length; i++) {
1047                 LOG_DEBUG("Next byte is %x", buffer[i]);
1048                 instruction += (buffer[i] << 8 * i);
1049         }
1050         LOG_DEBUG("Full instruction is %x", instruction);
1051
1052         /* find out which memory address is accessed by the instruction at dpc */
1053         /* opcode is first 7 bits of the instruction */
1054         uint8_t opcode = instruction & 0x7F;
1055         uint32_t rs1;
1056         int16_t imm;
1057         riscv_reg_t mem_addr;
1058
1059         if (opcode == MATCH_LB || opcode == MATCH_SB) {
1060                 rs1 = (instruction & 0xf8000) >> 15;
1061                 riscv_get_register(target, &mem_addr, rs1);
1062
1063                 if (opcode == MATCH_SB) {
1064                         LOG_DEBUG("%x is store instruction", instruction);
1065                         imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
1066                 } else {
1067                         LOG_DEBUG("%x is load instruction", instruction);
1068                         imm = (instruction & 0xfff00000) >> 20;
1069                 }
1070                 /* sign extend 12-bit imm to 16-bits */
1071                 if (imm & (1 << 11))
1072                         imm |= 0xf000;
1073                 mem_addr += imm;
1074                 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
1075         } else {
1076                 LOG_DEBUG("%x is not a RV32I load or store", instruction);
1077                 return ERROR_FAIL;
1078         }
1079
1080         while (wp) {
1081                 /*TODO support length/mask */
1082                 if (wp->address == mem_addr) {
1083                         *hit_watchpoint = wp;
1084                         LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
1085                         return ERROR_OK;
1086                 }
1087                 wp = wp->next;
1088         }
1089
1090         /* No match found - either we hit a watchpoint caused by an instruction that
1091          * this function does not yet disassemble, or we hit a breakpoint.
1092          *
1093          * OpenOCD will behave as if this function had never been implemented i.e.
1094          * report the halt to GDB with no address information. */
1095         return ERROR_FAIL;
1096 }
1097
1098
1099 static int oldriscv_step(struct target *target, int current, uint32_t address,
1100                 int handle_breakpoints)
1101 {
1102         struct target_type *tt = get_target_type(target);
1103         return tt->step(target, current, address, handle_breakpoints);
1104 }
1105
1106 static int old_or_new_riscv_step(struct target *target, int current,
1107                 target_addr_t address, int handle_breakpoints)
1108 {
1109         RISCV_INFO(r);
1110         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1111         if (!r->is_halted)
1112                 return oldriscv_step(target, current, address, handle_breakpoints);
1113         else
1114                 return riscv_openocd_step(target, current, address, handle_breakpoints);
1115 }
1116
1117
1118 static int riscv_examine(struct target *target)
1119 {
1120         LOG_DEBUG("riscv_examine()");
1121         if (target_was_examined(target)) {
1122                 LOG_DEBUG("Target was already examined.");
1123                 return ERROR_OK;
1124         }
1125
1126         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1127
1128         RISCV_INFO(info);
1129         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1130         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1131         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
1132         LOG_DEBUG("  version=0x%x", info->dtm_version);
1133
1134         struct target_type *tt = get_target_type(target);
1135         if (!tt)
1136                 return ERROR_FAIL;
1137
1138         int result = tt->init_target(info->cmd_ctx, target);
1139         if (result != ERROR_OK)
1140                 return result;
1141
1142         return tt->examine(target);
1143 }
1144
1145 static int oldriscv_poll(struct target *target)
1146 {
1147         struct target_type *tt = get_target_type(target);
1148         return tt->poll(target);
1149 }
1150
1151 static int old_or_new_riscv_poll(struct target *target)
1152 {
1153         RISCV_INFO(r);
1154         if (!r->is_halted)
1155                 return oldriscv_poll(target);
1156         else
1157                 return riscv_openocd_poll(target);
1158 }
1159
1160 int riscv_select_current_hart(struct target *target)
1161 {
1162         return riscv_set_current_hartid(target, target->coreid);
1163 }
1164
1165 static int halt_prep(struct target *target)
1166 {
1167         RISCV_INFO(r);
1168
1169         LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
1170                                 target->debug_reason);
1171         if (riscv_select_current_hart(target) != ERROR_OK)
1172                 return ERROR_FAIL;
1173         if (riscv_is_halted(target)) {
1174                 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1175                                 target_name(target), target->debug_reason);
1176         } else {
1177                 if (r->halt_prep(target) != ERROR_OK)
1178                         return ERROR_FAIL;
1179                 r->prepped = true;
1180         }
1181
1182         return ERROR_OK;
1183 }
1184
1185 static int riscv_halt_go_all_harts(struct target *target)
1186 {
1187         RISCV_INFO(r);
1188
1189         if (riscv_select_current_hart(target) != ERROR_OK)
1190                 return ERROR_FAIL;
1191         if (riscv_is_halted(target)) {
1192                 LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
1193         } else {
1194                 if (r->halt_go(target) != ERROR_OK)
1195                         return ERROR_FAIL;
1196         }
1197
1198         riscv_invalidate_register_cache(target);
1199
1200         return ERROR_OK;
1201 }
1202
1203 static int halt_go(struct target *target)
1204 {
1205         RISCV_INFO(r);
1206         int result;
1207         if (!r->is_halted) {
1208                 struct target_type *tt = get_target_type(target);
1209                 result = tt->halt(target);
1210         } else {
1211                 result = riscv_halt_go_all_harts(target);
1212         }
1213         target->state = TARGET_HALTED;
1214         if (target->debug_reason == DBG_REASON_NOTHALTED)
1215                 target->debug_reason = DBG_REASON_DBGRQ;
1216
1217         return result;
1218 }
1219
1220 static int halt_finish(struct target *target)
1221 {
1222         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1223 }
1224
1225 int riscv_halt(struct target *target)
1226 {
1227         RISCV_INFO(r);
1228
1229         if (!r->is_halted) {
1230                 struct target_type *tt = get_target_type(target);
1231                 return tt->halt(target);
1232         }
1233
1234         LOG_DEBUG("[%d] halting all harts", target->coreid);
1235
1236         int result = ERROR_OK;
1237         if (target->smp) {
1238                 struct target_list *tlist;
1239                 foreach_smp_target(tlist, target->smp_targets) {
1240                         struct target *t = tlist->target;
1241                         if (halt_prep(t) != ERROR_OK)
1242                                 result = ERROR_FAIL;
1243                 }
1244
1245                 foreach_smp_target(tlist, target->smp_targets) {
1246                         struct target *t = tlist->target;
1247                         struct riscv_info *i = riscv_info(t);
1248                         if (i->prepped) {
1249                                 if (halt_go(t) != ERROR_OK)
1250                                         result = ERROR_FAIL;
1251                         }
1252                 }
1253
1254                 foreach_smp_target(tlist, target->smp_targets) {
1255                         struct target *t = tlist->target;
1256                         if (halt_finish(t) != ERROR_OK)
1257                                 return ERROR_FAIL;
1258                 }
1259
1260         } else {
1261                 if (halt_prep(target) != ERROR_OK)
1262                         result = ERROR_FAIL;
1263                 if (halt_go(target) != ERROR_OK)
1264                         result = ERROR_FAIL;
1265                 if (halt_finish(target) != ERROR_OK)
1266                         return ERROR_FAIL;
1267         }
1268
1269         return result;
1270 }
1271
1272 static int riscv_assert_reset(struct target *target)
1273 {
1274         LOG_DEBUG("[%d]", target->coreid);
1275         struct target_type *tt = get_target_type(target);
1276         riscv_invalidate_register_cache(target);
1277         return tt->assert_reset(target);
1278 }
1279
1280 static int riscv_deassert_reset(struct target *target)
1281 {
1282         LOG_DEBUG("[%d]", target->coreid);
1283         struct target_type *tt = get_target_type(target);
1284         return tt->deassert_reset(target);
1285 }
1286
1287 static int riscv_resume_prep_all_harts(struct target *target)
1288 {
1289         RISCV_INFO(r);
1290
1291         LOG_DEBUG("[%s] prep hart", target_name(target));
1292         if (riscv_select_current_hart(target) != ERROR_OK)
1293                 return ERROR_FAIL;
1294         if (riscv_is_halted(target)) {
1295                 if (r->resume_prep(target) != ERROR_OK)
1296                         return ERROR_FAIL;
1297         } else {
1298                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1299                                 target_name(target));
1300         }
1301
1302         LOG_DEBUG("[%s] mark as prepped", target_name(target));
1303         r->prepped = true;
1304
1305         return ERROR_OK;
1306 }
1307
1308 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1309 static int disable_triggers(struct target *target, riscv_reg_t *state)
1310 {
1311         RISCV_INFO(r);
1312
1313         LOG_DEBUG("deal with triggers");
1314
1315         if (riscv_enumerate_triggers(target) != ERROR_OK)
1316                 return ERROR_FAIL;
1317
1318         if (r->manual_hwbp_set) {
1319                 /* Look at every trigger that may have been set. */
1320                 riscv_reg_t tselect;
1321                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1322                         return ERROR_FAIL;
1323                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1324                         if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1325                                 return ERROR_FAIL;
1326                         riscv_reg_t tdata1;
1327                         if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
1328                                 return ERROR_FAIL;
1329                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
1330                                 state[t] = tdata1;
1331                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
1332                                         return ERROR_FAIL;
1333                         }
1334                 }
1335                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1336                         return ERROR_FAIL;
1337
1338         } else {
1339                 /* Just go through the triggers we manage. */
1340                 struct watchpoint *watchpoint = target->watchpoints;
1341                 int i = 0;
1342                 while (watchpoint) {
1343                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set);
1344                         state[i] = watchpoint->is_set;
1345                         if (watchpoint->is_set) {
1346                                 if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
1347                                         return ERROR_FAIL;
1348                         }
1349                         watchpoint = watchpoint->next;
1350                         i++;
1351                 }
1352         }
1353
1354         return ERROR_OK;
1355 }
1356
1357 static int enable_triggers(struct target *target, riscv_reg_t *state)
1358 {
1359         RISCV_INFO(r);
1360
1361         if (r->manual_hwbp_set) {
1362                 /* Look at every trigger that may have been set. */
1363                 riscv_reg_t tselect;
1364                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1365                         return ERROR_FAIL;
1366                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1367                         if (state[t] != 0) {
1368                                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1369                                         return ERROR_FAIL;
1370                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
1371                                         return ERROR_FAIL;
1372                         }
1373                 }
1374                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1375                         return ERROR_FAIL;
1376
1377         } else {
1378                 struct watchpoint *watchpoint = target->watchpoints;
1379                 int i = 0;
1380                 while (watchpoint) {
1381                         LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
1382                         if (state[i]) {
1383                                 if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
1384                                         return ERROR_FAIL;
1385                         }
1386                         watchpoint = watchpoint->next;
1387                         i++;
1388                 }
1389         }
1390
1391         return ERROR_OK;
1392 }
1393
1394 /**
1395  * Get everything ready to resume.
1396  */
1397 static int resume_prep(struct target *target, int current,
1398                 target_addr_t address, int handle_breakpoints, int debug_execution)
1399 {
1400         RISCV_INFO(r);
1401         LOG_DEBUG("[%d]", target->coreid);
1402
1403         if (!current)
1404                 riscv_set_register(target, GDB_REGNO_PC, address);
1405
1406         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1407                 /* To be able to run off a trigger, disable all the triggers, step, and
1408                  * then resume as usual. */
1409                 riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
1410
1411                 if (disable_triggers(target, trigger_state) != ERROR_OK)
1412                         return ERROR_FAIL;
1413
1414                 if (old_or_new_riscv_step(target, true, 0, false) != ERROR_OK)
1415                         return ERROR_FAIL;
1416
1417                 if (enable_triggers(target, trigger_state) != ERROR_OK)
1418                         return ERROR_FAIL;
1419         }
1420
1421         if (r->is_halted) {
1422                 if (riscv_resume_prep_all_harts(target) != ERROR_OK)
1423                         return ERROR_FAIL;
1424         }
1425
1426         LOG_DEBUG("[%d] mark as prepped", target->coreid);
1427         r->prepped = true;
1428
1429         return ERROR_OK;
1430 }
1431
1432 /**
1433  * Resume all the harts that have been prepped, as close to instantaneous as
1434  * possible.
1435  */
1436 static int resume_go(struct target *target, int current,
1437                 target_addr_t address, int handle_breakpoints, int debug_execution)
1438 {
1439         RISCV_INFO(r);
1440         int result;
1441         if (!r->is_halted) {
1442                 struct target_type *tt = get_target_type(target);
1443                 result = tt->resume(target, current, address, handle_breakpoints,
1444                                 debug_execution);
1445         } else {
1446                 result = riscv_resume_go_all_harts(target);
1447         }
1448
1449         return result;
1450 }
1451
1452 static int resume_finish(struct target *target)
1453 {
1454         register_cache_invalidate(target->reg_cache);
1455
1456         target->state = TARGET_RUNNING;
1457         target->debug_reason = DBG_REASON_NOTHALTED;
1458         return target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1459 }
1460
1461 /**
1462  * @par single_hart When true, only resume a single hart even if SMP is
1463  * configured.  This is used to run algorithms on just one hart.
1464  */
1465 int riscv_resume(
1466                 struct target *target,
1467                 int current,
1468                 target_addr_t address,
1469                 int handle_breakpoints,
1470                 int debug_execution,
1471                 bool single_hart)
1472 {
1473         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1474         int result = ERROR_OK;
1475         if (target->smp && !single_hart) {
1476                 struct target_list *tlist;
1477                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1478                                                                          tlist, target->smp_targets) {
1479                         struct target *t = tlist->target;
1480                         if (resume_prep(t, current, address, handle_breakpoints,
1481                                                 debug_execution) != ERROR_OK)
1482                                 result = ERROR_FAIL;
1483                 }
1484
1485                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1486                                                                          tlist, target->smp_targets) {
1487                         struct target *t = tlist->target;
1488                         struct riscv_info *i = riscv_info(t);
1489                         if (i->prepped) {
1490                                 if (resume_go(t, current, address, handle_breakpoints,
1491                                                         debug_execution) != ERROR_OK)
1492                                         result = ERROR_FAIL;
1493                         }
1494                 }
1495
1496                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1497                                                                          tlist, target->smp_targets) {
1498                         struct target *t = tlist->target;
1499                         if (resume_finish(t) != ERROR_OK)
1500                                 return ERROR_FAIL;
1501                 }
1502
1503         } else {
1504                 if (resume_prep(target, current, address, handle_breakpoints,
1505                                         debug_execution) != ERROR_OK)
1506                         result = ERROR_FAIL;
1507                 if (resume_go(target, current, address, handle_breakpoints,
1508                                         debug_execution) != ERROR_OK)
1509                         result = ERROR_FAIL;
1510                 if (resume_finish(target) != ERROR_OK)
1511                         return ERROR_FAIL;
1512         }
1513
1514         return result;
1515 }
1516
1517 static int riscv_target_resume(struct target *target, int current, target_addr_t address,
1518                 int handle_breakpoints, int debug_execution)
1519 {
1520         return riscv_resume(target, current, address, handle_breakpoints,
1521                         debug_execution, false);
1522 }
1523
1524 static int riscv_mmu(struct target *target, int *enabled)
1525 {
1526         if (!riscv_enable_virt2phys) {
1527                 *enabled = 0;
1528                 return ERROR_OK;
1529         }
1530
1531         /* Don't use MMU in explicit or effective M (machine) mode */
1532         riscv_reg_t priv;
1533         if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
1534                 LOG_ERROR("Failed to read priv register.");
1535                 return ERROR_FAIL;
1536         }
1537
1538         riscv_reg_t mstatus;
1539         if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
1540                 LOG_ERROR("Failed to read mstatus register.");
1541                 return ERROR_FAIL;
1542         }
1543
1544         if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
1545                 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
1546                 *enabled = 0;
1547                 return ERROR_OK;
1548         }
1549
1550         riscv_reg_t satp;
1551         if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
1552                 LOG_DEBUG("Couldn't read SATP.");
1553                 /* If we can't read SATP, then there must not be an MMU. */
1554                 *enabled = 0;
1555                 return ERROR_OK;
1556         }
1557
1558         if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
1559                 LOG_DEBUG("MMU is disabled.");
1560                 *enabled = 0;
1561         } else {
1562                 LOG_DEBUG("MMU is enabled.");
1563                 *enabled = 1;
1564         }
1565
1566         return ERROR_OK;
1567 }
1568
1569 static int riscv_address_translate(struct target *target,
1570                 target_addr_t virtual, target_addr_t *physical)
1571 {
1572         RISCV_INFO(r);
1573         riscv_reg_t satp_value;
1574         int mode;
1575         uint64_t ppn_value;
1576         target_addr_t table_address;
1577         const virt2phys_info_t *info;
1578         uint64_t pte = 0;
1579         int i;
1580
1581         int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
1582         if (result != ERROR_OK)
1583                 return result;
1584
1585         unsigned xlen = riscv_xlen(target);
1586         mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
1587         switch (mode) {
1588                 case SATP_MODE_SV32:
1589                         info = &sv32;
1590                         break;
1591                 case SATP_MODE_SV39:
1592                         info = &sv39;
1593                         break;
1594                 case SATP_MODE_SV48:
1595                         info = &sv48;
1596                         break;
1597                 case SATP_MODE_OFF:
1598                         LOG_ERROR("No translation or protection." \
1599                                       " (satp: 0x%" PRIx64 ")", satp_value);
1600                         return ERROR_FAIL;
1601                 default:
1602                         LOG_ERROR("The translation mode is not supported." \
1603                                       " (satp: 0x%" PRIx64 ")", satp_value);
1604                         return ERROR_FAIL;
1605         }
1606         LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
1607
1608         /* verify bits xlen-1:va_bits-1 are all equal */
1609         target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
1610         target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
1611         if (masked_msbs != 0 && masked_msbs != mask) {
1612                 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
1613                                 "for %s mode.", virtual, info->name);
1614                 return ERROR_FAIL;
1615         }
1616
1617         ppn_value = get_field(satp_value, RISCV_SATP_PPN(xlen));
1618         table_address = ppn_value << RISCV_PGSHIFT;
1619         i = info->level - 1;
1620         while (i >= 0) {
1621                 uint64_t vpn = virtual >> info->vpn_shift[i];
1622                 vpn &= info->vpn_mask[i];
1623                 target_addr_t pte_address = table_address +
1624                                                                         (vpn << info->pte_shift);
1625                 uint8_t buffer[8];
1626                 assert(info->pte_shift <= 3);
1627                 int retval = r->read_memory(target, pte_address,
1628                                 4, (1 << info->pte_shift) / 4, buffer, 4);
1629                 if (retval != ERROR_OK)
1630                         return ERROR_FAIL;
1631
1632                 if (info->pte_shift == 2)
1633                         pte = buf_get_u32(buffer, 0, 32);
1634                 else
1635                         pte = buf_get_u64(buffer, 0, 64);
1636
1637                 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
1638                                 pte_address, pte);
1639
1640                 if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
1641                         return ERROR_FAIL;
1642
1643                 if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
1644                         break;
1645
1646                 i--;
1647                 if (i < 0)
1648                         break;
1649                 ppn_value = pte >> PTE_PPN_SHIFT;
1650                 table_address = ppn_value << RISCV_PGSHIFT;
1651         }
1652
1653         if (i < 0) {
1654                 LOG_ERROR("Couldn't find the PTE.");
1655                 return ERROR_FAIL;
1656         }
1657
1658         /* Make sure to clear out the high bits that may be set. */
1659         *physical = virtual & (((target_addr_t)1 << info->va_bits) - 1);
1660
1661         while (i < info->level) {
1662                 ppn_value = pte >> info->pte_ppn_shift[i];
1663                 ppn_value &= info->pte_ppn_mask[i];
1664                 *physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
1665                                 info->pa_ppn_shift[i]);
1666                 *physical |= (ppn_value << info->pa_ppn_shift[i]);
1667                 i++;
1668         }
1669         LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
1670                         *physical);
1671
1672         return ERROR_OK;
1673 }
1674
1675 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
1676 {
1677         int enabled;
1678         if (riscv_mmu(target, &enabled) == ERROR_OK) {
1679                 if (!enabled)
1680                         return ERROR_FAIL;
1681
1682                 if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
1683                         return ERROR_OK;
1684         }
1685
1686         return ERROR_FAIL;
1687 }
1688
1689 static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
1690                         uint32_t size, uint32_t count, uint8_t *buffer)
1691 {
1692         RISCV_INFO(r);
1693         if (riscv_select_current_hart(target) != ERROR_OK)
1694                 return ERROR_FAIL;
1695         return r->read_memory(target, phys_address, size, count, buffer, size);
1696 }
1697
1698 static int riscv_read_memory(struct target *target, target_addr_t address,
1699                 uint32_t size, uint32_t count, uint8_t *buffer)
1700 {
1701         if (count == 0) {
1702                 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address);
1703                 return ERROR_OK;
1704         }
1705
1706         if (riscv_select_current_hart(target) != ERROR_OK)
1707                 return ERROR_FAIL;
1708
1709         target_addr_t physical_addr;
1710         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1711                 address = physical_addr;
1712
1713         RISCV_INFO(r);
1714         return r->read_memory(target, address, size, count, buffer, size);
1715 }
1716
1717 static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
1718                         uint32_t size, uint32_t count, const uint8_t *buffer)
1719 {
1720         if (riscv_select_current_hart(target) != ERROR_OK)
1721                 return ERROR_FAIL;
1722         struct target_type *tt = get_target_type(target);
1723         return tt->write_memory(target, phys_address, size, count, buffer);
1724 }
1725
1726 static int riscv_write_memory(struct target *target, target_addr_t address,
1727                 uint32_t size, uint32_t count, const uint8_t *buffer)
1728 {
1729         if (count == 0) {
1730                 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address);
1731                 return ERROR_OK;
1732         }
1733
1734         if (riscv_select_current_hart(target) != ERROR_OK)
1735                 return ERROR_FAIL;
1736
1737         target_addr_t physical_addr;
1738         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1739                 address = physical_addr;
1740
1741         struct target_type *tt = get_target_type(target);
1742         return tt->write_memory(target, address, size, count, buffer);
1743 }
1744
1745 static const char *riscv_get_gdb_arch(struct target *target)
1746 {
1747         switch (riscv_xlen(target)) {
1748                 case 32:
1749                         return "riscv:rv32";
1750                 case 64:
1751                         return "riscv:rv64";
1752         }
1753         LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
1754         return NULL;
1755 }
1756
1757 static int riscv_get_gdb_reg_list_internal(struct target *target,
1758                 struct reg **reg_list[], int *reg_list_size,
1759                 enum target_register_class reg_class, bool read)
1760 {
1761         RISCV_INFO(r);
1762         LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1763                         target_name(target), r->current_hartid, reg_class, read);
1764
1765         if (!target->reg_cache) {
1766                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1767                 return ERROR_FAIL;
1768         }
1769
1770         if (riscv_select_current_hart(target) != ERROR_OK)
1771                 return ERROR_FAIL;
1772
1773         switch (reg_class) {
1774                 case REG_CLASS_GENERAL:
1775                         *reg_list_size = 33;
1776                         break;
1777                 case REG_CLASS_ALL:
1778                         *reg_list_size = target->reg_cache->num_regs;
1779                         break;
1780                 default:
1781                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
1782                         return ERROR_FAIL;
1783         }
1784
1785         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1786         if (!*reg_list)
1787                 return ERROR_FAIL;
1788
1789         for (int i = 0; i < *reg_list_size; i++) {
1790                 assert(!target->reg_cache->reg_list[i].valid ||
1791                                 target->reg_cache->reg_list[i].size > 0);
1792                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
1793                 if (read &&
1794                                 target->reg_cache->reg_list[i].exist &&
1795                                 !target->reg_cache->reg_list[i].valid) {
1796                         if (target->reg_cache->reg_list[i].type->get(
1797                                                 &target->reg_cache->reg_list[i]) != ERROR_OK)
1798                                 return ERROR_FAIL;
1799                 }
1800         }
1801
1802         return ERROR_OK;
1803 }
1804
1805 static int riscv_get_gdb_reg_list_noread(struct target *target,
1806                 struct reg **reg_list[], int *reg_list_size,
1807                 enum target_register_class reg_class)
1808 {
1809         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1810                         reg_class, false);
1811 }
1812
1813 static int riscv_get_gdb_reg_list(struct target *target,
1814                 struct reg **reg_list[], int *reg_list_size,
1815                 enum target_register_class reg_class)
1816 {
1817         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1818                         reg_class, true);
1819 }
1820
1821 static int riscv_arch_state(struct target *target)
1822 {
1823         struct target_type *tt = get_target_type(target);
1824         return tt->arch_state(target);
1825 }
1826
1827 /* Algorithm must end with a software breakpoint instruction. */
1828 static int riscv_run_algorithm(struct target *target, int num_mem_params,
1829                 struct mem_param *mem_params, int num_reg_params,
1830                 struct reg_param *reg_params, target_addr_t entry_point,
1831                 target_addr_t exit_point, int timeout_ms, void *arch_info)
1832 {
1833         RISCV_INFO(info);
1834
1835         if (num_mem_params > 0) {
1836                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1837                 return ERROR_FAIL;
1838         }
1839
1840         if (target->state != TARGET_HALTED) {
1841                 LOG_WARNING("target not halted");
1842                 return ERROR_TARGET_NOT_HALTED;
1843         }
1844
1845         /* Save registers */
1846         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", true);
1847         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1848                 return ERROR_FAIL;
1849         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1850         LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
1851
1852         uint64_t saved_regs[32];
1853         for (int i = 0; i < num_reg_params; i++) {
1854                 LOG_DEBUG("save %s", reg_params[i].reg_name);
1855                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1856                 if (!r) {
1857                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1858                         return ERROR_FAIL;
1859                 }
1860
1861                 if (r->size != reg_params[i].size) {
1862                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
1863                                         reg_params[i].reg_name, r->size, reg_params[i].size);
1864                         return ERROR_FAIL;
1865                 }
1866
1867                 if (r->number > GDB_REGNO_XPR31) {
1868                         LOG_ERROR("Only GPRs can be use as argument registers.");
1869                         return ERROR_FAIL;
1870                 }
1871
1872                 if (r->type->get(r) != ERROR_OK)
1873                         return ERROR_FAIL;
1874                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1875
1876                 if (reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT) {
1877                         if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1878                                 return ERROR_FAIL;
1879                 }
1880         }
1881
1882
1883         /* Disable Interrupts before attempting to run the algorithm. */
1884         uint64_t current_mstatus;
1885         uint8_t mstatus_bytes[8] = { 0 };
1886
1887         LOG_DEBUG("Disabling Interrupts");
1888         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1889                         "mstatus", true);
1890         if (!reg_mstatus) {
1891                 LOG_ERROR("Couldn't find mstatus!");
1892                 return ERROR_FAIL;
1893         }
1894
1895         reg_mstatus->type->get(reg_mstatus);
1896         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1897         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1898         buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
1899                                 ie_mask, 0));
1900
1901         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1902
1903         /* Run algorithm */
1904         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1905         if (riscv_resume(target, 0, entry_point, 0, 0, true) != ERROR_OK)
1906                 return ERROR_FAIL;
1907
1908         int64_t start = timeval_ms();
1909         while (target->state != TARGET_HALTED) {
1910                 LOG_DEBUG("poll()");
1911                 int64_t now = timeval_ms();
1912                 if (now - start > timeout_ms) {
1913                         LOG_ERROR("Algorithm timed out after %" PRId64 " ms.", now - start);
1914                         riscv_halt(target);
1915                         old_or_new_riscv_poll(target);
1916                         enum gdb_regno regnums[] = {
1917                                 GDB_REGNO_RA, GDB_REGNO_SP, GDB_REGNO_GP, GDB_REGNO_TP,
1918                                 GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_FP,
1919                                 GDB_REGNO_S1, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2,
1920                                 GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6,
1921                                 GDB_REGNO_A7, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4,
1922                                 GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8,
1923                                 GDB_REGNO_S9, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_T3,
1924                                 GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6,
1925                                 GDB_REGNO_PC,
1926                                 GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
1927                         };
1928                         for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
1929                                 enum gdb_regno regno = regnums[i];
1930                                 riscv_reg_t reg_value;
1931                                 if (riscv_get_register(target, &reg_value, regno) != ERROR_OK)
1932                                         break;
1933                                 LOG_ERROR("%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value);
1934                         }
1935                         return ERROR_TARGET_TIMEOUT;
1936                 }
1937
1938                 int result = old_or_new_riscv_poll(target);
1939                 if (result != ERROR_OK)
1940                         return result;
1941         }
1942
1943         /* The current hart id might have been changed in poll(). */
1944         if (riscv_select_current_hart(target) != ERROR_OK)
1945                 return ERROR_FAIL;
1946
1947         if (reg_pc->type->get(reg_pc) != ERROR_OK)
1948                 return ERROR_FAIL;
1949         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1950         if (exit_point && final_pc != exit_point) {
1951                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1952                                 TARGET_PRIxADDR, final_pc, exit_point);
1953                 return ERROR_FAIL;
1954         }
1955
1956         /* Restore Interrupts */
1957         LOG_DEBUG("Restoring Interrupts");
1958         buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
1959         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1960
1961         /* Restore registers */
1962         uint8_t buf[8] = { 0 };
1963         buf_set_u64(buf, 0, info->xlen, saved_pc);
1964         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1965                 return ERROR_FAIL;
1966
1967         for (int i = 0; i < num_reg_params; i++) {
1968                 if (reg_params[i].direction == PARAM_IN ||
1969                                 reg_params[i].direction == PARAM_IN_OUT) {
1970                         struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1971                         if (r->type->get(r) != ERROR_OK) {
1972                                 LOG_ERROR("get(%s) failed", r->name);
1973                                 return ERROR_FAIL;
1974                         }
1975                         buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
1976                 }
1977                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1978                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1979                 buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
1980                 if (r->type->set(r, buf) != ERROR_OK) {
1981                         LOG_ERROR("set(%s) failed", r->name);
1982                         return ERROR_FAIL;
1983                 }
1984         }
1985
1986         return ERROR_OK;
1987 }
1988
1989 static int riscv_checksum_memory(struct target *target,
1990                 target_addr_t address, uint32_t count,
1991                 uint32_t *checksum)
1992 {
1993         struct working_area *crc_algorithm;
1994         struct reg_param reg_params[2];
1995         int retval;
1996
1997         LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
1998
1999         static const uint8_t riscv32_crc_code[] = {
2000 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
2001         };
2002         static const uint8_t riscv64_crc_code[] = {
2003 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
2004         };
2005
2006         static const uint8_t *crc_code;
2007
2008         unsigned xlen = riscv_xlen(target);
2009         unsigned crc_code_size;
2010         if (xlen == 32) {
2011                 crc_code = riscv32_crc_code;
2012                 crc_code_size = sizeof(riscv32_crc_code);
2013         } else {
2014                 crc_code = riscv64_crc_code;
2015                 crc_code_size = sizeof(riscv64_crc_code);
2016         }
2017
2018         if (count < crc_code_size * 4) {
2019                 /* Don't use the algorithm for relatively small buffers. It's faster
2020                  * just to read the memory.  target_checksum_memory() will take care of
2021                  * that if we fail. */
2022                 return ERROR_FAIL;
2023         }
2024
2025         retval = target_alloc_working_area(target, crc_code_size, &crc_algorithm);
2026         if (retval != ERROR_OK)
2027                 return retval;
2028
2029         if (crc_algorithm->address + crc_algorithm->size > address &&
2030                         crc_algorithm->address < address + count) {
2031                 /* Region to checksum overlaps with the work area we've been assigned.
2032                  * Bail. (Would be better to manually checksum what we read there, and
2033                  * use the algorithm for the rest.) */
2034                 target_free_working_area(target, crc_algorithm);
2035                 return ERROR_FAIL;
2036         }
2037
2038         retval = target_write_buffer(target, crc_algorithm->address, crc_code_size,
2039                         crc_code);
2040         if (retval != ERROR_OK) {
2041                 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
2042                                 crc_algorithm->address, retval);
2043                 target_free_working_area(target, crc_algorithm);
2044                 return retval;
2045         }
2046
2047         init_reg_param(&reg_params[0], "a0", xlen, PARAM_IN_OUT);
2048         init_reg_param(&reg_params[1], "a1", xlen, PARAM_OUT);
2049         buf_set_u64(reg_params[0].value, 0, xlen, address);
2050         buf_set_u64(reg_params[1].value, 0, xlen, count);
2051
2052         /* 20 second timeout/megabyte */
2053         int timeout = 20000 * (1 + (count / (1024 * 1024)));
2054
2055         retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
2056                         crc_algorithm->address,
2057                         0,      /* Leave exit point unspecified because we don't know. */
2058                         timeout, NULL);
2059
2060         if (retval == ERROR_OK)
2061                 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2062         else
2063                 LOG_ERROR("error executing RISC-V CRC algorithm");
2064
2065         destroy_reg_param(&reg_params[0]);
2066         destroy_reg_param(&reg_params[1]);
2067
2068         target_free_working_area(target, crc_algorithm);
2069
2070         LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
2071
2072         return retval;
2073 }
2074
2075 /*** OpenOCD Helper Functions ***/
2076
2077 enum riscv_poll_hart {
2078         RPH_NO_CHANGE,
2079         RPH_DISCOVERED_HALTED,
2080         RPH_DISCOVERED_RUNNING,
2081         RPH_ERROR
2082 };
2083 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
2084 {
2085         RISCV_INFO(r);
2086         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2087                 return RPH_ERROR;
2088
2089         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
2090
2091         /* If OpenOCD thinks we're running but this hart is halted then it's time
2092          * to raise an event. */
2093         bool halted = riscv_is_halted(target);
2094         if (target->state != TARGET_HALTED && halted) {
2095                 LOG_DEBUG("  triggered a halt");
2096                 r->on_halt(target);
2097                 return RPH_DISCOVERED_HALTED;
2098         } else if (target->state != TARGET_RUNNING && !halted) {
2099                 LOG_DEBUG("  triggered running");
2100                 target->state = TARGET_RUNNING;
2101                 target->debug_reason = DBG_REASON_NOTHALTED;
2102                 return RPH_DISCOVERED_RUNNING;
2103         }
2104
2105         return RPH_NO_CHANGE;
2106 }
2107
2108 static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
2109 {
2110         switch (halt_reason) {
2111                 case RISCV_HALT_BREAKPOINT:
2112                         target->debug_reason = DBG_REASON_BREAKPOINT;
2113                         break;
2114                 case RISCV_HALT_TRIGGER:
2115                         target->debug_reason = DBG_REASON_WATCHPOINT;
2116                         break;
2117                 case RISCV_HALT_INTERRUPT:
2118                 case RISCV_HALT_GROUP:
2119                         target->debug_reason = DBG_REASON_DBGRQ;
2120                         break;
2121                 case RISCV_HALT_SINGLESTEP:
2122                         target->debug_reason = DBG_REASON_SINGLESTEP;
2123                         break;
2124                 case RISCV_HALT_UNKNOWN:
2125                         target->debug_reason = DBG_REASON_UNDEFINED;
2126                         break;
2127                 case RISCV_HALT_ERROR:
2128                         return ERROR_FAIL;
2129         }
2130         LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
2131         return ERROR_OK;
2132 }
2133
2134 static int sample_memory(struct target *target)
2135 {
2136         RISCV_INFO(r);
2137
2138         if (!r->sample_buf.buf || !r->sample_config.enabled)
2139                 return ERROR_OK;
2140
2141         LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
2142
2143         uint64_t start = timeval_ms();
2144         riscv_sample_buf_maybe_add_timestamp(target, true);
2145         int result = ERROR_OK;
2146         if (r->sample_memory) {
2147                 result = r->sample_memory(target, &r->sample_buf, &r->sample_config,
2148                                                                           start + TARGET_DEFAULT_POLLING_INTERVAL);
2149                 if (result != ERROR_NOT_IMPLEMENTED)
2150                         goto exit;
2151         }
2152
2153         /* Default slow path. */
2154         while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
2155                 for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
2156                         if (r->sample_config.bucket[i].enabled &&
2157                                         r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
2158                                 assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
2159                                 r->sample_buf.buf[r->sample_buf.used] = i;
2160                                 result = riscv_read_phys_memory(
2161                                         target, r->sample_config.bucket[i].address,
2162                                         r->sample_config.bucket[i].size_bytes, 1,
2163                                         r->sample_buf.buf + r->sample_buf.used + 1);
2164                                 if (result == ERROR_OK)
2165                                         r->sample_buf.used += 1 + r->sample_config.bucket[i].size_bytes;
2166                                 else
2167                                         goto exit;
2168                         }
2169                 }
2170         }
2171
2172 exit:
2173         riscv_sample_buf_maybe_add_timestamp(target, false);
2174         if (result != ERROR_OK) {
2175                 LOG_INFO("Turning off memory sampling because it failed.");
2176                 r->sample_config.enabled = false;
2177         }
2178         return result;
2179 }
2180
2181 /*** OpenOCD Interface ***/
2182 int riscv_openocd_poll(struct target *target)
2183 {
2184         LOG_DEBUG("polling all harts");
2185         int halted_hart = -1;
2186
2187         if (target->smp) {
2188                 unsigned halts_discovered = 0;
2189                 unsigned should_remain_halted = 0;
2190                 unsigned should_resume = 0;
2191                 struct target_list *list;
2192                 foreach_smp_target(list, target->smp_targets) {
2193                         struct target *t = list->target;
2194                         struct riscv_info *r = riscv_info(t);
2195                         enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
2196                         switch (out) {
2197                         case RPH_NO_CHANGE:
2198                                 break;
2199                         case RPH_DISCOVERED_RUNNING:
2200                                 t->state = TARGET_RUNNING;
2201                                 t->debug_reason = DBG_REASON_NOTHALTED;
2202                                 break;
2203                         case RPH_DISCOVERED_HALTED:
2204                                 halts_discovered++;
2205                                 t->state = TARGET_HALTED;
2206                                 enum riscv_halt_reason halt_reason =
2207                                         riscv_halt_reason(t, r->current_hartid);
2208                                 if (set_debug_reason(t, halt_reason) != ERROR_OK)
2209                                         return ERROR_FAIL;
2210
2211                                 if (halt_reason == RISCV_HALT_BREAKPOINT) {
2212                                         int retval;
2213                                         switch (riscv_semihosting(t, &retval)) {
2214                                         case SEMIHOSTING_NONE:
2215                                         case SEMIHOSTING_WAITING:
2216                                                 /* This hart should remain halted. */
2217                                                 should_remain_halted++;
2218                                                 break;
2219                                         case SEMIHOSTING_HANDLED:
2220                                                 /* This hart should be resumed, along with any other
2221                                                          * harts that halted due to haltgroups. */
2222                                                 should_resume++;
2223                                                 break;
2224                                         case SEMIHOSTING_ERROR:
2225                                                 return retval;
2226                                         }
2227                                 } else if (halt_reason != RISCV_HALT_GROUP) {
2228                                         should_remain_halted++;
2229                                 }
2230                                 break;
2231
2232                         case RPH_ERROR:
2233                                 return ERROR_FAIL;
2234                         }
2235                 }
2236
2237                 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2238                                   should_remain_halted, should_resume);
2239                 if (should_remain_halted && should_resume) {
2240                         LOG_WARNING("%d harts should remain halted, and %d should resume.",
2241                                                 should_remain_halted, should_resume);
2242                 }
2243                 if (should_remain_halted) {
2244                         LOG_DEBUG("halt all");
2245                         riscv_halt(target);
2246                 } else if (should_resume) {
2247                         LOG_DEBUG("resume all");
2248                         riscv_resume(target, true, 0, 0, 0, false);
2249                 }
2250
2251                 /* Sample memory if any target is running. */
2252                 foreach_smp_target(list, target->smp_targets) {
2253                         struct target *t = list->target;
2254                         if (t->state == TARGET_RUNNING) {
2255                                 sample_memory(target);
2256                                 break;
2257                         }
2258                 }
2259
2260                 return ERROR_OK;
2261
2262         } else {
2263                 enum riscv_poll_hart out = riscv_poll_hart(target,
2264                                 riscv_current_hartid(target));
2265                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
2266                         if (target->state == TARGET_RUNNING)
2267                                 sample_memory(target);
2268                         return ERROR_OK;
2269                 } else if (out == RPH_ERROR) {
2270                         return ERROR_FAIL;
2271                 }
2272
2273                 halted_hart = riscv_current_hartid(target);
2274                 LOG_DEBUG("  hart %d halted", halted_hart);
2275
2276                 enum riscv_halt_reason halt_reason = riscv_halt_reason(target, halted_hart);
2277                 if (set_debug_reason(target, halt_reason) != ERROR_OK)
2278                         return ERROR_FAIL;
2279                 target->state = TARGET_HALTED;
2280         }
2281
2282         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
2283                 int retval;
2284                 switch (riscv_semihosting(target, &retval)) {
2285                         case SEMIHOSTING_NONE:
2286                         case SEMIHOSTING_WAITING:
2287                                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2288                                 break;
2289                         case SEMIHOSTING_HANDLED:
2290                                 if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK)
2291                                         return ERROR_FAIL;
2292                                 break;
2293                         case SEMIHOSTING_ERROR:
2294                                 return retval;
2295                 }
2296         } else {
2297                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2298         }
2299
2300         return ERROR_OK;
2301 }
2302
2303 int riscv_openocd_step(struct target *target, int current,
2304                 target_addr_t address, int handle_breakpoints)
2305 {
2306         LOG_DEBUG("stepping rtos hart");
2307
2308         if (!current)
2309                 riscv_set_register(target, GDB_REGNO_PC, address);
2310
2311         riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
2312         if (disable_triggers(target, trigger_state) != ERROR_OK)
2313                 return ERROR_FAIL;
2314
2315         int out = riscv_step_rtos_hart(target);
2316         if (out != ERROR_OK) {
2317                 LOG_ERROR("unable to step rtos hart");
2318                 return out;
2319         }
2320
2321         register_cache_invalidate(target->reg_cache);
2322
2323         if (enable_triggers(target, trigger_state) != ERROR_OK)
2324                 return ERROR_FAIL;
2325
2326         target->state = TARGET_RUNNING;
2327         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
2328         target->state = TARGET_HALTED;
2329         target->debug_reason = DBG_REASON_SINGLESTEP;
2330         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2331         return out;
2332 }
2333
2334 /* Command Handlers */
2335 COMMAND_HANDLER(riscv_set_command_timeout_sec)
2336 {
2337         if (CMD_ARGC != 1) {
2338                 LOG_ERROR("Command takes exactly 1 parameter");
2339                 return ERROR_COMMAND_SYNTAX_ERROR;
2340         }
2341         int timeout = atoi(CMD_ARGV[0]);
2342         if (timeout <= 0) {
2343                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2344                 return ERROR_FAIL;
2345         }
2346
2347         riscv_command_timeout_sec = timeout;
2348
2349         return ERROR_OK;
2350 }
2351
2352 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
2353 {
2354         if (CMD_ARGC != 1) {
2355                 LOG_ERROR("Command takes exactly 1 parameter");
2356                 return ERROR_COMMAND_SYNTAX_ERROR;
2357         }
2358         int timeout = atoi(CMD_ARGV[0]);
2359         if (timeout <= 0) {
2360                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2361                 return ERROR_FAIL;
2362         }
2363
2364         riscv_reset_timeout_sec = timeout;
2365         return ERROR_OK;
2366 }
2367
2368 COMMAND_HANDLER(riscv_set_prefer_sba)
2369 {
2370         struct target *target = get_current_target(CMD_CTX);
2371         RISCV_INFO(r);
2372         bool prefer_sba;
2373         LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
2374         if (CMD_ARGC != 1) {
2375                 LOG_ERROR("Command takes exactly 1 parameter");
2376                 return ERROR_COMMAND_SYNTAX_ERROR;
2377         }
2378         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], prefer_sba);
2379         if (prefer_sba) {
2380                 /* Use system bus with highest priority */
2381                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_SYSBUS;
2382                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_PROGBUF;
2383                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2384         } else {
2385                 /* Use progbuf with highest priority */
2386                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
2387                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
2388                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2389         }
2390
2391         /* Reset warning flags */
2392         r->mem_access_progbuf_warn = true;
2393         r->mem_access_sysbus_warn = true;
2394         r->mem_access_abstract_warn = true;
2395
2396         return ERROR_OK;
2397 }
2398
2399 COMMAND_HANDLER(riscv_set_mem_access)
2400 {
2401         struct target *target = get_current_target(CMD_CTX);
2402         RISCV_INFO(r);
2403         int progbuf_cnt = 0;
2404         int sysbus_cnt = 0;
2405         int abstract_cnt = 0;
2406
2407         if (CMD_ARGC < 1 || CMD_ARGC > RISCV_NUM_MEM_ACCESS_METHODS) {
2408                 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS);
2409                 return ERROR_COMMAND_SYNTAX_ERROR;
2410         }
2411
2412         /* Check argument validity */
2413         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2414                 if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
2415                         progbuf_cnt++;
2416                 } else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
2417                         sysbus_cnt++;
2418                 } else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
2419                         abstract_cnt++;
2420                 } else {
2421                         LOG_ERROR("Unknown argument '%s'. "
2422                                 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
2423                         return ERROR_COMMAND_SYNTAX_ERROR;
2424                 }
2425         }
2426         if (progbuf_cnt > 1 || sysbus_cnt > 1 || abstract_cnt > 1) {
2427                 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2428                 return ERROR_COMMAND_SYNTAX_ERROR;
2429         }
2430
2431         /* Args are valid, store them */
2432         for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
2433                 r->mem_access_methods[i] = RISCV_MEM_ACCESS_UNSPECIFIED;
2434         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2435                 if (strcmp("progbuf", CMD_ARGV[i]) == 0)
2436                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_PROGBUF;
2437                 else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
2438                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_SYSBUS;
2439                 else if (strcmp("abstract", CMD_ARGV[i]) == 0)
2440                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_ABSTRACT;
2441         }
2442
2443         /* Reset warning flags */
2444         r->mem_access_progbuf_warn = true;
2445         r->mem_access_sysbus_warn = true;
2446         r->mem_access_abstract_warn = true;
2447
2448         return ERROR_OK;
2449 }
2450
2451 COMMAND_HANDLER(riscv_set_enable_virtual)
2452 {
2453         if (CMD_ARGC != 1) {
2454                 LOG_ERROR("Command takes exactly 1 parameter");
2455                 return ERROR_COMMAND_SYNTAX_ERROR;
2456         }
2457         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virtual);
2458         return ERROR_OK;
2459 }
2460
2461 static int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
2462 {
2463         char *args = strdup(tcl_arg);
2464         if (!args)
2465                 return ERROR_FAIL;
2466
2467         /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2468         char *arg = strtok(args, ",");
2469         while (arg) {
2470                 unsigned low = 0;
2471                 unsigned high = 0;
2472                 char *name = NULL;
2473
2474                 char *dash = strchr(arg, '-');
2475                 char *equals = strchr(arg, '=');
2476                 unsigned int pos;
2477
2478                 if (!dash && !equals) {
2479                         /* Expecting single register number. */
2480                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2481                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2482                                 free(args);
2483                                 return ERROR_COMMAND_SYNTAX_ERROR;
2484                         }
2485                 } else if (dash && !equals) {
2486                         /* Expecting register range - two numbers separated by a dash: ##-## */
2487                         *dash = 0;
2488                         dash++;
2489                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2490                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2491                                 free(args);
2492                                 return ERROR_COMMAND_SYNTAX_ERROR;
2493                         }
2494                         if (sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash)) {
2495                                 LOG_ERROR("Failed to parse single register number from '%s'.", dash);
2496                                 free(args);
2497                                 return ERROR_COMMAND_SYNTAX_ERROR;
2498                         }
2499                         if (high < low) {
2500                                 LOG_ERROR("Incorrect range encountered [%u, %u].", low, high);
2501                                 free(args);
2502                                 return ERROR_FAIL;
2503                         }
2504                 } else if (!dash && equals) {
2505                         /* Expecting single register number with textual name specified: ##=name */
2506                         *equals = 0;
2507                         equals++;
2508                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2509                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2510                                 free(args);
2511                                 return ERROR_COMMAND_SYNTAX_ERROR;
2512                         }
2513
2514                         name = calloc(1, strlen(equals) + strlen(reg_type) + 2);
2515                         if (!name) {
2516                                 LOG_ERROR("Failed to allocate register name.");
2517                                 free(args);
2518                                 return ERROR_FAIL;
2519                         }
2520
2521                         /* Register prefix: "csr_" or "custom_" */
2522                         strcpy(name, reg_type);
2523                         name[strlen(reg_type)] = '_';
2524
2525                         if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals)) {
2526                                 LOG_ERROR("Failed to parse register name from '%s'.", equals);
2527                                 free(args);
2528                                 free(name);
2529                                 return ERROR_COMMAND_SYNTAX_ERROR;
2530                         }
2531                 } else {
2532                         LOG_ERROR("Invalid argument '%s'.", arg);
2533                         free(args);
2534                         return ERROR_COMMAND_SYNTAX_ERROR;
2535                 }
2536
2537                 high = high > low ? high : low;
2538
2539                 if (high > max_val) {
2540                         LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type, high, max_val);
2541                         free(name);
2542                         free(args);
2543                         return ERROR_FAIL;
2544                 }
2545
2546                 /* Check for overlap, name uniqueness. */
2547                 range_list_t *entry;
2548                 list_for_each_entry(entry, ranges, list) {
2549                         if ((entry->low <= high) && (low <= entry->high)) {
2550                                 if (low == high)
2551                                         LOG_WARNING("Duplicate %s register number - "
2552                                                         "Register %u has already been exposed previously", reg_type, low);
2553                                 else
2554                                         LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2555                                                         "with already exposed register/range at %u.", low, entry->low);
2556                         }
2557
2558                         if (entry->name && name && (strcasecmp(entry->name, name) == 0)) {
2559                                 LOG_ERROR("Duplicate register name \"%s\" found.", name);
2560                                 free(name);
2561                                 free(args);
2562                                 return ERROR_FAIL;
2563                         }
2564                 }
2565
2566                 range_list_t *range = calloc(1, sizeof(range_list_t));
2567                 if (!range) {
2568                         LOG_ERROR("Failed to allocate range list.");
2569                         free(name);
2570                         free(args);
2571                         return ERROR_FAIL;
2572                 }
2573
2574                 range->low = low;
2575                 range->high = high;
2576                 range->name = name;
2577                 list_add(&range->list, ranges);
2578
2579                 arg = strtok(NULL, ",");
2580         }
2581
2582         free(args);
2583         return ERROR_OK;
2584 }
2585
2586 COMMAND_HANDLER(riscv_set_expose_csrs)
2587 {
2588         if (CMD_ARGC == 0) {
2589                 LOG_ERROR("Command expects parameters");
2590                 return ERROR_COMMAND_SYNTAX_ERROR;
2591         }
2592
2593         struct target *target = get_current_target(CMD_CTX);
2594         RISCV_INFO(info);
2595         int ret = ERROR_OK;
2596
2597         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2598                 ret = parse_ranges(&info->expose_csr, CMD_ARGV[i], "csr", 0xfff);
2599                 if (ret != ERROR_OK)
2600                         break;
2601         }
2602
2603         return ret;
2604 }
2605
2606 COMMAND_HANDLER(riscv_set_expose_custom)
2607 {
2608         if (CMD_ARGC == 0) {
2609                 LOG_ERROR("Command expects parameters");
2610                 return ERROR_COMMAND_SYNTAX_ERROR;
2611         }
2612
2613         struct target *target = get_current_target(CMD_CTX);
2614         RISCV_INFO(info);
2615         int ret = ERROR_OK;
2616
2617         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2618                 ret = parse_ranges(&info->expose_custom, CMD_ARGV[i], "custom", 0x3fff);
2619                 if (ret != ERROR_OK)
2620                         break;
2621         }
2622
2623         return ret;
2624 }
2625
2626 COMMAND_HANDLER(riscv_authdata_read)
2627 {
2628         unsigned int index = 0;
2629         if (CMD_ARGC == 0) {
2630                 /* nop */
2631         } else if (CMD_ARGC == 1) {
2632                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2633         } else {
2634                 LOG_ERROR("Command takes at most one parameter");
2635                 return ERROR_COMMAND_SYNTAX_ERROR;
2636         }
2637
2638         struct target *target = get_current_target(CMD_CTX);
2639         if (!target) {
2640                 LOG_ERROR("target is NULL!");
2641                 return ERROR_FAIL;
2642         }
2643
2644         RISCV_INFO(r);
2645         if (!r) {
2646                 LOG_ERROR("riscv_info is NULL!");
2647                 return ERROR_FAIL;
2648         }
2649
2650         if (r->authdata_read) {
2651                 uint32_t value;
2652                 if (r->authdata_read(target, &value, index) != ERROR_OK)
2653                         return ERROR_FAIL;
2654                 command_print_sameline(CMD, "0x%08" PRIx32, value);
2655                 return ERROR_OK;
2656         } else {
2657                 LOG_ERROR("authdata_read is not implemented for this target.");
2658                 return ERROR_FAIL;
2659         }
2660 }
2661
2662 COMMAND_HANDLER(riscv_authdata_write)
2663 {
2664         uint32_t value;
2665         unsigned int index = 0;
2666
2667         if (CMD_ARGC == 0) {
2668                 /* nop */
2669         } else if (CMD_ARGC == 1) {
2670                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
2671         } else if (CMD_ARGC == 2) {
2672                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2673                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2674         } else {
2675                 LOG_ERROR("Command takes at most 2 arguments");
2676                 return ERROR_COMMAND_SYNTAX_ERROR;
2677         }
2678
2679         struct target *target = get_current_target(CMD_CTX);
2680         RISCV_INFO(r);
2681
2682         if (r->authdata_write) {
2683                 return r->authdata_write(target, value, index);
2684         } else {
2685                 LOG_ERROR("authdata_write is not implemented for this target.");
2686                 return ERROR_FAIL;
2687         }
2688 }
2689
2690 COMMAND_HANDLER(riscv_dmi_read)
2691 {
2692         if (CMD_ARGC != 1) {
2693                 LOG_ERROR("Command takes 1 parameter");
2694                 return ERROR_COMMAND_SYNTAX_ERROR;
2695         }
2696
2697         struct target *target = get_current_target(CMD_CTX);
2698         if (!target) {
2699                 LOG_ERROR("target is NULL!");
2700                 return ERROR_FAIL;
2701         }
2702
2703         RISCV_INFO(r);
2704         if (!r) {
2705                 LOG_ERROR("riscv_info is NULL!");
2706                 return ERROR_FAIL;
2707         }
2708
2709         if (r->dmi_read) {
2710                 uint32_t address, value;
2711                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2712                 if (r->dmi_read(target, &value, address) != ERROR_OK)
2713                         return ERROR_FAIL;
2714                 command_print(CMD, "0x%" PRIx32, value);
2715                 return ERROR_OK;
2716         } else {
2717                 LOG_ERROR("dmi_read is not implemented for this target.");
2718                 return ERROR_FAIL;
2719         }
2720 }
2721
2722
2723 COMMAND_HANDLER(riscv_dmi_write)
2724 {
2725         if (CMD_ARGC != 2) {
2726                 LOG_ERROR("Command takes exactly 2 arguments");
2727                 return ERROR_COMMAND_SYNTAX_ERROR;
2728         }
2729
2730         struct target *target = get_current_target(CMD_CTX);
2731         RISCV_INFO(r);
2732
2733         uint32_t address, value;
2734         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2735         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2736
2737         if (r->dmi_write) {
2738                 return r->dmi_write(target, address, value);
2739         } else {
2740                 LOG_ERROR("dmi_write is not implemented for this target.");
2741                 return ERROR_FAIL;
2742         }
2743 }
2744
2745 COMMAND_HANDLER(riscv_test_sba_config_reg)
2746 {
2747         if (CMD_ARGC != 4) {
2748                 LOG_ERROR("Command takes exactly 4 arguments");
2749                 return ERROR_COMMAND_SYNTAX_ERROR;
2750         }
2751
2752         struct target *target = get_current_target(CMD_CTX);
2753         RISCV_INFO(r);
2754
2755         target_addr_t legal_address;
2756         uint32_t num_words;
2757         target_addr_t illegal_address;
2758         bool run_sbbusyerror_test;
2759
2760         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address);
2761         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
2762         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address);
2763         COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
2764
2765         if (r->test_sba_config_reg) {
2766                 return r->test_sba_config_reg(target, legal_address, num_words,
2767                                 illegal_address, run_sbbusyerror_test);
2768         } else {
2769                 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
2770                 return ERROR_FAIL;
2771         }
2772 }
2773
2774 COMMAND_HANDLER(riscv_reset_delays)
2775 {
2776         int wait = 0;
2777
2778         if (CMD_ARGC > 1) {
2779                 LOG_ERROR("Command takes at most one argument");
2780                 return ERROR_COMMAND_SYNTAX_ERROR;
2781         }
2782
2783         if (CMD_ARGC == 1)
2784                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
2785
2786         struct target *target = get_current_target(CMD_CTX);
2787         RISCV_INFO(r);
2788         r->reset_delays_wait = wait;
2789         return ERROR_OK;
2790 }
2791
2792 COMMAND_HANDLER(riscv_set_ir)
2793 {
2794         if (CMD_ARGC != 2) {
2795                 LOG_ERROR("Command takes exactly 2 arguments");
2796                 return ERROR_COMMAND_SYNTAX_ERROR;
2797         }
2798
2799         uint32_t value;
2800         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2801
2802         if (!strcmp(CMD_ARGV[0], "idcode"))
2803                 buf_set_u32(ir_idcode, 0, 32, value);
2804         else if (!strcmp(CMD_ARGV[0], "dtmcs"))
2805                 buf_set_u32(ir_dtmcontrol, 0, 32, value);
2806         else if (!strcmp(CMD_ARGV[0], "dmi"))
2807                 buf_set_u32(ir_dbus, 0, 32, value);
2808         else
2809                 return ERROR_FAIL;
2810
2811         return ERROR_OK;
2812 }
2813
2814 COMMAND_HANDLER(riscv_resume_order)
2815 {
2816         if (CMD_ARGC > 1) {
2817                 LOG_ERROR("Command takes at most one argument");
2818                 return ERROR_COMMAND_SYNTAX_ERROR;
2819         }
2820
2821         if (!strcmp(CMD_ARGV[0], "normal")) {
2822                 resume_order = RO_NORMAL;
2823         } else if (!strcmp(CMD_ARGV[0], "reversed")) {
2824                 resume_order = RO_REVERSED;
2825         } else {
2826                 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV[0]);
2827                 return ERROR_FAIL;
2828         }
2829
2830         return ERROR_OK;
2831 }
2832
2833 COMMAND_HANDLER(riscv_use_bscan_tunnel)
2834 {
2835         int irwidth = 0;
2836         int tunnel_type = BSCAN_TUNNEL_NESTED_TAP;
2837
2838         if (CMD_ARGC > 2) {
2839                 LOG_ERROR("Command takes at most two arguments");
2840                 return ERROR_COMMAND_SYNTAX_ERROR;
2841         } else if (CMD_ARGC == 1) {
2842                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2843         } else if (CMD_ARGC == 2) {
2844                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2845                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tunnel_type);
2846         }
2847         if (tunnel_type == BSCAN_TUNNEL_NESTED_TAP)
2848                 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2849         else if (tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
2850                 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2851         else
2852                 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2853
2854         bscan_tunnel_type = tunnel_type;
2855         bscan_tunnel_ir_width = irwidth;
2856         return ERROR_OK;
2857 }
2858
2859 COMMAND_HANDLER(riscv_set_enable_virt2phys)
2860 {
2861         if (CMD_ARGC != 1) {
2862                 LOG_ERROR("Command takes exactly 1 parameter");
2863                 return ERROR_COMMAND_SYNTAX_ERROR;
2864         }
2865         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virt2phys);
2866         return ERROR_OK;
2867 }
2868
2869 COMMAND_HANDLER(riscv_set_ebreakm)
2870 {
2871         if (CMD_ARGC != 1) {
2872                 LOG_ERROR("Command takes exactly 1 parameter");
2873                 return ERROR_COMMAND_SYNTAX_ERROR;
2874         }
2875         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreakm);
2876         return ERROR_OK;
2877 }
2878
2879 COMMAND_HANDLER(riscv_set_ebreaks)
2880 {
2881         if (CMD_ARGC != 1) {
2882                 LOG_ERROR("Command takes exactly 1 parameter");
2883                 return ERROR_COMMAND_SYNTAX_ERROR;
2884         }
2885         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaks);
2886         return ERROR_OK;
2887 }
2888
2889 COMMAND_HANDLER(riscv_set_ebreaku)
2890 {
2891         if (CMD_ARGC != 1) {
2892                 LOG_ERROR("Command takes exactly 1 parameter");
2893                 return ERROR_COMMAND_SYNTAX_ERROR;
2894         }
2895         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaku);
2896         return ERROR_OK;
2897 }
2898
2899 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
2900                            unsigned int value)
2901 {
2902         char full_key[80];
2903         snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
2904         command_print(CMD, "%-21s %3d", full_key, value);
2905         return 0;
2906 }
2907
2908 COMMAND_HANDLER(handle_info)
2909 {
2910         struct target *target = get_current_target(CMD_CTX);
2911         RISCV_INFO(r);
2912
2913         /* This output format can be fed directly into TCL's "array set". */
2914
2915         riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
2916         riscv_enumerate_triggers(target);
2917         riscv_print_info_line(CMD, "hart", "trigger_count",
2918                                                   r->trigger_count);
2919
2920         if (r->print_info)
2921                 return CALL_COMMAND_HANDLER(r->print_info, target);
2922
2923         return 0;
2924 }
2925
2926 static const struct command_registration riscv_exec_command_handlers[] = {
2927         {
2928                 .name = "info",
2929                 .handler = handle_info,
2930                 .mode = COMMAND_EXEC,
2931                 .usage = "",
2932                 .help = "Displays some information OpenOCD detected about the target."
2933         },
2934         {
2935                 .name = "set_command_timeout_sec",
2936                 .handler = riscv_set_command_timeout_sec,
2937                 .mode = COMMAND_ANY,
2938                 .usage = "[sec]",
2939                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
2940         },
2941         {
2942                 .name = "set_reset_timeout_sec",
2943                 .handler = riscv_set_reset_timeout_sec,
2944                 .mode = COMMAND_ANY,
2945                 .usage = "[sec]",
2946                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
2947         },
2948         {
2949                 .name = "set_prefer_sba",
2950                 .handler = riscv_set_prefer_sba,
2951                 .mode = COMMAND_ANY,
2952                 .usage = "on|off",
2953                 .help = "When on, prefer to use System Bus Access to access memory. "
2954                         "When off (default), prefer to use the Program Buffer to access memory."
2955         },
2956         {
2957                 .name = "set_mem_access",
2958                 .handler = riscv_set_mem_access,
2959                 .mode = COMMAND_ANY,
2960                 .usage = "method1 [method2] [method3]",
2961                 .help = "Set which memory access methods shall be used and in which order "
2962                         "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2963         },
2964         {
2965                 .name = "set_enable_virtual",
2966                 .handler = riscv_set_enable_virtual,
2967                 .mode = COMMAND_ANY,
2968                 .usage = "on|off",
2969                 .help = "When on, memory accesses are performed on physical or virtual "
2970                                 "memory depending on the current system configuration. "
2971                                 "When off (default), all memory accessses are performed on physical memory."
2972         },
2973         {
2974                 .name = "expose_csrs",
2975                 .handler = riscv_set_expose_csrs,
2976                 .mode = COMMAND_CONFIG,
2977                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2978                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
2979                                 "addition to the standard ones. This must be executed before "
2980                                 "`init`."
2981         },
2982         {
2983                 .name = "expose_custom",
2984                 .handler = riscv_set_expose_custom,
2985                 .mode = COMMAND_CONFIG,
2986                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2987                 .help = "Configure a list of inclusive ranges for custom registers to "
2988                         "expose. custom0 is accessed as abstract register number 0xc000, "
2989                         "etc. This must be executed before `init`."
2990         },
2991         {
2992                 .name = "authdata_read",
2993                 .handler = riscv_authdata_read,
2994                 .usage = "[index]",
2995                 .mode = COMMAND_ANY,
2996                 .help = "Return the 32-bit value read from authdata or authdata0 "
2997                                 "(index=0), or authdata1 (index=1)."
2998         },
2999         {
3000                 .name = "authdata_write",
3001                 .handler = riscv_authdata_write,
3002                 .mode = COMMAND_ANY,
3003                 .usage = "[index] value",
3004                 .help = "Write the 32-bit value to authdata or authdata0 (index=0), "
3005                                 "or authdata1 (index=1)."
3006         },
3007         {
3008                 .name = "dmi_read",
3009                 .handler = riscv_dmi_read,
3010                 .mode = COMMAND_ANY,
3011                 .usage = "address",
3012                 .help = "Perform a 32-bit DMI read at address, returning the value."
3013         },
3014         {
3015                 .name = "dmi_write",
3016                 .handler = riscv_dmi_write,
3017                 .mode = COMMAND_ANY,
3018                 .usage = "address value",
3019                 .help = "Perform a 32-bit DMI write of value at address."
3020         },
3021         {
3022                 .name = "test_sba_config_reg",
3023                 .handler = riscv_test_sba_config_reg,
3024                 .mode = COMMAND_ANY,
3025                 .usage = "legal_address num_words "
3026                         "illegal_address run_sbbusyerror_test[on/off]",
3027                 .help = "Perform a series of tests on the SBCS register. "
3028                         "Inputs are a legal, 128-byte aligned address and a number of words to "
3029                         "read/write starting at that address (i.e., address range [legal address, "
3030                         "legal_address+word_size*num_words) must be legally readable/writable), "
3031                         "an illegal, 128-byte aligned address for error flag/handling cases, "
3032                         "and whether sbbusyerror test should be run."
3033         },
3034         {
3035                 .name = "reset_delays",
3036                 .handler = riscv_reset_delays,
3037                 .mode = COMMAND_ANY,
3038                 .usage = "[wait]",
3039                 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
3040                         "between scans to avoid encountering the target being busy. This "
3041                         "command resets those learned values after `wait` scans. It's only "
3042                         "useful for testing OpenOCD itself."
3043         },
3044         {
3045                 .name = "resume_order",
3046                 .handler = riscv_resume_order,
3047                 .mode = COMMAND_ANY,
3048                 .usage = "normal|reversed",
3049                 .help = "Choose the order that harts are resumed in when `hasel` is not "
3050                         "supported. Normal order is from lowest hart index to highest. "
3051                         "Reversed order is from highest hart index to lowest."
3052         },
3053         {
3054                 .name = "set_ir",
3055                 .handler = riscv_set_ir,
3056                 .mode = COMMAND_ANY,
3057                 .usage = "[idcode|dtmcs|dmi] value",
3058                 .help = "Set IR value for specified JTAG register."
3059         },
3060         {
3061                 .name = "use_bscan_tunnel",
3062                 .handler = riscv_use_bscan_tunnel,
3063                 .mode = COMMAND_ANY,
3064                 .usage = "value [type]",
3065                 .help = "Enable or disable use of a BSCAN tunnel to reach DM.  Supply "
3066                         "the width of the DM transport TAP's instruction register to "
3067                         "enable.  Supply a value of 0 to disable. Pass A second argument "
3068                         "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
3069                         "1: DATA_REGISTER}"
3070         },
3071         {
3072                 .name = "set_enable_virt2phys",
3073                 .handler = riscv_set_enable_virt2phys,
3074                 .mode = COMMAND_ANY,
3075                 .usage = "on|off",
3076                 .help = "When on (default), enable translation from virtual address to "
3077                         "physical address."
3078         },
3079         {
3080                 .name = "set_ebreakm",
3081                 .handler = riscv_set_ebreakm,
3082                 .mode = COMMAND_ANY,
3083                 .usage = "on|off",
3084                 .help = "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3085                         "don't trap to OpenOCD. Defaults to on."
3086         },
3087         {
3088                 .name = "set_ebreaks",
3089                 .handler = riscv_set_ebreaks,
3090                 .mode = COMMAND_ANY,
3091                 .usage = "on|off",
3092                 .help = "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3093                         "don't trap to OpenOCD. Defaults to on."
3094         },
3095         {
3096                 .name = "set_ebreaku",
3097                 .handler = riscv_set_ebreaku,
3098                 .mode = COMMAND_ANY,
3099                 .usage = "on|off",
3100                 .help = "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3101                         "don't trap to OpenOCD. Defaults to on."
3102         },
3103         COMMAND_REGISTRATION_DONE
3104 };
3105
3106 /*
3107  * To be noted that RISC-V targets use the same semihosting commands as
3108  * ARM targets.
3109  *
3110  * The main reason is compatibility with existing tools. For example the
3111  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3112  * configure semihosting, which generate commands like `arm semihosting
3113  * enable`.
3114  * A secondary reason is the fact that the protocol used is exactly the
3115  * one specified by ARM. If RISC-V will ever define its own semihosting
3116  * protocol, then a command like `riscv semihosting enable` will make
3117  * sense, but for now all semihosting commands are prefixed with `arm`.
3118  */
3119
3120 static const struct command_registration riscv_command_handlers[] = {
3121         {
3122                 .name = "riscv",
3123                 .mode = COMMAND_ANY,
3124                 .help = "RISC-V Command Group",
3125                 .usage = "",
3126                 .chain = riscv_exec_command_handlers
3127         },
3128         {
3129                 .name = "arm",
3130                 .mode = COMMAND_ANY,
3131                 .help = "ARM Command Group",
3132                 .usage = "",
3133                 .chain = semihosting_common_handlers
3134         },
3135         COMMAND_REGISTRATION_DONE
3136 };
3137
3138 static unsigned riscv_xlen_nonconst(struct target *target)
3139 {
3140         return riscv_xlen(target);
3141 }
3142
3143 static unsigned int riscv_data_bits(struct target *target)
3144 {
3145         RISCV_INFO(r);
3146         if (r->data_bits)
3147                 return r->data_bits(target);
3148         return riscv_xlen(target);
3149 }
3150
3151 struct target_type riscv_target = {
3152         .name = "riscv",
3153
3154         .target_create = riscv_create_target,
3155         .init_target = riscv_init_target,
3156         .deinit_target = riscv_deinit_target,
3157         .examine = riscv_examine,
3158
3159         /* poll current target status */
3160         .poll = old_or_new_riscv_poll,
3161
3162         .halt = riscv_halt,
3163         .resume = riscv_target_resume,
3164         .step = old_or_new_riscv_step,
3165
3166         .assert_reset = riscv_assert_reset,
3167         .deassert_reset = riscv_deassert_reset,
3168
3169         .read_memory = riscv_read_memory,
3170         .write_memory = riscv_write_memory,
3171         .read_phys_memory = riscv_read_phys_memory,
3172         .write_phys_memory = riscv_write_phys_memory,
3173
3174         .checksum_memory = riscv_checksum_memory,
3175
3176         .mmu = riscv_mmu,
3177         .virt2phys = riscv_virt2phys,
3178
3179         .get_gdb_arch = riscv_get_gdb_arch,
3180         .get_gdb_reg_list = riscv_get_gdb_reg_list,
3181         .get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
3182
3183         .add_breakpoint = riscv_add_breakpoint,
3184         .remove_breakpoint = riscv_remove_breakpoint,
3185
3186         .add_watchpoint = riscv_add_watchpoint,
3187         .remove_watchpoint = riscv_remove_watchpoint,
3188         .hit_watchpoint = riscv_hit_watchpoint,
3189
3190         .arch_state = riscv_arch_state,
3191
3192         .run_algorithm = riscv_run_algorithm,
3193
3194         .commands = riscv_command_handlers,
3195
3196         .address_bits = riscv_xlen_nonconst,
3197         .data_bits = riscv_data_bits
3198 };
3199
3200 /*** RISC-V Interface ***/
3201
3202 void riscv_info_init(struct target *target, struct riscv_info *r)
3203 {
3204         memset(r, 0, sizeof(*r));
3205
3206         r->common_magic = RISCV_COMMON_MAGIC;
3207
3208         r->dtm_version = 1;
3209         r->current_hartid = target->coreid;
3210         r->version_specific = NULL;
3211
3212         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
3213
3214         r->xlen = -1;
3215
3216         r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
3217         r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
3218         r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
3219
3220         r->mem_access_progbuf_warn = true;
3221         r->mem_access_sysbus_warn = true;
3222         r->mem_access_abstract_warn = true;
3223
3224         INIT_LIST_HEAD(&r->expose_csr);
3225         INIT_LIST_HEAD(&r->expose_custom);
3226 }
3227
3228 static int riscv_resume_go_all_harts(struct target *target)
3229 {
3230         RISCV_INFO(r);
3231
3232         LOG_DEBUG("[%s] resuming hart", target_name(target));
3233         if (riscv_select_current_hart(target) != ERROR_OK)
3234                 return ERROR_FAIL;
3235         if (riscv_is_halted(target)) {
3236                 if (r->resume_go(target) != ERROR_OK)
3237                         return ERROR_FAIL;
3238         } else {
3239                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3240                                 target_name(target));
3241         }
3242
3243         riscv_invalidate_register_cache(target);
3244         return ERROR_OK;
3245 }
3246
3247 int riscv_step_rtos_hart(struct target *target)
3248 {
3249         RISCV_INFO(r);
3250         if (riscv_select_current_hart(target) != ERROR_OK)
3251                 return ERROR_FAIL;
3252         LOG_DEBUG("[%s] stepping", target_name(target));
3253
3254         if (!riscv_is_halted(target)) {
3255                 LOG_ERROR("Hart isn't halted before single step!");
3256                 return ERROR_FAIL;
3257         }
3258         riscv_invalidate_register_cache(target);
3259         r->on_step(target);
3260         if (r->step_current_hart(target) != ERROR_OK)
3261                 return ERROR_FAIL;
3262         riscv_invalidate_register_cache(target);
3263         r->on_halt(target);
3264         if (!riscv_is_halted(target)) {
3265                 LOG_ERROR("Hart was not halted after single step!");
3266                 return ERROR_FAIL;
3267         }
3268         return ERROR_OK;
3269 }
3270
3271 bool riscv_supports_extension(struct target *target, char letter)
3272 {
3273         RISCV_INFO(r);
3274         unsigned num;
3275         if (letter >= 'a' && letter <= 'z')
3276                 num = letter - 'a';
3277         else if (letter >= 'A' && letter <= 'Z')
3278                 num = letter - 'A';
3279         else
3280                 return false;
3281         return r->misa & BIT(num);
3282 }
3283
3284 unsigned riscv_xlen(const struct target *target)
3285 {
3286         RISCV_INFO(r);
3287         return r->xlen;
3288 }
3289
3290 int riscv_set_current_hartid(struct target *target, int hartid)
3291 {
3292         RISCV_INFO(r);
3293         if (!r->select_current_hart)
3294                 return ERROR_OK;
3295
3296         int previous_hartid = riscv_current_hartid(target);
3297         r->current_hartid = hartid;
3298         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
3299         if (r->select_current_hart(target) != ERROR_OK)
3300                 return ERROR_FAIL;
3301
3302         return ERROR_OK;
3303 }
3304
3305 void riscv_invalidate_register_cache(struct target *target)
3306 {
3307         LOG_DEBUG("[%d]", target->coreid);
3308         register_cache_invalidate(target->reg_cache);
3309         for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
3310                 struct reg *reg = &target->reg_cache->reg_list[i];
3311                 reg->valid = false;
3312         }
3313 }
3314
3315 int riscv_current_hartid(const struct target *target)
3316 {
3317         RISCV_INFO(r);
3318         return r->current_hartid;
3319 }
3320
3321 int riscv_count_harts(struct target *target)
3322 {
3323         if (!target)
3324                 return 1;
3325         RISCV_INFO(r);
3326         if (!r || !r->hart_count)
3327                 return 1;
3328         return r->hart_count(target);
3329 }
3330
3331 /**
3332  * If write is true:
3333  *   return true iff we are guaranteed that the register will contain exactly
3334  *       the value we just wrote when it's read.
3335  * If write is false:
3336  *   return true iff we are guaranteed that the register will read the same
3337  *       value in the future as the value we just read.
3338  */
3339 static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
3340 {
3341         /* GPRs, FPRs, vector registers are just normal data stores. */
3342         if (regno <= GDB_REGNO_XPR31 ||
3343                         (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
3344                         (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
3345                 return true;
3346
3347         /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3348          * CSRs. */
3349         switch (regno) {
3350                 case GDB_REGNO_DPC:
3351                         return true;
3352
3353                 case GDB_REGNO_VSTART:
3354                 case GDB_REGNO_VXSAT:
3355                 case GDB_REGNO_VXRM:
3356                 case GDB_REGNO_VLENB:
3357                 case GDB_REGNO_VL:
3358                 case GDB_REGNO_VTYPE:
3359                 case GDB_REGNO_MISA:
3360                 case GDB_REGNO_DCSR:
3361                 case GDB_REGNO_DSCRATCH0:
3362                 case GDB_REGNO_MSTATUS:
3363                 case GDB_REGNO_MEPC:
3364                 case GDB_REGNO_MCAUSE:
3365                 case GDB_REGNO_SATP:
3366                         /*
3367                          * WARL registers might not contain the value we just wrote, but
3368                          * these ones won't spontaneously change their value either. *
3369                          */
3370                         return !write;
3371
3372                 case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
3373                 case GDB_REGNO_TDATA1:  /* Changes value when tselect is changed. */
3374                 case GDB_REGNO_TDATA2:  /* Changse value when tselect is changed. */
3375                 default:
3376                         return false;
3377         }
3378 }
3379
3380 /**
3381  * This function is called when the debug user wants to change the value of a
3382  * register. The new value may be cached, and may not be written until the hart
3383  * is resumed. */
3384 int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t value)
3385 {
3386         RISCV_INFO(r);
3387         LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
3388         assert(r->set_register);
3389
3390         keep_alive();
3391
3392         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3393         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
3394                         riscv_supports_extension(target, 'E'))
3395                 return ERROR_OK;
3396
3397         struct reg *reg = &target->reg_cache->reg_list[regid];
3398         buf_set_u64(reg->value, 0, reg->size, value);
3399
3400         int result = r->set_register(target, regid, value);
3401         if (result == ERROR_OK)
3402                 reg->valid = gdb_regno_cacheable(regid, true);
3403         else
3404                 reg->valid = false;
3405         LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
3406                           target_name(target), value, reg->name, reg->valid);
3407         return result;
3408 }
3409
3410 int riscv_get_register(struct target *target, riscv_reg_t *value,
3411                 enum gdb_regno regid)
3412 {
3413         RISCV_INFO(r);
3414
3415         keep_alive();
3416
3417         struct reg *reg = &target->reg_cache->reg_list[regid];
3418         if (!reg->exist) {
3419                 LOG_DEBUG("[%s] %s does not exist.",
3420                                   target_name(target), gdb_regno_name(regid));
3421                 return ERROR_FAIL;
3422         }
3423
3424         if (reg && reg->valid) {
3425                 *value = buf_get_u64(reg->value, 0, reg->size);
3426                 LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
3427                                   gdb_regno_name(regid), *value);
3428                 return ERROR_OK;
3429         }
3430
3431         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3432         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
3433                         riscv_supports_extension(target, 'E')) {
3434                 *value = 0;
3435                 return ERROR_OK;
3436         }
3437
3438         int result = r->get_register(target, value, regid);
3439
3440         if (result == ERROR_OK)
3441                 reg->valid = gdb_regno_cacheable(regid, false);
3442
3443         LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
3444                         gdb_regno_name(regid), *value);
3445         return result;
3446 }
3447
3448 bool riscv_is_halted(struct target *target)
3449 {
3450         RISCV_INFO(r);
3451         assert(r->is_halted);
3452         return r->is_halted(target);
3453 }
3454
3455 enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
3456 {
3457         RISCV_INFO(r);
3458         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
3459                 return RISCV_HALT_ERROR;
3460         if (!riscv_is_halted(target)) {
3461                 LOG_ERROR("Hart is not halted!");
3462                 return RISCV_HALT_UNKNOWN;
3463         }
3464         return r->halt_reason(target);
3465 }
3466
3467 size_t riscv_debug_buffer_size(struct target *target)
3468 {
3469         RISCV_INFO(r);
3470         return r->debug_buffer_size;
3471 }
3472
3473 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
3474 {
3475         RISCV_INFO(r);
3476         r->write_debug_buffer(target, index, insn);
3477         return ERROR_OK;
3478 }
3479
3480 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
3481 {
3482         RISCV_INFO(r);
3483         return r->read_debug_buffer(target, index);
3484 }
3485
3486 int riscv_execute_debug_buffer(struct target *target)
3487 {
3488         RISCV_INFO(r);
3489         return r->execute_debug_buffer(target);
3490 }
3491
3492 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
3493 {
3494         RISCV_INFO(r);
3495         r->fill_dmi_write_u64(target, buf, a, d);
3496 }
3497
3498 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
3499 {
3500         RISCV_INFO(r);
3501         r->fill_dmi_read_u64(target, buf, a);
3502 }
3503
3504 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
3505 {
3506         RISCV_INFO(r);
3507         r->fill_dmi_nop_u64(target, buf);
3508 }
3509
3510 int riscv_dmi_write_u64_bits(struct target *target)
3511 {
3512         RISCV_INFO(r);
3513         return r->dmi_write_u64_bits(target);
3514 }
3515
3516 /**
3517  * Count triggers, and initialize trigger_count for each hart.
3518  * trigger_count is initialized even if this function fails to discover
3519  * something.
3520  * Disable any hardware triggers that have dmode set. We can't have set them
3521  * ourselves. Maybe they're left over from some killed debug session.
3522  * */
3523 int riscv_enumerate_triggers(struct target *target)
3524 {
3525         RISCV_INFO(r);
3526
3527         if (r->triggers_enumerated)
3528                 return ERROR_OK;
3529
3530         r->triggers_enumerated = true;  /* At the very least we tried. */
3531
3532         riscv_reg_t tselect;
3533         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
3534         /* If tselect is not readable, the trigger module is likely not
3535                 * implemented. There are no triggers to enumerate then and no error
3536                 * should be thrown. */
3537         if (result != ERROR_OK) {
3538                 LOG_DEBUG("[%s] Cannot access tselect register. "
3539                                 "Assuming that triggers are not implemented.", target_name(target));
3540                 r->trigger_count = 0;
3541                 return ERROR_OK;
3542         }
3543
3544         for (unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
3545                 r->trigger_count = t;
3546
3547                 /* If we can't write tselect, then this hart does not support triggers. */
3548                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
3549                         break;
3550                 uint64_t tselect_rb;
3551                 result = riscv_get_register(target, &tselect_rb, GDB_REGNO_TSELECT);
3552                 if (result != ERROR_OK)
3553                         return result;
3554                 /* Mask off the top bit, which is used as tdrmode in old
3555                         * implementations. */
3556                 tselect_rb &= ~(1ULL << (riscv_xlen(target) - 1));
3557                 if (tselect_rb != t)
3558                         break;
3559                 uint64_t tdata1;
3560                 result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
3561                 if (result != ERROR_OK)
3562                         return result;
3563
3564                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
3565                 if (type == 0)
3566                         break;
3567                 switch (type) {
3568                         case 1:
3569                                 /* On these older cores we don't support software using
3570                                         * triggers. */
3571                                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3572                                 break;
3573                         case 2:
3574                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3575                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3576                                 break;
3577                         case 6:
3578                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3579                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3580                                 break;
3581                 }
3582         }
3583
3584         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
3585
3586         LOG_INFO("[%s] Found %d triggers", target_name(target), r->trigger_count);
3587
3588         return ERROR_OK;
3589 }
3590
3591 const char *gdb_regno_name(enum gdb_regno regno)
3592 {
3593         static char buf[32];
3594
3595         switch (regno) {
3596                 case GDB_REGNO_ZERO:
3597                         return "zero";
3598                 case GDB_REGNO_RA:
3599                         return "ra";
3600                 case GDB_REGNO_SP:
3601                         return "sp";
3602                 case GDB_REGNO_GP:
3603                         return "gp";
3604                 case GDB_REGNO_TP:
3605                         return "tp";
3606                 case GDB_REGNO_T0:
3607                         return "t0";
3608                 case GDB_REGNO_T1:
3609                         return "t1";
3610                 case GDB_REGNO_T2:
3611                         return "t2";
3612                 case GDB_REGNO_S0:
3613                         return "s0";
3614                 case GDB_REGNO_S1:
3615                         return "s1";
3616                 case GDB_REGNO_A0:
3617                         return "a0";
3618                 case GDB_REGNO_A1:
3619                         return "a1";
3620                 case GDB_REGNO_A2:
3621                         return "a2";
3622                 case GDB_REGNO_A3:
3623                         return "a3";
3624                 case GDB_REGNO_A4:
3625                         return "a4";
3626                 case GDB_REGNO_A5:
3627                         return "a5";
3628                 case GDB_REGNO_A6:
3629                         return "a6";
3630                 case GDB_REGNO_A7:
3631                         return "a7";
3632                 case GDB_REGNO_S2:
3633                         return "s2";
3634                 case GDB_REGNO_S3:
3635                         return "s3";
3636                 case GDB_REGNO_S4:
3637                         return "s4";
3638                 case GDB_REGNO_S5:
3639                         return "s5";
3640                 case GDB_REGNO_S6:
3641                         return "s6";
3642                 case GDB_REGNO_S7:
3643                         return "s7";
3644                 case GDB_REGNO_S8:
3645                         return "s8";
3646                 case GDB_REGNO_S9:
3647                         return "s9";
3648                 case GDB_REGNO_S10:
3649                         return "s10";
3650                 case GDB_REGNO_S11:
3651                         return "s11";
3652                 case GDB_REGNO_T3:
3653                         return "t3";
3654                 case GDB_REGNO_T4:
3655                         return "t4";
3656                 case GDB_REGNO_T5:
3657                         return "t5";
3658                 case GDB_REGNO_T6:
3659                         return "t6";
3660                 case GDB_REGNO_PC:
3661                         return "pc";
3662                 case GDB_REGNO_FPR0:
3663                         return "fpr0";
3664                 case GDB_REGNO_FPR31:
3665                         return "fpr31";
3666                 case GDB_REGNO_CSR0:
3667                         return "csr0";
3668                 case GDB_REGNO_TSELECT:
3669                         return "tselect";
3670                 case GDB_REGNO_TDATA1:
3671                         return "tdata1";
3672                 case GDB_REGNO_TDATA2:
3673                         return "tdata2";
3674                 case GDB_REGNO_MISA:
3675                         return "misa";
3676                 case GDB_REGNO_DPC:
3677                         return "dpc";
3678                 case GDB_REGNO_DCSR:
3679                         return "dcsr";
3680                 case GDB_REGNO_DSCRATCH0:
3681                         return "dscratch0";
3682                 case GDB_REGNO_MSTATUS:
3683                         return "mstatus";
3684                 case GDB_REGNO_MEPC:
3685                         return "mepc";
3686                 case GDB_REGNO_MCAUSE:
3687                         return "mcause";
3688                 case GDB_REGNO_PRIV:
3689                         return "priv";
3690                 case GDB_REGNO_SATP:
3691                         return "satp";
3692                 case GDB_REGNO_VTYPE:
3693                         return "vtype";
3694                 case GDB_REGNO_VL:
3695                         return "vl";
3696                 case GDB_REGNO_V0:
3697                         return "v0";
3698                 case GDB_REGNO_V1:
3699                         return "v1";
3700                 case GDB_REGNO_V2:
3701                         return "v2";
3702                 case GDB_REGNO_V3:
3703                         return "v3";
3704                 case GDB_REGNO_V4:
3705                         return "v4";
3706                 case GDB_REGNO_V5:
3707                         return "v5";
3708                 case GDB_REGNO_V6:
3709                         return "v6";
3710                 case GDB_REGNO_V7:
3711                         return "v7";
3712                 case GDB_REGNO_V8:
3713                         return "v8";
3714                 case GDB_REGNO_V9:
3715                         return "v9";
3716                 case GDB_REGNO_V10:
3717                         return "v10";
3718                 case GDB_REGNO_V11:
3719                         return "v11";
3720                 case GDB_REGNO_V12:
3721                         return "v12";
3722                 case GDB_REGNO_V13:
3723                         return "v13";
3724                 case GDB_REGNO_V14:
3725                         return "v14";
3726                 case GDB_REGNO_V15:
3727                         return "v15";
3728                 case GDB_REGNO_V16:
3729                         return "v16";
3730                 case GDB_REGNO_V17:
3731                         return "v17";
3732                 case GDB_REGNO_V18:
3733                         return "v18";
3734                 case GDB_REGNO_V19:
3735                         return "v19";
3736                 case GDB_REGNO_V20:
3737                         return "v20";
3738                 case GDB_REGNO_V21:
3739                         return "v21";
3740                 case GDB_REGNO_V22:
3741                         return "v22";
3742                 case GDB_REGNO_V23:
3743                         return "v23";
3744                 case GDB_REGNO_V24:
3745                         return "v24";
3746                 case GDB_REGNO_V25:
3747                         return "v25";
3748                 case GDB_REGNO_V26:
3749                         return "v26";
3750                 case GDB_REGNO_V27:
3751                         return "v27";
3752                 case GDB_REGNO_V28:
3753                         return "v28";
3754                 case GDB_REGNO_V29:
3755                         return "v29";
3756                 case GDB_REGNO_V30:
3757                         return "v30";
3758                 case GDB_REGNO_V31:
3759                         return "v31";
3760                 default:
3761                         if (regno <= GDB_REGNO_XPR31)
3762                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
3763                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
3764                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
3765                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
3766                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
3767                         else
3768                                 sprintf(buf, "gdb_regno_%d", regno);
3769                         return buf;
3770         }
3771 }
3772
3773 static int register_get(struct reg *reg)
3774 {
3775         riscv_reg_info_t *reg_info = reg->arch_info;
3776         struct target *target = reg_info->target;
3777         RISCV_INFO(r);
3778
3779         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3780                 if (!r->get_register_buf) {
3781                         LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3782                                         gdb_regno_name(reg->number));
3783                         return ERROR_FAIL;
3784                 }
3785
3786                 if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
3787                         return ERROR_FAIL;
3788         } else {
3789                 uint64_t value;
3790                 int result = riscv_get_register(target, &value, reg->number);
3791                 if (result != ERROR_OK)
3792                         return result;
3793                 buf_set_u64(reg->value, 0, reg->size, value);
3794         }
3795         reg->valid = gdb_regno_cacheable(reg->number, false);
3796         char *str = buf_to_hex_str(reg->value, reg->size);
3797         LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
3798                         str, reg->name, reg->valid);
3799         free(str);
3800         return ERROR_OK;
3801 }
3802
3803 static int register_set(struct reg *reg, uint8_t *buf)
3804 {
3805         riscv_reg_info_t *reg_info = reg->arch_info;
3806         struct target *target = reg_info->target;
3807         RISCV_INFO(r);
3808
3809         char *str = buf_to_hex_str(buf, reg->size);
3810         LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
3811                         str, reg->name, reg->valid);
3812         free(str);
3813
3814         /* Exit early for writing x0, which on the hardware would be ignored, and we
3815          * don't want to update our cache. */
3816         if (reg->number == GDB_REGNO_ZERO)
3817                 return ERROR_OK;
3818
3819         memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
3820         reg->valid = gdb_regno_cacheable(reg->number, true);
3821
3822         if (reg->number == GDB_REGNO_TDATA1 ||
3823                         reg->number == GDB_REGNO_TDATA2) {
3824                 r->manual_hwbp_set = true;
3825                 /* When enumerating triggers, we clear any triggers with DMODE set,
3826                  * assuming they were left over from a previous debug session. So make
3827                  * sure that is done before a user might be setting their own triggers.
3828                  */
3829                 if (riscv_enumerate_triggers(target) != ERROR_OK)
3830                         return ERROR_FAIL;
3831         }
3832
3833         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3834                 if (!r->set_register_buf) {
3835                         LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3836                                         gdb_regno_name(reg->number));
3837                         return ERROR_FAIL;
3838                 }
3839
3840                 if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
3841                         return ERROR_FAIL;
3842         } else {
3843                 uint64_t value = buf_get_u64(buf, 0, reg->size);
3844                 if (riscv_set_register(target, reg->number, value) != ERROR_OK)
3845                         return ERROR_FAIL;
3846         }
3847
3848         return ERROR_OK;
3849 }
3850
3851 static struct reg_arch_type riscv_reg_arch_type = {
3852         .get = register_get,
3853         .set = register_set
3854 };
3855
3856 struct csr_info {
3857         unsigned number;
3858         const char *name;
3859 };
3860
3861 static int cmp_csr_info(const void *p1, const void *p2)
3862 {
3863         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
3864 }
3865
3866 int riscv_init_registers(struct target *target)
3867 {
3868         RISCV_INFO(info);
3869
3870         riscv_free_registers(target);
3871
3872         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
3873         if (!target->reg_cache)
3874                 return ERROR_FAIL;
3875         target->reg_cache->name = "RISC-V Registers";
3876         target->reg_cache->num_regs = GDB_REGNO_COUNT;
3877
3878         if (!list_empty(&info->expose_custom)) {
3879                 range_list_t *entry;
3880                 list_for_each_entry(entry, &info->expose_custom, list)
3881                         target->reg_cache->num_regs += entry->high - entry->low + 1;
3882         }
3883
3884         LOG_DEBUG("create register cache for %d registers",
3885                         target->reg_cache->num_regs);
3886
3887         target->reg_cache->reg_list =
3888                 calloc(target->reg_cache->num_regs, sizeof(struct reg));
3889         if (!target->reg_cache->reg_list)
3890                 return ERROR_FAIL;
3891
3892         const unsigned int max_reg_name_len = 12;
3893         free(info->reg_names);
3894         info->reg_names =
3895                 calloc(target->reg_cache->num_regs, max_reg_name_len);
3896         if (!info->reg_names)
3897                 return ERROR_FAIL;
3898         char *reg_name = info->reg_names;
3899
3900         static struct reg_feature feature_cpu = {
3901                 .name = "org.gnu.gdb.riscv.cpu"
3902         };
3903         static struct reg_feature feature_fpu = {
3904                 .name = "org.gnu.gdb.riscv.fpu"
3905         };
3906         static struct reg_feature feature_csr = {
3907                 .name = "org.gnu.gdb.riscv.csr"
3908         };
3909         static struct reg_feature feature_vector = {
3910                 .name = "org.gnu.gdb.riscv.vector"
3911         };
3912         static struct reg_feature feature_virtual = {
3913                 .name = "org.gnu.gdb.riscv.virtual"
3914         };
3915         static struct reg_feature feature_custom = {
3916                 .name = "org.gnu.gdb.riscv.custom"
3917         };
3918
3919         /* These types are built into gdb. */
3920         static struct reg_data_type type_ieee_single = { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" };
3921         static struct reg_data_type type_ieee_double = { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" };
3922         static struct reg_data_type_union_field single_double_fields[] = {
3923                 {"float", &type_ieee_single, single_double_fields + 1},
3924                 {"double", &type_ieee_double, NULL},
3925         };
3926         static struct reg_data_type_union single_double_union = {
3927                 .fields = single_double_fields
3928         };
3929         static struct reg_data_type type_ieee_single_double = {
3930                 .type = REG_TYPE_ARCH_DEFINED,
3931                 .id = "FPU_FD",
3932                 .type_class = REG_TYPE_CLASS_UNION,
3933                 .reg_type_union = &single_double_union
3934         };
3935         static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" };
3936         static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" };
3937         static struct reg_data_type type_uint32 = { .type = REG_TYPE_UINT32, .id = "uint32" };
3938         static struct reg_data_type type_uint64 = { .type = REG_TYPE_UINT64, .id = "uint64" };
3939         static struct reg_data_type type_uint128 = { .type = REG_TYPE_UINT128, .id = "uint128" };
3940
3941         /* This is roughly the XML we want:
3942          * <vector id="bytes" type="uint8" count="16"/>
3943          * <vector id="shorts" type="uint16" count="8"/>
3944          * <vector id="words" type="uint32" count="4"/>
3945          * <vector id="longs" type="uint64" count="2"/>
3946          * <vector id="quads" type="uint128" count="1"/>
3947          * <union id="riscv_vector_type">
3948          *   <field name="b" type="bytes"/>
3949          *   <field name="s" type="shorts"/>
3950          *   <field name="w" type="words"/>
3951          *   <field name="l" type="longs"/>
3952          *   <field name="q" type="quads"/>
3953          * </union>
3954          */
3955
3956         info->vector_uint8.type = &type_uint8;
3957         info->vector_uint8.count = info->vlenb;
3958         info->type_uint8_vector.type = REG_TYPE_ARCH_DEFINED;
3959         info->type_uint8_vector.id = "bytes";
3960         info->type_uint8_vector.type_class = REG_TYPE_CLASS_VECTOR;
3961         info->type_uint8_vector.reg_type_vector = &info->vector_uint8;
3962
3963         info->vector_uint16.type = &type_uint16;
3964         info->vector_uint16.count = info->vlenb / 2;
3965         info->type_uint16_vector.type = REG_TYPE_ARCH_DEFINED;
3966         info->type_uint16_vector.id = "shorts";
3967         info->type_uint16_vector.type_class = REG_TYPE_CLASS_VECTOR;
3968         info->type_uint16_vector.reg_type_vector = &info->vector_uint16;
3969
3970         info->vector_uint32.type = &type_uint32;
3971         info->vector_uint32.count = info->vlenb / 4;
3972         info->type_uint32_vector.type = REG_TYPE_ARCH_DEFINED;
3973         info->type_uint32_vector.id = "words";
3974         info->type_uint32_vector.type_class = REG_TYPE_CLASS_VECTOR;
3975         info->type_uint32_vector.reg_type_vector = &info->vector_uint32;
3976
3977         info->vector_uint64.type = &type_uint64;
3978         info->vector_uint64.count = info->vlenb / 8;
3979         info->type_uint64_vector.type = REG_TYPE_ARCH_DEFINED;
3980         info->type_uint64_vector.id = "longs";
3981         info->type_uint64_vector.type_class = REG_TYPE_CLASS_VECTOR;
3982         info->type_uint64_vector.reg_type_vector = &info->vector_uint64;
3983
3984         info->vector_uint128.type = &type_uint128;
3985         info->vector_uint128.count = info->vlenb / 16;
3986         info->type_uint128_vector.type = REG_TYPE_ARCH_DEFINED;
3987         info->type_uint128_vector.id = "quads";
3988         info->type_uint128_vector.type_class = REG_TYPE_CLASS_VECTOR;
3989         info->type_uint128_vector.reg_type_vector = &info->vector_uint128;
3990
3991         info->vector_fields[0].name = "b";
3992         info->vector_fields[0].type = &info->type_uint8_vector;
3993         if (info->vlenb >= 2) {
3994                 info->vector_fields[0].next = info->vector_fields + 1;
3995                 info->vector_fields[1].name = "s";
3996                 info->vector_fields[1].type = &info->type_uint16_vector;
3997         } else {
3998                 info->vector_fields[0].next = NULL;
3999         }
4000         if (info->vlenb >= 4) {
4001                 info->vector_fields[1].next = info->vector_fields + 2;
4002                 info->vector_fields[2].name = "w";
4003                 info->vector_fields[2].type = &info->type_uint32_vector;
4004         } else {
4005                 info->vector_fields[1].next = NULL;
4006         }
4007         if (info->vlenb >= 8) {
4008                 info->vector_fields[2].next = info->vector_fields + 3;
4009                 info->vector_fields[3].name = "l";
4010                 info->vector_fields[3].type = &info->type_uint64_vector;
4011         } else {
4012                 info->vector_fields[2].next = NULL;
4013         }
4014         if (info->vlenb >= 16) {
4015                 info->vector_fields[3].next = info->vector_fields + 4;
4016                 info->vector_fields[4].name = "q";
4017                 info->vector_fields[4].type = &info->type_uint128_vector;
4018         } else {
4019                 info->vector_fields[3].next = NULL;
4020         }
4021         info->vector_fields[4].next = NULL;
4022
4023         info->vector_union.fields = info->vector_fields;
4024
4025         info->type_vector.type = REG_TYPE_ARCH_DEFINED;
4026         info->type_vector.id = "riscv_vector";
4027         info->type_vector.type_class = REG_TYPE_CLASS_UNION;
4028         info->type_vector.reg_type_union = &info->vector_union;
4029
4030         struct csr_info csr_info[] = {
4031 #define DECLARE_CSR(name, number) { number, #name },
4032 #include "encoding.h"
4033 #undef DECLARE_CSR
4034         };
4035         /* encoding.h does not contain the registers in sorted order. */
4036         qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
4037         unsigned csr_info_index = 0;
4038
4039         int custom_within_range = 0;
4040
4041         riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
4042         if (!shared_reg_info)
4043                 return ERROR_FAIL;
4044         shared_reg_info->target = target;
4045
4046         /* When gdb requests register N, gdb_get_register_packet() assumes that this
4047          * is register at index N in reg_list. So if there are certain registers
4048          * that don't exist, we need to leave holes in the list (or renumber, but
4049          * it would be nice not to have yet another set of numbers to translate
4050          * between). */
4051         for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
4052                 struct reg *r = &target->reg_cache->reg_list[number];
4053                 r->dirty = false;
4054                 r->valid = false;
4055                 r->exist = true;
4056                 r->type = &riscv_reg_arch_type;
4057                 r->arch_info = shared_reg_info;
4058                 r->number = number;
4059                 r->size = riscv_xlen(target);
4060                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
4061                  * target is in theory allowed to change XLEN on us. But I expect a lot
4062                  * of other things to break in that case as well. */
4063                 if (number <= GDB_REGNO_XPR31) {
4064                         r->exist = number <= GDB_REGNO_XPR15 ||
4065                                 !riscv_supports_extension(target, 'E');
4066                         /* TODO: For now we fake that all GPRs exist because otherwise gdb
4067                          * doesn't work. */
4068                         r->exist = true;
4069                         r->caller_save = true;
4070                         switch (number) {
4071                                 case GDB_REGNO_ZERO:
4072                                         r->name = "zero";
4073                                         break;
4074                                 case GDB_REGNO_RA:
4075                                         r->name = "ra";
4076                                         break;
4077                                 case GDB_REGNO_SP:
4078                                         r->name = "sp";
4079                                         break;
4080                                 case GDB_REGNO_GP:
4081                                         r->name = "gp";
4082                                         break;
4083                                 case GDB_REGNO_TP:
4084                                         r->name = "tp";
4085                                         break;
4086                                 case GDB_REGNO_T0:
4087                                         r->name = "t0";
4088                                         break;
4089                                 case GDB_REGNO_T1:
4090                                         r->name = "t1";
4091                                         break;
4092                                 case GDB_REGNO_T2:
4093                                         r->name = "t2";
4094                                         break;
4095                                 case GDB_REGNO_FP:
4096                                         r->name = "fp";
4097                                         break;
4098                                 case GDB_REGNO_S1:
4099                                         r->name = "s1";
4100                                         break;
4101                                 case GDB_REGNO_A0:
4102                                         r->name = "a0";
4103                                         break;
4104                                 case GDB_REGNO_A1:
4105                                         r->name = "a1";
4106                                         break;
4107                                 case GDB_REGNO_A2:
4108                                         r->name = "a2";
4109                                         break;
4110                                 case GDB_REGNO_A3:
4111                                         r->name = "a3";
4112                                         break;
4113                                 case GDB_REGNO_A4:
4114                                         r->name = "a4";
4115                                         break;
4116                                 case GDB_REGNO_A5:
4117                                         r->name = "a5";
4118                                         break;
4119                                 case GDB_REGNO_A6:
4120                                         r->name = "a6";
4121                                         break;
4122                                 case GDB_REGNO_A7:
4123                                         r->name = "a7";
4124                                         break;
4125                                 case GDB_REGNO_S2:
4126                                         r->name = "s2";
4127                                         break;
4128                                 case GDB_REGNO_S3:
4129                                         r->name = "s3";
4130                                         break;
4131                                 case GDB_REGNO_S4:
4132                                         r->name = "s4";
4133                                         break;
4134                                 case GDB_REGNO_S5:
4135                                         r->name = "s5";
4136                                         break;
4137                                 case GDB_REGNO_S6:
4138                                         r->name = "s6";
4139                                         break;
4140                                 case GDB_REGNO_S7:
4141                                         r->name = "s7";
4142                                         break;
4143                                 case GDB_REGNO_S8:
4144                                         r->name = "s8";
4145                                         break;
4146                                 case GDB_REGNO_S9:
4147                                         r->name = "s9";
4148                                         break;
4149                                 case GDB_REGNO_S10:
4150                                         r->name = "s10";
4151                                         break;
4152                                 case GDB_REGNO_S11:
4153                                         r->name = "s11";
4154                                         break;
4155                                 case GDB_REGNO_T3:
4156                                         r->name = "t3";
4157                                         break;
4158                                 case GDB_REGNO_T4:
4159                                         r->name = "t4";
4160                                         break;
4161                                 case GDB_REGNO_T5:
4162                                         r->name = "t5";
4163                                         break;
4164                                 case GDB_REGNO_T6:
4165                                         r->name = "t6";
4166                                         break;
4167                         }
4168                         r->group = "general";
4169                         r->feature = &feature_cpu;
4170                 } else if (number == GDB_REGNO_PC) {
4171                         r->caller_save = true;
4172                         sprintf(reg_name, "pc");
4173                         r->group = "general";
4174                         r->feature = &feature_cpu;
4175                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
4176                         r->caller_save = true;
4177                         if (riscv_supports_extension(target, 'D')) {
4178                                 r->size = 64;
4179                                 if (riscv_supports_extension(target, 'F'))
4180                                         r->reg_data_type = &type_ieee_single_double;
4181                                 else
4182                                         r->reg_data_type = &type_ieee_double;
4183                         } else if (riscv_supports_extension(target, 'F')) {
4184                                 r->reg_data_type = &type_ieee_single;
4185                                 r->size = 32;
4186                         } else {
4187                                 r->exist = false;
4188                         }
4189                         switch (number) {
4190                                 case GDB_REGNO_FT0:
4191                                         r->name = "ft0";
4192                                         break;
4193                                 case GDB_REGNO_FT1:
4194                                         r->name = "ft1";
4195                                         break;
4196                                 case GDB_REGNO_FT2:
4197                                         r->name = "ft2";
4198                                         break;
4199                                 case GDB_REGNO_FT3:
4200                                         r->name = "ft3";
4201                                         break;
4202                                 case GDB_REGNO_FT4:
4203                                         r->name = "ft4";
4204                                         break;
4205                                 case GDB_REGNO_FT5:
4206                                         r->name = "ft5";
4207                                         break;
4208                                 case GDB_REGNO_FT6:
4209                                         r->name = "ft6";
4210                                         break;
4211                                 case GDB_REGNO_FT7:
4212                                         r->name = "ft7";
4213                                         break;
4214                                 case GDB_REGNO_FS0:
4215                                         r->name = "fs0";
4216                                         break;
4217                                 case GDB_REGNO_FS1:
4218                                         r->name = "fs1";
4219                                         break;
4220                                 case GDB_REGNO_FA0:
4221                                         r->name = "fa0";
4222                                         break;
4223                                 case GDB_REGNO_FA1:
4224                                         r->name = "fa1";
4225                                         break;
4226                                 case GDB_REGNO_FA2:
4227                                         r->name = "fa2";
4228                                         break;
4229                                 case GDB_REGNO_FA3:
4230                                         r->name = "fa3";
4231                                         break;
4232                                 case GDB_REGNO_FA4:
4233                                         r->name = "fa4";
4234                                         break;
4235                                 case GDB_REGNO_FA5:
4236                                         r->name = "fa5";
4237                                         break;
4238                                 case GDB_REGNO_FA6:
4239                                         r->name = "fa6";
4240                                         break;
4241                                 case GDB_REGNO_FA7:
4242                                         r->name = "fa7";
4243                                         break;
4244                                 case GDB_REGNO_FS2:
4245                                         r->name = "fs2";
4246                                         break;
4247                                 case GDB_REGNO_FS3:
4248                                         r->name = "fs3";
4249                                         break;
4250                                 case GDB_REGNO_FS4:
4251                                         r->name = "fs4";
4252                                         break;
4253                                 case GDB_REGNO_FS5:
4254                                         r->name = "fs5";
4255                                         break;
4256                                 case GDB_REGNO_FS6:
4257                                         r->name = "fs6";
4258                                         break;
4259                                 case GDB_REGNO_FS7:
4260                                         r->name = "fs7";
4261                                         break;
4262                                 case GDB_REGNO_FS8:
4263                                         r->name = "fs8";
4264                                         break;
4265                                 case GDB_REGNO_FS9:
4266                                         r->name = "fs9";
4267                                         break;
4268                                 case GDB_REGNO_FS10:
4269                                         r->name = "fs10";
4270                                         break;
4271                                 case GDB_REGNO_FS11:
4272                                         r->name = "fs11";
4273                                         break;
4274                                 case GDB_REGNO_FT8:
4275                                         r->name = "ft8";
4276                                         break;
4277                                 case GDB_REGNO_FT9:
4278                                         r->name = "ft9";
4279                                         break;
4280                                 case GDB_REGNO_FT10:
4281                                         r->name = "ft10";
4282                                         break;
4283                                 case GDB_REGNO_FT11:
4284                                         r->name = "ft11";
4285                                         break;
4286                         }
4287                         r->group = "float";
4288                         r->feature = &feature_fpu;
4289                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
4290                         r->group = "csr";
4291                         r->feature = &feature_csr;
4292                         unsigned csr_number = number - GDB_REGNO_CSR0;
4293
4294                         while (csr_info[csr_info_index].number < csr_number &&
4295                                         csr_info_index < ARRAY_SIZE(csr_info) - 1) {
4296                                 csr_info_index++;
4297                         }
4298                         if (csr_info[csr_info_index].number == csr_number) {
4299                                 r->name = csr_info[csr_info_index].name;
4300                         } else {
4301                                 sprintf(reg_name, "csr%d", csr_number);
4302                                 /* Assume unnamed registers don't exist, unless we have some
4303                                  * configuration that tells us otherwise. That's important
4304                                  * because eg. Eclipse crashes if a target has too many
4305                                  * registers, and apparently has no way of only showing a
4306                                  * subset of registers in any case. */
4307                                 r->exist = false;
4308                         }
4309
4310                         switch (csr_number) {
4311                                 case CSR_FFLAGS:
4312                                 case CSR_FRM:
4313                                 case CSR_FCSR:
4314                                         r->exist = riscv_supports_extension(target, 'F');
4315                                         r->group = "float";
4316                                         r->feature = &feature_fpu;
4317                                         break;
4318                                 case CSR_SSTATUS:
4319                                 case CSR_STVEC:
4320                                 case CSR_SIP:
4321                                 case CSR_SIE:
4322                                 case CSR_SCOUNTEREN:
4323                                 case CSR_SSCRATCH:
4324                                 case CSR_SEPC:
4325                                 case CSR_SCAUSE:
4326                                 case CSR_STVAL:
4327                                 case CSR_SATP:
4328                                         r->exist = riscv_supports_extension(target, 'S');
4329                                         break;
4330                                 case CSR_MEDELEG:
4331                                 case CSR_MIDELEG:
4332                                         /* "In systems with only M-mode, or with both M-mode and
4333                                          * U-mode but without U-mode trap support, the medeleg and
4334                                          * mideleg registers should not exist." */
4335                                         r->exist = riscv_supports_extension(target, 'S') ||
4336                                                 riscv_supports_extension(target, 'N');
4337                                         break;
4338
4339                                 case CSR_PMPCFG1:
4340                                 case CSR_PMPCFG3:
4341                                 case CSR_CYCLEH:
4342                                 case CSR_TIMEH:
4343                                 case CSR_INSTRETH:
4344                                 case CSR_HPMCOUNTER3H:
4345                                 case CSR_HPMCOUNTER4H:
4346                                 case CSR_HPMCOUNTER5H:
4347                                 case CSR_HPMCOUNTER6H:
4348                                 case CSR_HPMCOUNTER7H:
4349                                 case CSR_HPMCOUNTER8H:
4350                                 case CSR_HPMCOUNTER9H:
4351                                 case CSR_HPMCOUNTER10H:
4352                                 case CSR_HPMCOUNTER11H:
4353                                 case CSR_HPMCOUNTER12H:
4354                                 case CSR_HPMCOUNTER13H:
4355                                 case CSR_HPMCOUNTER14H:
4356                                 case CSR_HPMCOUNTER15H:
4357                                 case CSR_HPMCOUNTER16H:
4358                                 case CSR_HPMCOUNTER17H:
4359                                 case CSR_HPMCOUNTER18H:
4360                                 case CSR_HPMCOUNTER19H:
4361                                 case CSR_HPMCOUNTER20H:
4362                                 case CSR_HPMCOUNTER21H:
4363                                 case CSR_HPMCOUNTER22H:
4364                                 case CSR_HPMCOUNTER23H:
4365                                 case CSR_HPMCOUNTER24H:
4366                                 case CSR_HPMCOUNTER25H:
4367                                 case CSR_HPMCOUNTER26H:
4368                                 case CSR_HPMCOUNTER27H:
4369                                 case CSR_HPMCOUNTER28H:
4370                                 case CSR_HPMCOUNTER29H:
4371                                 case CSR_HPMCOUNTER30H:
4372                                 case CSR_HPMCOUNTER31H:
4373                                 case CSR_MCYCLEH:
4374                                 case CSR_MINSTRETH:
4375                                 case CSR_MHPMCOUNTER3H:
4376                                 case CSR_MHPMCOUNTER4H:
4377                                 case CSR_MHPMCOUNTER5H:
4378                                 case CSR_MHPMCOUNTER6H:
4379                                 case CSR_MHPMCOUNTER7H:
4380                                 case CSR_MHPMCOUNTER8H:
4381                                 case CSR_MHPMCOUNTER9H:
4382                                 case CSR_MHPMCOUNTER10H:
4383                                 case CSR_MHPMCOUNTER11H:
4384                                 case CSR_MHPMCOUNTER12H:
4385                                 case CSR_MHPMCOUNTER13H:
4386                                 case CSR_MHPMCOUNTER14H:
4387                                 case CSR_MHPMCOUNTER15H:
4388                                 case CSR_MHPMCOUNTER16H:
4389                                 case CSR_MHPMCOUNTER17H:
4390                                 case CSR_MHPMCOUNTER18H:
4391                                 case CSR_MHPMCOUNTER19H:
4392                                 case CSR_MHPMCOUNTER20H:
4393                                 case CSR_MHPMCOUNTER21H:
4394                                 case CSR_MHPMCOUNTER22H:
4395                                 case CSR_MHPMCOUNTER23H:
4396                                 case CSR_MHPMCOUNTER24H:
4397                                 case CSR_MHPMCOUNTER25H:
4398                                 case CSR_MHPMCOUNTER26H:
4399                                 case CSR_MHPMCOUNTER27H:
4400                                 case CSR_MHPMCOUNTER28H:
4401                                 case CSR_MHPMCOUNTER29H:
4402                                 case CSR_MHPMCOUNTER30H:
4403                                 case CSR_MHPMCOUNTER31H:
4404                                         r->exist = riscv_xlen(target) == 32;
4405                                         break;
4406
4407                                 case CSR_VSTART:
4408                                 case CSR_VXSAT:
4409                                 case CSR_VXRM:
4410                                 case CSR_VL:
4411                                 case CSR_VTYPE:
4412                                 case CSR_VLENB:
4413                                         r->exist = riscv_supports_extension(target, 'V');
4414                                         break;
4415                         }
4416
4417                         if (!r->exist && !list_empty(&info->expose_csr)) {
4418                                 range_list_t *entry;
4419                                 list_for_each_entry(entry, &info->expose_csr, list)
4420                                         if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
4421                                                 if (entry->name) {
4422                                                         *reg_name = 0;
4423                                                         r->name = entry->name;
4424                                                 }
4425
4426                                                 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4427                                                                 csr_number, entry->name ? entry->name : reg_name);
4428
4429                                                 r->exist = true;
4430                                                 break;
4431                                         }
4432                         }
4433
4434                 } else if (number == GDB_REGNO_PRIV) {
4435                         sprintf(reg_name, "priv");
4436                         r->group = "general";
4437                         r->feature = &feature_virtual;
4438                         r->size = 8;
4439
4440                 } else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
4441                         r->caller_save = false;
4442                         r->exist = riscv_supports_extension(target, 'V') && info->vlenb;
4443                         r->size = info->vlenb * 8;
4444                         sprintf(reg_name, "v%d", number - GDB_REGNO_V0);
4445                         r->group = "vector";
4446                         r->feature = &feature_vector;
4447                         r->reg_data_type = &info->type_vector;
4448
4449                 } else if (number >= GDB_REGNO_COUNT) {
4450                         /* Custom registers. */
4451                         assert(!list_empty(&info->expose_custom));
4452
4453                         range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
4454
4455                         unsigned custom_number = range->low + custom_within_range;
4456
4457                         r->group = "custom";
4458                         r->feature = &feature_custom;
4459                         r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
4460                         if (!r->arch_info)
4461                                 return ERROR_FAIL;
4462                         ((riscv_reg_info_t *) r->arch_info)->target = target;
4463                         ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
4464                         sprintf(reg_name, "custom%d", custom_number);
4465
4466                         if (range->name) {
4467                                 *reg_name = 0;
4468                                 r->name = range->name;
4469                         }
4470
4471                         LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4472                                         number, range->name ? range->name : reg_name);
4473
4474                         custom_within_range++;
4475                         if (custom_within_range > range->high - range->low) {
4476                                 custom_within_range = 0;
4477                                 list_rotate_left(&info->expose_custom);
4478                         }
4479                 }
4480
4481                 if (reg_name[0]) {
4482                         r->name = reg_name;
4483                         reg_name += strlen(reg_name) + 1;
4484                         assert(reg_name < info->reg_names + target->reg_cache->num_regs *
4485                                         max_reg_name_len);
4486                 }
4487                 r->value = calloc(1, DIV_ROUND_UP(r->size, 8));
4488         }
4489
4490         return ERROR_OK;
4491 }
4492
4493
4494 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
4495                                         riscv_bscan_tunneled_scan_context_t *ctxt)
4496 {
4497         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
4498
4499         memset(ctxt->tunneled_dr, 0, sizeof(ctxt->tunneled_dr));
4500         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
4501                 ctxt->tunneled_dr[3].num_bits = 1;
4502                 ctxt->tunneled_dr[3].out_value = bscan_one;
4503                 ctxt->tunneled_dr[2].num_bits = 7;
4504                 ctxt->tunneled_dr_width = field->num_bits;
4505                 ctxt->tunneled_dr[2].out_value = &ctxt->tunneled_dr_width;
4506                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4507                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4508
4509                 ctxt->tunneled_dr[1].num_bits = field->num_bits + 1;
4510                 ctxt->tunneled_dr[1].out_value = field->out_value;
4511                 ctxt->tunneled_dr[1].in_value = field->in_value;
4512
4513                 ctxt->tunneled_dr[0].num_bits = 3;
4514                 ctxt->tunneled_dr[0].out_value = bscan_zero;
4515         } else {
4516                 /* BSCAN_TUNNEL_NESTED_TAP */
4517                 ctxt->tunneled_dr[0].num_bits = 1;
4518                 ctxt->tunneled_dr[0].out_value = bscan_one;
4519                 ctxt->tunneled_dr[1].num_bits = 7;
4520                 ctxt->tunneled_dr_width = field->num_bits;
4521                 ctxt->tunneled_dr[1].out_value = &ctxt->tunneled_dr_width;
4522                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4523                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4524                 ctxt->tunneled_dr[2].num_bits = field->num_bits + 1;
4525                 ctxt->tunneled_dr[2].out_value = field->out_value;
4526                 ctxt->tunneled_dr[2].in_value = field->in_value;
4527                 ctxt->tunneled_dr[3].num_bits = 3;
4528                 ctxt->tunneled_dr[3].out_value = bscan_zero;
4529         }
4530         jtag_add_dr_scan(target->tap, ARRAY_SIZE(ctxt->tunneled_dr), ctxt->tunneled_dr, TAP_IDLE);
4531 }