git.gag.com Git - fw/openocd/blob - src/target/riscv/riscv.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <assert.h>
   4 #include <stdlib.h>
   5 #include <time.h>
   6
   7 #ifdef HAVE_CONFIG_H
   8 #include "config.h"
   9 #endif
  10
  11 #include <helper/log.h>
  12 #include <helper/time_support.h>
  13 #include "target/target.h"
  14 #include "target/algorithm.h"
  15 #include "target/target_type.h"
  16 #include <target/smp.h>
  17 #include "jtag/jtag.h"
  18 #include "target/register.h"
  19 #include "target/breakpoints.h"
  20 #include "riscv.h"
  21 #include "gdb_regs.h"
  22 #include "rtos/rtos.h"
  23 #include "debug_defines.h"
  24 #include <helper/bits.h>
  25
  26 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
  27 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
  28
  29 /* Constants for legacy SiFive hardware breakpoints. */
  30 #define CSR_BPCONTROL_X                 (1<<0)
  31 #define CSR_BPCONTROL_W                 (1<<1)
  32 #define CSR_BPCONTROL_R                 (1<<2)
  33 #define CSR_BPCONTROL_U                 (1<<3)
  34 #define CSR_BPCONTROL_S                 (1<<4)
  35 #define CSR_BPCONTROL_H                 (1<<5)
  36 #define CSR_BPCONTROL_M                 (1<<6)
  37 #define CSR_BPCONTROL_BPMATCH   (0xf<<7)
  38 #define CSR_BPCONTROL_BPACTION  (0xff<<11)
  39
  40 #define DEBUG_ROM_START         0x800
  41 #define DEBUG_ROM_RESUME        (DEBUG_ROM_START + 4)
  42 #define DEBUG_ROM_EXCEPTION     (DEBUG_ROM_START + 8)
  43 #define DEBUG_RAM_START         0x400
  44
  45 #define SETHALTNOT                              0x10c
  46
  47 /*** JTAG registers. ***/
  48
  49 #define DTMCONTROL                                      0x10
  50 #define DTMCONTROL_DBUS_RESET           (1<<16)
  51 #define DTMCONTROL_IDLE                         (7<<10)
  52 #define DTMCONTROL_ADDRBITS                     (0xf<<4)
  53 #define DTMCONTROL_VERSION                      (0xf)
  54
  55 #define DBUS                                            0x11
  56 #define DBUS_OP_START                           0
  57 #define DBUS_OP_SIZE                            2
  58 typedef enum {
  59         DBUS_OP_NOP = 0,
  60         DBUS_OP_READ = 1,
  61         DBUS_OP_WRITE = 2
  62 } dbus_op_t;
  63 typedef enum {
  64         DBUS_STATUS_SUCCESS = 0,
  65         DBUS_STATUS_FAILED = 2,
  66         DBUS_STATUS_BUSY = 3
  67 } dbus_status_t;
  68 #define DBUS_DATA_START                         2
  69 #define DBUS_DATA_SIZE                          34
  70 #define DBUS_ADDRESS_START                      36
  71
  72 typedef enum slot {
  73         SLOT0,
  74         SLOT1,
  75         SLOT_LAST,
  76 } slot_t;
  77
  78 /*** Debug Bus registers. ***/
  79
  80 #define DMCONTROL                               0x10
  81 #define DMCONTROL_INTERRUPT             (((uint64_t)1)<<33)
  82 #define DMCONTROL_HALTNOT               (((uint64_t)1)<<32)
  83 #define DMCONTROL_BUSERROR              (7<<19)
  84 #define DMCONTROL_SERIAL                (3<<16)
  85 #define DMCONTROL_AUTOINCREMENT (1<<15)
  86 #define DMCONTROL_ACCESS                (7<<12)
  87 #define DMCONTROL_HARTID                (0x3ff<<2)
  88 #define DMCONTROL_NDRESET               (1<<1)
  89 #define DMCONTROL_FULLRESET             1
  90
  91 #define DMINFO                                  0x11
  92 #define DMINFO_ABUSSIZE                 (0x7fU<<25)
  93 #define DMINFO_SERIALCOUNT              (0xf<<21)
  94 #define DMINFO_ACCESS128                (1<<20)
  95 #define DMINFO_ACCESS64                 (1<<19)
  96 #define DMINFO_ACCESS32                 (1<<18)
  97 #define DMINFO_ACCESS16                 (1<<17)
  98 #define DMINFO_ACCESS8                  (1<<16)
  99 #define DMINFO_DRAMSIZE                 (0x3f<<10)
 100 #define DMINFO_AUTHENTICATED    (1<<5)
 101 #define DMINFO_AUTHBUSY                 (1<<4)
 102 #define DMINFO_AUTHTYPE                 (3<<2)
 103 #define DMINFO_VERSION                  3
 104
 105 /*** Info about the core being debugged. ***/
 106
 107 #define DBUS_ADDRESS_UNKNOWN    0xffff
 108
 109 #define MAX_HWBPS                       16
 110 #define DRAM_CACHE_SIZE         16
 111
 112 static uint8_t ir_dtmcontrol[4] = {DTMCONTROL};
 113 struct scan_field select_dtmcontrol = {
 114         .in_value = NULL,
 115         .out_value = ir_dtmcontrol
 116 };
 117 static uint8_t ir_dbus[4] = {DBUS};
 118 struct scan_field select_dbus = {
 119         .in_value = NULL,
 120         .out_value = ir_dbus
 121 };
 122 static uint8_t ir_idcode[4] = {0x1};
 123 struct scan_field select_idcode = {
 124         .in_value = NULL,
 125         .out_value = ir_idcode
 126 };
 127
 128 static bscan_tunnel_type_t bscan_tunnel_type;
 129 int bscan_tunnel_ir_width; /* if zero, then tunneling is not present/active */
 130
 131 static const uint8_t bscan_zero[4] = {0};
 132 static const uint8_t bscan_one[4] = {1};
 133
 134 static uint8_t ir_user4[4];
 135 static struct scan_field select_user4 = {
 136         .in_value = NULL,
 137         .out_value = ir_user4
 138 };
 139
 140
 141 static uint8_t bscan_tunneled_ir_width[4] = {5};  /* overridden by assignment in riscv_init_target */
 142 static struct scan_field _bscan_tunnel_data_register_select_dmi[] = {
 143                 {
 144                         .num_bits = 3,
 145                         .out_value = bscan_zero,
 146                         .in_value = NULL,
 147                 },
 148                 {
 149                         .num_bits = 5, /* initialized in riscv_init_target to ir width of DM */
 150                         .out_value = ir_dbus,
 151                         .in_value = NULL,
 152                 },
 153                 {
 154                         .num_bits = 7,
 155                         .out_value = bscan_tunneled_ir_width,
 156                         .in_value = NULL,
 157                 },
 158                 {
 159                         .num_bits = 1,
 160                         .out_value = bscan_zero,
 161                         .in_value = NULL,
 162                 }
 163 };
 164
 165 static struct scan_field _bscan_tunnel_nested_tap_select_dmi[] = {
 166                 {
 167                         .num_bits = 1,
 168                         .out_value = bscan_zero,
 169                         .in_value = NULL,
 170                 },
 171                 {
 172                         .num_bits = 7,
 173                         .out_value = bscan_tunneled_ir_width,
 174                         .in_value = NULL,
 175                 },
 176                 {
 177                         .num_bits = 0, /* initialized in riscv_init_target to ir width of DM */
 178                         .out_value = ir_dbus,
 179                         .in_value = NULL,
 180                 },
 181                 {
 182                         .num_bits = 3,
 183                         .out_value = bscan_zero,
 184                         .in_value = NULL,
 185                 }
 186 };
 187 static struct scan_field *bscan_tunnel_nested_tap_select_dmi = _bscan_tunnel_nested_tap_select_dmi;
 188 static uint32_t bscan_tunnel_nested_tap_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_nested_tap_select_dmi);
 189
 190 static struct scan_field *bscan_tunnel_data_register_select_dmi = _bscan_tunnel_data_register_select_dmi;
 191 static uint32_t bscan_tunnel_data_register_select_dmi_num_fields = ARRAY_SIZE(_bscan_tunnel_data_register_select_dmi);
 192
 193 struct trigger {
 194         uint64_t address;
 195         uint32_t length;
 196         uint64_t mask;
 197         uint64_t value;
 198         bool read, write, execute;
 199         int unique_id;
 200 };
 201
 202 /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
 203 int riscv_command_timeout_sec = DEFAULT_COMMAND_TIMEOUT_SEC;
 204
 205 /* Wall-clock timeout after reset. Settable via RISC-V Target commands.*/
 206 int riscv_reset_timeout_sec = DEFAULT_RESET_TIMEOUT_SEC;
 207
 208 static bool riscv_enable_virt2phys = true;
 209 bool riscv_ebreakm = true;
 210 bool riscv_ebreaks = true;
 211 bool riscv_ebreaku = true;
 212
 213 bool riscv_enable_virtual;
 214
 215 static enum {
 216         RO_NORMAL,
 217         RO_REVERSED
 218 } resume_order;
 219
 220 static const virt2phys_info_t sv32 = {
 221         .name = "Sv32",
 222         .va_bits = 32,
 223         .level = 2,
 224         .pte_shift = 2,
 225         .vpn_shift = {12, 22},
 226         .vpn_mask = {0x3ff, 0x3ff},
 227         .pte_ppn_shift = {10, 20},
 228         .pte_ppn_mask = {0x3ff, 0xfff},
 229         .pa_ppn_shift = {12, 22},
 230         .pa_ppn_mask = {0x3ff, 0xfff},
 231 };
 232
 233 static const virt2phys_info_t sv39 = {
 234         .name = "Sv39",
 235         .va_bits = 39,
 236         .level = 3,
 237         .pte_shift = 3,
 238         .vpn_shift = {12, 21, 30},
 239         .vpn_mask = {0x1ff, 0x1ff, 0x1ff},
 240         .pte_ppn_shift = {10, 19, 28},
 241         .pte_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 242         .pa_ppn_shift = {12, 21, 30},
 243         .pa_ppn_mask = {0x1ff, 0x1ff, 0x3ffffff},
 244 };
 245
 246 static const virt2phys_info_t sv48 = {
 247         .name = "Sv48",
 248         .va_bits = 48,
 249         .level = 4,
 250         .pte_shift = 3,
 251         .vpn_shift = {12, 21, 30, 39},
 252         .vpn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff},
 253         .pte_ppn_shift = {10, 19, 28, 37},
 254         .pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 255         .pa_ppn_shift = {12, 21, 30, 39},
 256         .pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ffff},
 257 };
 258
 259 static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid);
 260 static void riscv_info_init(struct target *target, struct riscv_info *r);
 261 static void riscv_invalidate_register_cache(struct target *target);
 262 static int riscv_step_rtos_hart(struct target *target);
 263
 264 static void riscv_sample_buf_maybe_add_timestamp(struct target *target, bool before)
 265 {
 266         RISCV_INFO(r);
 267         uint32_t now = timeval_ms() & 0xffffffff;
 268         if (r->sample_buf.used + 5 < r->sample_buf.size) {
 269                 if (before)
 270                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE;
 271                 else
 272                         r->sample_buf.buf[r->sample_buf.used++] = RISCV_SAMPLE_BUF_TIMESTAMP_AFTER;
 273                 r->sample_buf.buf[r->sample_buf.used++] = now & 0xff;
 274                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 8) & 0xff;
 275                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 16) & 0xff;
 276                 r->sample_buf.buf[r->sample_buf.used++] = (now >> 24) & 0xff;
 277         }
 278 }
 279
 280 static int riscv_resume_go_all_harts(struct target *target);
 281
 282 void select_dmi_via_bscan(struct target *target)
 283 {
 284         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 285         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 286                 jtag_add_dr_scan(target->tap, bscan_tunnel_data_register_select_dmi_num_fields,
 287                                                                                 bscan_tunnel_data_register_select_dmi, TAP_IDLE);
 288         else /* BSCAN_TUNNEL_NESTED_TAP */
 289                 jtag_add_dr_scan(target->tap, bscan_tunnel_nested_tap_select_dmi_num_fields,
 290                                                                                 bscan_tunnel_nested_tap_select_dmi, TAP_IDLE);
 291 }
 292
 293 uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out)
 294 {
 295         /* On BSCAN TAP: Select IR=USER4, issue tunneled IR scan via BSCAN TAP's DR */
 296         uint8_t tunneled_ir_width[4] = {bscan_tunnel_ir_width};
 297         uint8_t tunneled_dr_width[4] = {32};
 298         uint8_t out_value[5] = {0};
 299         uint8_t in_value[5] = {0};
 300
 301         buf_set_u32(out_value, 0, 32, out);
 302         struct scan_field tunneled_ir[4] = {};
 303         struct scan_field tunneled_dr[4] = {};
 304
 305         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
 306                 tunneled_ir[0].num_bits = 3;
 307                 tunneled_ir[0].out_value = bscan_zero;
 308                 tunneled_ir[0].in_value = NULL;
 309                 tunneled_ir[1].num_bits = bscan_tunnel_ir_width;
 310                 tunneled_ir[1].out_value = ir_dtmcontrol;
 311                 tunneled_ir[1].in_value = NULL;
 312                 tunneled_ir[2].num_bits = 7;
 313                 tunneled_ir[2].out_value = tunneled_ir_width;
 314                 tunneled_ir[2].in_value = NULL;
 315                 tunneled_ir[3].num_bits = 1;
 316                 tunneled_ir[3].out_value = bscan_zero;
 317                 tunneled_ir[3].in_value = NULL;
 318
 319                 tunneled_dr[0].num_bits = 3;
 320                 tunneled_dr[0].out_value = bscan_zero;
 321                 tunneled_dr[0].in_value = NULL;
 322                 tunneled_dr[1].num_bits = 32 + 1;
 323                 tunneled_dr[1].out_value = out_value;
 324                 tunneled_dr[1].in_value = in_value;
 325                 tunneled_dr[2].num_bits = 7;
 326                 tunneled_dr[2].out_value = tunneled_dr_width;
 327                 tunneled_dr[2].in_value = NULL;
 328                 tunneled_dr[3].num_bits = 1;
 329                 tunneled_dr[3].out_value = bscan_one;
 330                 tunneled_dr[3].in_value = NULL;
 331         } else {
 332                 /* BSCAN_TUNNEL_NESTED_TAP */
 333                 tunneled_ir[3].num_bits = 3;
 334                 tunneled_ir[3].out_value = bscan_zero;
 335                 tunneled_ir[3].in_value = NULL;
 336                 tunneled_ir[2].num_bits = bscan_tunnel_ir_width;
 337                 tunneled_ir[2].out_value = ir_dtmcontrol;
 338                 tunneled_ir[1].in_value = NULL;
 339                 tunneled_ir[1].num_bits = 7;
 340                 tunneled_ir[1].out_value = tunneled_ir_width;
 341                 tunneled_ir[2].in_value = NULL;
 342                 tunneled_ir[0].num_bits = 1;
 343                 tunneled_ir[0].out_value = bscan_zero;
 344                 tunneled_ir[0].in_value = NULL;
 345
 346                 tunneled_dr[3].num_bits = 3;
 347                 tunneled_dr[3].out_value = bscan_zero;
 348                 tunneled_dr[3].in_value = NULL;
 349                 tunneled_dr[2].num_bits = 32 + 1;
 350                 tunneled_dr[2].out_value = out_value;
 351                 tunneled_dr[2].in_value = in_value;
 352                 tunneled_dr[1].num_bits = 7;
 353                 tunneled_dr[1].out_value = tunneled_dr_width;
 354                 tunneled_dr[1].in_value = NULL;
 355                 tunneled_dr[0].num_bits = 1;
 356                 tunneled_dr[0].out_value = bscan_one;
 357                 tunneled_dr[0].in_value = NULL;
 358         }
 359         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
 360         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_ir), tunneled_ir, TAP_IDLE);
 361         jtag_add_dr_scan(target->tap, ARRAY_SIZE(tunneled_dr), tunneled_dr, TAP_IDLE);
 362         select_dmi_via_bscan(target);
 363
 364         int retval = jtag_execute_queue();
 365         if (retval != ERROR_OK) {
 366                 LOG_ERROR("failed jtag scan: %d", retval);
 367                 return retval;
 368         }
 369         /* Note the starting offset is bit 1, not bit 0.  In BSCAN tunnel, there is a one-bit TCK skew between
 370            output and input */
 371         uint32_t in = buf_get_u32(in_value, 1, 32);
 372         LOG_DEBUG("DTMCS: 0x%x -> 0x%x", out, in);
 373
 374         return in;
 375 }
 376
 377 static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
 378 {
 379         struct scan_field field;
 380         uint8_t in_value[4];
 381         uint8_t out_value[4] = { 0 };
 382
 383         if (bscan_tunnel_ir_width != 0)
 384                 return dtmcontrol_scan_via_bscan(target, out);
 385
 386
 387         buf_set_u32(out_value, 0, 32, out);
 388
 389         jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
 390
 391         field.num_bits = 32;
 392         field.out_value = out_value;
 393         field.in_value = in_value;
 394         jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
 395
 396         /* Always return to dbus. */
 397         jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 398
 399         int retval = jtag_execute_queue();
 400         if (retval != ERROR_OK) {
 401                 LOG_ERROR("failed jtag scan: %d", retval);
 402                 return retval;
 403         }
 404
 405         uint32_t in = buf_get_u32(field.in_value, 0, 32);
 406         LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
 407
 408         return in;
 409 }
 410
 411 static struct target_type *get_target_type(struct target *target)
 412 {
 413         if (!target->arch_info) {
 414                 LOG_ERROR("Target has not been initialized");
 415                 return NULL;
 416         }
 417
 418         RISCV_INFO(info);
 419         switch (info->dtm_version) {
 420                 case 0:
 421                         return &riscv011_target;
 422                 case 1:
 423                         return &riscv013_target;
 424                 default:
 425                         LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
 426                         return NULL;
 427         }
 428 }
 429
 430 static int riscv_create_target(struct target *target, Jim_Interp *interp)
 431 {
 432         LOG_DEBUG("riscv_create_target()");
 433         target->arch_info = calloc(1, sizeof(struct riscv_info));
 434         if (!target->arch_info) {
 435                 LOG_ERROR("Failed to allocate RISC-V target structure.");
 436                 return ERROR_FAIL;
 437         }
 438         riscv_info_init(target, target->arch_info);
 439         return ERROR_OK;
 440 }
 441
 442 static int riscv_init_target(struct command_context *cmd_ctx,
 443                 struct target *target)
 444 {
 445         LOG_DEBUG("riscv_init_target()");
 446         RISCV_INFO(info);
 447         info->cmd_ctx = cmd_ctx;
 448
 449         select_dtmcontrol.num_bits = target->tap->ir_length;
 450         select_dbus.num_bits = target->tap->ir_length;
 451         select_idcode.num_bits = target->tap->ir_length;
 452
 453         if (bscan_tunnel_ir_width != 0) {
 454                 assert(target->tap->ir_length >= 6);
 455                 uint32_t ir_user4_raw = 0x23 << (target->tap->ir_length - 6);
 456                 ir_user4[0] = (uint8_t)ir_user4_raw;
 457                 ir_user4[1] = (uint8_t)(ir_user4_raw >>= 8);
 458                 ir_user4[2] = (uint8_t)(ir_user4_raw >>= 8);
 459                 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
 460                 select_user4.num_bits = target->tap->ir_length;
 461                 bscan_tunneled_ir_width[0] = bscan_tunnel_ir_width;
 462                 if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
 463                         bscan_tunnel_data_register_select_dmi[1].num_bits = bscan_tunnel_ir_width;
 464                 else /* BSCAN_TUNNEL_NESTED_TAP */
 465                         bscan_tunnel_nested_tap_select_dmi[2].num_bits = bscan_tunnel_ir_width;
 466         }
 467
 468         riscv_semihosting_init(target);
 469
 470         target->debug_reason = DBG_REASON_DBGRQ;
 471
 472         return ERROR_OK;
 473 }
 474
 475 static void riscv_free_registers(struct target *target)
 476 {
 477         /* Free the shared structure use for most registers. */
 478         if (target->reg_cache) {
 479                 if (target->reg_cache->reg_list) {
 480                         free(target->reg_cache->reg_list[0].arch_info);
 481                         /* Free the ones we allocated separately. */
 482                         for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
 483                                 free(target->reg_cache->reg_list[i].arch_info);
 484                         for (unsigned int i = 0; i < target->reg_cache->num_regs; i++)
 485                                 free(target->reg_cache->reg_list[i].value);
 486                         free(target->reg_cache->reg_list);
 487                 }
 488                 free(target->reg_cache);
 489         }
 490 }
 491
 492 static void riscv_deinit_target(struct target *target)
 493 {
 494         LOG_DEBUG("riscv_deinit_target()");
 495
 496         struct riscv_info *info = target->arch_info;
 497         struct target_type *tt = get_target_type(target);
 498
 499         if (tt && info && info->version_specific)
 500                 tt->deinit_target(target);
 501
 502         riscv_free_registers(target);
 503
 504         if (!info)
 505                 return;
 506
 507         range_list_t *entry, *tmp;
 508         list_for_each_entry_safe(entry, tmp, &info->expose_csr, list) {
 509                 free(entry->name);
 510                 free(entry);
 511         }
 512
 513         list_for_each_entry_safe(entry, tmp, &info->expose_custom, list) {
 514                 free(entry->name);
 515                 free(entry);
 516         }
 517
 518         free(info->reg_names);
 519         free(target->arch_info);
 520
 521         target->arch_info = NULL;
 522 }
 523
 524 static void trigger_from_breakpoint(struct trigger *trigger,
 525                 const struct breakpoint *breakpoint)
 526 {
 527         trigger->address = breakpoint->address;
 528         trigger->length = breakpoint->length;
 529         trigger->mask = ~0LL;
 530         trigger->read = false;
 531         trigger->write = false;
 532         trigger->execute = true;
 533         /* unique_id is unique across both breakpoints and watchpoints. */
 534         trigger->unique_id = breakpoint->unique_id;
 535 }
 536
 537 static int maybe_add_trigger_t1(struct target *target,
 538                 struct trigger *trigger, uint64_t tdata1)
 539 {
 540         RISCV_INFO(r);
 541
 542         const uint32_t bpcontrol_x = 1<<0;
 543         const uint32_t bpcontrol_w = 1<<1;
 544         const uint32_t bpcontrol_r = 1<<2;
 545         const uint32_t bpcontrol_u = 1<<3;
 546         const uint32_t bpcontrol_s = 1<<4;
 547         const uint32_t bpcontrol_h = 1<<5;
 548         const uint32_t bpcontrol_m = 1<<6;
 549         const uint32_t bpcontrol_bpmatch = 0xf << 7;
 550         const uint32_t bpcontrol_bpaction = 0xff << 11;
 551
 552         if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
 553                 /* Trigger is already in use, presumably by user code. */
 554                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 555         }
 556
 557         tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
 558         tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
 559         tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
 560         tdata1 = set_field(tdata1, bpcontrol_u,
 561                         !!(r->misa & BIT('U' - 'A')));
 562         tdata1 = set_field(tdata1, bpcontrol_s,
 563                         !!(r->misa & BIT('S' - 'A')));
 564         tdata1 = set_field(tdata1, bpcontrol_h,
 565                         !!(r->misa & BIT('H' - 'A')));
 566         tdata1 |= bpcontrol_m;
 567         tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); /* exact match */
 568         tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); /* cause bp exception */
 569
 570         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 571
 572         riscv_reg_t tdata1_rb;
 573         if (riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1) != ERROR_OK)
 574                 return ERROR_FAIL;
 575         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 576
 577         if (tdata1 != tdata1_rb) {
 578                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 579                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 580                                 tdata1, tdata1_rb);
 581                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 582                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 583         }
 584
 585         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 586
 587         return ERROR_OK;
 588 }
 589
 590 static int maybe_add_trigger_t2(struct target *target,
 591                 struct trigger *trigger, uint64_t tdata1)
 592 {
 593         RISCV_INFO(r);
 594
 595         /* tselect is already set */
 596         if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
 597                 /* Trigger is already in use, presumably by user code. */
 598                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 599         }
 600
 601         /* address/data match trigger */
 602         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 603         tdata1 = set_field(tdata1, MCONTROL_ACTION,
 604                         MCONTROL_ACTION_DEBUG_MODE);
 605         tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
 606         tdata1 |= MCONTROL_M;
 607         if (r->misa & (1 << ('S' - 'A')))
 608                 tdata1 |= MCONTROL_S;
 609         if (r->misa & (1 << ('U' - 'A')))
 610                 tdata1 |= MCONTROL_U;
 611
 612         if (trigger->execute)
 613                 tdata1 |= MCONTROL_EXECUTE;
 614         if (trigger->read)
 615                 tdata1 |= MCONTROL_LOAD;
 616         if (trigger->write)
 617                 tdata1 |= MCONTROL_STORE;
 618
 619         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 620
 621         uint64_t tdata1_rb;
 622         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 623         if (result != ERROR_OK)
 624                 return result;
 625         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 626
 627         if (tdata1 != tdata1_rb) {
 628                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 629                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 630                                 tdata1, tdata1_rb);
 631                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 632                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 633         }
 634
 635         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 636
 637         return ERROR_OK;
 638 }
 639
 640 static int maybe_add_trigger_t6(struct target *target,
 641                 struct trigger *trigger, uint64_t tdata1)
 642 {
 643         RISCV_INFO(r);
 644
 645         /* tselect is already set */
 646         if (tdata1 & (CSR_MCONTROL6_EXECUTE | CSR_MCONTROL6_STORE | CSR_MCONTROL6_LOAD)) {
 647                 /* Trigger is already in use, presumably by user code. */
 648                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 649         }
 650
 651         /* address/data match trigger */
 652         tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
 653         tdata1 = set_field(tdata1, CSR_MCONTROL6_ACTION,
 654                         MCONTROL_ACTION_DEBUG_MODE);
 655         tdata1 = set_field(tdata1, CSR_MCONTROL6_MATCH, MCONTROL_MATCH_EQUAL);
 656         tdata1 |= CSR_MCONTROL6_M;
 657         if (r->misa & (1 << ('H' - 'A')))
 658                 tdata1 |= CSR_MCONTROL6_VS | CSR_MCONTROL6_VU;
 659         if (r->misa & (1 << ('S' - 'A')))
 660                 tdata1 |= CSR_MCONTROL6_S;
 661         if (r->misa & (1 << ('U' - 'A')))
 662                 tdata1 |= CSR_MCONTROL6_U;
 663
 664         if (trigger->execute)
 665                 tdata1 |= CSR_MCONTROL6_EXECUTE;
 666         if (trigger->read)
 667                 tdata1 |= CSR_MCONTROL6_LOAD;
 668         if (trigger->write)
 669                 tdata1 |= CSR_MCONTROL6_STORE;
 670
 671         riscv_set_register(target, GDB_REGNO_TDATA1, tdata1);
 672
 673         uint64_t tdata1_rb;
 674         int result = riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1);
 675         if (result != ERROR_OK)
 676                 return result;
 677         LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
 678
 679         if (tdata1 != tdata1_rb) {
 680                 LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
 681                                 PRIx64 " to tdata1 it contains 0x%" PRIx64,
 682                                 tdata1, tdata1_rb);
 683                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 684                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 685         }
 686
 687         riscv_set_register(target, GDB_REGNO_TDATA2, trigger->address);
 688
 689         return ERROR_OK;
 690 }
 691
 692 static int add_trigger(struct target *target, struct trigger *trigger)
 693 {
 694         RISCV_INFO(r);
 695
 696         if (riscv_enumerate_triggers(target) != ERROR_OK)
 697                 return ERROR_FAIL;
 698
 699         riscv_reg_t tselect;
 700         if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
 701                 return ERROR_FAIL;
 702
 703         unsigned int i;
 704         for (i = 0; i < r->trigger_count; i++) {
 705                 if (r->trigger_unique_id[i] != -1)
 706                         continue;
 707
 708                 riscv_set_register(target, GDB_REGNO_TSELECT, i);
 709
 710                 uint64_t tdata1;
 711                 int result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
 712                 if (result != ERROR_OK)
 713                         return result;
 714                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
 715
 716                 result = ERROR_OK;
 717                 switch (type) {
 718                         case 1:
 719                                 result = maybe_add_trigger_t1(target, trigger, tdata1);
 720                                 break;
 721                         case 2:
 722                                 result = maybe_add_trigger_t2(target, trigger, tdata1);
 723                                 break;
 724                         case 6:
 725                                 result = maybe_add_trigger_t6(target, trigger, tdata1);
 726                                 break;
 727                         default:
 728                                 LOG_DEBUG("trigger %d has unknown type %d", i, type);
 729                                 continue;
 730                 }
 731
 732                 if (result != ERROR_OK)
 733                         continue;
 734
 735                 LOG_DEBUG("[%d] Using trigger %d (type %d) for bp %d", target->coreid,
 736                                 i, type, trigger->unique_id);
 737                 r->trigger_unique_id[i] = trigger->unique_id;
 738                 break;
 739         }
 740
 741         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 742
 743         if (i >= r->trigger_count) {
 744                 LOG_ERROR("Couldn't find an available hardware trigger.");
 745                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 746         }
 747
 748         return ERROR_OK;
 749 }
 750
 751 /**
 752  * Write one memory item of given "size". Use memory access of given "access_size".
 753  * Utilize read-modify-write, if needed.
 754  * */
 755 static int write_by_given_size(struct target *target, target_addr_t address,
 756                 uint32_t size, uint8_t *buffer, uint32_t access_size)
 757 {
 758         assert(size == 1 || size == 2 || size == 4 || size == 8);
 759         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 760
 761         if (access_size <= size && address % access_size == 0)
 762                 /* Can do the memory access directly without a helper buffer. */
 763                 return target_write_memory(target, address, access_size, size / access_size, buffer);
 764
 765         unsigned int offset_head = address % access_size;
 766         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 767         uint8_t helper_buf[n_blocks * access_size];
 768
 769         /* Read from memory */
 770         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 771                 return ERROR_FAIL;
 772
 773         /* Modify and write back */
 774         memcpy(helper_buf + offset_head, buffer, size);
 775         return target_write_memory(target, address - offset_head, access_size, n_blocks, helper_buf);
 776 }
 777
 778 /**
 779  * Read one memory item of given "size". Use memory access of given "access_size".
 780  * Read larger section of memory and pick out the required portion, if needed.
 781  * */
 782 static int read_by_given_size(struct target *target, target_addr_t address,
 783         uint32_t size, uint8_t *buffer, uint32_t access_size)
 784 {
 785         assert(size == 1 || size == 2 || size == 4 || size == 8);
 786         assert(access_size == 1 || access_size == 2 || access_size == 4 || access_size == 8);
 787
 788         if (access_size <= size && address % access_size == 0)
 789                 /* Can do the memory access directly without a helper buffer. */
 790                 return target_read_memory(target, address, access_size, size / access_size, buffer);
 791
 792         unsigned int offset_head = address % access_size;
 793         unsigned int n_blocks = ((size + offset_head) <= access_size) ? 1 : 2;
 794         uint8_t helper_buf[n_blocks * access_size];
 795
 796         /* Read from memory */
 797         if (target_read_memory(target, address - offset_head, access_size, n_blocks, helper_buf) != ERROR_OK)
 798                 return ERROR_FAIL;
 799
 800         /* Pick the requested portion from the buffer */
 801         memcpy(buffer, helper_buf + offset_head, size);
 802         return ERROR_OK;
 803 }
 804
 805 /**
 806  * Write one memory item using any memory access size that will work.
 807  * Utilize read-modify-write, if needed.
 808  * */
 809 int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 810 {
 811         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 812
 813         /* Find access size that correspond to data size and the alignment. */
 814         unsigned int preferred_size = size;
 815         while (address % preferred_size != 0)
 816                 preferred_size /= 2;
 817
 818         /* First try the preferred (most natural) access size. */
 819         if (write_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 820                 return ERROR_OK;
 821
 822         /* On failure, try other access sizes.
 823            Minimize the number of accesses by trying first the largest size. */
 824         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 825                 if (access_size == preferred_size)
 826                         /* Already tried this size. */
 827                         continue;
 828
 829                 if (write_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 830                         return ERROR_OK;
 831         }
 832
 833         /* No access attempt succeeded. */
 834         return ERROR_FAIL;
 835 }
 836
 837 /**
 838  * Read one memory item using any memory access size that will work.
 839  * Read larger section of memory and pick out the required portion, if needed.
 840  * */
 841 int riscv_read_by_any_size(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 842 {
 843         assert(size == 1 || size == 2 ||  size == 4 || size == 8);
 844
 845         /* Find access size that correspond to data size and the alignment. */
 846         unsigned int preferred_size = size;
 847         while (address % preferred_size != 0)
 848                 preferred_size /= 2;
 849
 850         /* First try the preferred (most natural) access size. */
 851         if (read_by_given_size(target, address, size, buffer, preferred_size) == ERROR_OK)
 852                 return ERROR_OK;
 853
 854         /* On failure, try other access sizes.
 855            Minimize the number of accesses by trying first the largest size. */
 856         for (unsigned int access_size = 8; access_size > 0; access_size /= 2) {
 857                 if (access_size == preferred_size)
 858                         /* Already tried this size. */
 859                         continue;
 860
 861                 if (read_by_given_size(target, address, size, buffer, access_size) == ERROR_OK)
 862                         return ERROR_OK;
 863         }
 864
 865         /* No access attempt succeeded. */
 866         return ERROR_FAIL;
 867 }
 868
 869 static int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 870 {
 871         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, breakpoint->address);
 872         assert(breakpoint);
 873         if (breakpoint->type == BKPT_SOFT) {
 874                 /** @todo check RVC for size/alignment */
 875                 if (!(breakpoint->length == 4 || breakpoint->length == 2)) {
 876                         LOG_ERROR("Invalid breakpoint length %d", breakpoint->length);
 877                         return ERROR_FAIL;
 878                 }
 879
 880                 if (0 != (breakpoint->address % 2)) {
 881                         LOG_ERROR("Invalid breakpoint alignment for address 0x%" TARGET_PRIxADDR, breakpoint->address);
 882                         return ERROR_FAIL;
 883                 }
 884
 885                 /* Read the original instruction. */
 886                 if (riscv_read_by_any_size(
 887                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 888                         LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
 889                                         breakpoint->address);
 890                         return ERROR_FAIL;
 891                 }
 892
 893                 uint8_t buff[4] = { 0 };
 894                 buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
 895                 /* Write the ebreak instruction. */
 896                 if (riscv_write_by_any_size(target, breakpoint->address, breakpoint->length, buff) != ERROR_OK) {
 897                         LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
 898                                         TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 899                         return ERROR_FAIL;
 900                 }
 901
 902         } else if (breakpoint->type == BKPT_HARD) {
 903                 struct trigger trigger;
 904                 trigger_from_breakpoint(&trigger, breakpoint);
 905                 int const result = add_trigger(target, &trigger);
 906                 if (result != ERROR_OK)
 907                         return result;
 908         } else {
 909                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 910                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 911         }
 912
 913         breakpoint->is_set = true;
 914         return ERROR_OK;
 915 }
 916
 917 static int remove_trigger(struct target *target, struct trigger *trigger)
 918 {
 919         RISCV_INFO(r);
 920
 921         if (riscv_enumerate_triggers(target) != ERROR_OK)
 922                 return ERROR_FAIL;
 923
 924         unsigned int i;
 925         for (i = 0; i < r->trigger_count; i++) {
 926                 if (r->trigger_unique_id[i] == trigger->unique_id)
 927                         break;
 928         }
 929         if (i >= r->trigger_count) {
 930                 LOG_ERROR("Couldn't find the hardware resources used by hardware "
 931                                 "trigger.");
 932                 return ERROR_FAIL;
 933         }
 934         LOG_DEBUG("[%d] Stop using resource %d for bp %d", target->coreid, i,
 935                         trigger->unique_id);
 936
 937         riscv_reg_t tselect;
 938         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
 939         if (result != ERROR_OK)
 940                 return result;
 941         riscv_set_register(target, GDB_REGNO_TSELECT, i);
 942         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
 943         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
 944         r->trigger_unique_id[i] = -1;
 945
 946         return ERROR_OK;
 947 }
 948
 949 static int riscv_remove_breakpoint(struct target *target,
 950                 struct breakpoint *breakpoint)
 951 {
 952         if (breakpoint->type == BKPT_SOFT) {
 953                 /* Write the original instruction. */
 954                 if (riscv_write_by_any_size(
 955                                 target, breakpoint->address, breakpoint->length, breakpoint->orig_instr) != ERROR_OK) {
 956                         LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
 957                                         "0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
 958                         return ERROR_FAIL;
 959                 }
 960
 961         } else if (breakpoint->type == BKPT_HARD) {
 962                 struct trigger trigger;
 963                 trigger_from_breakpoint(&trigger, breakpoint);
 964                 int result = remove_trigger(target, &trigger);
 965                 if (result != ERROR_OK)
 966                         return result;
 967
 968         } else {
 969                 LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
 970                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 971         }
 972
 973         breakpoint->is_set = false;
 974
 975         return ERROR_OK;
 976 }
 977
 978 static void trigger_from_watchpoint(struct trigger *trigger,
 979                 const struct watchpoint *watchpoint)
 980 {
 981         trigger->address = watchpoint->address;
 982         trigger->length = watchpoint->length;
 983         trigger->mask = watchpoint->mask;
 984         trigger->value = watchpoint->value;
 985         trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
 986         trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
 987         trigger->execute = false;
 988         /* unique_id is unique across both breakpoints and watchpoints. */
 989         trigger->unique_id = watchpoint->unique_id;
 990 }
 991
 992 int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 993 {
 994         struct trigger trigger;
 995         trigger_from_watchpoint(&trigger, watchpoint);
 996
 997         int result = add_trigger(target, &trigger);
 998         if (result != ERROR_OK)
 999                 return result;
1000         watchpoint->is_set = true;
1001
1002         return ERROR_OK;
1003 }
1004
1005 int riscv_remove_watchpoint(struct target *target,
1006                 struct watchpoint *watchpoint)
1007 {
1008         LOG_DEBUG("[%d] @0x%" TARGET_PRIxADDR, target->coreid, watchpoint->address);
1009
1010         struct trigger trigger;
1011         trigger_from_watchpoint(&trigger, watchpoint);
1012
1013         int result = remove_trigger(target, &trigger);
1014         if (result != ERROR_OK)
1015                 return result;
1016         watchpoint->is_set = false;
1017
1018         return ERROR_OK;
1019 }
1020
1021 /* Sets *hit_watchpoint to the first watchpoint identified as causing the
1022  * current halt.
1023  *
1024  * The GDB server uses this information to tell GDB what data address has
1025  * been hit, which enables GDB to print the hit variable along with its old
1026  * and new value. */
1027 static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_watchpoint)
1028 {
1029         struct watchpoint *wp = target->watchpoints;
1030
1031         LOG_DEBUG("Current hartid = %d", riscv_current_hartid(target));
1032
1033         /*TODO instead of disassembling the instruction that we think caused the
1034          * trigger, check the hit bit of each watchpoint first. The hit bit is
1035          * simpler and more reliable to check but as it is optional and relatively
1036          * new, not all hardware will implement it  */
1037         riscv_reg_t dpc;
1038         riscv_get_register(target, &dpc, GDB_REGNO_DPC);
1039         const uint8_t length = 4;
1040         LOG_DEBUG("dpc is 0x%" PRIx64, dpc);
1041
1042         /* fetch the instruction at dpc */
1043         uint8_t buffer[length];
1044         if (target_read_buffer(target, dpc, length, buffer) != ERROR_OK) {
1045                 LOG_ERROR("Failed to read instruction at dpc 0x%" PRIx64, dpc);
1046                 return ERROR_FAIL;
1047         }
1048
1049         uint32_t instruction = 0;
1050
1051         for (int i = 0; i < length; i++) {
1052                 LOG_DEBUG("Next byte is %x", buffer[i]);
1053                 instruction += (buffer[i] << 8 * i);
1054         }
1055         LOG_DEBUG("Full instruction is %x", instruction);
1056
1057         /* find out which memory address is accessed by the instruction at dpc */
1058         /* opcode is first 7 bits of the instruction */
1059         uint8_t opcode = instruction & 0x7F;
1060         uint32_t rs1;
1061         int16_t imm;
1062         riscv_reg_t mem_addr;
1063
1064         if (opcode == MATCH_LB || opcode == MATCH_SB) {
1065                 rs1 = (instruction & 0xf8000) >> 15;
1066                 riscv_get_register(target, &mem_addr, rs1);
1067
1068                 if (opcode == MATCH_SB) {
1069                         LOG_DEBUG("%x is store instruction", instruction);
1070                         imm = ((instruction & 0xf80) >> 7) | ((instruction & 0xfe000000) >> 20);
1071                 } else {
1072                         LOG_DEBUG("%x is load instruction", instruction);
1073                         imm = (instruction & 0xfff00000) >> 20;
1074                 }
1075                 /* sign extend 12-bit imm to 16-bits */
1076                 if (imm & (1 << 11))
1077                         imm |= 0xf000;
1078                 mem_addr += imm;
1079                 LOG_DEBUG("memory address=0x%" PRIx64, mem_addr);
1080         } else {
1081                 LOG_DEBUG("%x is not a RV32I load or store", instruction);
1082                 return ERROR_FAIL;
1083         }
1084
1085         while (wp) {
1086                 /*TODO support length/mask */
1087                 if (wp->address == mem_addr) {
1088                         *hit_watchpoint = wp;
1089                         LOG_DEBUG("Hit address=%" TARGET_PRIxADDR, wp->address);
1090                         return ERROR_OK;
1091                 }
1092                 wp = wp->next;
1093         }
1094
1095         /* No match found - either we hit a watchpoint caused by an instruction that
1096          * this function does not yet disassemble, or we hit a breakpoint.
1097          *
1098          * OpenOCD will behave as if this function had never been implemented i.e.
1099          * report the halt to GDB with no address information. */
1100         return ERROR_FAIL;
1101 }
1102
1103
1104 static int oldriscv_step(struct target *target, int current, uint32_t address,
1105                 int handle_breakpoints)
1106 {
1107         struct target_type *tt = get_target_type(target);
1108         return tt->step(target, current, address, handle_breakpoints);
1109 }
1110
1111 static int old_or_new_riscv_step(struct target *target, int current,
1112                 target_addr_t address, int handle_breakpoints)
1113 {
1114         RISCV_INFO(r);
1115         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1116         if (!r->is_halted)
1117                 return oldriscv_step(target, current, address, handle_breakpoints);
1118         else
1119                 return riscv_openocd_step(target, current, address, handle_breakpoints);
1120 }
1121
1122
1123 static int riscv_examine(struct target *target)
1124 {
1125         LOG_DEBUG("riscv_examine()");
1126         if (target_was_examined(target)) {
1127                 LOG_DEBUG("Target was already examined.");
1128                 return ERROR_OK;
1129         }
1130
1131         /* Don't need to select dbus, since the first thing we do is read dtmcontrol. */
1132
1133         RISCV_INFO(info);
1134         uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
1135         LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
1136         info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
1137         LOG_DEBUG("  version=0x%x", info->dtm_version);
1138
1139         struct target_type *tt = get_target_type(target);
1140         if (!tt)
1141                 return ERROR_FAIL;
1142
1143         int result = tt->init_target(info->cmd_ctx, target);
1144         if (result != ERROR_OK)
1145                 return result;
1146
1147         return tt->examine(target);
1148 }
1149
1150 static int oldriscv_poll(struct target *target)
1151 {
1152         struct target_type *tt = get_target_type(target);
1153         return tt->poll(target);
1154 }
1155
1156 static int old_or_new_riscv_poll(struct target *target)
1157 {
1158         RISCV_INFO(r);
1159         if (!r->is_halted)
1160                 return oldriscv_poll(target);
1161         else
1162                 return riscv_openocd_poll(target);
1163 }
1164
1165 int riscv_select_current_hart(struct target *target)
1166 {
1167         return riscv_set_current_hartid(target, target->coreid);
1168 }
1169
1170 static int halt_prep(struct target *target)
1171 {
1172         RISCV_INFO(r);
1173
1174         LOG_DEBUG("[%s] prep hart, debug_reason=%d", target_name(target),
1175                                 target->debug_reason);
1176         if (riscv_select_current_hart(target) != ERROR_OK)
1177                 return ERROR_FAIL;
1178         if (riscv_is_halted(target)) {
1179                 LOG_DEBUG("[%s] Hart is already halted (reason=%d).",
1180                                 target_name(target), target->debug_reason);
1181         } else {
1182                 if (r->halt_prep(target) != ERROR_OK)
1183                         return ERROR_FAIL;
1184                 r->prepped = true;
1185         }
1186
1187         return ERROR_OK;
1188 }
1189
1190 static int riscv_halt_go_all_harts(struct target *target)
1191 {
1192         RISCV_INFO(r);
1193
1194         if (riscv_select_current_hart(target) != ERROR_OK)
1195                 return ERROR_FAIL;
1196         if (riscv_is_halted(target)) {
1197                 LOG_DEBUG("[%s] Hart is already halted.", target_name(target));
1198         } else {
1199                 if (r->halt_go(target) != ERROR_OK)
1200                         return ERROR_FAIL;
1201         }
1202
1203         riscv_invalidate_register_cache(target);
1204
1205         return ERROR_OK;
1206 }
1207
1208 static int halt_go(struct target *target)
1209 {
1210         RISCV_INFO(r);
1211         int result;
1212         if (!r->is_halted) {
1213                 struct target_type *tt = get_target_type(target);
1214                 result = tt->halt(target);
1215         } else {
1216                 result = riscv_halt_go_all_harts(target);
1217         }
1218         target->state = TARGET_HALTED;
1219         if (target->debug_reason == DBG_REASON_NOTHALTED)
1220                 target->debug_reason = DBG_REASON_DBGRQ;
1221
1222         return result;
1223 }
1224
1225 static int halt_finish(struct target *target)
1226 {
1227         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
1228 }
1229
1230 int riscv_halt(struct target *target)
1231 {
1232         RISCV_INFO(r);
1233
1234         if (!r->is_halted) {
1235                 struct target_type *tt = get_target_type(target);
1236                 return tt->halt(target);
1237         }
1238
1239         LOG_DEBUG("[%d] halting all harts", target->coreid);
1240
1241         int result = ERROR_OK;
1242         if (target->smp) {
1243                 struct target_list *tlist;
1244                 foreach_smp_target(tlist, target->smp_targets) {
1245                         struct target *t = tlist->target;
1246                         if (halt_prep(t) != ERROR_OK)
1247                                 result = ERROR_FAIL;
1248                 }
1249
1250                 foreach_smp_target(tlist, target->smp_targets) {
1251                         struct target *t = tlist->target;
1252                         struct riscv_info *i = riscv_info(t);
1253                         if (i->prepped) {
1254                                 if (halt_go(t) != ERROR_OK)
1255                                         result = ERROR_FAIL;
1256                         }
1257                 }
1258
1259                 foreach_smp_target(tlist, target->smp_targets) {
1260                         struct target *t = tlist->target;
1261                         if (halt_finish(t) != ERROR_OK)
1262                                 return ERROR_FAIL;
1263                 }
1264
1265         } else {
1266                 if (halt_prep(target) != ERROR_OK)
1267                         result = ERROR_FAIL;
1268                 if (halt_go(target) != ERROR_OK)
1269                         result = ERROR_FAIL;
1270                 if (halt_finish(target) != ERROR_OK)
1271                         return ERROR_FAIL;
1272         }
1273
1274         return result;
1275 }
1276
1277 static int riscv_assert_reset(struct target *target)
1278 {
1279         LOG_DEBUG("[%d]", target->coreid);
1280         struct target_type *tt = get_target_type(target);
1281         riscv_invalidate_register_cache(target);
1282         return tt->assert_reset(target);
1283 }
1284
1285 static int riscv_deassert_reset(struct target *target)
1286 {
1287         LOG_DEBUG("[%d]", target->coreid);
1288         struct target_type *tt = get_target_type(target);
1289         return tt->deassert_reset(target);
1290 }
1291
1292 static int riscv_resume_prep_all_harts(struct target *target)
1293 {
1294         RISCV_INFO(r);
1295
1296         LOG_DEBUG("[%s] prep hart", target_name(target));
1297         if (riscv_select_current_hart(target) != ERROR_OK)
1298                 return ERROR_FAIL;
1299         if (riscv_is_halted(target)) {
1300                 if (r->resume_prep(target) != ERROR_OK)
1301                         return ERROR_FAIL;
1302         } else {
1303                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
1304                                 target_name(target));
1305         }
1306
1307         LOG_DEBUG("[%s] mark as prepped", target_name(target));
1308         r->prepped = true;
1309
1310         return ERROR_OK;
1311 }
1312
1313 /* state must be riscv_reg_t state[RISCV_MAX_HWBPS] = {0}; */
1314 static int disable_triggers(struct target *target, riscv_reg_t *state)
1315 {
1316         RISCV_INFO(r);
1317
1318         LOG_DEBUG("deal with triggers");
1319
1320         if (riscv_enumerate_triggers(target) != ERROR_OK)
1321                 return ERROR_FAIL;
1322
1323         if (r->manual_hwbp_set) {
1324                 /* Look at every trigger that may have been set. */
1325                 riscv_reg_t tselect;
1326                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1327                         return ERROR_FAIL;
1328                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1329                         if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1330                                 return ERROR_FAIL;
1331                         riscv_reg_t tdata1;
1332                         if (riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1) != ERROR_OK)
1333                                 return ERROR_FAIL;
1334                         if (tdata1 & MCONTROL_DMODE(riscv_xlen(target))) {
1335                                 state[t] = tdata1;
1336                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, 0) != ERROR_OK)
1337                                         return ERROR_FAIL;
1338                         }
1339                 }
1340                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1341                         return ERROR_FAIL;
1342
1343         } else {
1344                 /* Just go through the triggers we manage. */
1345                 struct watchpoint *watchpoint = target->watchpoints;
1346                 int i = 0;
1347                 while (watchpoint) {
1348                         LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->is_set);
1349                         state[i] = watchpoint->is_set;
1350                         if (watchpoint->is_set) {
1351                                 if (riscv_remove_watchpoint(target, watchpoint) != ERROR_OK)
1352                                         return ERROR_FAIL;
1353                         }
1354                         watchpoint = watchpoint->next;
1355                         i++;
1356                 }
1357         }
1358
1359         return ERROR_OK;
1360 }
1361
1362 static int enable_triggers(struct target *target, riscv_reg_t *state)
1363 {
1364         RISCV_INFO(r);
1365
1366         if (r->manual_hwbp_set) {
1367                 /* Look at every trigger that may have been set. */
1368                 riscv_reg_t tselect;
1369                 if (riscv_get_register(target, &tselect, GDB_REGNO_TSELECT) != ERROR_OK)
1370                         return ERROR_FAIL;
1371                 for (unsigned int t = 0; t < r->trigger_count; t++) {
1372                         if (state[t] != 0) {
1373                                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
1374                                         return ERROR_FAIL;
1375                                 if (riscv_set_register(target, GDB_REGNO_TDATA1, state[t]) != ERROR_OK)
1376                                         return ERROR_FAIL;
1377                         }
1378                 }
1379                 if (riscv_set_register(target, GDB_REGNO_TSELECT, tselect) != ERROR_OK)
1380                         return ERROR_FAIL;
1381
1382         } else {
1383                 struct watchpoint *watchpoint = target->watchpoints;
1384                 int i = 0;
1385                 while (watchpoint) {
1386                         LOG_DEBUG("watchpoint %d: cleared=%" PRId64, i, state[i]);
1387                         if (state[i]) {
1388                                 if (riscv_add_watchpoint(target, watchpoint) != ERROR_OK)
1389                                         return ERROR_FAIL;
1390                         }
1391                         watchpoint = watchpoint->next;
1392                         i++;
1393                 }
1394         }
1395
1396         return ERROR_OK;
1397 }
1398
1399 /**
1400  * Get everything ready to resume.
1401  */
1402 static int resume_prep(struct target *target, int current,
1403                 target_addr_t address, int handle_breakpoints, int debug_execution)
1404 {
1405         RISCV_INFO(r);
1406         LOG_DEBUG("[%d]", target->coreid);
1407
1408         if (!current)
1409                 riscv_set_register(target, GDB_REGNO_PC, address);
1410
1411         if (target->debug_reason == DBG_REASON_WATCHPOINT) {
1412                 /* To be able to run off a trigger, disable all the triggers, step, and
1413                  * then resume as usual. */
1414                 riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
1415
1416                 if (disable_triggers(target, trigger_state) != ERROR_OK)
1417                         return ERROR_FAIL;
1418
1419                 if (old_or_new_riscv_step(target, true, 0, false) != ERROR_OK)
1420                         return ERROR_FAIL;
1421
1422                 if (enable_triggers(target, trigger_state) != ERROR_OK)
1423                         return ERROR_FAIL;
1424         }
1425
1426         if (r->is_halted) {
1427                 if (riscv_resume_prep_all_harts(target) != ERROR_OK)
1428                         return ERROR_FAIL;
1429         }
1430
1431         LOG_DEBUG("[%d] mark as prepped", target->coreid);
1432         r->prepped = true;
1433
1434         return ERROR_OK;
1435 }
1436
1437 /**
1438  * Resume all the harts that have been prepped, as close to instantaneous as
1439  * possible.
1440  */
1441 static int resume_go(struct target *target, int current,
1442                 target_addr_t address, int handle_breakpoints, int debug_execution)
1443 {
1444         RISCV_INFO(r);
1445         int result;
1446         if (!r->is_halted) {
1447                 struct target_type *tt = get_target_type(target);
1448                 result = tt->resume(target, current, address, handle_breakpoints,
1449                                 debug_execution);
1450         } else {
1451                 result = riscv_resume_go_all_harts(target);
1452         }
1453
1454         return result;
1455 }
1456
1457 static int resume_finish(struct target *target)
1458 {
1459         register_cache_invalidate(target->reg_cache);
1460
1461         target->state = TARGET_RUNNING;
1462         target->debug_reason = DBG_REASON_NOTHALTED;
1463         return target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
1464 }
1465
1466 /**
1467  * @par single_hart When true, only resume a single hart even if SMP is
1468  * configured.  This is used to run algorithms on just one hart.
1469  */
1470 static int riscv_resume(
1471                 struct target *target,
1472                 int current,
1473                 target_addr_t address,
1474                 int handle_breakpoints,
1475                 int debug_execution,
1476                 bool single_hart)
1477 {
1478         LOG_DEBUG("handle_breakpoints=%d", handle_breakpoints);
1479         int result = ERROR_OK;
1480         if (target->smp && !single_hart) {
1481                 struct target_list *tlist;
1482                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1483                                                                          tlist, target->smp_targets) {
1484                         struct target *t = tlist->target;
1485                         if (resume_prep(t, current, address, handle_breakpoints,
1486                                                 debug_execution) != ERROR_OK)
1487                                 result = ERROR_FAIL;
1488                 }
1489
1490                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1491                                                                          tlist, target->smp_targets) {
1492                         struct target *t = tlist->target;
1493                         struct riscv_info *i = riscv_info(t);
1494                         if (i->prepped) {
1495                                 if (resume_go(t, current, address, handle_breakpoints,
1496                                                         debug_execution) != ERROR_OK)
1497                                         result = ERROR_FAIL;
1498                         }
1499                 }
1500
1501                 foreach_smp_target_direction(resume_order == RO_NORMAL,
1502                                                                          tlist, target->smp_targets) {
1503                         struct target *t = tlist->target;
1504                         if (resume_finish(t) != ERROR_OK)
1505                                 return ERROR_FAIL;
1506                 }
1507
1508         } else {
1509                 if (resume_prep(target, current, address, handle_breakpoints,
1510                                         debug_execution) != ERROR_OK)
1511                         result = ERROR_FAIL;
1512                 if (resume_go(target, current, address, handle_breakpoints,
1513                                         debug_execution) != ERROR_OK)
1514                         result = ERROR_FAIL;
1515                 if (resume_finish(target) != ERROR_OK)
1516                         return ERROR_FAIL;
1517         }
1518
1519         return result;
1520 }
1521
1522 static int riscv_target_resume(struct target *target, int current, target_addr_t address,
1523                 int handle_breakpoints, int debug_execution)
1524 {
1525         return riscv_resume(target, current, address, handle_breakpoints,
1526                         debug_execution, false);
1527 }
1528
1529 static int riscv_mmu(struct target *target, int *enabled)
1530 {
1531         if (!riscv_enable_virt2phys) {
1532                 *enabled = 0;
1533                 return ERROR_OK;
1534         }
1535
1536         /* Don't use MMU in explicit or effective M (machine) mode */
1537         riscv_reg_t priv;
1538         if (riscv_get_register(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) {
1539                 LOG_ERROR("Failed to read priv register.");
1540                 return ERROR_FAIL;
1541         }
1542
1543         riscv_reg_t mstatus;
1544         if (riscv_get_register(target, &mstatus, GDB_REGNO_MSTATUS) != ERROR_OK) {
1545                 LOG_ERROR("Failed to read mstatus register.");
1546                 return ERROR_FAIL;
1547         }
1548
1549         if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
1550                 LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
1551                 *enabled = 0;
1552                 return ERROR_OK;
1553         }
1554
1555         riscv_reg_t satp;
1556         if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
1557                 LOG_DEBUG("Couldn't read SATP.");
1558                 /* If we can't read SATP, then there must not be an MMU. */
1559                 *enabled = 0;
1560                 return ERROR_OK;
1561         }
1562
1563         if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
1564                 LOG_DEBUG("MMU is disabled.");
1565                 *enabled = 0;
1566         } else {
1567                 LOG_DEBUG("MMU is enabled.");
1568                 *enabled = 1;
1569         }
1570
1571         return ERROR_OK;
1572 }
1573
1574 static int riscv_address_translate(struct target *target,
1575                 target_addr_t virtual, target_addr_t *physical)
1576 {
1577         RISCV_INFO(r);
1578         riscv_reg_t satp_value;
1579         int mode;
1580         uint64_t ppn_value;
1581         target_addr_t table_address;
1582         const virt2phys_info_t *info;
1583         uint64_t pte = 0;
1584         int i;
1585
1586         int result = riscv_get_register(target, &satp_value, GDB_REGNO_SATP);
1587         if (result != ERROR_OK)
1588                 return result;
1589
1590         unsigned xlen = riscv_xlen(target);
1591         mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
1592         switch (mode) {
1593                 case SATP_MODE_SV32:
1594                         info = &sv32;
1595                         break;
1596                 case SATP_MODE_SV39:
1597                         info = &sv39;
1598                         break;
1599                 case SATP_MODE_SV48:
1600                         info = &sv48;
1601                         break;
1602                 case SATP_MODE_OFF:
1603                         LOG_ERROR("No translation or protection." \
1604                                       " (satp: 0x%" PRIx64 ")", satp_value);
1605                         return ERROR_FAIL;
1606                 default:
1607                         LOG_ERROR("The translation mode is not supported." \
1608                                       " (satp: 0x%" PRIx64 ")", satp_value);
1609                         return ERROR_FAIL;
1610         }
1611         LOG_DEBUG("virtual=0x%" TARGET_PRIxADDR "; mode=%s", virtual, info->name);
1612
1613         /* verify bits xlen-1:va_bits-1 are all equal */
1614         target_addr_t mask = ((target_addr_t)1 << (xlen - (info->va_bits - 1))) - 1;
1615         target_addr_t masked_msbs = (virtual >> (info->va_bits - 1)) & mask;
1616         if (masked_msbs != 0 && masked_msbs != mask) {
1617                 LOG_ERROR("Virtual address 0x%" TARGET_PRIxADDR " is not sign-extended "
1618                                 "for %s mode.", virtual, info->name);
1619                 return ERROR_FAIL;
1620         }
1621
1622         ppn_value = get_field(satp_value, RISCV_SATP_PPN(xlen));
1623         table_address = ppn_value << RISCV_PGSHIFT;
1624         i = info->level - 1;
1625         while (i >= 0) {
1626                 uint64_t vpn = virtual >> info->vpn_shift[i];
1627                 vpn &= info->vpn_mask[i];
1628                 target_addr_t pte_address = table_address +
1629                                                                         (vpn << info->pte_shift);
1630                 uint8_t buffer[8];
1631                 assert(info->pte_shift <= 3);
1632                 int retval = r->read_memory(target, pte_address,
1633                                 4, (1 << info->pte_shift) / 4, buffer, 4);
1634                 if (retval != ERROR_OK)
1635                         return ERROR_FAIL;
1636
1637                 if (info->pte_shift == 2)
1638                         pte = buf_get_u32(buffer, 0, 32);
1639                 else
1640                         pte = buf_get_u64(buffer, 0, 64);
1641
1642                 LOG_DEBUG("i=%d; PTE @0x%" TARGET_PRIxADDR " = 0x%" PRIx64, i,
1643                                 pte_address, pte);
1644
1645                 if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W)))
1646                         return ERROR_FAIL;
1647
1648                 if ((pte & PTE_R) || (pte & PTE_X)) /* Found leaf PTE. */
1649                         break;
1650
1651                 i--;
1652                 if (i < 0)
1653                         break;
1654                 ppn_value = pte >> PTE_PPN_SHIFT;
1655                 table_address = ppn_value << RISCV_PGSHIFT;
1656         }
1657
1658         if (i < 0) {
1659                 LOG_ERROR("Couldn't find the PTE.");
1660                 return ERROR_FAIL;
1661         }
1662
1663         /* Make sure to clear out the high bits that may be set. */
1664         *physical = virtual & (((target_addr_t)1 << info->va_bits) - 1);
1665
1666         while (i < info->level) {
1667                 ppn_value = pte >> info->pte_ppn_shift[i];
1668                 ppn_value &= info->pte_ppn_mask[i];
1669                 *physical &= ~(((target_addr_t)info->pa_ppn_mask[i]) <<
1670                                 info->pa_ppn_shift[i]);
1671                 *physical |= (ppn_value << info->pa_ppn_shift[i]);
1672                 i++;
1673         }
1674         LOG_DEBUG("0x%" TARGET_PRIxADDR " -> 0x%" TARGET_PRIxADDR, virtual,
1675                         *physical);
1676
1677         return ERROR_OK;
1678 }
1679
1680 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
1681 {
1682         int enabled;
1683         if (riscv_mmu(target, &enabled) == ERROR_OK) {
1684                 if (!enabled)
1685                         return ERROR_FAIL;
1686
1687                 if (riscv_address_translate(target, virtual, physical) == ERROR_OK)
1688                         return ERROR_OK;
1689         }
1690
1691         return ERROR_FAIL;
1692 }
1693
1694 static int riscv_read_phys_memory(struct target *target, target_addr_t phys_address,
1695                         uint32_t size, uint32_t count, uint8_t *buffer)
1696 {
1697         RISCV_INFO(r);
1698         if (riscv_select_current_hart(target) != ERROR_OK)
1699                 return ERROR_FAIL;
1700         return r->read_memory(target, phys_address, size, count, buffer, size);
1701 }
1702
1703 static int riscv_read_memory(struct target *target, target_addr_t address,
1704                 uint32_t size, uint32_t count, uint8_t *buffer)
1705 {
1706         if (count == 0) {
1707                 LOG_WARNING("0-length read from 0x%" TARGET_PRIxADDR, address);
1708                 return ERROR_OK;
1709         }
1710
1711         if (riscv_select_current_hart(target) != ERROR_OK)
1712                 return ERROR_FAIL;
1713
1714         target_addr_t physical_addr;
1715         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1716                 address = physical_addr;
1717
1718         RISCV_INFO(r);
1719         return r->read_memory(target, address, size, count, buffer, size);
1720 }
1721
1722 static int riscv_write_phys_memory(struct target *target, target_addr_t phys_address,
1723                         uint32_t size, uint32_t count, const uint8_t *buffer)
1724 {
1725         if (riscv_select_current_hart(target) != ERROR_OK)
1726                 return ERROR_FAIL;
1727         struct target_type *tt = get_target_type(target);
1728         return tt->write_memory(target, phys_address, size, count, buffer);
1729 }
1730
1731 static int riscv_write_memory(struct target *target, target_addr_t address,
1732                 uint32_t size, uint32_t count, const uint8_t *buffer)
1733 {
1734         if (count == 0) {
1735                 LOG_WARNING("0-length write to 0x%" TARGET_PRIxADDR, address);
1736                 return ERROR_OK;
1737         }
1738
1739         if (riscv_select_current_hart(target) != ERROR_OK)
1740                 return ERROR_FAIL;
1741
1742         target_addr_t physical_addr;
1743         if (target->type->virt2phys(target, address, &physical_addr) == ERROR_OK)
1744                 address = physical_addr;
1745
1746         struct target_type *tt = get_target_type(target);
1747         return tt->write_memory(target, address, size, count, buffer);
1748 }
1749
1750 static const char *riscv_get_gdb_arch(struct target *target)
1751 {
1752         switch (riscv_xlen(target)) {
1753                 case 32:
1754                         return "riscv:rv32";
1755                 case 64:
1756                         return "riscv:rv64";
1757         }
1758         LOG_ERROR("Unsupported xlen: %d", riscv_xlen(target));
1759         return NULL;
1760 }
1761
1762 static int riscv_get_gdb_reg_list_internal(struct target *target,
1763                 struct reg **reg_list[], int *reg_list_size,
1764                 enum target_register_class reg_class, bool read)
1765 {
1766         RISCV_INFO(r);
1767         LOG_DEBUG("[%s] {%d} reg_class=%d, read=%d",
1768                         target_name(target), r->current_hartid, reg_class, read);
1769
1770         if (!target->reg_cache) {
1771                 LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
1772                 return ERROR_FAIL;
1773         }
1774
1775         if (riscv_select_current_hart(target) != ERROR_OK)
1776                 return ERROR_FAIL;
1777
1778         switch (reg_class) {
1779                 case REG_CLASS_GENERAL:
1780                         *reg_list_size = 33;
1781                         break;
1782                 case REG_CLASS_ALL:
1783                         *reg_list_size = target->reg_cache->num_regs;
1784                         break;
1785                 default:
1786                         LOG_ERROR("Unsupported reg_class: %d", reg_class);
1787                         return ERROR_FAIL;
1788         }
1789
1790         *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
1791         if (!*reg_list)
1792                 return ERROR_FAIL;
1793
1794         for (int i = 0; i < *reg_list_size; i++) {
1795                 assert(!target->reg_cache->reg_list[i].valid ||
1796                                 target->reg_cache->reg_list[i].size > 0);
1797                 (*reg_list)[i] = &target->reg_cache->reg_list[i];
1798                 if (read &&
1799                                 target->reg_cache->reg_list[i].exist &&
1800                                 !target->reg_cache->reg_list[i].valid) {
1801                         if (target->reg_cache->reg_list[i].type->get(
1802                                                 &target->reg_cache->reg_list[i]) != ERROR_OK)
1803                                 return ERROR_FAIL;
1804                 }
1805         }
1806
1807         return ERROR_OK;
1808 }
1809
1810 static int riscv_get_gdb_reg_list_noread(struct target *target,
1811                 struct reg **reg_list[], int *reg_list_size,
1812                 enum target_register_class reg_class)
1813 {
1814         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1815                         reg_class, false);
1816 }
1817
1818 static int riscv_get_gdb_reg_list(struct target *target,
1819                 struct reg **reg_list[], int *reg_list_size,
1820                 enum target_register_class reg_class)
1821 {
1822         return riscv_get_gdb_reg_list_internal(target, reg_list, reg_list_size,
1823                         reg_class, true);
1824 }
1825
1826 static int riscv_arch_state(struct target *target)
1827 {
1828         struct target_type *tt = get_target_type(target);
1829         return tt->arch_state(target);
1830 }
1831
1832 /* Algorithm must end with a software breakpoint instruction. */
1833 static int riscv_run_algorithm(struct target *target, int num_mem_params,
1834                 struct mem_param *mem_params, int num_reg_params,
1835                 struct reg_param *reg_params, target_addr_t entry_point,
1836                 target_addr_t exit_point, int timeout_ms, void *arch_info)
1837 {
1838         RISCV_INFO(info);
1839
1840         if (num_mem_params > 0) {
1841                 LOG_ERROR("Memory parameters are not supported for RISC-V algorithms.");
1842                 return ERROR_FAIL;
1843         }
1844
1845         if (target->state != TARGET_HALTED) {
1846                 LOG_WARNING("target not halted");
1847                 return ERROR_TARGET_NOT_HALTED;
1848         }
1849
1850         /* Save registers */
1851         struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", true);
1852         if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK)
1853                 return ERROR_FAIL;
1854         uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1855         LOG_DEBUG("saved_pc=0x%" PRIx64, saved_pc);
1856
1857         uint64_t saved_regs[32];
1858         for (int i = 0; i < num_reg_params; i++) {
1859                 LOG_DEBUG("save %s", reg_params[i].reg_name);
1860                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1861                 if (!r) {
1862                         LOG_ERROR("Couldn't find register named '%s'", reg_params[i].reg_name);
1863                         return ERROR_FAIL;
1864                 }
1865
1866                 if (r->size != reg_params[i].size) {
1867                         LOG_ERROR("Register %s is %d bits instead of %d bits.",
1868                                         reg_params[i].reg_name, r->size, reg_params[i].size);
1869                         return ERROR_FAIL;
1870                 }
1871
1872                 if (r->number > GDB_REGNO_XPR31) {
1873                         LOG_ERROR("Only GPRs can be use as argument registers.");
1874                         return ERROR_FAIL;
1875                 }
1876
1877                 if (r->type->get(r) != ERROR_OK)
1878                         return ERROR_FAIL;
1879                 saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
1880
1881                 if (reg_params[i].direction == PARAM_OUT || reg_params[i].direction == PARAM_IN_OUT) {
1882                         if (r->type->set(r, reg_params[i].value) != ERROR_OK)
1883                                 return ERROR_FAIL;
1884                 }
1885         }
1886
1887
1888         /* Disable Interrupts before attempting to run the algorithm. */
1889         uint64_t current_mstatus;
1890         uint8_t mstatus_bytes[8] = { 0 };
1891
1892         LOG_DEBUG("Disabling Interrupts");
1893         struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
1894                         "mstatus", true);
1895         if (!reg_mstatus) {
1896                 LOG_ERROR("Couldn't find mstatus!");
1897                 return ERROR_FAIL;
1898         }
1899
1900         reg_mstatus->type->get(reg_mstatus);
1901         current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
1902         uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
1903         buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
1904                                 ie_mask, 0));
1905
1906         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1907
1908         /* Run algorithm */
1909         LOG_DEBUG("resume at 0x%" TARGET_PRIxADDR, entry_point);
1910         if (riscv_resume(target, 0, entry_point, 0, 0, true) != ERROR_OK)
1911                 return ERROR_FAIL;
1912
1913         int64_t start = timeval_ms();
1914         while (target->state != TARGET_HALTED) {
1915                 LOG_DEBUG("poll()");
1916                 int64_t now = timeval_ms();
1917                 if (now - start > timeout_ms) {
1918                         LOG_ERROR("Algorithm timed out after %" PRId64 " ms.", now - start);
1919                         riscv_halt(target);
1920                         old_or_new_riscv_poll(target);
1921                         enum gdb_regno regnums[] = {
1922                                 GDB_REGNO_RA, GDB_REGNO_SP, GDB_REGNO_GP, GDB_REGNO_TP,
1923                                 GDB_REGNO_T0, GDB_REGNO_T1, GDB_REGNO_T2, GDB_REGNO_FP,
1924                                 GDB_REGNO_S1, GDB_REGNO_A0, GDB_REGNO_A1, GDB_REGNO_A2,
1925                                 GDB_REGNO_A3, GDB_REGNO_A4, GDB_REGNO_A5, GDB_REGNO_A6,
1926                                 GDB_REGNO_A7, GDB_REGNO_S2, GDB_REGNO_S3, GDB_REGNO_S4,
1927                                 GDB_REGNO_S5, GDB_REGNO_S6, GDB_REGNO_S7, GDB_REGNO_S8,
1928                                 GDB_REGNO_S9, GDB_REGNO_S10, GDB_REGNO_S11, GDB_REGNO_T3,
1929                                 GDB_REGNO_T4, GDB_REGNO_T5, GDB_REGNO_T6,
1930                                 GDB_REGNO_PC,
1931                                 GDB_REGNO_MSTATUS, GDB_REGNO_MEPC, GDB_REGNO_MCAUSE,
1932                         };
1933                         for (unsigned i = 0; i < ARRAY_SIZE(regnums); i++) {
1934                                 enum gdb_regno regno = regnums[i];
1935                                 riscv_reg_t reg_value;
1936                                 if (riscv_get_register(target, &reg_value, regno) != ERROR_OK)
1937                                         break;
1938                                 LOG_ERROR("%s = 0x%" PRIx64, gdb_regno_name(regno), reg_value);
1939                         }
1940                         return ERROR_TARGET_TIMEOUT;
1941                 }
1942
1943                 int result = old_or_new_riscv_poll(target);
1944                 if (result != ERROR_OK)
1945                         return result;
1946         }
1947
1948         /* The current hart id might have been changed in poll(). */
1949         if (riscv_select_current_hart(target) != ERROR_OK)
1950                 return ERROR_FAIL;
1951
1952         if (reg_pc->type->get(reg_pc) != ERROR_OK)
1953                 return ERROR_FAIL;
1954         uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
1955         if (exit_point && final_pc != exit_point) {
1956                 LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%"
1957                                 TARGET_PRIxADDR, final_pc, exit_point);
1958                 return ERROR_FAIL;
1959         }
1960
1961         /* Restore Interrupts */
1962         LOG_DEBUG("Restoring Interrupts");
1963         buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
1964         reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
1965
1966         /* Restore registers */
1967         uint8_t buf[8] = { 0 };
1968         buf_set_u64(buf, 0, info->xlen, saved_pc);
1969         if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
1970                 return ERROR_FAIL;
1971
1972         for (int i = 0; i < num_reg_params; i++) {
1973                 if (reg_params[i].direction == PARAM_IN ||
1974                                 reg_params[i].direction == PARAM_IN_OUT) {
1975                         struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1976                         if (r->type->get(r) != ERROR_OK) {
1977                                 LOG_ERROR("get(%s) failed", r->name);
1978                                 return ERROR_FAIL;
1979                         }
1980                         buf_cpy(r->value, reg_params[i].value, reg_params[i].size);
1981                 }
1982                 LOG_DEBUG("restore %s", reg_params[i].reg_name);
1983                 struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, false);
1984                 buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
1985                 if (r->type->set(r, buf) != ERROR_OK) {
1986                         LOG_ERROR("set(%s) failed", r->name);
1987                         return ERROR_FAIL;
1988                 }
1989         }
1990
1991         return ERROR_OK;
1992 }
1993
1994 static int riscv_checksum_memory(struct target *target,
1995                 target_addr_t address, uint32_t count,
1996                 uint32_t *checksum)
1997 {
1998         struct working_area *crc_algorithm;
1999         struct reg_param reg_params[2];
2000         int retval;
2001
2002         LOG_DEBUG("address=0x%" TARGET_PRIxADDR "; count=0x%" PRIx32, address, count);
2003
2004         static const uint8_t riscv32_crc_code[] = {
2005 #include "../../../contrib/loaders/checksum/riscv32_crc.inc"
2006         };
2007         static const uint8_t riscv64_crc_code[] = {
2008 #include "../../../contrib/loaders/checksum/riscv64_crc.inc"
2009         };
2010
2011         static const uint8_t *crc_code;
2012
2013         unsigned xlen = riscv_xlen(target);
2014         unsigned crc_code_size;
2015         if (xlen == 32) {
2016                 crc_code = riscv32_crc_code;
2017                 crc_code_size = sizeof(riscv32_crc_code);
2018         } else {
2019                 crc_code = riscv64_crc_code;
2020                 crc_code_size = sizeof(riscv64_crc_code);
2021         }
2022
2023         if (count < crc_code_size * 4) {
2024                 /* Don't use the algorithm for relatively small buffers. It's faster
2025                  * just to read the memory.  target_checksum_memory() will take care of
2026                  * that if we fail. */
2027                 return ERROR_FAIL;
2028         }
2029
2030         retval = target_alloc_working_area(target, crc_code_size, &crc_algorithm);
2031         if (retval != ERROR_OK)
2032                 return retval;
2033
2034         if (crc_algorithm->address + crc_algorithm->size > address &&
2035                         crc_algorithm->address < address + count) {
2036                 /* Region to checksum overlaps with the work area we've been assigned.
2037                  * Bail. (Would be better to manually checksum what we read there, and
2038                  * use the algorithm for the rest.) */
2039                 target_free_working_area(target, crc_algorithm);
2040                 return ERROR_FAIL;
2041         }
2042
2043         retval = target_write_buffer(target, crc_algorithm->address, crc_code_size,
2044                         crc_code);
2045         if (retval != ERROR_OK) {
2046                 LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
2047                                 crc_algorithm->address, retval);
2048                 target_free_working_area(target, crc_algorithm);
2049                 return retval;
2050         }
2051
2052         init_reg_param(&reg_params[0], "a0", xlen, PARAM_IN_OUT);
2053         init_reg_param(&reg_params[1], "a1", xlen, PARAM_OUT);
2054         buf_set_u64(reg_params[0].value, 0, xlen, address);
2055         buf_set_u64(reg_params[1].value, 0, xlen, count);
2056
2057         /* 20 second timeout/megabyte */
2058         int timeout = 20000 * (1 + (count / (1024 * 1024)));
2059
2060         retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
2061                         crc_algorithm->address,
2062                         0,      /* Leave exit point unspecified because we don't know. */
2063                         timeout, NULL);
2064
2065         if (retval == ERROR_OK)
2066                 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
2067         else
2068                 LOG_ERROR("error executing RISC-V CRC algorithm");
2069
2070         destroy_reg_param(&reg_params[0]);
2071         destroy_reg_param(&reg_params[1]);
2072
2073         target_free_working_area(target, crc_algorithm);
2074
2075         LOG_DEBUG("checksum=0x%" PRIx32 ", result=%d", *checksum, retval);
2076
2077         return retval;
2078 }
2079
2080 /*** OpenOCD Helper Functions ***/
2081
2082 enum riscv_poll_hart {
2083         RPH_NO_CHANGE,
2084         RPH_DISCOVERED_HALTED,
2085         RPH_DISCOVERED_RUNNING,
2086         RPH_ERROR
2087 };
2088 static enum riscv_poll_hart riscv_poll_hart(struct target *target, int hartid)
2089 {
2090         RISCV_INFO(r);
2091         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
2092                 return RPH_ERROR;
2093
2094         LOG_DEBUG("polling hart %d, target->state=%d", hartid, target->state);
2095
2096         /* If OpenOCD thinks we're running but this hart is halted then it's time
2097          * to raise an event. */
2098         bool halted = riscv_is_halted(target);
2099         if (target->state != TARGET_HALTED && halted) {
2100                 LOG_DEBUG("  triggered a halt");
2101                 r->on_halt(target);
2102                 return RPH_DISCOVERED_HALTED;
2103         } else if (target->state != TARGET_RUNNING && !halted) {
2104                 LOG_DEBUG("  triggered running");
2105                 target->state = TARGET_RUNNING;
2106                 target->debug_reason = DBG_REASON_NOTHALTED;
2107                 return RPH_DISCOVERED_RUNNING;
2108         }
2109
2110         return RPH_NO_CHANGE;
2111 }
2112
2113 static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
2114 {
2115         switch (halt_reason) {
2116                 case RISCV_HALT_BREAKPOINT:
2117                         target->debug_reason = DBG_REASON_BREAKPOINT;
2118                         break;
2119                 case RISCV_HALT_TRIGGER:
2120                         target->debug_reason = DBG_REASON_WATCHPOINT;
2121                         break;
2122                 case RISCV_HALT_INTERRUPT:
2123                 case RISCV_HALT_GROUP:
2124                         target->debug_reason = DBG_REASON_DBGRQ;
2125                         break;
2126                 case RISCV_HALT_SINGLESTEP:
2127                         target->debug_reason = DBG_REASON_SINGLESTEP;
2128                         break;
2129                 case RISCV_HALT_UNKNOWN:
2130                         target->debug_reason = DBG_REASON_UNDEFINED;
2131                         break;
2132                 case RISCV_HALT_ERROR:
2133                         return ERROR_FAIL;
2134         }
2135         LOG_DEBUG("[%s] debug_reason=%d", target_name(target), target->debug_reason);
2136         return ERROR_OK;
2137 }
2138
2139 static int sample_memory(struct target *target)
2140 {
2141         RISCV_INFO(r);
2142
2143         if (!r->sample_buf.buf || !r->sample_config.enabled)
2144                 return ERROR_OK;
2145
2146         LOG_DEBUG("buf used/size: %d/%d", r->sample_buf.used, r->sample_buf.size);
2147
2148         uint64_t start = timeval_ms();
2149         riscv_sample_buf_maybe_add_timestamp(target, true);
2150         int result = ERROR_OK;
2151         if (r->sample_memory) {
2152                 result = r->sample_memory(target, &r->sample_buf, &r->sample_config,
2153                                                                           start + TARGET_DEFAULT_POLLING_INTERVAL);
2154                 if (result != ERROR_NOT_IMPLEMENTED)
2155                         goto exit;
2156         }
2157
2158         /* Default slow path. */
2159         while (timeval_ms() - start < TARGET_DEFAULT_POLLING_INTERVAL) {
2160                 for (unsigned int i = 0; i < ARRAY_SIZE(r->sample_config.bucket); i++) {
2161                         if (r->sample_config.bucket[i].enabled &&
2162                                         r->sample_buf.used + 1 + r->sample_config.bucket[i].size_bytes < r->sample_buf.size) {
2163                                 assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
2164                                 r->sample_buf.buf[r->sample_buf.used] = i;
2165                                 result = riscv_read_phys_memory(
2166                                         target, r->sample_config.bucket[i].address,
2167                                         r->sample_config.bucket[i].size_bytes, 1,
2168                                         r->sample_buf.buf + r->sample_buf.used + 1);
2169                                 if (result == ERROR_OK)
2170                                         r->sample_buf.used += 1 + r->sample_config.bucket[i].size_bytes;
2171                                 else
2172                                         goto exit;
2173                         }
2174                 }
2175         }
2176
2177 exit:
2178         riscv_sample_buf_maybe_add_timestamp(target, false);
2179         if (result != ERROR_OK) {
2180                 LOG_INFO("Turning off memory sampling because it failed.");
2181                 r->sample_config.enabled = false;
2182         }
2183         return result;
2184 }
2185
2186 /*** OpenOCD Interface ***/
2187 int riscv_openocd_poll(struct target *target)
2188 {
2189         LOG_DEBUG("polling all harts");
2190         int halted_hart = -1;
2191
2192         if (target->smp) {
2193                 unsigned halts_discovered = 0;
2194                 unsigned should_remain_halted = 0;
2195                 unsigned should_resume = 0;
2196                 struct target_list *list;
2197                 foreach_smp_target(list, target->smp_targets) {
2198                         struct target *t = list->target;
2199                         struct riscv_info *r = riscv_info(t);
2200                         enum riscv_poll_hart out = riscv_poll_hart(t, r->current_hartid);
2201                         switch (out) {
2202                         case RPH_NO_CHANGE:
2203                                 break;
2204                         case RPH_DISCOVERED_RUNNING:
2205                                 t->state = TARGET_RUNNING;
2206                                 t->debug_reason = DBG_REASON_NOTHALTED;
2207                                 break;
2208                         case RPH_DISCOVERED_HALTED:
2209                                 halts_discovered++;
2210                                 t->state = TARGET_HALTED;
2211                                 enum riscv_halt_reason halt_reason =
2212                                         riscv_halt_reason(t, r->current_hartid);
2213                                 if (set_debug_reason(t, halt_reason) != ERROR_OK)
2214                                         return ERROR_FAIL;
2215
2216                                 if (halt_reason == RISCV_HALT_BREAKPOINT) {
2217                                         int retval;
2218                                         switch (riscv_semihosting(t, &retval)) {
2219                                         case SEMIHOSTING_NONE:
2220                                         case SEMIHOSTING_WAITING:
2221                                                 /* This hart should remain halted. */
2222                                                 should_remain_halted++;
2223                                                 break;
2224                                         case SEMIHOSTING_HANDLED:
2225                                                 /* This hart should be resumed, along with any other
2226                                                          * harts that halted due to haltgroups. */
2227                                                 should_resume++;
2228                                                 break;
2229                                         case SEMIHOSTING_ERROR:
2230                                                 return retval;
2231                                         }
2232                                 } else if (halt_reason != RISCV_HALT_GROUP) {
2233                                         should_remain_halted++;
2234                                 }
2235                                 break;
2236
2237                         case RPH_ERROR:
2238                                 return ERROR_FAIL;
2239                         }
2240                 }
2241
2242                 LOG_DEBUG("should_remain_halted=%d, should_resume=%d",
2243                                   should_remain_halted, should_resume);
2244                 if (should_remain_halted && should_resume) {
2245                         LOG_WARNING("%d harts should remain halted, and %d should resume.",
2246                                                 should_remain_halted, should_resume);
2247                 }
2248                 if (should_remain_halted) {
2249                         LOG_DEBUG("halt all");
2250                         riscv_halt(target);
2251                 } else if (should_resume) {
2252                         LOG_DEBUG("resume all");
2253                         riscv_resume(target, true, 0, 0, 0, false);
2254                 }
2255
2256                 /* Sample memory if any target is running. */
2257                 foreach_smp_target(list, target->smp_targets) {
2258                         struct target *t = list->target;
2259                         if (t->state == TARGET_RUNNING) {
2260                                 sample_memory(target);
2261                                 break;
2262                         }
2263                 }
2264
2265                 return ERROR_OK;
2266
2267         } else {
2268                 enum riscv_poll_hart out = riscv_poll_hart(target,
2269                                 riscv_current_hartid(target));
2270                 if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
2271                         if (target->state == TARGET_RUNNING)
2272                                 sample_memory(target);
2273                         return ERROR_OK;
2274                 } else if (out == RPH_ERROR) {
2275                         return ERROR_FAIL;
2276                 }
2277
2278                 halted_hart = riscv_current_hartid(target);
2279                 LOG_DEBUG("  hart %d halted", halted_hart);
2280
2281                 enum riscv_halt_reason halt_reason = riscv_halt_reason(target, halted_hart);
2282                 if (set_debug_reason(target, halt_reason) != ERROR_OK)
2283                         return ERROR_FAIL;
2284                 target->state = TARGET_HALTED;
2285         }
2286
2287         if (target->debug_reason == DBG_REASON_BREAKPOINT) {
2288                 int retval;
2289                 switch (riscv_semihosting(target, &retval)) {
2290                         case SEMIHOSTING_NONE:
2291                         case SEMIHOSTING_WAITING:
2292                                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2293                                 break;
2294                         case SEMIHOSTING_HANDLED:
2295                                 if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK)
2296                                         return ERROR_FAIL;
2297                                 break;
2298                         case SEMIHOSTING_ERROR:
2299                                 return retval;
2300                 }
2301         } else {
2302                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2303         }
2304
2305         return ERROR_OK;
2306 }
2307
2308 int riscv_openocd_step(struct target *target, int current,
2309                 target_addr_t address, int handle_breakpoints)
2310 {
2311         LOG_DEBUG("stepping rtos hart");
2312
2313         if (!current)
2314                 riscv_set_register(target, GDB_REGNO_PC, address);
2315
2316         riscv_reg_t trigger_state[RISCV_MAX_HWBPS] = {0};
2317         if (disable_triggers(target, trigger_state) != ERROR_OK)
2318                 return ERROR_FAIL;
2319
2320         int out = riscv_step_rtos_hart(target);
2321         if (out != ERROR_OK) {
2322                 LOG_ERROR("unable to step rtos hart");
2323                 return out;
2324         }
2325
2326         register_cache_invalidate(target->reg_cache);
2327
2328         if (enable_triggers(target, trigger_state) != ERROR_OK)
2329                 return ERROR_FAIL;
2330
2331         target->state = TARGET_RUNNING;
2332         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
2333         target->state = TARGET_HALTED;
2334         target->debug_reason = DBG_REASON_SINGLESTEP;
2335         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
2336         return out;
2337 }
2338
2339 /* Command Handlers */
2340 COMMAND_HANDLER(riscv_set_command_timeout_sec)
2341 {
2342         if (CMD_ARGC != 1) {
2343                 LOG_ERROR("Command takes exactly 1 parameter");
2344                 return ERROR_COMMAND_SYNTAX_ERROR;
2345         }
2346         int timeout = atoi(CMD_ARGV[0]);
2347         if (timeout <= 0) {
2348                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2349                 return ERROR_FAIL;
2350         }
2351
2352         riscv_command_timeout_sec = timeout;
2353
2354         return ERROR_OK;
2355 }
2356
2357 COMMAND_HANDLER(riscv_set_reset_timeout_sec)
2358 {
2359         if (CMD_ARGC != 1) {
2360                 LOG_ERROR("Command takes exactly 1 parameter");
2361                 return ERROR_COMMAND_SYNTAX_ERROR;
2362         }
2363         int timeout = atoi(CMD_ARGV[0]);
2364         if (timeout <= 0) {
2365                 LOG_ERROR("%s is not a valid integer argument for command.", CMD_ARGV[0]);
2366                 return ERROR_FAIL;
2367         }
2368
2369         riscv_reset_timeout_sec = timeout;
2370         return ERROR_OK;
2371 }
2372
2373 COMMAND_HANDLER(riscv_set_prefer_sba)
2374 {
2375         struct target *target = get_current_target(CMD_CTX);
2376         RISCV_INFO(r);
2377         bool prefer_sba;
2378         LOG_WARNING("`riscv set_prefer_sba` is deprecated. Please use `riscv set_mem_access` instead.");
2379         if (CMD_ARGC != 1) {
2380                 LOG_ERROR("Command takes exactly 1 parameter");
2381                 return ERROR_COMMAND_SYNTAX_ERROR;
2382         }
2383         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], prefer_sba);
2384         if (prefer_sba) {
2385                 /* Use system bus with highest priority */
2386                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_SYSBUS;
2387                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_PROGBUF;
2388                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2389         } else {
2390                 /* Use progbuf with highest priority */
2391                 r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
2392                 r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
2393                 r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
2394         }
2395
2396         /* Reset warning flags */
2397         r->mem_access_progbuf_warn = true;
2398         r->mem_access_sysbus_warn = true;
2399         r->mem_access_abstract_warn = true;
2400
2401         return ERROR_OK;
2402 }
2403
2404 COMMAND_HANDLER(riscv_set_mem_access)
2405 {
2406         struct target *target = get_current_target(CMD_CTX);
2407         RISCV_INFO(r);
2408         int progbuf_cnt = 0;
2409         int sysbus_cnt = 0;
2410         int abstract_cnt = 0;
2411
2412         if (CMD_ARGC < 1 || CMD_ARGC > RISCV_NUM_MEM_ACCESS_METHODS) {
2413                 LOG_ERROR("Command takes 1 to %d parameters", RISCV_NUM_MEM_ACCESS_METHODS);
2414                 return ERROR_COMMAND_SYNTAX_ERROR;
2415         }
2416
2417         /* Check argument validity */
2418         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2419                 if (strcmp("progbuf", CMD_ARGV[i]) == 0) {
2420                         progbuf_cnt++;
2421                 } else if (strcmp("sysbus", CMD_ARGV[i]) == 0) {
2422                         sysbus_cnt++;
2423                 } else if (strcmp("abstract", CMD_ARGV[i]) == 0) {
2424                         abstract_cnt++;
2425                 } else {
2426                         LOG_ERROR("Unknown argument '%s'. "
2427                                 "Must be one of: 'progbuf', 'sysbus' or 'abstract'.", CMD_ARGV[i]);
2428                         return ERROR_COMMAND_SYNTAX_ERROR;
2429                 }
2430         }
2431         if (progbuf_cnt > 1 || sysbus_cnt > 1 || abstract_cnt > 1) {
2432                 LOG_ERROR("Syntax error - duplicate arguments to `riscv set_mem_access`.");
2433                 return ERROR_COMMAND_SYNTAX_ERROR;
2434         }
2435
2436         /* Args are valid, store them */
2437         for (unsigned int i = 0; i < RISCV_NUM_MEM_ACCESS_METHODS; i++)
2438                 r->mem_access_methods[i] = RISCV_MEM_ACCESS_UNSPECIFIED;
2439         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2440                 if (strcmp("progbuf", CMD_ARGV[i]) == 0)
2441                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_PROGBUF;
2442                 else if (strcmp("sysbus", CMD_ARGV[i]) == 0)
2443                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_SYSBUS;
2444                 else if (strcmp("abstract", CMD_ARGV[i]) == 0)
2445                         r->mem_access_methods[i] = RISCV_MEM_ACCESS_ABSTRACT;
2446         }
2447
2448         /* Reset warning flags */
2449         r->mem_access_progbuf_warn = true;
2450         r->mem_access_sysbus_warn = true;
2451         r->mem_access_abstract_warn = true;
2452
2453         return ERROR_OK;
2454 }
2455
2456 COMMAND_HANDLER(riscv_set_enable_virtual)
2457 {
2458         if (CMD_ARGC != 1) {
2459                 LOG_ERROR("Command takes exactly 1 parameter");
2460                 return ERROR_COMMAND_SYNTAX_ERROR;
2461         }
2462         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virtual);
2463         return ERROR_OK;
2464 }
2465
2466 static int parse_ranges(struct list_head *ranges, const char *tcl_arg, const char *reg_type, unsigned int max_val)
2467 {
2468         char *args = strdup(tcl_arg);
2469         if (!args)
2470                 return ERROR_FAIL;
2471
2472         /* For backward compatibility, allow multiple parameters within one TCL argument, separated by ',' */
2473         char *arg = strtok(args, ",");
2474         while (arg) {
2475                 unsigned low = 0;
2476                 unsigned high = 0;
2477                 char *name = NULL;
2478
2479                 char *dash = strchr(arg, '-');
2480                 char *equals = strchr(arg, '=');
2481                 unsigned int pos;
2482
2483                 if (!dash && !equals) {
2484                         /* Expecting single register number. */
2485                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2486                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2487                                 free(args);
2488                                 return ERROR_COMMAND_SYNTAX_ERROR;
2489                         }
2490                 } else if (dash && !equals) {
2491                         /* Expecting register range - two numbers separated by a dash: ##-## */
2492                         *dash = 0;
2493                         dash++;
2494                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2495                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2496                                 free(args);
2497                                 return ERROR_COMMAND_SYNTAX_ERROR;
2498                         }
2499                         if (sscanf(dash, "%u%n", &high, &pos) != 1 || pos != strlen(dash)) {
2500                                 LOG_ERROR("Failed to parse single register number from '%s'.", dash);
2501                                 free(args);
2502                                 return ERROR_COMMAND_SYNTAX_ERROR;
2503                         }
2504                         if (high < low) {
2505                                 LOG_ERROR("Incorrect range encountered [%u, %u].", low, high);
2506                                 free(args);
2507                                 return ERROR_FAIL;
2508                         }
2509                 } else if (!dash && equals) {
2510                         /* Expecting single register number with textual name specified: ##=name */
2511                         *equals = 0;
2512                         equals++;
2513                         if (sscanf(arg, "%u%n", &low, &pos) != 1 || pos != strlen(arg)) {
2514                                 LOG_ERROR("Failed to parse single register number from '%s'.", arg);
2515                                 free(args);
2516                                 return ERROR_COMMAND_SYNTAX_ERROR;
2517                         }
2518
2519                         name = calloc(1, strlen(equals) + strlen(reg_type) + 2);
2520                         if (!name) {
2521                                 LOG_ERROR("Failed to allocate register name.");
2522                                 free(args);
2523                                 return ERROR_FAIL;
2524                         }
2525
2526                         /* Register prefix: "csr_" or "custom_" */
2527                         strcpy(name, reg_type);
2528                         name[strlen(reg_type)] = '_';
2529
2530                         if (sscanf(equals, "%[_a-zA-Z0-9]%n", name + strlen(reg_type) + 1, &pos) != 1 || pos != strlen(equals)) {
2531                                 LOG_ERROR("Failed to parse register name from '%s'.", equals);
2532                                 free(args);
2533                                 free(name);
2534                                 return ERROR_COMMAND_SYNTAX_ERROR;
2535                         }
2536                 } else {
2537                         LOG_ERROR("Invalid argument '%s'.", arg);
2538                         free(args);
2539                         return ERROR_COMMAND_SYNTAX_ERROR;
2540                 }
2541
2542                 high = high > low ? high : low;
2543
2544                 if (high > max_val) {
2545                         LOG_ERROR("Cannot expose %s register number %u, maximum allowed value is %u.", reg_type, high, max_val);
2546                         free(name);
2547                         free(args);
2548                         return ERROR_FAIL;
2549                 }
2550
2551                 /* Check for overlap, name uniqueness. */
2552                 range_list_t *entry;
2553                 list_for_each_entry(entry, ranges, list) {
2554                         if ((entry->low <= high) && (low <= entry->high)) {
2555                                 if (low == high)
2556                                         LOG_WARNING("Duplicate %s register number - "
2557                                                         "Register %u has already been exposed previously", reg_type, low);
2558                                 else
2559                                         LOG_WARNING("Overlapping register ranges - Register range starting from %u overlaps "
2560                                                         "with already exposed register/range at %u.", low, entry->low);
2561                         }
2562
2563                         if (entry->name && name && (strcasecmp(entry->name, name) == 0)) {
2564                                 LOG_ERROR("Duplicate register name \"%s\" found.", name);
2565                                 free(name);
2566                                 free(args);
2567                                 return ERROR_FAIL;
2568                         }
2569                 }
2570
2571                 range_list_t *range = calloc(1, sizeof(range_list_t));
2572                 if (!range) {
2573                         LOG_ERROR("Failed to allocate range list.");
2574                         free(name);
2575                         free(args);
2576                         return ERROR_FAIL;
2577                 }
2578
2579                 range->low = low;
2580                 range->high = high;
2581                 range->name = name;
2582                 list_add(&range->list, ranges);
2583
2584                 arg = strtok(NULL, ",");
2585         }
2586
2587         free(args);
2588         return ERROR_OK;
2589 }
2590
2591 COMMAND_HANDLER(riscv_set_expose_csrs)
2592 {
2593         if (CMD_ARGC == 0) {
2594                 LOG_ERROR("Command expects parameters");
2595                 return ERROR_COMMAND_SYNTAX_ERROR;
2596         }
2597
2598         struct target *target = get_current_target(CMD_CTX);
2599         RISCV_INFO(info);
2600         int ret = ERROR_OK;
2601
2602         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2603                 ret = parse_ranges(&info->expose_csr, CMD_ARGV[i], "csr", 0xfff);
2604                 if (ret != ERROR_OK)
2605                         break;
2606         }
2607
2608         return ret;
2609 }
2610
2611 COMMAND_HANDLER(riscv_set_expose_custom)
2612 {
2613         if (CMD_ARGC == 0) {
2614                 LOG_ERROR("Command expects parameters");
2615                 return ERROR_COMMAND_SYNTAX_ERROR;
2616         }
2617
2618         struct target *target = get_current_target(CMD_CTX);
2619         RISCV_INFO(info);
2620         int ret = ERROR_OK;
2621
2622         for (unsigned int i = 0; i < CMD_ARGC; i++) {
2623                 ret = parse_ranges(&info->expose_custom, CMD_ARGV[i], "custom", 0x3fff);
2624                 if (ret != ERROR_OK)
2625                         break;
2626         }
2627
2628         return ret;
2629 }
2630
2631 COMMAND_HANDLER(riscv_authdata_read)
2632 {
2633         unsigned int index = 0;
2634         if (CMD_ARGC == 0) {
2635                 /* nop */
2636         } else if (CMD_ARGC == 1) {
2637                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2638         } else {
2639                 LOG_ERROR("Command takes at most one parameter");
2640                 return ERROR_COMMAND_SYNTAX_ERROR;
2641         }
2642
2643         struct target *target = get_current_target(CMD_CTX);
2644         if (!target) {
2645                 LOG_ERROR("target is NULL!");
2646                 return ERROR_FAIL;
2647         }
2648
2649         RISCV_INFO(r);
2650         if (!r) {
2651                 LOG_ERROR("riscv_info is NULL!");
2652                 return ERROR_FAIL;
2653         }
2654
2655         if (r->authdata_read) {
2656                 uint32_t value;
2657                 if (r->authdata_read(target, &value, index) != ERROR_OK)
2658                         return ERROR_FAIL;
2659                 command_print_sameline(CMD, "0x%08" PRIx32, value);
2660                 return ERROR_OK;
2661         } else {
2662                 LOG_ERROR("authdata_read is not implemented for this target.");
2663                 return ERROR_FAIL;
2664         }
2665 }
2666
2667 COMMAND_HANDLER(riscv_authdata_write)
2668 {
2669         uint32_t value;
2670         unsigned int index = 0;
2671
2672         if (CMD_ARGC == 0) {
2673                 /* nop */
2674         } else if (CMD_ARGC == 1) {
2675                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], value);
2676         } else if (CMD_ARGC == 2) {
2677                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], index);
2678                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2679         } else {
2680                 LOG_ERROR("Command takes at most 2 arguments");
2681                 return ERROR_COMMAND_SYNTAX_ERROR;
2682         }
2683
2684         struct target *target = get_current_target(CMD_CTX);
2685         RISCV_INFO(r);
2686
2687         if (r->authdata_write) {
2688                 return r->authdata_write(target, value, index);
2689         } else {
2690                 LOG_ERROR("authdata_write is not implemented for this target.");
2691                 return ERROR_FAIL;
2692         }
2693 }
2694
2695 COMMAND_HANDLER(riscv_dmi_read)
2696 {
2697         if (CMD_ARGC != 1) {
2698                 LOG_ERROR("Command takes 1 parameter");
2699                 return ERROR_COMMAND_SYNTAX_ERROR;
2700         }
2701
2702         struct target *target = get_current_target(CMD_CTX);
2703         if (!target) {
2704                 LOG_ERROR("target is NULL!");
2705                 return ERROR_FAIL;
2706         }
2707
2708         RISCV_INFO(r);
2709         if (!r) {
2710                 LOG_ERROR("riscv_info is NULL!");
2711                 return ERROR_FAIL;
2712         }
2713
2714         if (r->dmi_read) {
2715                 uint32_t address, value;
2716                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2717                 if (r->dmi_read(target, &value, address) != ERROR_OK)
2718                         return ERROR_FAIL;
2719                 command_print(CMD, "0x%" PRIx32, value);
2720                 return ERROR_OK;
2721         } else {
2722                 LOG_ERROR("dmi_read is not implemented for this target.");
2723                 return ERROR_FAIL;
2724         }
2725 }
2726
2727
2728 COMMAND_HANDLER(riscv_dmi_write)
2729 {
2730         if (CMD_ARGC != 2) {
2731                 LOG_ERROR("Command takes exactly 2 arguments");
2732                 return ERROR_COMMAND_SYNTAX_ERROR;
2733         }
2734
2735         struct target *target = get_current_target(CMD_CTX);
2736         RISCV_INFO(r);
2737
2738         uint32_t address, value;
2739         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
2740         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2741
2742         if (r->dmi_write) {
2743                 return r->dmi_write(target, address, value);
2744         } else {
2745                 LOG_ERROR("dmi_write is not implemented for this target.");
2746                 return ERROR_FAIL;
2747         }
2748 }
2749
2750 COMMAND_HANDLER(riscv_test_sba_config_reg)
2751 {
2752         if (CMD_ARGC != 4) {
2753                 LOG_ERROR("Command takes exactly 4 arguments");
2754                 return ERROR_COMMAND_SYNTAX_ERROR;
2755         }
2756
2757         struct target *target = get_current_target(CMD_CTX);
2758         RISCV_INFO(r);
2759
2760         target_addr_t legal_address;
2761         uint32_t num_words;
2762         target_addr_t illegal_address;
2763         bool run_sbbusyerror_test;
2764
2765         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[0], legal_address);
2766         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], num_words);
2767         COMMAND_PARSE_NUMBER(target_addr, CMD_ARGV[2], illegal_address);
2768         COMMAND_PARSE_ON_OFF(CMD_ARGV[3], run_sbbusyerror_test);
2769
2770         if (r->test_sba_config_reg) {
2771                 return r->test_sba_config_reg(target, legal_address, num_words,
2772                                 illegal_address, run_sbbusyerror_test);
2773         } else {
2774                 LOG_ERROR("test_sba_config_reg is not implemented for this target.");
2775                 return ERROR_FAIL;
2776         }
2777 }
2778
2779 COMMAND_HANDLER(riscv_reset_delays)
2780 {
2781         int wait = 0;
2782
2783         if (CMD_ARGC > 1) {
2784                 LOG_ERROR("Command takes at most one argument");
2785                 return ERROR_COMMAND_SYNTAX_ERROR;
2786         }
2787
2788         if (CMD_ARGC == 1)
2789                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], wait);
2790
2791         struct target *target = get_current_target(CMD_CTX);
2792         RISCV_INFO(r);
2793         r->reset_delays_wait = wait;
2794         return ERROR_OK;
2795 }
2796
2797 COMMAND_HANDLER(riscv_set_ir)
2798 {
2799         if (CMD_ARGC != 2) {
2800                 LOG_ERROR("Command takes exactly 2 arguments");
2801                 return ERROR_COMMAND_SYNTAX_ERROR;
2802         }
2803
2804         uint32_t value;
2805         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
2806
2807         if (!strcmp(CMD_ARGV[0], "idcode"))
2808                 buf_set_u32(ir_idcode, 0, 32, value);
2809         else if (!strcmp(CMD_ARGV[0], "dtmcs"))
2810                 buf_set_u32(ir_dtmcontrol, 0, 32, value);
2811         else if (!strcmp(CMD_ARGV[0], "dmi"))
2812                 buf_set_u32(ir_dbus, 0, 32, value);
2813         else
2814                 return ERROR_FAIL;
2815
2816         return ERROR_OK;
2817 }
2818
2819 COMMAND_HANDLER(riscv_resume_order)
2820 {
2821         if (CMD_ARGC > 1) {
2822                 LOG_ERROR("Command takes at most one argument");
2823                 return ERROR_COMMAND_SYNTAX_ERROR;
2824         }
2825
2826         if (!strcmp(CMD_ARGV[0], "normal")) {
2827                 resume_order = RO_NORMAL;
2828         } else if (!strcmp(CMD_ARGV[0], "reversed")) {
2829                 resume_order = RO_REVERSED;
2830         } else {
2831                 LOG_ERROR("Unsupported resume order: %s", CMD_ARGV[0]);
2832                 return ERROR_FAIL;
2833         }
2834
2835         return ERROR_OK;
2836 }
2837
2838 COMMAND_HANDLER(riscv_use_bscan_tunnel)
2839 {
2840         int irwidth = 0;
2841         int tunnel_type = BSCAN_TUNNEL_NESTED_TAP;
2842
2843         if (CMD_ARGC > 2) {
2844                 LOG_ERROR("Command takes at most two arguments");
2845                 return ERROR_COMMAND_SYNTAX_ERROR;
2846         } else if (CMD_ARGC == 1) {
2847                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2848         } else if (CMD_ARGC == 2) {
2849                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], irwidth);
2850                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tunnel_type);
2851         }
2852         if (tunnel_type == BSCAN_TUNNEL_NESTED_TAP)
2853                 LOG_INFO("Nested Tap based Bscan Tunnel Selected");
2854         else if (tunnel_type == BSCAN_TUNNEL_DATA_REGISTER)
2855                 LOG_INFO("Simple Register based Bscan Tunnel Selected");
2856         else
2857                 LOG_INFO("Invalid Tunnel type selected ! : selecting default Nested Tap Type");
2858
2859         bscan_tunnel_type = tunnel_type;
2860         bscan_tunnel_ir_width = irwidth;
2861         return ERROR_OK;
2862 }
2863
2864 COMMAND_HANDLER(riscv_set_enable_virt2phys)
2865 {
2866         if (CMD_ARGC != 1) {
2867                 LOG_ERROR("Command takes exactly 1 parameter");
2868                 return ERROR_COMMAND_SYNTAX_ERROR;
2869         }
2870         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_enable_virt2phys);
2871         return ERROR_OK;
2872 }
2873
2874 COMMAND_HANDLER(riscv_set_ebreakm)
2875 {
2876         if (CMD_ARGC != 1) {
2877                 LOG_ERROR("Command takes exactly 1 parameter");
2878                 return ERROR_COMMAND_SYNTAX_ERROR;
2879         }
2880         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreakm);
2881         return ERROR_OK;
2882 }
2883
2884 COMMAND_HANDLER(riscv_set_ebreaks)
2885 {
2886         if (CMD_ARGC != 1) {
2887                 LOG_ERROR("Command takes exactly 1 parameter");
2888                 return ERROR_COMMAND_SYNTAX_ERROR;
2889         }
2890         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaks);
2891         return ERROR_OK;
2892 }
2893
2894 COMMAND_HANDLER(riscv_set_ebreaku)
2895 {
2896         if (CMD_ARGC != 1) {
2897                 LOG_ERROR("Command takes exactly 1 parameter");
2898                 return ERROR_COMMAND_SYNTAX_ERROR;
2899         }
2900         COMMAND_PARSE_ON_OFF(CMD_ARGV[0], riscv_ebreaku);
2901         return ERROR_OK;
2902 }
2903
2904 COMMAND_HELPER(riscv_print_info_line, const char *section, const char *key,
2905                            unsigned int value)
2906 {
2907         char full_key[80];
2908         snprintf(full_key, sizeof(full_key), "%s.%s", section, key);
2909         command_print(CMD, "%-21s %3d", full_key, value);
2910         return 0;
2911 }
2912
2913 COMMAND_HANDLER(handle_info)
2914 {
2915         struct target *target = get_current_target(CMD_CTX);
2916         RISCV_INFO(r);
2917
2918         /* This output format can be fed directly into TCL's "array set". */
2919
2920         riscv_print_info_line(CMD, "hart", "xlen", riscv_xlen(target));
2921         riscv_enumerate_triggers(target);
2922         riscv_print_info_line(CMD, "hart", "trigger_count",
2923                                                   r->trigger_count);
2924
2925         if (r->print_info)
2926                 return CALL_COMMAND_HANDLER(r->print_info, target);
2927
2928         return 0;
2929 }
2930
2931 static const struct command_registration riscv_exec_command_handlers[] = {
2932         {
2933                 .name = "info",
2934                 .handler = handle_info,
2935                 .mode = COMMAND_EXEC,
2936                 .usage = "",
2937                 .help = "Displays some information OpenOCD detected about the target."
2938         },
2939         {
2940                 .name = "set_command_timeout_sec",
2941                 .handler = riscv_set_command_timeout_sec,
2942                 .mode = COMMAND_ANY,
2943                 .usage = "[sec]",
2944                 .help = "Set the wall-clock timeout (in seconds) for individual commands"
2945         },
2946         {
2947                 .name = "set_reset_timeout_sec",
2948                 .handler = riscv_set_reset_timeout_sec,
2949                 .mode = COMMAND_ANY,
2950                 .usage = "[sec]",
2951                 .help = "Set the wall-clock timeout (in seconds) after reset is deasserted"
2952         },
2953         {
2954                 .name = "set_prefer_sba",
2955                 .handler = riscv_set_prefer_sba,
2956                 .mode = COMMAND_ANY,
2957                 .usage = "on|off",
2958                 .help = "When on, prefer to use System Bus Access to access memory. "
2959                         "When off (default), prefer to use the Program Buffer to access memory."
2960         },
2961         {
2962                 .name = "set_mem_access",
2963                 .handler = riscv_set_mem_access,
2964                 .mode = COMMAND_ANY,
2965                 .usage = "method1 [method2] [method3]",
2966                 .help = "Set which memory access methods shall be used and in which order "
2967                         "of priority. Method can be one of: 'progbuf', 'sysbus' or 'abstract'."
2968         },
2969         {
2970                 .name = "set_enable_virtual",
2971                 .handler = riscv_set_enable_virtual,
2972                 .mode = COMMAND_ANY,
2973                 .usage = "on|off",
2974                 .help = "When on, memory accesses are performed on physical or virtual "
2975                                 "memory depending on the current system configuration. "
2976                                 "When off (default), all memory accessses are performed on physical memory."
2977         },
2978         {
2979                 .name = "expose_csrs",
2980                 .handler = riscv_set_expose_csrs,
2981                 .mode = COMMAND_CONFIG,
2982                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2983                 .help = "Configure a list of inclusive ranges for CSRs to expose in "
2984                                 "addition to the standard ones. This must be executed before "
2985                                 "`init`."
2986         },
2987         {
2988                 .name = "expose_custom",
2989                 .handler = riscv_set_expose_custom,
2990                 .mode = COMMAND_CONFIG,
2991                 .usage = "n0[-m0|=name0][,n1[-m1|=name1]]...",
2992                 .help = "Configure a list of inclusive ranges for custom registers to "
2993                         "expose. custom0 is accessed as abstract register number 0xc000, "
2994                         "etc. This must be executed before `init`."
2995         },
2996         {
2997                 .name = "authdata_read",
2998                 .handler = riscv_authdata_read,
2999                 .usage = "[index]",
3000                 .mode = COMMAND_ANY,
3001                 .help = "Return the 32-bit value read from authdata or authdata0 "
3002                                 "(index=0), or authdata1 (index=1)."
3003         },
3004         {
3005                 .name = "authdata_write",
3006                 .handler = riscv_authdata_write,
3007                 .mode = COMMAND_ANY,
3008                 .usage = "[index] value",
3009                 .help = "Write the 32-bit value to authdata or authdata0 (index=0), "
3010                                 "or authdata1 (index=1)."
3011         },
3012         {
3013                 .name = "dmi_read",
3014                 .handler = riscv_dmi_read,
3015                 .mode = COMMAND_ANY,
3016                 .usage = "address",
3017                 .help = "Perform a 32-bit DMI read at address, returning the value."
3018         },
3019         {
3020                 .name = "dmi_write",
3021                 .handler = riscv_dmi_write,
3022                 .mode = COMMAND_ANY,
3023                 .usage = "address value",
3024                 .help = "Perform a 32-bit DMI write of value at address."
3025         },
3026         {
3027                 .name = "test_sba_config_reg",
3028                 .handler = riscv_test_sba_config_reg,
3029                 .mode = COMMAND_ANY,
3030                 .usage = "legal_address num_words "
3031                         "illegal_address run_sbbusyerror_test[on/off]",
3032                 .help = "Perform a series of tests on the SBCS register. "
3033                         "Inputs are a legal, 128-byte aligned address and a number of words to "
3034                         "read/write starting at that address (i.e., address range [legal address, "
3035                         "legal_address+word_size*num_words) must be legally readable/writable), "
3036                         "an illegal, 128-byte aligned address for error flag/handling cases, "
3037                         "and whether sbbusyerror test should be run."
3038         },
3039         {
3040                 .name = "reset_delays",
3041                 .handler = riscv_reset_delays,
3042                 .mode = COMMAND_ANY,
3043                 .usage = "[wait]",
3044                 .help = "OpenOCD learns how many Run-Test/Idle cycles are required "
3045                         "between scans to avoid encountering the target being busy. This "
3046                         "command resets those learned values after `wait` scans. It's only "
3047                         "useful for testing OpenOCD itself."
3048         },
3049         {
3050                 .name = "resume_order",
3051                 .handler = riscv_resume_order,
3052                 .mode = COMMAND_ANY,
3053                 .usage = "normal|reversed",
3054                 .help = "Choose the order that harts are resumed in when `hasel` is not "
3055                         "supported. Normal order is from lowest hart index to highest. "
3056                         "Reversed order is from highest hart index to lowest."
3057         },
3058         {
3059                 .name = "set_ir",
3060                 .handler = riscv_set_ir,
3061                 .mode = COMMAND_ANY,
3062                 .usage = "[idcode|dtmcs|dmi] value",
3063                 .help = "Set IR value for specified JTAG register."
3064         },
3065         {
3066                 .name = "use_bscan_tunnel",
3067                 .handler = riscv_use_bscan_tunnel,
3068                 .mode = COMMAND_ANY,
3069                 .usage = "value [type]",
3070                 .help = "Enable or disable use of a BSCAN tunnel to reach DM.  Supply "
3071                         "the width of the DM transport TAP's instruction register to "
3072                         "enable.  Supply a value of 0 to disable. Pass A second argument "
3073                         "(optional) to indicate Bscan Tunnel Type {0:(default) NESTED_TAP , "
3074                         "1: DATA_REGISTER}"
3075         },
3076         {
3077                 .name = "set_enable_virt2phys",
3078                 .handler = riscv_set_enable_virt2phys,
3079                 .mode = COMMAND_ANY,
3080                 .usage = "on|off",
3081                 .help = "When on (default), enable translation from virtual address to "
3082                         "physical address."
3083         },
3084         {
3085                 .name = "set_ebreakm",
3086                 .handler = riscv_set_ebreakm,
3087                 .mode = COMMAND_ANY,
3088                 .usage = "on|off",
3089                 .help = "Control dcsr.ebreakm. When off, M-mode ebreak instructions "
3090                         "don't trap to OpenOCD. Defaults to on."
3091         },
3092         {
3093                 .name = "set_ebreaks",
3094                 .handler = riscv_set_ebreaks,
3095                 .mode = COMMAND_ANY,
3096                 .usage = "on|off",
3097                 .help = "Control dcsr.ebreaks. When off, S-mode ebreak instructions "
3098                         "don't trap to OpenOCD. Defaults to on."
3099         },
3100         {
3101                 .name = "set_ebreaku",
3102                 .handler = riscv_set_ebreaku,
3103                 .mode = COMMAND_ANY,
3104                 .usage = "on|off",
3105                 .help = "Control dcsr.ebreaku. When off, U-mode ebreak instructions "
3106                         "don't trap to OpenOCD. Defaults to on."
3107         },
3108         COMMAND_REGISTRATION_DONE
3109 };
3110
3111 /*
3112  * To be noted that RISC-V targets use the same semihosting commands as
3113  * ARM targets.
3114  *
3115  * The main reason is compatibility with existing tools. For example the
3116  * Eclipse OpenOCD/SEGGER J-Link/QEMU plug-ins have several widgets to
3117  * configure semihosting, which generate commands like `arm semihosting
3118  * enable`.
3119  * A secondary reason is the fact that the protocol used is exactly the
3120  * one specified by ARM. If RISC-V will ever define its own semihosting
3121  * protocol, then a command like `riscv semihosting enable` will make
3122  * sense, but for now all semihosting commands are prefixed with `arm`.
3123  */
3124
3125 static const struct command_registration riscv_command_handlers[] = {
3126         {
3127                 .name = "riscv",
3128                 .mode = COMMAND_ANY,
3129                 .help = "RISC-V Command Group",
3130                 .usage = "",
3131                 .chain = riscv_exec_command_handlers
3132         },
3133         {
3134                 .name = "arm",
3135                 .mode = COMMAND_ANY,
3136                 .help = "ARM Command Group",
3137                 .usage = "",
3138                 .chain = semihosting_common_handlers
3139         },
3140         COMMAND_REGISTRATION_DONE
3141 };
3142
3143 static unsigned riscv_xlen_nonconst(struct target *target)
3144 {
3145         return riscv_xlen(target);
3146 }
3147
3148 static unsigned int riscv_data_bits(struct target *target)
3149 {
3150         RISCV_INFO(r);
3151         if (r->data_bits)
3152                 return r->data_bits(target);
3153         return riscv_xlen(target);
3154 }
3155
3156 struct target_type riscv_target = {
3157         .name = "riscv",
3158
3159         .target_create = riscv_create_target,
3160         .init_target = riscv_init_target,
3161         .deinit_target = riscv_deinit_target,
3162         .examine = riscv_examine,
3163
3164         /* poll current target status */
3165         .poll = old_or_new_riscv_poll,
3166
3167         .halt = riscv_halt,
3168         .resume = riscv_target_resume,
3169         .step = old_or_new_riscv_step,
3170
3171         .assert_reset = riscv_assert_reset,
3172         .deassert_reset = riscv_deassert_reset,
3173
3174         .read_memory = riscv_read_memory,
3175         .write_memory = riscv_write_memory,
3176         .read_phys_memory = riscv_read_phys_memory,
3177         .write_phys_memory = riscv_write_phys_memory,
3178
3179         .checksum_memory = riscv_checksum_memory,
3180
3181         .mmu = riscv_mmu,
3182         .virt2phys = riscv_virt2phys,
3183
3184         .get_gdb_arch = riscv_get_gdb_arch,
3185         .get_gdb_reg_list = riscv_get_gdb_reg_list,
3186         .get_gdb_reg_list_noread = riscv_get_gdb_reg_list_noread,
3187
3188         .add_breakpoint = riscv_add_breakpoint,
3189         .remove_breakpoint = riscv_remove_breakpoint,
3190
3191         .add_watchpoint = riscv_add_watchpoint,
3192         .remove_watchpoint = riscv_remove_watchpoint,
3193         .hit_watchpoint = riscv_hit_watchpoint,
3194
3195         .arch_state = riscv_arch_state,
3196
3197         .run_algorithm = riscv_run_algorithm,
3198
3199         .commands = riscv_command_handlers,
3200
3201         .address_bits = riscv_xlen_nonconst,
3202         .data_bits = riscv_data_bits
3203 };
3204
3205 /*** RISC-V Interface ***/
3206
3207 /* Initializes the shared RISC-V structure. */
3208 static void riscv_info_init(struct target *target, struct riscv_info *r)
3209 {
3210         memset(r, 0, sizeof(*r));
3211
3212         r->common_magic = RISCV_COMMON_MAGIC;
3213
3214         r->dtm_version = 1;
3215         r->current_hartid = target->coreid;
3216         r->version_specific = NULL;
3217
3218         memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
3219
3220         r->xlen = -1;
3221
3222         r->mem_access_methods[0] = RISCV_MEM_ACCESS_PROGBUF;
3223         r->mem_access_methods[1] = RISCV_MEM_ACCESS_SYSBUS;
3224         r->mem_access_methods[2] = RISCV_MEM_ACCESS_ABSTRACT;
3225
3226         r->mem_access_progbuf_warn = true;
3227         r->mem_access_sysbus_warn = true;
3228         r->mem_access_abstract_warn = true;
3229
3230         INIT_LIST_HEAD(&r->expose_csr);
3231         INIT_LIST_HEAD(&r->expose_custom);
3232 }
3233
3234 static int riscv_resume_go_all_harts(struct target *target)
3235 {
3236         RISCV_INFO(r);
3237
3238         LOG_DEBUG("[%s] resuming hart", target_name(target));
3239         if (riscv_select_current_hart(target) != ERROR_OK)
3240                 return ERROR_FAIL;
3241         if (riscv_is_halted(target)) {
3242                 if (r->resume_go(target) != ERROR_OK)
3243                         return ERROR_FAIL;
3244         } else {
3245                 LOG_DEBUG("[%s] hart requested resume, but was already resumed",
3246                                 target_name(target));
3247         }
3248
3249         riscv_invalidate_register_cache(target);
3250         return ERROR_OK;
3251 }
3252
3253 /* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
3254  * then the only hart. */
3255 static int riscv_step_rtos_hart(struct target *target)
3256 {
3257         RISCV_INFO(r);
3258         if (riscv_select_current_hart(target) != ERROR_OK)
3259                 return ERROR_FAIL;
3260         LOG_DEBUG("[%s] stepping", target_name(target));
3261
3262         if (!riscv_is_halted(target)) {
3263                 LOG_ERROR("Hart isn't halted before single step!");
3264                 return ERROR_FAIL;
3265         }
3266         riscv_invalidate_register_cache(target);
3267         r->on_step(target);
3268         if (r->step_current_hart(target) != ERROR_OK)
3269                 return ERROR_FAIL;
3270         riscv_invalidate_register_cache(target);
3271         r->on_halt(target);
3272         if (!riscv_is_halted(target)) {
3273                 LOG_ERROR("Hart was not halted after single step!");
3274                 return ERROR_FAIL;
3275         }
3276         return ERROR_OK;
3277 }
3278
3279 bool riscv_supports_extension(struct target *target, char letter)
3280 {
3281         RISCV_INFO(r);
3282         unsigned num;
3283         if (letter >= 'a' && letter <= 'z')
3284                 num = letter - 'a';
3285         else if (letter >= 'A' && letter <= 'Z')
3286                 num = letter - 'A';
3287         else
3288                 return false;
3289         return r->misa & BIT(num);
3290 }
3291
3292 unsigned riscv_xlen(const struct target *target)
3293 {
3294         RISCV_INFO(r);
3295         return r->xlen;
3296 }
3297
3298 int riscv_set_current_hartid(struct target *target, int hartid)
3299 {
3300         RISCV_INFO(r);
3301         if (!r->select_current_hart)
3302                 return ERROR_OK;
3303
3304         int previous_hartid = riscv_current_hartid(target);
3305         r->current_hartid = hartid;
3306         LOG_DEBUG("setting hartid to %d, was %d", hartid, previous_hartid);
3307         if (r->select_current_hart(target) != ERROR_OK)
3308                 return ERROR_FAIL;
3309
3310         return ERROR_OK;
3311 }
3312
3313 /* Invalidates the register cache. */
3314 static void riscv_invalidate_register_cache(struct target *target)
3315 {
3316         LOG_DEBUG("[%d]", target->coreid);
3317         register_cache_invalidate(target->reg_cache);
3318         for (size_t i = 0; i < target->reg_cache->num_regs; ++i) {
3319                 struct reg *reg = &target->reg_cache->reg_list[i];
3320                 reg->valid = false;
3321         }
3322 }
3323
3324 int riscv_current_hartid(const struct target *target)
3325 {
3326         RISCV_INFO(r);
3327         return r->current_hartid;
3328 }
3329
3330 int riscv_count_harts(struct target *target)
3331 {
3332         if (!target)
3333                 return 1;
3334         RISCV_INFO(r);
3335         if (!r || !r->hart_count)
3336                 return 1;
3337         return r->hart_count(target);
3338 }
3339
3340 /**
3341  * If write is true:
3342  *   return true iff we are guaranteed that the register will contain exactly
3343  *       the value we just wrote when it's read.
3344  * If write is false:
3345  *   return true iff we are guaranteed that the register will read the same
3346  *       value in the future as the value we just read.
3347  */
3348 static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
3349 {
3350         /* GPRs, FPRs, vector registers are just normal data stores. */
3351         if (regno <= GDB_REGNO_XPR31 ||
3352                         (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31) ||
3353                         (regno >= GDB_REGNO_V0 && regno <= GDB_REGNO_V31))
3354                 return true;
3355
3356         /* Most CSRs won't change value on us, but we can't assume it about arbitrary
3357          * CSRs. */
3358         switch (regno) {
3359                 case GDB_REGNO_DPC:
3360                         return true;
3361
3362                 case GDB_REGNO_VSTART:
3363                 case GDB_REGNO_VXSAT:
3364                 case GDB_REGNO_VXRM:
3365                 case GDB_REGNO_VLENB:
3366                 case GDB_REGNO_VL:
3367                 case GDB_REGNO_VTYPE:
3368                 case GDB_REGNO_MISA:
3369                 case GDB_REGNO_DCSR:
3370                 case GDB_REGNO_DSCRATCH0:
3371                 case GDB_REGNO_MSTATUS:
3372                 case GDB_REGNO_MEPC:
3373                 case GDB_REGNO_MCAUSE:
3374                 case GDB_REGNO_SATP:
3375                         /*
3376                          * WARL registers might not contain the value we just wrote, but
3377                          * these ones won't spontaneously change their value either. *
3378                          */
3379                         return !write;
3380
3381                 case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
3382                 case GDB_REGNO_TDATA1:  /* Changes value when tselect is changed. */
3383                 case GDB_REGNO_TDATA2:  /* Changse value when tselect is changed. */
3384                 default:
3385                         return false;
3386         }
3387 }
3388
3389 /**
3390  * This function is called when the debug user wants to change the value of a
3391  * register. The new value may be cached, and may not be written until the hart
3392  * is resumed. */
3393 int riscv_set_register(struct target *target, enum gdb_regno regid, riscv_reg_t value)
3394 {
3395         RISCV_INFO(r);
3396         LOG_DEBUG("[%s] %s <- %" PRIx64, target_name(target), gdb_regno_name(regid), value);
3397         assert(r->set_register);
3398
3399         keep_alive();
3400
3401         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3402         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 && value == 0 &&
3403                         riscv_supports_extension(target, 'E'))
3404                 return ERROR_OK;
3405
3406         struct reg *reg = &target->reg_cache->reg_list[regid];
3407         buf_set_u64(reg->value, 0, reg->size, value);
3408
3409         int result = r->set_register(target, regid, value);
3410         if (result == ERROR_OK)
3411                 reg->valid = gdb_regno_cacheable(regid, true);
3412         else
3413                 reg->valid = false;
3414         LOG_DEBUG("[%s] wrote 0x%" PRIx64 " to %s valid=%d",
3415                           target_name(target), value, reg->name, reg->valid);
3416         return result;
3417 }
3418
3419 int riscv_get_register(struct target *target, riscv_reg_t *value,
3420                 enum gdb_regno regid)
3421 {
3422         RISCV_INFO(r);
3423
3424         keep_alive();
3425
3426         struct reg *reg = &target->reg_cache->reg_list[regid];
3427         if (!reg->exist) {
3428                 LOG_DEBUG("[%s] %s does not exist.",
3429                                   target_name(target), gdb_regno_name(regid));
3430                 return ERROR_FAIL;
3431         }
3432
3433         if (reg && reg->valid) {
3434                 *value = buf_get_u64(reg->value, 0, reg->size);
3435                 LOG_DEBUG("[%s] %s: %" PRIx64 " (cached)", target_name(target),
3436                                   gdb_regno_name(regid), *value);
3437                 return ERROR_OK;
3438         }
3439
3440         /* TODO: Hack to deal with gdb that thinks these registers still exist. */
3441         if (regid > GDB_REGNO_XPR15 && regid <= GDB_REGNO_XPR31 &&
3442                         riscv_supports_extension(target, 'E')) {
3443                 *value = 0;
3444                 return ERROR_OK;
3445         }
3446
3447         int result = r->get_register(target, value, regid);
3448
3449         if (result == ERROR_OK)
3450                 reg->valid = gdb_regno_cacheable(regid, false);
3451
3452         LOG_DEBUG("[%s] %s: %" PRIx64, target_name(target),
3453                         gdb_regno_name(regid), *value);
3454         return result;
3455 }
3456
3457 bool riscv_is_halted(struct target *target)
3458 {
3459         RISCV_INFO(r);
3460         assert(r->is_halted);
3461         return r->is_halted(target);
3462 }
3463
3464 static enum riscv_halt_reason riscv_halt_reason(struct target *target, int hartid)
3465 {
3466         RISCV_INFO(r);
3467         if (riscv_set_current_hartid(target, hartid) != ERROR_OK)
3468                 return RISCV_HALT_ERROR;
3469         if (!riscv_is_halted(target)) {
3470                 LOG_ERROR("Hart is not halted!");
3471                 return RISCV_HALT_UNKNOWN;
3472         }
3473         return r->halt_reason(target);
3474 }
3475
3476 size_t riscv_debug_buffer_size(struct target *target)
3477 {
3478         RISCV_INFO(r);
3479         return r->debug_buffer_size;
3480 }
3481
3482 int riscv_write_debug_buffer(struct target *target, int index, riscv_insn_t insn)
3483 {
3484         RISCV_INFO(r);
3485         r->write_debug_buffer(target, index, insn);
3486         return ERROR_OK;
3487 }
3488
3489 riscv_insn_t riscv_read_debug_buffer(struct target *target, int index)
3490 {
3491         RISCV_INFO(r);
3492         return r->read_debug_buffer(target, index);
3493 }
3494
3495 int riscv_execute_debug_buffer(struct target *target)
3496 {
3497         RISCV_INFO(r);
3498         return r->execute_debug_buffer(target);
3499 }
3500
3501 void riscv_fill_dmi_write_u64(struct target *target, char *buf, int a, uint64_t d)
3502 {
3503         RISCV_INFO(r);
3504         r->fill_dmi_write_u64(target, buf, a, d);
3505 }
3506
3507 void riscv_fill_dmi_read_u64(struct target *target, char *buf, int a)
3508 {
3509         RISCV_INFO(r);
3510         r->fill_dmi_read_u64(target, buf, a);
3511 }
3512
3513 void riscv_fill_dmi_nop_u64(struct target *target, char *buf)
3514 {
3515         RISCV_INFO(r);
3516         r->fill_dmi_nop_u64(target, buf);
3517 }
3518
3519 int riscv_dmi_write_u64_bits(struct target *target)
3520 {
3521         RISCV_INFO(r);
3522         return r->dmi_write_u64_bits(target);
3523 }
3524
3525 /**
3526  * Count triggers, and initialize trigger_count for each hart.
3527  * trigger_count is initialized even if this function fails to discover
3528  * something.
3529  * Disable any hardware triggers that have dmode set. We can't have set them
3530  * ourselves. Maybe they're left over from some killed debug session.
3531  * */
3532 int riscv_enumerate_triggers(struct target *target)
3533 {
3534         RISCV_INFO(r);
3535
3536         if (r->triggers_enumerated)
3537                 return ERROR_OK;
3538
3539         r->triggers_enumerated = true;  /* At the very least we tried. */
3540
3541         riscv_reg_t tselect;
3542         int result = riscv_get_register(target, &tselect, GDB_REGNO_TSELECT);
3543         /* If tselect is not readable, the trigger module is likely not
3544                 * implemented. There are no triggers to enumerate then and no error
3545                 * should be thrown. */
3546         if (result != ERROR_OK) {
3547                 LOG_DEBUG("[%s] Cannot access tselect register. "
3548                                 "Assuming that triggers are not implemented.", target_name(target));
3549                 r->trigger_count = 0;
3550                 return ERROR_OK;
3551         }
3552
3553         for (unsigned int t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
3554                 r->trigger_count = t;
3555
3556                 /* If we can't write tselect, then this hart does not support triggers. */
3557                 if (riscv_set_register(target, GDB_REGNO_TSELECT, t) != ERROR_OK)
3558                         break;
3559                 uint64_t tselect_rb;
3560                 result = riscv_get_register(target, &tselect_rb, GDB_REGNO_TSELECT);
3561                 if (result != ERROR_OK)
3562                         return result;
3563                 /* Mask off the top bit, which is used as tdrmode in old
3564                         * implementations. */
3565                 tselect_rb &= ~(1ULL << (riscv_xlen(target) - 1));
3566                 if (tselect_rb != t)
3567                         break;
3568                 uint64_t tdata1;
3569                 result = riscv_get_register(target, &tdata1, GDB_REGNO_TDATA1);
3570                 if (result != ERROR_OK)
3571                         return result;
3572
3573                 int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
3574                 if (type == 0)
3575                         break;
3576                 switch (type) {
3577                         case 1:
3578                                 /* On these older cores we don't support software using
3579                                         * triggers. */
3580                                 riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3581                                 break;
3582                         case 2:
3583                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3584                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3585                                 break;
3586                         case 6:
3587                                 if (tdata1 & MCONTROL_DMODE(riscv_xlen(target)))
3588                                         riscv_set_register(target, GDB_REGNO_TDATA1, 0);
3589                                 break;
3590                 }
3591         }
3592
3593         riscv_set_register(target, GDB_REGNO_TSELECT, tselect);
3594
3595         LOG_INFO("[%s] Found %d triggers", target_name(target), r->trigger_count);
3596
3597         return ERROR_OK;
3598 }
3599
3600 const char *gdb_regno_name(enum gdb_regno regno)
3601 {
3602         static char buf[32];
3603
3604         switch (regno) {
3605                 case GDB_REGNO_ZERO:
3606                         return "zero";
3607                 case GDB_REGNO_RA:
3608                         return "ra";
3609                 case GDB_REGNO_SP:
3610                         return "sp";
3611                 case GDB_REGNO_GP:
3612                         return "gp";
3613                 case GDB_REGNO_TP:
3614                         return "tp";
3615                 case GDB_REGNO_T0:
3616                         return "t0";
3617                 case GDB_REGNO_T1:
3618                         return "t1";
3619                 case GDB_REGNO_T2:
3620                         return "t2";
3621                 case GDB_REGNO_S0:
3622                         return "s0";
3623                 case GDB_REGNO_S1:
3624                         return "s1";
3625                 case GDB_REGNO_A0:
3626                         return "a0";
3627                 case GDB_REGNO_A1:
3628                         return "a1";
3629                 case GDB_REGNO_A2:
3630                         return "a2";
3631                 case GDB_REGNO_A3:
3632                         return "a3";
3633                 case GDB_REGNO_A4:
3634                         return "a4";
3635                 case GDB_REGNO_A5:
3636                         return "a5";
3637                 case GDB_REGNO_A6:
3638                         return "a6";
3639                 case GDB_REGNO_A7:
3640                         return "a7";
3641                 case GDB_REGNO_S2:
3642                         return "s2";
3643                 case GDB_REGNO_S3:
3644                         return "s3";
3645                 case GDB_REGNO_S4:
3646                         return "s4";
3647                 case GDB_REGNO_S5:
3648                         return "s5";
3649                 case GDB_REGNO_S6:
3650                         return "s6";
3651                 case GDB_REGNO_S7:
3652                         return "s7";
3653                 case GDB_REGNO_S8:
3654                         return "s8";
3655                 case GDB_REGNO_S9:
3656                         return "s9";
3657                 case GDB_REGNO_S10:
3658                         return "s10";
3659                 case GDB_REGNO_S11:
3660                         return "s11";
3661                 case GDB_REGNO_T3:
3662                         return "t3";
3663                 case GDB_REGNO_T4:
3664                         return "t4";
3665                 case GDB_REGNO_T5:
3666                         return "t5";
3667                 case GDB_REGNO_T6:
3668                         return "t6";
3669                 case GDB_REGNO_PC:
3670                         return "pc";
3671                 case GDB_REGNO_FPR0:
3672                         return "fpr0";
3673                 case GDB_REGNO_FPR31:
3674                         return "fpr31";
3675                 case GDB_REGNO_CSR0:
3676                         return "csr0";
3677                 case GDB_REGNO_TSELECT:
3678                         return "tselect";
3679                 case GDB_REGNO_TDATA1:
3680                         return "tdata1";
3681                 case GDB_REGNO_TDATA2:
3682                         return "tdata2";
3683                 case GDB_REGNO_MISA:
3684                         return "misa";
3685                 case GDB_REGNO_DPC:
3686                         return "dpc";
3687                 case GDB_REGNO_DCSR:
3688                         return "dcsr";
3689                 case GDB_REGNO_DSCRATCH0:
3690                         return "dscratch0";
3691                 case GDB_REGNO_MSTATUS:
3692                         return "mstatus";
3693                 case GDB_REGNO_MEPC:
3694                         return "mepc";
3695                 case GDB_REGNO_MCAUSE:
3696                         return "mcause";
3697                 case GDB_REGNO_PRIV:
3698                         return "priv";
3699                 case GDB_REGNO_SATP:
3700                         return "satp";
3701                 case GDB_REGNO_VTYPE:
3702                         return "vtype";
3703                 case GDB_REGNO_VL:
3704                         return "vl";
3705                 case GDB_REGNO_V0:
3706                         return "v0";
3707                 case GDB_REGNO_V1:
3708                         return "v1";
3709                 case GDB_REGNO_V2:
3710                         return "v2";
3711                 case GDB_REGNO_V3:
3712                         return "v3";
3713                 case GDB_REGNO_V4:
3714                         return "v4";
3715                 case GDB_REGNO_V5:
3716                         return "v5";
3717                 case GDB_REGNO_V6:
3718                         return "v6";
3719                 case GDB_REGNO_V7:
3720                         return "v7";
3721                 case GDB_REGNO_V8:
3722                         return "v8";
3723                 case GDB_REGNO_V9:
3724                         return "v9";
3725                 case GDB_REGNO_V10:
3726                         return "v10";
3727                 case GDB_REGNO_V11:
3728                         return "v11";
3729                 case GDB_REGNO_V12:
3730                         return "v12";
3731                 case GDB_REGNO_V13:
3732                         return "v13";
3733                 case GDB_REGNO_V14:
3734                         return "v14";
3735                 case GDB_REGNO_V15:
3736                         return "v15";
3737                 case GDB_REGNO_V16:
3738                         return "v16";
3739                 case GDB_REGNO_V17:
3740                         return "v17";
3741                 case GDB_REGNO_V18:
3742                         return "v18";
3743                 case GDB_REGNO_V19:
3744                         return "v19";
3745                 case GDB_REGNO_V20:
3746                         return "v20";
3747                 case GDB_REGNO_V21:
3748                         return "v21";
3749                 case GDB_REGNO_V22:
3750                         return "v22";
3751                 case GDB_REGNO_V23:
3752                         return "v23";
3753                 case GDB_REGNO_V24:
3754                         return "v24";
3755                 case GDB_REGNO_V25:
3756                         return "v25";
3757                 case GDB_REGNO_V26:
3758                         return "v26";
3759                 case GDB_REGNO_V27:
3760                         return "v27";
3761                 case GDB_REGNO_V28:
3762                         return "v28";
3763                 case GDB_REGNO_V29:
3764                         return "v29";
3765                 case GDB_REGNO_V30:
3766                         return "v30";
3767                 case GDB_REGNO_V31:
3768                         return "v31";
3769                 default:
3770                         if (regno <= GDB_REGNO_XPR31)
3771                                 sprintf(buf, "x%d", regno - GDB_REGNO_ZERO);
3772                         else if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095)
3773                                 sprintf(buf, "csr%d", regno - GDB_REGNO_CSR0);
3774                         else if (regno >= GDB_REGNO_FPR0 && regno <= GDB_REGNO_FPR31)
3775                                 sprintf(buf, "f%d", regno - GDB_REGNO_FPR0);
3776                         else
3777                                 sprintf(buf, "gdb_regno_%d", regno);
3778                         return buf;
3779         }
3780 }
3781
3782 static int register_get(struct reg *reg)
3783 {
3784         riscv_reg_info_t *reg_info = reg->arch_info;
3785         struct target *target = reg_info->target;
3786         RISCV_INFO(r);
3787
3788         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3789                 if (!r->get_register_buf) {
3790                         LOG_ERROR("Reading register %s not supported on this RISC-V target.",
3791                                         gdb_regno_name(reg->number));
3792                         return ERROR_FAIL;
3793                 }
3794
3795                 if (r->get_register_buf(target, reg->value, reg->number) != ERROR_OK)
3796                         return ERROR_FAIL;
3797         } else {
3798                 uint64_t value;
3799                 int result = riscv_get_register(target, &value, reg->number);
3800                 if (result != ERROR_OK)
3801                         return result;
3802                 buf_set_u64(reg->value, 0, reg->size, value);
3803         }
3804         reg->valid = gdb_regno_cacheable(reg->number, false);
3805         char *str = buf_to_hex_str(reg->value, reg->size);
3806         LOG_DEBUG("[%s] read 0x%s from %s (valid=%d)", target_name(target),
3807                         str, reg->name, reg->valid);
3808         free(str);
3809         return ERROR_OK;
3810 }
3811
3812 static int register_set(struct reg *reg, uint8_t *buf)
3813 {
3814         riscv_reg_info_t *reg_info = reg->arch_info;
3815         struct target *target = reg_info->target;
3816         RISCV_INFO(r);
3817
3818         char *str = buf_to_hex_str(buf, reg->size);
3819         LOG_DEBUG("[%s] write 0x%s to %s (valid=%d)", target_name(target),
3820                         str, reg->name, reg->valid);
3821         free(str);
3822
3823         /* Exit early for writing x0, which on the hardware would be ignored, and we
3824          * don't want to update our cache. */
3825         if (reg->number == GDB_REGNO_ZERO)
3826                 return ERROR_OK;
3827
3828         memcpy(reg->value, buf, DIV_ROUND_UP(reg->size, 8));
3829         reg->valid = gdb_regno_cacheable(reg->number, true);
3830
3831         if (reg->number == GDB_REGNO_TDATA1 ||
3832                         reg->number == GDB_REGNO_TDATA2) {
3833                 r->manual_hwbp_set = true;
3834                 /* When enumerating triggers, we clear any triggers with DMODE set,
3835                  * assuming they were left over from a previous debug session. So make
3836                  * sure that is done before a user might be setting their own triggers.
3837                  */
3838                 if (riscv_enumerate_triggers(target) != ERROR_OK)
3839                         return ERROR_FAIL;
3840         }
3841
3842         if (reg->number >= GDB_REGNO_V0 && reg->number <= GDB_REGNO_V31) {
3843                 if (!r->set_register_buf) {
3844                         LOG_ERROR("Writing register %s not supported on this RISC-V target.",
3845                                         gdb_regno_name(reg->number));
3846                         return ERROR_FAIL;
3847                 }
3848
3849                 if (r->set_register_buf(target, reg->number, reg->value) != ERROR_OK)
3850                         return ERROR_FAIL;
3851         } else {
3852                 uint64_t value = buf_get_u64(buf, 0, reg->size);
3853                 if (riscv_set_register(target, reg->number, value) != ERROR_OK)
3854                         return ERROR_FAIL;
3855         }
3856
3857         return ERROR_OK;
3858 }
3859
3860 static struct reg_arch_type riscv_reg_arch_type = {
3861         .get = register_get,
3862         .set = register_set
3863 };
3864
3865 struct csr_info {
3866         unsigned number;
3867         const char *name;
3868 };
3869
3870 static int cmp_csr_info(const void *p1, const void *p2)
3871 {
3872         return (int) (((struct csr_info *)p1)->number) - (int) (((struct csr_info *)p2)->number);
3873 }
3874
3875 int riscv_init_registers(struct target *target)
3876 {
3877         RISCV_INFO(info);
3878
3879         riscv_free_registers(target);
3880
3881         target->reg_cache = calloc(1, sizeof(*target->reg_cache));
3882         if (!target->reg_cache)
3883                 return ERROR_FAIL;
3884         target->reg_cache->name = "RISC-V Registers";
3885         target->reg_cache->num_regs = GDB_REGNO_COUNT;
3886
3887         if (!list_empty(&info->expose_custom)) {
3888                 range_list_t *entry;
3889                 list_for_each_entry(entry, &info->expose_custom, list)
3890                         target->reg_cache->num_regs += entry->high - entry->low + 1;
3891         }
3892
3893         LOG_DEBUG("create register cache for %d registers",
3894                         target->reg_cache->num_regs);
3895
3896         target->reg_cache->reg_list =
3897                 calloc(target->reg_cache->num_regs, sizeof(struct reg));
3898         if (!target->reg_cache->reg_list)
3899                 return ERROR_FAIL;
3900
3901         const unsigned int max_reg_name_len = 12;
3902         free(info->reg_names);
3903         info->reg_names =
3904                 calloc(target->reg_cache->num_regs, max_reg_name_len);
3905         if (!info->reg_names)
3906                 return ERROR_FAIL;
3907         char *reg_name = info->reg_names;
3908
3909         static struct reg_feature feature_cpu = {
3910                 .name = "org.gnu.gdb.riscv.cpu"
3911         };
3912         static struct reg_feature feature_fpu = {
3913                 .name = "org.gnu.gdb.riscv.fpu"
3914         };
3915         static struct reg_feature feature_csr = {
3916                 .name = "org.gnu.gdb.riscv.csr"
3917         };
3918         static struct reg_feature feature_vector = {
3919                 .name = "org.gnu.gdb.riscv.vector"
3920         };
3921         static struct reg_feature feature_virtual = {
3922                 .name = "org.gnu.gdb.riscv.virtual"
3923         };
3924         static struct reg_feature feature_custom = {
3925                 .name = "org.gnu.gdb.riscv.custom"
3926         };
3927
3928         /* These types are built into gdb. */
3929         static struct reg_data_type type_ieee_single = { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" };
3930         static struct reg_data_type type_ieee_double = { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" };
3931         static struct reg_data_type_union_field single_double_fields[] = {
3932                 {"float", &type_ieee_single, single_double_fields + 1},
3933                 {"double", &type_ieee_double, NULL},
3934         };
3935         static struct reg_data_type_union single_double_union = {
3936                 .fields = single_double_fields
3937         };
3938         static struct reg_data_type type_ieee_single_double = {
3939                 .type = REG_TYPE_ARCH_DEFINED,
3940                 .id = "FPU_FD",
3941                 .type_class = REG_TYPE_CLASS_UNION,
3942                 .reg_type_union = &single_double_union
3943         };
3944         static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" };
3945         static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" };
3946         static struct reg_data_type type_uint32 = { .type = REG_TYPE_UINT32, .id = "uint32" };
3947         static struct reg_data_type type_uint64 = { .type = REG_TYPE_UINT64, .id = "uint64" };
3948         static struct reg_data_type type_uint128 = { .type = REG_TYPE_UINT128, .id = "uint128" };
3949
3950         /* This is roughly the XML we want:
3951          * <vector id="bytes" type="uint8" count="16"/>
3952          * <vector id="shorts" type="uint16" count="8"/>
3953          * <vector id="words" type="uint32" count="4"/>
3954          * <vector id="longs" type="uint64" count="2"/>
3955          * <vector id="quads" type="uint128" count="1"/>
3956          * <union id="riscv_vector_type">
3957          *   <field name="b" type="bytes"/>
3958          *   <field name="s" type="shorts"/>
3959          *   <field name="w" type="words"/>
3960          *   <field name="l" type="longs"/>
3961          *   <field name="q" type="quads"/>
3962          * </union>
3963          */
3964
3965         info->vector_uint8.type = &type_uint8;
3966         info->vector_uint8.count = info->vlenb;
3967         info->type_uint8_vector.type = REG_TYPE_ARCH_DEFINED;
3968         info->type_uint8_vector.id = "bytes";
3969         info->type_uint8_vector.type_class = REG_TYPE_CLASS_VECTOR;
3970         info->type_uint8_vector.reg_type_vector = &info->vector_uint8;
3971
3972         info->vector_uint16.type = &type_uint16;
3973         info->vector_uint16.count = info->vlenb / 2;
3974         info->type_uint16_vector.type = REG_TYPE_ARCH_DEFINED;
3975         info->type_uint16_vector.id = "shorts";
3976         info->type_uint16_vector.type_class = REG_TYPE_CLASS_VECTOR;
3977         info->type_uint16_vector.reg_type_vector = &info->vector_uint16;
3978
3979         info->vector_uint32.type = &type_uint32;
3980         info->vector_uint32.count = info->vlenb / 4;
3981         info->type_uint32_vector.type = REG_TYPE_ARCH_DEFINED;
3982         info->type_uint32_vector.id = "words";
3983         info->type_uint32_vector.type_class = REG_TYPE_CLASS_VECTOR;
3984         info->type_uint32_vector.reg_type_vector = &info->vector_uint32;
3985
3986         info->vector_uint64.type = &type_uint64;
3987         info->vector_uint64.count = info->vlenb / 8;
3988         info->type_uint64_vector.type = REG_TYPE_ARCH_DEFINED;
3989         info->type_uint64_vector.id = "longs";
3990         info->type_uint64_vector.type_class = REG_TYPE_CLASS_VECTOR;
3991         info->type_uint64_vector.reg_type_vector = &info->vector_uint64;
3992
3993         info->vector_uint128.type = &type_uint128;
3994         info->vector_uint128.count = info->vlenb / 16;
3995         info->type_uint128_vector.type = REG_TYPE_ARCH_DEFINED;
3996         info->type_uint128_vector.id = "quads";
3997         info->type_uint128_vector.type_class = REG_TYPE_CLASS_VECTOR;
3998         info->type_uint128_vector.reg_type_vector = &info->vector_uint128;
3999
4000         info->vector_fields[0].name = "b";
4001         info->vector_fields[0].type = &info->type_uint8_vector;
4002         if (info->vlenb >= 2) {
4003                 info->vector_fields[0].next = info->vector_fields + 1;
4004                 info->vector_fields[1].name = "s";
4005                 info->vector_fields[1].type = &info->type_uint16_vector;
4006         } else {
4007                 info->vector_fields[0].next = NULL;
4008         }
4009         if (info->vlenb >= 4) {
4010                 info->vector_fields[1].next = info->vector_fields + 2;
4011                 info->vector_fields[2].name = "w";
4012                 info->vector_fields[2].type = &info->type_uint32_vector;
4013         } else {
4014                 info->vector_fields[1].next = NULL;
4015         }
4016         if (info->vlenb >= 8) {
4017                 info->vector_fields[2].next = info->vector_fields + 3;
4018                 info->vector_fields[3].name = "l";
4019                 info->vector_fields[3].type = &info->type_uint64_vector;
4020         } else {
4021                 info->vector_fields[2].next = NULL;
4022         }
4023         if (info->vlenb >= 16) {
4024                 info->vector_fields[3].next = info->vector_fields + 4;
4025                 info->vector_fields[4].name = "q";
4026                 info->vector_fields[4].type = &info->type_uint128_vector;
4027         } else {
4028                 info->vector_fields[3].next = NULL;
4029         }
4030         info->vector_fields[4].next = NULL;
4031
4032         info->vector_union.fields = info->vector_fields;
4033
4034         info->type_vector.type = REG_TYPE_ARCH_DEFINED;
4035         info->type_vector.id = "riscv_vector";
4036         info->type_vector.type_class = REG_TYPE_CLASS_UNION;
4037         info->type_vector.reg_type_union = &info->vector_union;
4038
4039         struct csr_info csr_info[] = {
4040 #define DECLARE_CSR(name, number) { number, #name },
4041 #include "encoding.h"
4042 #undef DECLARE_CSR
4043         };
4044         /* encoding.h does not contain the registers in sorted order. */
4045         qsort(csr_info, ARRAY_SIZE(csr_info), sizeof(*csr_info), cmp_csr_info);
4046         unsigned csr_info_index = 0;
4047
4048         int custom_within_range = 0;
4049
4050         riscv_reg_info_t *shared_reg_info = calloc(1, sizeof(riscv_reg_info_t));
4051         if (!shared_reg_info)
4052                 return ERROR_FAIL;
4053         shared_reg_info->target = target;
4054
4055         /* When gdb requests register N, gdb_get_register_packet() assumes that this
4056          * is register at index N in reg_list. So if there are certain registers
4057          * that don't exist, we need to leave holes in the list (or renumber, but
4058          * it would be nice not to have yet another set of numbers to translate
4059          * between). */
4060         for (uint32_t number = 0; number < target->reg_cache->num_regs; number++) {
4061                 struct reg *r = &target->reg_cache->reg_list[number];
4062                 r->dirty = false;
4063                 r->valid = false;
4064                 r->exist = true;
4065                 r->type = &riscv_reg_arch_type;
4066                 r->arch_info = shared_reg_info;
4067                 r->number = number;
4068                 r->size = riscv_xlen(target);
4069                 /* r->size is set in riscv_invalidate_register_cache, maybe because the
4070                  * target is in theory allowed to change XLEN on us. But I expect a lot
4071                  * of other things to break in that case as well. */
4072                 if (number <= GDB_REGNO_XPR31) {
4073                         r->exist = number <= GDB_REGNO_XPR15 ||
4074                                 !riscv_supports_extension(target, 'E');
4075                         /* TODO: For now we fake that all GPRs exist because otherwise gdb
4076                          * doesn't work. */
4077                         r->exist = true;
4078                         r->caller_save = true;
4079                         switch (number) {
4080                                 case GDB_REGNO_ZERO:
4081                                         r->name = "zero";
4082                                         break;
4083                                 case GDB_REGNO_RA:
4084                                         r->name = "ra";
4085                                         break;
4086                                 case GDB_REGNO_SP:
4087                                         r->name = "sp";
4088                                         break;
4089                                 case GDB_REGNO_GP:
4090                                         r->name = "gp";
4091                                         break;
4092                                 case GDB_REGNO_TP:
4093                                         r->name = "tp";
4094                                         break;
4095                                 case GDB_REGNO_T0:
4096                                         r->name = "t0";
4097                                         break;
4098                                 case GDB_REGNO_T1:
4099                                         r->name = "t1";
4100                                         break;
4101                                 case GDB_REGNO_T2:
4102                                         r->name = "t2";
4103                                         break;
4104                                 case GDB_REGNO_FP:
4105                                         r->name = "fp";
4106                                         break;
4107                                 case GDB_REGNO_S1:
4108                                         r->name = "s1";
4109                                         break;
4110                                 case GDB_REGNO_A0:
4111                                         r->name = "a0";
4112                                         break;
4113                                 case GDB_REGNO_A1:
4114                                         r->name = "a1";
4115                                         break;
4116                                 case GDB_REGNO_A2:
4117                                         r->name = "a2";
4118                                         break;
4119                                 case GDB_REGNO_A3:
4120                                         r->name = "a3";
4121                                         break;
4122                                 case GDB_REGNO_A4:
4123                                         r->name = "a4";
4124                                         break;
4125                                 case GDB_REGNO_A5:
4126                                         r->name = "a5";
4127                                         break;
4128                                 case GDB_REGNO_A6:
4129                                         r->name = "a6";
4130                                         break;
4131                                 case GDB_REGNO_A7:
4132                                         r->name = "a7";
4133                                         break;
4134                                 case GDB_REGNO_S2:
4135                                         r->name = "s2";
4136                                         break;
4137                                 case GDB_REGNO_S3:
4138                                         r->name = "s3";
4139                                         break;
4140                                 case GDB_REGNO_S4:
4141                                         r->name = "s4";
4142                                         break;
4143                                 case GDB_REGNO_S5:
4144                                         r->name = "s5";
4145                                         break;
4146                                 case GDB_REGNO_S6:
4147                                         r->name = "s6";
4148                                         break;
4149                                 case GDB_REGNO_S7:
4150                                         r->name = "s7";
4151                                         break;
4152                                 case GDB_REGNO_S8:
4153                                         r->name = "s8";
4154                                         break;
4155                                 case GDB_REGNO_S9:
4156                                         r->name = "s9";
4157                                         break;
4158                                 case GDB_REGNO_S10:
4159                                         r->name = "s10";
4160                                         break;
4161                                 case GDB_REGNO_S11:
4162                                         r->name = "s11";
4163                                         break;
4164                                 case GDB_REGNO_T3:
4165                                         r->name = "t3";
4166                                         break;
4167                                 case GDB_REGNO_T4:
4168                                         r->name = "t4";
4169                                         break;
4170                                 case GDB_REGNO_T5:
4171                                         r->name = "t5";
4172                                         break;
4173                                 case GDB_REGNO_T6:
4174                                         r->name = "t6";
4175                                         break;
4176                         }
4177                         r->group = "general";
4178                         r->feature = &feature_cpu;
4179                 } else if (number == GDB_REGNO_PC) {
4180                         r->caller_save = true;
4181                         sprintf(reg_name, "pc");
4182                         r->group = "general";
4183                         r->feature = &feature_cpu;
4184                 } else if (number >= GDB_REGNO_FPR0 && number <= GDB_REGNO_FPR31) {
4185                         r->caller_save = true;
4186                         if (riscv_supports_extension(target, 'D')) {
4187                                 r->size = 64;
4188                                 if (riscv_supports_extension(target, 'F'))
4189                                         r->reg_data_type = &type_ieee_single_double;
4190                                 else
4191                                         r->reg_data_type = &type_ieee_double;
4192                         } else if (riscv_supports_extension(target, 'F')) {
4193                                 r->reg_data_type = &type_ieee_single;
4194                                 r->size = 32;
4195                         } else {
4196                                 r->exist = false;
4197                         }
4198                         switch (number) {
4199                                 case GDB_REGNO_FT0:
4200                                         r->name = "ft0";
4201                                         break;
4202                                 case GDB_REGNO_FT1:
4203                                         r->name = "ft1";
4204                                         break;
4205                                 case GDB_REGNO_FT2:
4206                                         r->name = "ft2";
4207                                         break;
4208                                 case GDB_REGNO_FT3:
4209                                         r->name = "ft3";
4210                                         break;
4211                                 case GDB_REGNO_FT4:
4212                                         r->name = "ft4";
4213                                         break;
4214                                 case GDB_REGNO_FT5:
4215                                         r->name = "ft5";
4216                                         break;
4217                                 case GDB_REGNO_FT6:
4218                                         r->name = "ft6";
4219                                         break;
4220                                 case GDB_REGNO_FT7:
4221                                         r->name = "ft7";
4222                                         break;
4223                                 case GDB_REGNO_FS0:
4224                                         r->name = "fs0";
4225                                         break;
4226                                 case GDB_REGNO_FS1:
4227                                         r->name = "fs1";
4228                                         break;
4229                                 case GDB_REGNO_FA0:
4230                                         r->name = "fa0";
4231                                         break;
4232                                 case GDB_REGNO_FA1:
4233                                         r->name = "fa1";
4234                                         break;
4235                                 case GDB_REGNO_FA2:
4236                                         r->name = "fa2";
4237                                         break;
4238                                 case GDB_REGNO_FA3:
4239                                         r->name = "fa3";
4240                                         break;
4241                                 case GDB_REGNO_FA4:
4242                                         r->name = "fa4";
4243                                         break;
4244                                 case GDB_REGNO_FA5:
4245                                         r->name = "fa5";
4246                                         break;
4247                                 case GDB_REGNO_FA6:
4248                                         r->name = "fa6";
4249                                         break;
4250                                 case GDB_REGNO_FA7:
4251                                         r->name = "fa7";
4252                                         break;
4253                                 case GDB_REGNO_FS2:
4254                                         r->name = "fs2";
4255                                         break;
4256                                 case GDB_REGNO_FS3:
4257                                         r->name = "fs3";
4258                                         break;
4259                                 case GDB_REGNO_FS4:
4260                                         r->name = "fs4";
4261                                         break;
4262                                 case GDB_REGNO_FS5:
4263                                         r->name = "fs5";
4264                                         break;
4265                                 case GDB_REGNO_FS6:
4266                                         r->name = "fs6";
4267                                         break;
4268                                 case GDB_REGNO_FS7:
4269                                         r->name = "fs7";
4270                                         break;
4271                                 case GDB_REGNO_FS8:
4272                                         r->name = "fs8";
4273                                         break;
4274                                 case GDB_REGNO_FS9:
4275                                         r->name = "fs9";
4276                                         break;
4277                                 case GDB_REGNO_FS10:
4278                                         r->name = "fs10";
4279                                         break;
4280                                 case GDB_REGNO_FS11:
4281                                         r->name = "fs11";
4282                                         break;
4283                                 case GDB_REGNO_FT8:
4284                                         r->name = "ft8";
4285                                         break;
4286                                 case GDB_REGNO_FT9:
4287                                         r->name = "ft9";
4288                                         break;
4289                                 case GDB_REGNO_FT10:
4290                                         r->name = "ft10";
4291                                         break;
4292                                 case GDB_REGNO_FT11:
4293                                         r->name = "ft11";
4294                                         break;
4295                         }
4296                         r->group = "float";
4297                         r->feature = &feature_fpu;
4298                 } else if (number >= GDB_REGNO_CSR0 && number <= GDB_REGNO_CSR4095) {
4299                         r->group = "csr";
4300                         r->feature = &feature_csr;
4301                         unsigned csr_number = number - GDB_REGNO_CSR0;
4302
4303                         while (csr_info[csr_info_index].number < csr_number &&
4304                                         csr_info_index < ARRAY_SIZE(csr_info) - 1) {
4305                                 csr_info_index++;
4306                         }
4307                         if (csr_info[csr_info_index].number == csr_number) {
4308                                 r->name = csr_info[csr_info_index].name;
4309                         } else {
4310                                 sprintf(reg_name, "csr%d", csr_number);
4311                                 /* Assume unnamed registers don't exist, unless we have some
4312                                  * configuration that tells us otherwise. That's important
4313                                  * because eg. Eclipse crashes if a target has too many
4314                                  * registers, and apparently has no way of only showing a
4315                                  * subset of registers in any case. */
4316                                 r->exist = false;
4317                         }
4318
4319                         switch (csr_number) {
4320                                 case CSR_FFLAGS:
4321                                 case CSR_FRM:
4322                                 case CSR_FCSR:
4323                                         r->exist = riscv_supports_extension(target, 'F');
4324                                         r->group = "float";
4325                                         r->feature = &feature_fpu;
4326                                         break;
4327                                 case CSR_SSTATUS:
4328                                 case CSR_STVEC:
4329                                 case CSR_SIP:
4330                                 case CSR_SIE:
4331                                 case CSR_SCOUNTEREN:
4332                                 case CSR_SSCRATCH:
4333                                 case CSR_SEPC:
4334                                 case CSR_SCAUSE:
4335                                 case CSR_STVAL:
4336                                 case CSR_SATP:
4337                                         r->exist = riscv_supports_extension(target, 'S');
4338                                         break;
4339                                 case CSR_MEDELEG:
4340                                 case CSR_MIDELEG:
4341                                         /* "In systems with only M-mode, or with both M-mode and
4342                                          * U-mode but without U-mode trap support, the medeleg and
4343                                          * mideleg registers should not exist." */
4344                                         r->exist = riscv_supports_extension(target, 'S') ||
4345                                                 riscv_supports_extension(target, 'N');
4346                                         break;
4347
4348                                 case CSR_PMPCFG1:
4349                                 case CSR_PMPCFG3:
4350                                 case CSR_CYCLEH:
4351                                 case CSR_TIMEH:
4352                                 case CSR_INSTRETH:
4353                                 case CSR_HPMCOUNTER3H:
4354                                 case CSR_HPMCOUNTER4H:
4355                                 case CSR_HPMCOUNTER5H:
4356                                 case CSR_HPMCOUNTER6H:
4357                                 case CSR_HPMCOUNTER7H:
4358                                 case CSR_HPMCOUNTER8H:
4359                                 case CSR_HPMCOUNTER9H:
4360                                 case CSR_HPMCOUNTER10H:
4361                                 case CSR_HPMCOUNTER11H:
4362                                 case CSR_HPMCOUNTER12H:
4363                                 case CSR_HPMCOUNTER13H:
4364                                 case CSR_HPMCOUNTER14H:
4365                                 case CSR_HPMCOUNTER15H:
4366                                 case CSR_HPMCOUNTER16H:
4367                                 case CSR_HPMCOUNTER17H:
4368                                 case CSR_HPMCOUNTER18H:
4369                                 case CSR_HPMCOUNTER19H:
4370                                 case CSR_HPMCOUNTER20H:
4371                                 case CSR_HPMCOUNTER21H:
4372                                 case CSR_HPMCOUNTER22H:
4373                                 case CSR_HPMCOUNTER23H:
4374                                 case CSR_HPMCOUNTER24H:
4375                                 case CSR_HPMCOUNTER25H:
4376                                 case CSR_HPMCOUNTER26H:
4377                                 case CSR_HPMCOUNTER27H:
4378                                 case CSR_HPMCOUNTER28H:
4379                                 case CSR_HPMCOUNTER29H:
4380                                 case CSR_HPMCOUNTER30H:
4381                                 case CSR_HPMCOUNTER31H:
4382                                 case CSR_MCYCLEH:
4383                                 case CSR_MINSTRETH:
4384                                 case CSR_MHPMCOUNTER3H:
4385                                 case CSR_MHPMCOUNTER4H:
4386                                 case CSR_MHPMCOUNTER5H:
4387                                 case CSR_MHPMCOUNTER6H:
4388                                 case CSR_MHPMCOUNTER7H:
4389                                 case CSR_MHPMCOUNTER8H:
4390                                 case CSR_MHPMCOUNTER9H:
4391                                 case CSR_MHPMCOUNTER10H:
4392                                 case CSR_MHPMCOUNTER11H:
4393                                 case CSR_MHPMCOUNTER12H:
4394                                 case CSR_MHPMCOUNTER13H:
4395                                 case CSR_MHPMCOUNTER14H:
4396                                 case CSR_MHPMCOUNTER15H:
4397                                 case CSR_MHPMCOUNTER16H:
4398                                 case CSR_MHPMCOUNTER17H:
4399                                 case CSR_MHPMCOUNTER18H:
4400                                 case CSR_MHPMCOUNTER19H:
4401                                 case CSR_MHPMCOUNTER20H:
4402                                 case CSR_MHPMCOUNTER21H:
4403                                 case CSR_MHPMCOUNTER22H:
4404                                 case CSR_MHPMCOUNTER23H:
4405                                 case CSR_MHPMCOUNTER24H:
4406                                 case CSR_MHPMCOUNTER25H:
4407                                 case CSR_MHPMCOUNTER26H:
4408                                 case CSR_MHPMCOUNTER27H:
4409                                 case CSR_MHPMCOUNTER28H:
4410                                 case CSR_MHPMCOUNTER29H:
4411                                 case CSR_MHPMCOUNTER30H:
4412                                 case CSR_MHPMCOUNTER31H:
4413                                         r->exist = riscv_xlen(target) == 32;
4414                                         break;
4415
4416                                 case CSR_VSTART:
4417                                 case CSR_VXSAT:
4418                                 case CSR_VXRM:
4419                                 case CSR_VL:
4420                                 case CSR_VTYPE:
4421                                 case CSR_VLENB:
4422                                         r->exist = riscv_supports_extension(target, 'V');
4423                                         break;
4424                         }
4425
4426                         if (!r->exist && !list_empty(&info->expose_csr)) {
4427                                 range_list_t *entry;
4428                                 list_for_each_entry(entry, &info->expose_csr, list)
4429                                         if ((entry->low <= csr_number) && (csr_number <= entry->high)) {
4430                                                 if (entry->name) {
4431                                                         *reg_name = 0;
4432                                                         r->name = entry->name;
4433                                                 }
4434
4435                                                 LOG_DEBUG("Exposing additional CSR %d (name=%s)",
4436                                                                 csr_number, entry->name ? entry->name : reg_name);
4437
4438                                                 r->exist = true;
4439                                                 break;
4440                                         }
4441                         }
4442
4443                 } else if (number == GDB_REGNO_PRIV) {
4444                         sprintf(reg_name, "priv");
4445                         r->group = "general";
4446                         r->feature = &feature_virtual;
4447                         r->size = 8;
4448
4449                 } else if (number >= GDB_REGNO_V0 && number <= GDB_REGNO_V31) {
4450                         r->caller_save = false;
4451                         r->exist = riscv_supports_extension(target, 'V') && info->vlenb;
4452                         r->size = info->vlenb * 8;
4453                         sprintf(reg_name, "v%d", number - GDB_REGNO_V0);
4454                         r->group = "vector";
4455                         r->feature = &feature_vector;
4456                         r->reg_data_type = &info->type_vector;
4457
4458                 } else if (number >= GDB_REGNO_COUNT) {
4459                         /* Custom registers. */
4460                         assert(!list_empty(&info->expose_custom));
4461
4462                         range_list_t *range = list_first_entry(&info->expose_custom, range_list_t, list);
4463
4464                         unsigned custom_number = range->low + custom_within_range;
4465
4466                         r->group = "custom";
4467                         r->feature = &feature_custom;
4468                         r->arch_info = calloc(1, sizeof(riscv_reg_info_t));
4469                         if (!r->arch_info)
4470                                 return ERROR_FAIL;
4471                         ((riscv_reg_info_t *) r->arch_info)->target = target;
4472                         ((riscv_reg_info_t *) r->arch_info)->custom_number = custom_number;
4473                         sprintf(reg_name, "custom%d", custom_number);
4474
4475                         if (range->name) {
4476                                 *reg_name = 0;
4477                                 r->name = range->name;
4478                         }
4479
4480                         LOG_DEBUG("Exposing additional custom register %d (name=%s)",
4481                                         number, range->name ? range->name : reg_name);
4482
4483                         custom_within_range++;
4484                         if (custom_within_range > range->high - range->low) {
4485                                 custom_within_range = 0;
4486                                 list_rotate_left(&info->expose_custom);
4487                         }
4488                 }
4489
4490                 if (reg_name[0]) {
4491                         r->name = reg_name;
4492                         reg_name += strlen(reg_name) + 1;
4493                         assert(reg_name < info->reg_names + target->reg_cache->num_regs *
4494                                         max_reg_name_len);
4495                 }
4496                 r->value = calloc(1, DIV_ROUND_UP(r->size, 8));
4497         }
4498
4499         return ERROR_OK;
4500 }
4501
4502
4503 void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
4504                                         riscv_bscan_tunneled_scan_context_t *ctxt)
4505 {
4506         jtag_add_ir_scan(target->tap, &select_user4, TAP_IDLE);
4507
4508         memset(ctxt->tunneled_dr, 0, sizeof(ctxt->tunneled_dr));
4509         if (bscan_tunnel_type == BSCAN_TUNNEL_DATA_REGISTER) {
4510                 ctxt->tunneled_dr[3].num_bits = 1;
4511                 ctxt->tunneled_dr[3].out_value = bscan_one;
4512                 ctxt->tunneled_dr[2].num_bits = 7;
4513                 ctxt->tunneled_dr_width = field->num_bits;
4514                 ctxt->tunneled_dr[2].out_value = &ctxt->tunneled_dr_width;
4515                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4516                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4517
4518                 ctxt->tunneled_dr[1].num_bits = field->num_bits + 1;
4519                 ctxt->tunneled_dr[1].out_value = field->out_value;
4520                 ctxt->tunneled_dr[1].in_value = field->in_value;
4521
4522                 ctxt->tunneled_dr[0].num_bits = 3;
4523                 ctxt->tunneled_dr[0].out_value = bscan_zero;
4524         } else {
4525                 /* BSCAN_TUNNEL_NESTED_TAP */
4526                 ctxt->tunneled_dr[0].num_bits = 1;
4527                 ctxt->tunneled_dr[0].out_value = bscan_one;
4528                 ctxt->tunneled_dr[1].num_bits = 7;
4529                 ctxt->tunneled_dr_width = field->num_bits;
4530                 ctxt->tunneled_dr[1].out_value = &ctxt->tunneled_dr_width;
4531                 /* for BSCAN tunnel, there is a one-TCK skew between shift in and shift out, so
4532                    scanning num_bits + 1, and then will right shift the input field after executing the queues */
4533                 ctxt->tunneled_dr[2].num_bits = field->num_bits + 1;
4534                 ctxt->tunneled_dr[2].out_value = field->out_value;
4535                 ctxt->tunneled_dr[2].in_value = field->in_value;
4536                 ctxt->tunneled_dr[3].num_bits = 3;
4537                 ctxt->tunneled_dr[3].out_value = bscan_zero;
4538         }
4539         jtag_add_dr_scan(target->tap, ARRAY_SIZE(ctxt->tunneled_dr), ctxt->tunneled_dr, TAP_IDLE);
4540 }