2 * This file is auto-generated by running 'make debug_defines.h' in
3 * https://github.com/riscv/riscv-debug-spec/ (3dfe4f7)
4 * License: Creative Commons Attribution 4.0 International Public License (CC BY 4.0)
7 #define DTM_IDCODE 0x01
9 * Identifies the release version of this part.
11 #define DTM_IDCODE_VERSION_OFFSET 28
12 #define DTM_IDCODE_VERSION_LENGTH 4
13 #define DTM_IDCODE_VERSION (0xfU << DTM_IDCODE_VERSION_OFFSET)
15 * Identifies the designer's part number of this part.
17 #define DTM_IDCODE_PARTNUMBER_OFFSET 12
18 #define DTM_IDCODE_PARTNUMBER_LENGTH 16
19 #define DTM_IDCODE_PARTNUMBER (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET)
21 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
22 * bits 6:0 of the designer/manufacturer's Identification Code as
23 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
24 * count of the number of continuation characters (0x7f) in that same
25 * Identification Code.
27 #define DTM_IDCODE_MANUFID_OFFSET 1
28 #define DTM_IDCODE_MANUFID_LENGTH 11
29 #define DTM_IDCODE_MANUFID (0x7ffU << DTM_IDCODE_MANUFID_OFFSET)
30 #define DTM_IDCODE_1_OFFSET 0
31 #define DTM_IDCODE_1_LENGTH 1
32 #define DTM_IDCODE_1 (0x1U << DTM_IDCODE_1_OFFSET)
33 #define DTM_DTMCS 0x10
35 * Writing 1 to this bit does a hard reset of the DTM,
36 * causing the DTM to forget about any outstanding DMI transactions, and
37 * returning all registers and internal state to their reset value.
38 * In general this should only be used when the Debugger has
39 * reason to expect that the outstanding DMI transaction will never
40 * complete (e.g. a reset condition caused an inflight DMI transaction to
43 #define DTM_DTMCS_DMIHARDRESET_OFFSET 17
44 #define DTM_DTMCS_DMIHARDRESET_LENGTH 1
45 #define DTM_DTMCS_DMIHARDRESET (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET)
47 * Writing 1 to this bit clears the sticky error state, but does
48 * not affect outstanding DMI transactions.
50 #define DTM_DTMCS_DMIRESET_OFFSET 16
51 #define DTM_DTMCS_DMIRESET_LENGTH 1
52 #define DTM_DTMCS_DMIRESET (0x1U << DTM_DTMCS_DMIRESET_OFFSET)
54 * This is a hint to the debugger of the minimum number of
55 * cycles a debugger should spend in
56 * Run-Test/Idle after every DMI scan to avoid a `busy'
57 * return code (\FdtmDtmcsDmistat of 3). A debugger must still
58 * check \FdtmDtmcsDmistat when necessary.
60 * 0: It is not necessary to enter Run-Test/Idle at all.
62 * 1: Enter Run-Test/Idle and leave it immediately.
64 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
68 #define DTM_DTMCS_IDLE_OFFSET 12
69 #define DTM_DTMCS_IDLE_LENGTH 3
70 #define DTM_DTMCS_IDLE (0x7U << DTM_DTMCS_IDLE_OFFSET)
74 * 1: Reserved. Interpret the same as 2.
76 * 2: An operation failed (resulted in \FdtmDmiOp of 2).
78 * 3: An operation was attempted while a DMI access was still in
79 * progress (resulted in \FdtmDmiOp of 3).
81 #define DTM_DTMCS_DMISTAT_OFFSET 10
82 #define DTM_DTMCS_DMISTAT_LENGTH 2
83 #define DTM_DTMCS_DMISTAT (0x3U << DTM_DTMCS_DMISTAT_OFFSET)
85 * The size of \FdmSbaddressZeroAddress in \RdtmDmi.
87 #define DTM_DTMCS_ABITS_OFFSET 4
88 #define DTM_DTMCS_ABITS_LENGTH 6
89 #define DTM_DTMCS_ABITS (0x3fU << DTM_DTMCS_ABITS_OFFSET)
91 * 0: Version described in spec version 0.11.
93 * 1: Version described in spec versions 0.13 and 1.0.
95 * 15: Version not described in any available version of this spec.
97 #define DTM_DTMCS_VERSION_OFFSET 0
98 #define DTM_DTMCS_VERSION_LENGTH 4
99 #define DTM_DTMCS_VERSION (0xfU << DTM_DTMCS_VERSION_OFFSET)
102 * Address used for DMI access. In Update-DR this value is used
103 * to access the DM over the DMI.
105 #define DTM_DMI_ADDRESS_OFFSET 34
106 #define DTM_DMI_ADDRESS_LENGTH abits
107 #define DTM_DMI_ADDRESS (((1L << abits) - 1) << DTM_DMI_ADDRESS_OFFSET)
109 * The data to send to the DM over the DMI during Update-DR, and
110 * the data returned from the DM as a result of the previous operation.
112 #define DTM_DMI_DATA_OFFSET 2
113 #define DTM_DMI_DATA_LENGTH 32
114 #define DTM_DMI_DATA (0xffffffffULL << DTM_DMI_DATA_OFFSET)
116 * When the debugger writes this field, it has the following meaning:
118 * 0: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. (nop)
120 * Don't send anything over the DMI during Update-DR.
121 * This operation should never result in a busy or error response.
122 * The address and data reported in the following Capture-DR
125 * 1: Read from \FdmSbaddressZeroAddress. (read)
127 * 2: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. (write)
131 * When the debugger reads this field, it means the following:
133 * 0: The previous operation completed successfully.
137 * 2: A previous operation failed. The data scanned into \RdtmDmi in
138 * this access will be ignored. This status is sticky and can be
139 * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs.
141 * This indicates that the DM itself responded with an error.
142 * There are no specified cases in which the DM would
143 * respond with an error, and DMI is not required to support
146 * 3: An operation was attempted while a DMI request is still in
147 * progress. The data scanned into \RdtmDmi in this access will be
148 * ignored. This status is sticky and can be cleared by writing
149 * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it
150 * needs to give the target more TCK edges between Update-DR and
151 * Capture-DR. The simplest way to do that is to add extra transitions
154 #define DTM_DMI_OP_OFFSET 0
155 #define DTM_DMI_OP_LENGTH 2
156 #define DTM_DMI_OP (0x3ULL << DTM_DMI_OP_OFFSET)
157 #define CSR_DCSR 0x7b0
159 * 0: There is no debug support.
161 * 4: Debug support exists as it is described in this document.
163 * 15: There is debug support, but it does not conform to any
164 * available version of this spec.
166 #define CSR_DCSR_DEBUGVER_OFFSET 28
167 #define CSR_DCSR_DEBUGVER_LENGTH 4
168 #define CSR_DCSR_DEBUGVER (0xfU << CSR_DCSR_DEBUGVER_OFFSET)
170 * 0: {\tt ebreak} instructions in VS-mode behave as described in the
173 * 1: {\tt ebreak} instructions in VS-mode enter Debug Mode.
175 * This bit is hardwired to 0 if the hart does not support virtualization mode.
177 #define CSR_DCSR_EBREAKVS_OFFSET 17
178 #define CSR_DCSR_EBREAKVS_LENGTH 1
179 #define CSR_DCSR_EBREAKVS (0x1U << CSR_DCSR_EBREAKVS_OFFSET)
181 * 0: {\tt ebreak} instructions in VU-mode behave as described in the
184 * 1: {\tt ebreak} instructions in VU-mode enter Debug Mode.
186 * This bit is hardwired to 0 if the hart does not support virtualization mode.
188 #define CSR_DCSR_EBREAKVU_OFFSET 16
189 #define CSR_DCSR_EBREAKVU_LENGTH 1
190 #define CSR_DCSR_EBREAKVU (0x1U << CSR_DCSR_EBREAKVU_OFFSET)
192 * 0: {\tt ebreak} instructions in M-mode behave as described in the
195 * 1: {\tt ebreak} instructions in M-mode enter Debug Mode.
197 #define CSR_DCSR_EBREAKM_OFFSET 15
198 #define CSR_DCSR_EBREAKM_LENGTH 1
199 #define CSR_DCSR_EBREAKM (0x1U << CSR_DCSR_EBREAKM_OFFSET)
201 * 0: {\tt ebreak} instructions in S-mode behave as described in the
204 * 1: {\tt ebreak} instructions in S-mode enter Debug Mode.
206 * This bit is hardwired to 0 if the hart does not support S-mode.
208 #define CSR_DCSR_EBREAKS_OFFSET 13
209 #define CSR_DCSR_EBREAKS_LENGTH 1
210 #define CSR_DCSR_EBREAKS (0x1U << CSR_DCSR_EBREAKS_OFFSET)
212 * 0: {\tt ebreak} instructions in U-mode behave as described in the
215 * 1: {\tt ebreak} instructions in U-mode enter Debug Mode.
217 * This bit is hardwired to 0 if the hart does not support U-mode.
219 #define CSR_DCSR_EBREAKU_OFFSET 12
220 #define CSR_DCSR_EBREAKU_LENGTH 1
221 #define CSR_DCSR_EBREAKU (0x1U << CSR_DCSR_EBREAKU_OFFSET)
223 * 0: Interrupts (including NMI) are disabled during single stepping.
225 * 1: Interrupts (including NMI) are enabled during single stepping.
227 * Implementations may hard wire this bit to 0.
228 * In that case interrupt behavior can be emulated by the debugger.
230 * The debugger must not change the value of this bit while the hart
233 #define CSR_DCSR_STEPIE_OFFSET 11
234 #define CSR_DCSR_STEPIE_LENGTH 1
235 #define CSR_DCSR_STEPIE (0x1U << CSR_DCSR_STEPIE_OFFSET)
237 * 0: Increment counters as usual.
239 * 1: Don't increment any hart-local counters while in Debug Mode or
240 * on {\tt ebreak} instructions that cause entry into Debug Mode.
241 * These counters include the {\tt instret} CSR. On single-hart cores
242 * {\tt cycle} should be stopped, but on multi-hart cores it must keep
245 * An implementation may hardwire this bit to 0 or 1.
247 #define CSR_DCSR_STOPCOUNT_OFFSET 10
248 #define CSR_DCSR_STOPCOUNT_LENGTH 1
249 #define CSR_DCSR_STOPCOUNT (0x1U << CSR_DCSR_STOPCOUNT_OFFSET)
251 * 0: Increment timers as usual.
253 * 1: Don't increment any hart-local timers while in Debug Mode.
255 * An implementation may hardwire this bit to 0 or 1.
257 #define CSR_DCSR_STOPTIME_OFFSET 9
258 #define CSR_DCSR_STOPTIME_LENGTH 1
259 #define CSR_DCSR_STOPTIME (0x1U << CSR_DCSR_STOPTIME_OFFSET)
261 * Explains why Debug Mode was entered.
263 * When there are multiple reasons to enter Debug Mode in a single
264 * cycle, hardware should set \FcsrDcsrCause to the cause with the highest
267 * 1: An {\tt ebreak} instruction was executed. (priority 3)
269 * 2: A Trigger Module trigger fired with action=0. (priority 4)
271 * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
274 * 4: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest)
276 * 5: The hart halted directly out of reset due to \Fresethaltreq. It
277 * is also acceptable to report 3 when this happens. (priority 2)
279 * 6: The hart halted because it's part of a halt group. (priority 5,
280 * highest) Harts may report 3 for this cause instead.
282 * Other values are reserved for future use.
284 #define CSR_DCSR_CAUSE_OFFSET 6
285 #define CSR_DCSR_CAUSE_LENGTH 3
286 #define CSR_DCSR_CAUSE (0x7U << CSR_DCSR_CAUSE_OFFSET)
288 * Extends the prv field with the virtualization mode the hart was operating
289 * in when Debug Mode was entered. The encoding is described in Table
290 * \ref{tab:privlevel}.
291 * A debugger can change this value to change the hart's virtualization mode
292 * when exiting Debug Mode.
293 * This bit is hardwired to 0 on harts that do not support virtualization mode.
295 #define CSR_DCSR_V_OFFSET 5
296 #define CSR_DCSR_V_LENGTH 1
297 #define CSR_DCSR_V (0x1U << CSR_DCSR_V_OFFSET)
299 * 0: \FcsrMstatusMprv in \Rmstatus is ignored in Debug Mode.
301 * 1: \FcsrMstatusMprv in \Rmstatus takes effect in Debug Mode.
303 * Implementing this bit is optional. It may be tied to either 0 or 1.
305 #define CSR_DCSR_MPRVEN_OFFSET 4
306 #define CSR_DCSR_MPRVEN_LENGTH 1
307 #define CSR_DCSR_MPRVEN (0x1U << CSR_DCSR_MPRVEN_OFFSET)
309 * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
311 * Since an NMI can indicate a hardware error condition,
312 * reliable debugging may no longer be possible once this bit becomes set.
313 * This is implementation-dependent.
315 #define CSR_DCSR_NMIP_OFFSET 3
316 #define CSR_DCSR_NMIP_LENGTH 1
317 #define CSR_DCSR_NMIP (0x1U << CSR_DCSR_NMIP_OFFSET)
319 * When set and not in Debug Mode, the hart will only execute a single
320 * instruction and then enter Debug Mode. See Section~\ref{stepBit}
323 * The debugger must not change the value of this bit while the hart
326 #define CSR_DCSR_STEP_OFFSET 2
327 #define CSR_DCSR_STEP_LENGTH 1
328 #define CSR_DCSR_STEP (0x1U << CSR_DCSR_STEP_OFFSET)
330 * Contains the privilege level the hart was operating in when Debug
331 * Mode was entered. The encoding is described in Table
332 * \ref{tab:privlevel}. A debugger can change this value to change
333 * the hart's privilege level when exiting Debug Mode.
335 * Not all privilege levels are supported on all harts. If the
336 * encoding written is not supported or the debugger is not allowed to
337 * change to it, the hart may change to any supported privilege level.
339 #define CSR_DCSR_PRV_OFFSET 0
340 #define CSR_DCSR_PRV_LENGTH 2
341 #define CSR_DCSR_PRV (0x3U << CSR_DCSR_PRV_OFFSET)
342 #define CSR_DPC 0x7b1
343 #define CSR_DPC_DPC_OFFSET 0
344 #define CSR_DPC_DPC_LENGTH DXLEN
345 #define CSR_DPC_DPC (((1L << DXLEN) - 1) << CSR_DPC_DPC_OFFSET)
346 #define CSR_DSCRATCH0 0x7b2
347 #define CSR_DSCRATCH1 0x7b3
348 #define CSR_TSELECT 0x7a0
349 #define CSR_TSELECT_INDEX_OFFSET 0
350 #define CSR_TSELECT_INDEX_LENGTH XLEN
351 #define CSR_TSELECT_INDEX (((1L << XLEN) - 1) << CSR_TSELECT_INDEX_OFFSET)
352 #define CSR_TDATA1 0x7a1
354 * 0: There is no trigger at this \RcsrTselect.
356 * 1: The trigger is a legacy SiFive address match trigger. These
357 * should not be implemented and aren't further documented here.
359 * 2: The trigger is an address/data match trigger. The remaining bits
360 * in this register act as described in \RcsrMcontrol.
362 * 3: The trigger is an instruction count trigger. The remaining bits
363 * in this register act as described in \RcsrIcount.
365 * 4: The trigger is an interrupt trigger. The remaining bits
366 * in this register act as described in \RcsrItrigger.
368 * 5: The trigger is an exception trigger. The remaining bits
369 * in this register act as described in \RcsrEtrigger.
371 * 6: The trigger is an address/data match trigger. The remaining bits
372 * in this register act as described in \RcsrMcontrolSix. This is similar
373 * to a type 2 trigger, but provides additional functionality and
374 * should be used instead of type 2 in newer implementations.
376 * 7: The trigger is a trigger source external to the TM. The
377 * remaining bits in this register act as described in \RcsrTmexttrigger.
379 * 12--14: These trigger types are available for non-standard use.
381 * 15: This trigger exists (so enumeration shouldn't terminate), but
382 * is not currently available.
384 * Other values are reserved for future use.
386 #define CSR_TDATA1_TYPE_OFFSET (XLEN-4)
387 #define CSR_TDATA1_TYPE_LENGTH 4
388 #define CSR_TDATA1_TYPE (0xfULL << CSR_TDATA1_TYPE_OFFSET)
390 * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.
392 * 0: Both Debug and M-mode can write the {\tt tdata} registers at the
393 * selected \RcsrTselect.
395 * 1: Only Debug Mode can write the {\tt tdata} registers at the
396 * selected \RcsrTselect. Writes from other modes are ignored.
398 * This bit is only writable from Debug Mode.
399 * In ordinary use, external debuggers will always set this bit when
400 * configuring a trigger.
401 * When clearing this bit, debuggers should also clear the action field
402 * (whose location depends on \FcsrTdataOneType).
404 #define CSR_TDATA1_DMODE_OFFSET (XLEN-5)
405 #define CSR_TDATA1_DMODE_LENGTH 1
406 #define CSR_TDATA1_DMODE (0x1ULL << CSR_TDATA1_DMODE_OFFSET)
408 * If \FcsrTdataOneType is 0, then this field is hard-wired to 0.
410 * Trigger-specific data.
412 #define CSR_TDATA1_DATA_OFFSET 0
413 #define CSR_TDATA1_DATA_LENGTH (XLEN - 5)
414 #define CSR_TDATA1_DATA (((1L << XLEN - 5) - 1) << CSR_TDATA1_DATA_OFFSET)
415 #define CSR_TDATA2 0x7a2
416 #define CSR_TDATA2_DATA_OFFSET 0
417 #define CSR_TDATA2_DATA_LENGTH XLEN
418 #define CSR_TDATA2_DATA (((1L << XLEN) - 1) << CSR_TDATA2_DATA_OFFSET)
419 #define CSR_TDATA3 0x7a3
420 #define CSR_TDATA3_DATA_OFFSET 0
421 #define CSR_TDATA3_DATA_LENGTH XLEN
422 #define CSR_TDATA3_DATA (((1L << XLEN) - 1) << CSR_TDATA3_DATA_OFFSET)
423 #define CSR_TINFO 0x7a4
425 * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N
426 * corresponds to type N. If the bit is set, then that type is
427 * supported by the currently selected trigger.
429 * If the currently selected trigger doesn't exist, this field
432 #define CSR_TINFO_INFO_OFFSET 0
433 #define CSR_TINFO_INFO_LENGTH 16
434 #define CSR_TINFO_INFO (0xffffULL << CSR_TINFO_INFO_OFFSET)
435 #define CSR_TCONTROL 0x7a5
437 * \RcsrHcontext enable.
439 * 0: \RcsrHcontext is set to 0 and writes are ignored.
441 * 1: \RcsrHcontext may be written and read.
443 #define CSR_TCONTROL_HCXE_OFFSET 9
444 #define CSR_TCONTROL_HCXE_LENGTH 1
445 #define CSR_TCONTROL_HCXE (0x1ULL << CSR_TCONTROL_HCXE_OFFSET)
447 * \RcsrScontext enable.
449 * 0: \RcsrScontext is set to 0 and writes are ignored.
451 * 1: \RcsrScontext may be written and read.
453 * Enabling \RcsrScontext can be a security risk in a
454 * virtualized system with a hypervisor that does not swap \RcsrScontext.
456 #define CSR_TCONTROL_SCXE_OFFSET 8
457 #define CSR_TCONTROL_SCXE_LENGTH 1
458 #define CSR_TCONTROL_SCXE (0x1ULL << CSR_TCONTROL_SCXE_OFFSET)
460 * M-mode previous trigger enable field.
462 * \FcsrTcontrolMpte and \FcsrTcontrolMte provide one solution to a problem
463 * regarding triggers with action=0 firing in M-mode trap handlers. See
464 * Section~\ref{sec:nativetrigger} for more details.
466 * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
469 #define CSR_TCONTROL_MPTE_OFFSET 7
470 #define CSR_TCONTROL_MPTE_LENGTH 1
471 #define CSR_TCONTROL_MPTE (0x1ULL << CSR_TCONTROL_MPTE_OFFSET)
473 * M-mode trigger enable field.
475 * 0: Triggers with action=0 do not match/fire while the hart is in M-mode.
477 * 1: Triggers do match/fire while the hart is in M-mode.
479 * When a trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt
480 * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
482 #define CSR_TCONTROL_MTE_OFFSET 3
483 #define CSR_TCONTROL_MTE_LENGTH 1
484 #define CSR_TCONTROL_MTE (0x1ULL << CSR_TCONTROL_MTE_OFFSET)
485 #define CSR_HCONTEXT 0x6a8
487 * Hypervisor mode software can write a context number to this register,
488 * which can be used to set triggers that only fire in that specific
491 * An implementation may tie any number of upper bits in this field to
492 * 0. If the H extension is not implemented, it's recommended to implement
493 * no more than 6 bits on RV32 and 13 on RV64 (as visible through the
494 * \RcsrMcontext register). If the H extension is implemented,
495 * it's recommended to implement no more than 7 bits on RV32
498 #define CSR_HCONTEXT_HCONTEXT_OFFSET 0
499 #define CSR_HCONTEXT_HCONTEXT_LENGTH XLEN
500 #define CSR_HCONTEXT_HCONTEXT (((1L << XLEN) - 1) << CSR_HCONTEXT_HCONTEXT_OFFSET)
501 #define CSR_SCONTEXT 0x5a8
503 * Supervisor mode software can write a context number to this
504 * register, which can be used to set triggers that only fire in that
507 * An implementation may tie any number of high bits in this field to
508 * 0. It's recommended to implement no more than 16 bits on RV32, and
511 #define CSR_SCONTEXT_DATA_OFFSET 0
512 #define CSR_SCONTEXT_DATA_LENGTH XLEN
513 #define CSR_SCONTEXT_DATA (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET)
514 #define CSR_MCONTEXT 0x7a8
515 #define CSR_MSCONTEXT 0x7aa
516 #define CSR_MCONTROL 0x7a1
517 #define CSR_MCONTROL_TYPE_OFFSET (XLEN-4)
518 #define CSR_MCONTROL_TYPE_LENGTH 4
519 #define CSR_MCONTROL_TYPE (0xfULL << CSR_MCONTROL_TYPE_OFFSET)
520 #define CSR_MCONTROL_DMODE_OFFSET (XLEN-5)
521 #define CSR_MCONTROL_DMODE_LENGTH 1
522 #define CSR_MCONTROL_DMODE (0x1ULL << CSR_MCONTROL_DMODE_OFFSET)
524 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
525 * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
526 * logarithm base 2 of the number of bytes in that range.
527 * A value of 0 indicates \FcsrMcontrolMatch 1 is not supported.
528 * A value of 63 corresponds to the maximum NAPOT range, which is
529 * $2^{63}$ bytes in size.
531 #define CSR_MCONTROL_MASKMAX_OFFSET (XLEN-11)
532 #define CSR_MCONTROL_MASKMAX_LENGTH 6
533 #define CSR_MCONTROL_MASKMAX (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET)
535 * This field only exists when XLEN is at least 64.
536 * It contains the 2 high bits of the access size. The low bits
537 * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this
540 #define CSR_MCONTROL_SIZEHI_OFFSET 21
541 #define CSR_MCONTROL_SIZEHI_LENGTH 2
542 #define CSR_MCONTROL_SIZEHI (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET)
544 * If this bit is implemented then it must become set when this
545 * trigger fires and may become set when this trigger matches.
546 * The trigger's user can set or clear it at any
547 * time. It is used to determine which
548 * trigger(s) matched. If the bit is not implemented, it is always 0
549 * and writing it has no effect.
551 #define CSR_MCONTROL_HIT_OFFSET 20
552 #define CSR_MCONTROL_HIT_LENGTH 1
553 #define CSR_MCONTROL_HIT (0x1ULL << CSR_MCONTROL_HIT_OFFSET)
555 * This bit determines the contents of the XLEN-bit compare values.
557 * 0: There is at least one compare value and it contains the lowest
558 * virtual address of the access.
559 * It is recommended that there are additional compare values for
560 * the other accessed virtual addresses.
561 * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
562 * and the other addresses are 0x4001, 0x4002, and 0x4003.)
564 * 1: There is exactly one compare value and it contains the data
565 * value loaded or stored, or the instruction executed.
566 * Any bits beyond the size of the data access will contain 0.
568 #define CSR_MCONTROL_SELECT_OFFSET 19
569 #define CSR_MCONTROL_SELECT_LENGTH 1
570 #define CSR_MCONTROL_SELECT (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
572 * 0: The action for this trigger will be taken just before the
573 * instruction that triggered it is committed, but after all preceding
574 * instructions are committed. \Rxepc or \RcsrDpc (depending
575 * on \FcsrMcontrolAction) must be set to the virtual address of the
576 * instruction that matched.
578 * If this is combined with \FcsrMcontrolLoad and
579 * \FcsrMcontrolSelect=1 then a memory access will be
580 * performed (including any side effects of performing such an access) even
581 * though the load will not update its destination register. Debuggers
582 * should consider this when setting such breakpoints on, for example,
583 * memory-mapped I/O addresses.
585 * 1: The action for this trigger will be taken after the instruction
586 * that triggered it is committed. It should be taken before the next
587 * instruction is committed, but it is better to implement triggers imprecisely
588 * than to not implement them at all. \Rxepc or
589 * \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
590 * the virtual address of the next instruction that must be executed to
591 * preserve the program flow.
593 * Most hardware will only implement one timing or the other, possibly
594 * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute,
595 * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit
596 * primarily exists for the hardware to communicate to the debugger
597 * what will happen. Hardware may implement the bit fully writable, in
598 * which case the debugger has a little more control.
600 * Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load
601 * happening again when the debugger lets the hart run. For data load
602 * triggers, debuggers must first attempt to set the breakpoint with
603 * \FcsrMcontrolTiming of 1.
605 * If a trigger with \FcsrMcontrolTiming of 0 matches, it is
606 * implementation-dependent whether that prevents a trigger with
607 * \FcsrMcontrolTiming of 1 matching as well.
609 #define CSR_MCONTROL_TIMING_OFFSET 18
610 #define CSR_MCONTROL_TIMING_LENGTH 1
611 #define CSR_MCONTROL_TIMING (0x1ULL << CSR_MCONTROL_TIMING_OFFSET)
613 * This field contains the 2 low bits of the access size. The high bits come
614 * from \FcsrMcontrolSizehi. The combined value is interpreted as follows:
616 * 0: The trigger will attempt to match against an access of any size.
617 * The behavior is only well-defined if $|select|=0$, or if the access
620 * 1: The trigger will only match against 8-bit memory accesses.
622 * 2: The trigger will only match against 16-bit memory accesses or
623 * execution of 16-bit instructions.
625 * 3: The trigger will only match against 32-bit memory accesses or
626 * execution of 32-bit instructions.
628 * 4: The trigger will only match against execution of 48-bit instructions.
630 * 5: The trigger will only match against 64-bit memory accesses or
631 * execution of 64-bit instructions.
633 * 6: The trigger will only match against execution of 80-bit instructions.
635 * 7: The trigger will only match against execution of 96-bit instructions.
637 * 8: The trigger will only match against execution of 112-bit instructions.
639 * 9: The trigger will only match against 128-bit memory accesses or
640 * execution of 128-bit instructions.
642 * An implementation must support the value of 0, but all other values
643 * are optional. When an implementation supports address triggers
644 * (\FcsrMcontrolSelect=0), it is recommended that those triggers
645 * support every access size that the hart supports, as well as for
646 * every instruction size that the hart supports.
648 * Implementations such as RV32D or RV64V are able to perform loads
649 * and stores that are wider than XLEN. Custom extensions may also
650 * support instructions that are wider than XLEN. Because
651 * \RcsrTdataTwo is of size XLEN, there is a known limitation that
652 * data value triggers (\FcsrMcontrolSelect=1) can only be supported
653 * for access sizes up to XLEN bits. When an implementation supports
654 * data value triggers (\FcsrMcontrolSelect=1), it is recommended
655 * that those triggers support every access size up to XLEN that the
656 * hart supports, as well as for every instruction length up to XLEN
657 * that the hart supports.
659 #define CSR_MCONTROL_SIZELO_OFFSET 16
660 #define CSR_MCONTROL_SIZELO_LENGTH 2
661 #define CSR_MCONTROL_SIZELO (0x3ULL << CSR_MCONTROL_SIZELO_OFFSET)
663 * The action to take when the trigger fires. The values are explained
664 * in Table~\ref{tab:action}.
666 #define CSR_MCONTROL_ACTION_OFFSET 12
667 #define CSR_MCONTROL_ACTION_LENGTH 4
668 #define CSR_MCONTROL_ACTION (0xfULL << CSR_MCONTROL_ACTION_OFFSET)
670 * 0: When this trigger matches, the configured action is taken.
672 * 1: While this trigger does not match, it prevents the trigger with
673 * the next index from matching.
675 * A trigger chain starts on the first trigger with $|chain|=1$ after
676 * a trigger with $|chain|=0$, or simply on the first trigger if that
677 * has $|chain|=1$. It ends on the first trigger after that which has
678 * $|chain|=0$. This final trigger is part of the chain. The action
679 * on all but the final trigger is ignored. The action on that final
680 * trigger will be taken if and only if all the triggers in the chain
681 * match at the same time.
683 * Debuggers should not terminate a chain with a trigger with a
684 * different type. It is undefined when exactly such a chain fires.
686 * Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in
687 * writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has
688 * \FcsrTdataOneDmode of 1.
689 * In addition hardware should ignore writes to \RcsrMcontrol that set
690 * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
691 * \FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking
692 * \FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol.
694 * Implementations that wish to limit the maximum length of a trigger
695 * chain (eg. to meet timing requirements) may do so by zeroing
696 * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long.
698 #define CSR_MCONTROL_CHAIN_OFFSET 11
699 #define CSR_MCONTROL_CHAIN_LENGTH 1
700 #define CSR_MCONTROL_CHAIN (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
702 * 0: Matches when any compare value equals \RcsrTdataTwo.
704 * 1: Matches when the top $M$ bits of any compare value match the top
705 * $M$ bits of \RcsrTdataTwo.
706 * $M$ is $|XLEN|-1$ minus the index of the least-significant
707 * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values
708 * to \RcsrTdataTwo such that $M + $\FcsrMcontrolMaskmax$ \geq |XLEN|$
709 * and $M\gt0$ , otherwise it's undefined on what conditions the
710 * trigger will match.
712 * 2: Matches when any compare value is greater than (unsigned) or
713 * equal to \RcsrTdataTwo.
715 * 3: Matches when any compare value is less than (unsigned)
718 * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
719 * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
720 * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
721 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
723 * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
724 * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
725 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
726 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
728 * 8: Matches when \FcsrMcontrolMatch$=0$ would not match.
730 * 9: Matches when \FcsrMcontrolMatch$=1$ would not match.
732 * 12: Matches when \FcsrMcontrolMatch$=4$ would not match.
734 * 13: Matches when \FcsrMcontrolMatch$=5$ would not match.
736 * Other values are reserved for future use.
738 * All comparisons only look at the lower XLEN (in the current mode)
739 * bits of the compare values and of \RcsrTdataTwo.
740 * When \FcsrMcontrolSelect=1 and access size is N, this is further
741 * reduced, and comparisons only look at the lower N bits of the
742 * compare values and of \RcsrTdataTwo.
744 #define CSR_MCONTROL_MATCH_OFFSET 7
745 #define CSR_MCONTROL_MATCH_LENGTH 4
746 #define CSR_MCONTROL_MATCH (0xfULL << CSR_MCONTROL_MATCH_OFFSET)
748 * When set, enable this trigger in M-mode.
750 #define CSR_MCONTROL_M_OFFSET 6
751 #define CSR_MCONTROL_M_LENGTH 1
752 #define CSR_MCONTROL_M (0x1ULL << CSR_MCONTROL_M_OFFSET)
754 * When set, enable this trigger in S/HS-mode.
755 * This bit is hard-wired to 0 if the hart does not support
758 #define CSR_MCONTROL_S_OFFSET 4
759 #define CSR_MCONTROL_S_LENGTH 1
760 #define CSR_MCONTROL_S (0x1ULL << CSR_MCONTROL_S_OFFSET)
762 * When set, enable this trigger in U-mode.
763 * This bit is hard-wired to 0 if the hart does not support
766 #define CSR_MCONTROL_U_OFFSET 3
767 #define CSR_MCONTROL_U_LENGTH 1
768 #define CSR_MCONTROL_U (0x1ULL << CSR_MCONTROL_U_OFFSET)
770 * When set, the trigger fires on the virtual address or opcode of an
771 * instruction that is executed.
773 #define CSR_MCONTROL_EXECUTE_OFFSET 2
774 #define CSR_MCONTROL_EXECUTE_LENGTH 1
775 #define CSR_MCONTROL_EXECUTE (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET)
777 * When set, the trigger fires on the virtual address or data of any
780 #define CSR_MCONTROL_STORE_OFFSET 1
781 #define CSR_MCONTROL_STORE_LENGTH 1
782 #define CSR_MCONTROL_STORE (0x1ULL << CSR_MCONTROL_STORE_OFFSET)
784 * When set, the trigger fires on the virtual address or data of any
787 #define CSR_MCONTROL_LOAD_OFFSET 0
788 #define CSR_MCONTROL_LOAD_LENGTH 1
789 #define CSR_MCONTROL_LOAD (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
790 #define CSR_MCONTROL6 0x7a1
791 #define CSR_MCONTROL6_TYPE_OFFSET (XLEN-4)
792 #define CSR_MCONTROL6_TYPE_LENGTH 4
793 #define CSR_MCONTROL6_TYPE (0xfULL << CSR_MCONTROL6_TYPE_OFFSET)
794 #define CSR_MCONTROL6_DMODE_OFFSET (XLEN-5)
795 #define CSR_MCONTROL6_DMODE_LENGTH 1
796 #define CSR_MCONTROL6_DMODE (0x1ULL << CSR_MCONTROL6_DMODE_OFFSET)
798 * When set, enable this trigger in VS-mode.
799 * This bit is hard-wired to 0 if the hart does not support
800 * virtualization mode.
802 #define CSR_MCONTROL6_VS_OFFSET 24
803 #define CSR_MCONTROL6_VS_LENGTH 1
804 #define CSR_MCONTROL6_VS (0x1ULL << CSR_MCONTROL6_VS_OFFSET)
806 * When set, enable this trigger in VU-mode.
807 * This bit is hard-wired to 0 if the hart does not support
808 * virtualization mode.
810 #define CSR_MCONTROL6_VU_OFFSET 23
811 #define CSR_MCONTROL6_VU_LENGTH 1
812 #define CSR_MCONTROL6_VU (0x1ULL << CSR_MCONTROL6_VU_OFFSET)
814 * If this bit is implemented then it must become set when this
815 * trigger fires and may become set when this trigger matches.
816 * The trigger's user can set or clear it at any
817 * time. It is used to determine which
818 * trigger(s) matched. If the bit is not implemented, it is always 0
819 * and writing it has no effect.
821 #define CSR_MCONTROL6_HIT_OFFSET 22
822 #define CSR_MCONTROL6_HIT_LENGTH 1
823 #define CSR_MCONTROL6_HIT (0x1ULL << CSR_MCONTROL6_HIT_OFFSET)
825 * This bit determines the contents of the XLEN-bit compare values.
827 * 0: There is at least one compare value and it contains the lowest
828 * virtual address of the access.
829 * In addition, it is recommended that there are additional compare
830 * values for the other accessed virtual addresses match.
831 * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
832 * and the other addresses are 0x4001, 0x4002, and 0x4003.)
834 * 1: There is exactly one compare value and it contains the data
835 * value loaded or stored, or the instruction executed.
836 * Any bits beyond the size of the data access will contain 0.
838 #define CSR_MCONTROL6_SELECT_OFFSET 21
839 #define CSR_MCONTROL6_SELECT_LENGTH 1
840 #define CSR_MCONTROL6_SELECT (0x1ULL << CSR_MCONTROL6_SELECT_OFFSET)
842 * 0: The action for this trigger will be taken just before the
843 * instruction that triggered it is committed, but after all preceding
844 * instructions are committed. \Rxepc or \RcsrDpc (depending
845 * on \FcsrMcontrolSixAction) must be set to the virtual address of the
846 * instruction that matched.
848 * If this is combined with \FcsrMcontrolSixLoad and
849 * \FcsrMcontrolSixSelect=1 then a memory access will be
850 * performed (including any side effects of performing such an access) even
851 * though the load will not update its destination register. Debuggers
852 * should consider this when setting such breakpoints on, for example,
853 * memory-mapped I/O addresses.
855 * 1: The action for this trigger will be taken after the instruction
856 * that triggered it is committed. It should be taken before the next
857 * instruction is committed, but it is better to implement triggers imprecisely
858 * than to not implement them at all. \Rxepc or
859 * \RcsrDpc (depending on \FcsrMcontrolSixAction) must be set to
860 * the virtual address of the next instruction that must be executed to
861 * preserve the program flow.
863 * Most hardware will only implement one timing or the other, possibly
864 * dependent on \FcsrMcontrolSixSelect, \FcsrMcontrolSixExecute,
865 * \FcsrMcontrolSixLoad, and \FcsrMcontrolSixStore. This bit
866 * primarily exists for the hardware to communicate to the debugger
867 * what will happen. Hardware may implement the bit fully writable, in
868 * which case the debugger has a little more control.
870 * Data load triggers with \FcsrMcontrolSixTiming of 0 will result in the same load
871 * happening again when the debugger lets the hart run. For data load
872 * triggers, debuggers must first attempt to set the breakpoint with
873 * \FcsrMcontrolSixTiming of 1.
875 * If a trigger with \FcsrMcontrolSixTiming of 0 matches, it is
876 * implementation-dependent whether that prevents a trigger with
877 * \FcsrMcontrolSixTiming of 1 matching as well.
879 #define CSR_MCONTROL6_TIMING_OFFSET 20
880 #define CSR_MCONTROL6_TIMING_LENGTH 1
881 #define CSR_MCONTROL6_TIMING (0x1ULL << CSR_MCONTROL6_TIMING_OFFSET)
883 * 0: The trigger will attempt to match against an access of any size.
884 * The behavior is only well-defined if $|select|=0$, or if the access
887 * 1: The trigger will only match against 8-bit memory accesses.
889 * 2: The trigger will only match against 16-bit memory accesses or
890 * execution of 16-bit instructions.
892 * 3: The trigger will only match against 32-bit memory accesses or
893 * execution of 32-bit instructions.
895 * 4: The trigger will only match against execution of 48-bit instructions.
897 * 5: The trigger will only match against 64-bit memory accesses or
898 * execution of 64-bit instructions.
900 * 6: The trigger will only match against execution of 80-bit instructions.
902 * 7: The trigger will only match against execution of 96-bit instructions.
904 * 8: The trigger will only match against execution of 112-bit instructions.
906 * 9: The trigger will only match against 128-bit memory accesses or
907 * execution of 128-bit instructions.
909 * An implementation must support the value of 0, but all other values
910 * are optional. When an implementation supports address triggers
911 * (\FcsrMcontrolSixSelect=0), it is recommended that those triggers
912 * support every access size that the hart supports, as well as for
913 * every instruction size that the hart supports.
915 * Implementations such as RV32D or RV64V are able to perform loads
916 * and stores that are wider than XLEN. Custom extensions may also
917 * support instructions that are wider than XLEN. Because
918 * \RcsrTdataTwo is of size XLEN, there is a known limitation that
919 * data value triggers (\FcsrMcontrolSixSelect=1) can only be supported
920 * for access sizes up to XLEN bits. When an implementation supports
921 * data value triggers (\FcsrMcontrolSixSelect=1), it is recommended
922 * that those triggers support every access size up to XLEN that the
923 * hart supports, as well as for every instruction length up to XLEN
924 * that the hart supports.
926 #define CSR_MCONTROL6_SIZE_OFFSET 16
927 #define CSR_MCONTROL6_SIZE_LENGTH 4
928 #define CSR_MCONTROL6_SIZE (0xfULL << CSR_MCONTROL6_SIZE_OFFSET)
930 * The action to take when the trigger fires. The values are explained
931 * in Table~\ref{tab:action}.
933 #define CSR_MCONTROL6_ACTION_OFFSET 12
934 #define CSR_MCONTROL6_ACTION_LENGTH 4
935 #define CSR_MCONTROL6_ACTION (0xfULL << CSR_MCONTROL6_ACTION_OFFSET)
937 * 0: When this trigger matches, the configured action is taken.
939 * 1: While this trigger does not match, it prevents the trigger with
940 * the next index from matching.
942 * A trigger chain starts on the first trigger with $|chain|=1$ after
943 * a trigger with $|chain|=0$, or simply on the first trigger if that
944 * has $|chain|=1$. It ends on the first trigger after that which has
945 * $|chain|=0$. This final trigger is part of the chain. The action
946 * on all but the final trigger is ignored. The action on that final
947 * trigger will be taken if and only if all the triggers in the chain
948 * match at the same time.
950 * Debuggers should not terminate a chain with a trigger with a
951 * different type. It is undefined when exactly such a chain fires.
953 * Because \FcsrMcontrolSixChain affects the next trigger, hardware must zero it in
954 * writes to \RcsrMcontrolSix that set \FcsrTdataOneDmode to 0 if the next trigger has
955 * \FcsrTdataOneDmode of 1.
956 * In addition hardware should ignore writes to \RcsrMcontrolSix that set
957 * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
958 * \FcsrMcontrolSixChain of 1. Debuggers must avoid the latter case by checking
959 * \FcsrMcontrolSixChain on the previous trigger if they're writing \RcsrMcontrolSix.
961 * Implementations that wish to limit the maximum length of a trigger
962 * chain (eg. to meet timing requirements) may do so by zeroing
963 * \FcsrMcontrolSixChain in writes to \RcsrMcontrolSix that would make the chain too long.
965 #define CSR_MCONTROL6_CHAIN_OFFSET 11
966 #define CSR_MCONTROL6_CHAIN_LENGTH 1
967 #define CSR_MCONTROL6_CHAIN (0x1ULL << CSR_MCONTROL6_CHAIN_OFFSET)
969 * 0: Matches when any compare value equals \RcsrTdataTwo.
971 * 1: Matches when the top $M$ bits of any compare value match the top
972 * $M$ bits of \RcsrTdataTwo.
973 * $M$ is $|XLEN|-1$ minus the index of the least-significant bit
974 * containing 0 in \RcsrTdataTwo.
975 * \RcsrTdataTwo is WARL and bit $|maskmax6|-1$ will be set to 0 if no
976 * less significant bits are written with 0.
977 * Legal values for \RcsrTdataTwo require $M + |maskmax6| \geq |XLEN|$ and $M\gt0$.
978 * See above for how to determine maskmax6.
980 * 2: Matches when any compare value is greater than (unsigned) or
981 * equal to \RcsrTdataTwo.
983 * 3: Matches when any compare value is less than (unsigned)
986 * 4: Matches when $\frac{|XLEN|}{2}-1$:$0$ of any compare value
987 * equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
988 * $\frac{|XLEN|}{2}-1$:$0$ of the compare value is ANDed with
989 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
991 * 5: Matches when $|XLEN|-1$:$\frac{|XLEN|}{2}$ of any compare
992 * value equals $\frac{|XLEN|}{2}-1$:$0$ of \RcsrTdataTwo after
993 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of the compare value is ANDed with
994 * $|XLEN|-1$:$\frac{|XLEN|}{2}$ of \RcsrTdataTwo.
996 * 8: Matches when \FcsrMcontrolSixMatch$=0$ would not match.
998 * 9: Matches when \FcsrMcontrolSixMatch$=1$ would not match.
1000 * 12: Matches when \FcsrMcontrolSixMatch$=4$ would not match.
1002 * 13: Matches when \FcsrMcontrolSixMatch$=5$ would not match.
1004 * Other values are reserved for future use.
1006 * All comparisons only look at the lower XLEN (in the current mode)
1007 * bits of the compare values and of \RcsrTdataTwo.
1008 * When \FcsrMcontrolSelect=1 and access size is N, this is further
1009 * reduced, and comparisons only look at the lower N bits of the
1010 * compare values and of \RcsrTdataTwo.
1012 #define CSR_MCONTROL6_MATCH_OFFSET 7
1013 #define CSR_MCONTROL6_MATCH_LENGTH 4
1014 #define CSR_MCONTROL6_MATCH (0xfULL << CSR_MCONTROL6_MATCH_OFFSET)
1016 * When set, enable this trigger in M-mode.
1018 #define CSR_MCONTROL6_M_OFFSET 6
1019 #define CSR_MCONTROL6_M_LENGTH 1
1020 #define CSR_MCONTROL6_M (0x1ULL << CSR_MCONTROL6_M_OFFSET)
1022 * When set, enable this trigger in S/HS-mode.
1023 * This bit is hard-wired to 0 if the hart does not support
1026 #define CSR_MCONTROL6_S_OFFSET 4
1027 #define CSR_MCONTROL6_S_LENGTH 1
1028 #define CSR_MCONTROL6_S (0x1ULL << CSR_MCONTROL6_S_OFFSET)
1030 * When set, enable this trigger in U-mode.
1031 * This bit is hard-wired to 0 if the hart does not support
1034 #define CSR_MCONTROL6_U_OFFSET 3
1035 #define CSR_MCONTROL6_U_LENGTH 1
1036 #define CSR_MCONTROL6_U (0x1ULL << CSR_MCONTROL6_U_OFFSET)
1038 * When set, the trigger fires on the virtual address or opcode of an
1039 * instruction that is executed.
1041 #define CSR_MCONTROL6_EXECUTE_OFFSET 2
1042 #define CSR_MCONTROL6_EXECUTE_LENGTH 1
1043 #define CSR_MCONTROL6_EXECUTE (0x1ULL << CSR_MCONTROL6_EXECUTE_OFFSET)
1045 * When set, the trigger fires on the virtual address or data of any
1048 #define CSR_MCONTROL6_STORE_OFFSET 1
1049 #define CSR_MCONTROL6_STORE_LENGTH 1
1050 #define CSR_MCONTROL6_STORE (0x1ULL << CSR_MCONTROL6_STORE_OFFSET)
1052 * When set, the trigger fires on the virtual address or data of any
1055 #define CSR_MCONTROL6_LOAD_OFFSET 0
1056 #define CSR_MCONTROL6_LOAD_LENGTH 1
1057 #define CSR_MCONTROL6_LOAD (0x1ULL << CSR_MCONTROL6_LOAD_OFFSET)
1058 #define CSR_ICOUNT 0x7a1
1059 #define CSR_ICOUNT_TYPE_OFFSET (XLEN-4)
1060 #define CSR_ICOUNT_TYPE_LENGTH 4
1061 #define CSR_ICOUNT_TYPE (0xfULL << CSR_ICOUNT_TYPE_OFFSET)
1062 #define CSR_ICOUNT_DMODE_OFFSET (XLEN-5)
1063 #define CSR_ICOUNT_DMODE_LENGTH 1
1064 #define CSR_ICOUNT_DMODE (0x1ULL << CSR_ICOUNT_DMODE_OFFSET)
1066 * When set, enable this trigger in VS-mode.
1067 * This bit is hard-wired to 0 if the hart does not support
1068 * virtualization mode.
1070 #define CSR_ICOUNT_VS_OFFSET 26
1071 #define CSR_ICOUNT_VS_LENGTH 1
1072 #define CSR_ICOUNT_VS (0x1ULL << CSR_ICOUNT_VS_OFFSET)
1074 * When set, enable this trigger in VU-mode.
1075 * This bit is hard-wired to 0 if the hart does not support
1076 * virtualization mode.
1078 #define CSR_ICOUNT_VU_OFFSET 25
1079 #define CSR_ICOUNT_VU_LENGTH 1
1080 #define CSR_ICOUNT_VU (0x1ULL << CSR_ICOUNT_VU_OFFSET)
1082 * If this bit is implemented, the hardware sets it when this
1083 * trigger matches. The trigger's user can set or clear it at any
1084 * time. It is used to determine which
1085 * trigger(s) matched. If the bit is not implemented, it is always 0
1086 * and writing it has no effect.
1088 #define CSR_ICOUNT_HIT_OFFSET 24
1089 #define CSR_ICOUNT_HIT_LENGTH 1
1090 #define CSR_ICOUNT_HIT (0x1ULL << CSR_ICOUNT_HIT_OFFSET)
1092 * When count is decremented to 0, the trigger fires. Instead of
1093 * changing \FcsrIcountCount from 1 to 0, it is also acceptable for hardware to
1094 * clear \FcsrIcountM, \FcsrIcountS, \FcsrIcountU, \FcsrIcountVs, and
1095 * \FcsrIcountVu. This allows \FcsrIcountCount to be hard-wired
1096 * to 1 if this register just exists for single step.
1098 #define CSR_ICOUNT_COUNT_OFFSET 10
1099 #define CSR_ICOUNT_COUNT_LENGTH 14
1100 #define CSR_ICOUNT_COUNT (0x3fffULL << CSR_ICOUNT_COUNT_OFFSET)
1102 * When set, enable this trigger in M-mode.
1104 #define CSR_ICOUNT_M_OFFSET 9
1105 #define CSR_ICOUNT_M_LENGTH 1
1106 #define CSR_ICOUNT_M (0x1ULL << CSR_ICOUNT_M_OFFSET)
1108 * This bit becomes set when \FcsrIcountCount is decremented from 1
1109 * to 0. It is cleared when the trigger fires.
1111 #define CSR_ICOUNT_PENDING_OFFSET 8
1112 #define CSR_ICOUNT_PENDING_LENGTH 1
1113 #define CSR_ICOUNT_PENDING (0x1ULL << CSR_ICOUNT_PENDING_OFFSET)
1115 * When set, enable this trigger in S/HS-mode.
1116 * This bit is hard-wired to 0 if the hart does not support
1119 #define CSR_ICOUNT_S_OFFSET 7
1120 #define CSR_ICOUNT_S_LENGTH 1
1121 #define CSR_ICOUNT_S (0x1ULL << CSR_ICOUNT_S_OFFSET)
1123 * When set, enable this trigger in U-mode.
1124 * This bit is hard-wired to 0 if the hart does not support
1127 #define CSR_ICOUNT_U_OFFSET 6
1128 #define CSR_ICOUNT_U_LENGTH 1
1129 #define CSR_ICOUNT_U (0x1ULL << CSR_ICOUNT_U_OFFSET)
1131 * The action to take when the trigger fires. The values are explained
1132 * in Table~\ref{tab:action}.
1134 #define CSR_ICOUNT_ACTION_OFFSET 0
1135 #define CSR_ICOUNT_ACTION_LENGTH 6
1136 #define CSR_ICOUNT_ACTION (0x3fULL << CSR_ICOUNT_ACTION_OFFSET)
1137 #define CSR_ITRIGGER 0x7a1
1138 #define CSR_ITRIGGER_TYPE_OFFSET (XLEN-4)
1139 #define CSR_ITRIGGER_TYPE_LENGTH 4
1140 #define CSR_ITRIGGER_TYPE (0xfULL << CSR_ITRIGGER_TYPE_OFFSET)
1141 #define CSR_ITRIGGER_DMODE_OFFSET (XLEN-5)
1142 #define CSR_ITRIGGER_DMODE_LENGTH 1
1143 #define CSR_ITRIGGER_DMODE (0x1ULL << CSR_ITRIGGER_DMODE_OFFSET)
1145 * If this bit is implemented, the hardware sets it when this
1146 * trigger matches. The trigger's user can set or clear it at any
1147 * time. It is used to determine which
1148 * trigger(s) matched. If the bit is not implemented, it is always 0
1149 * and writing it has no effect.
1151 #define CSR_ITRIGGER_HIT_OFFSET (XLEN-6)
1152 #define CSR_ITRIGGER_HIT_LENGTH 1
1153 #define CSR_ITRIGGER_HIT (0x1ULL << CSR_ITRIGGER_HIT_OFFSET)
1155 * When set, enable this trigger for interrupts that are taken from VS
1157 * This bit is hard-wired to 0 if the hart does not support
1158 * virtualization mode.
1160 #define CSR_ITRIGGER_VS_OFFSET 12
1161 #define CSR_ITRIGGER_VS_LENGTH 1
1162 #define CSR_ITRIGGER_VS (0x1ULL << CSR_ITRIGGER_VS_OFFSET)
1164 * When set, enable this trigger for interrupts that are taken from VU
1166 * This bit is hard-wired to 0 if the hart does not support
1167 * virtualization mode.
1169 #define CSR_ITRIGGER_VU_OFFSET 11
1170 #define CSR_ITRIGGER_VU_LENGTH 1
1171 #define CSR_ITRIGGER_VU (0x1ULL << CSR_ITRIGGER_VU_OFFSET)
1173 * When set, enable this trigger for interrupts that are taken from M
1176 #define CSR_ITRIGGER_M_OFFSET 9
1177 #define CSR_ITRIGGER_M_LENGTH 1
1178 #define CSR_ITRIGGER_M (0x1ULL << CSR_ITRIGGER_M_OFFSET)
1180 * When set, enable this trigger for interrupts that are taken from S/HS
1182 * This bit is hard-wired to 0 if the hart does not support
1185 #define CSR_ITRIGGER_S_OFFSET 7
1186 #define CSR_ITRIGGER_S_LENGTH 1
1187 #define CSR_ITRIGGER_S (0x1ULL << CSR_ITRIGGER_S_OFFSET)
1189 * When set, enable this trigger for interrupts that are taken from U
1191 * This bit is hard-wired to 0 if the hart does not support
1194 #define CSR_ITRIGGER_U_OFFSET 6
1195 #define CSR_ITRIGGER_U_LENGTH 1
1196 #define CSR_ITRIGGER_U (0x1ULL << CSR_ITRIGGER_U_OFFSET)
1198 * The action to take when the trigger fires. The values are explained
1199 * in Table~\ref{tab:action}.
1201 #define CSR_ITRIGGER_ACTION_OFFSET 0
1202 #define CSR_ITRIGGER_ACTION_LENGTH 6
1203 #define CSR_ITRIGGER_ACTION (0x3fULL << CSR_ITRIGGER_ACTION_OFFSET)
1204 #define CSR_ETRIGGER 0x7a1
1205 #define CSR_ETRIGGER_TYPE_OFFSET (XLEN-4)
1206 #define CSR_ETRIGGER_TYPE_LENGTH 4
1207 #define CSR_ETRIGGER_TYPE (0xfULL << CSR_ETRIGGER_TYPE_OFFSET)
1208 #define CSR_ETRIGGER_DMODE_OFFSET (XLEN-5)
1209 #define CSR_ETRIGGER_DMODE_LENGTH 1
1210 #define CSR_ETRIGGER_DMODE (0x1ULL << CSR_ETRIGGER_DMODE_OFFSET)
1212 * If this bit is implemented, the hardware sets it when this
1213 * trigger matches. The trigger's user can set or clear it at any
1214 * time. It is used to determine which
1215 * trigger(s) matched. If the bit is not implemented, it is always 0
1216 * and writing it has no effect.
1218 #define CSR_ETRIGGER_HIT_OFFSET (XLEN-6)
1219 #define CSR_ETRIGGER_HIT_LENGTH 1
1220 #define CSR_ETRIGGER_HIT (0x1ULL << CSR_ETRIGGER_HIT_OFFSET)
1222 * When set, enable this trigger for exceptions that are taken from VS
1224 * This bit is hard-wired to 0 if the hart does not support
1225 * virtualization mode.
1227 #define CSR_ETRIGGER_VS_OFFSET 12
1228 #define CSR_ETRIGGER_VS_LENGTH 1
1229 #define CSR_ETRIGGER_VS (0x1ULL << CSR_ETRIGGER_VS_OFFSET)
1231 * When set, enable this trigger for exceptions that are taken from VU
1233 * This bit is hard-wired to 0 if the hart does not support
1234 * virtualization mode.
1236 #define CSR_ETRIGGER_VU_OFFSET 11
1237 #define CSR_ETRIGGER_VU_LENGTH 1
1238 #define CSR_ETRIGGER_VU (0x1ULL << CSR_ETRIGGER_VU_OFFSET)
1240 * When set, non-maskable interrupts cause this
1241 * trigger to fire, regardless of the values of \FcsrEtriggerM,
1242 * \FcsrEtriggerS, \FcsrEtriggerU, \FcsrEtriggerVs, and \FcsrEtriggerVu.
1244 #define CSR_ETRIGGER_NMI_OFFSET 10
1245 #define CSR_ETRIGGER_NMI_LENGTH 1
1246 #define CSR_ETRIGGER_NMI (0x1ULL << CSR_ETRIGGER_NMI_OFFSET)
1248 * When set, enable this trigger for exceptions that are taken from M
1251 #define CSR_ETRIGGER_M_OFFSET 9
1252 #define CSR_ETRIGGER_M_LENGTH 1
1253 #define CSR_ETRIGGER_M (0x1ULL << CSR_ETRIGGER_M_OFFSET)
1255 * When set, enable this trigger for exceptions that are taken from S/HS
1257 * This bit is hard-wired to 0 if the hart does not support
1260 #define CSR_ETRIGGER_S_OFFSET 7
1261 #define CSR_ETRIGGER_S_LENGTH 1
1262 #define CSR_ETRIGGER_S (0x1ULL << CSR_ETRIGGER_S_OFFSET)
1264 * When set, enable this trigger for exceptions that are taken from U
1266 * This bit is hard-wired to 0 if the hart does not support
1269 #define CSR_ETRIGGER_U_OFFSET 6
1270 #define CSR_ETRIGGER_U_LENGTH 1
1271 #define CSR_ETRIGGER_U (0x1ULL << CSR_ETRIGGER_U_OFFSET)
1273 * The action to take when the trigger fires. The values are explained
1274 * in Table~\ref{tab:action}.
1276 #define CSR_ETRIGGER_ACTION_OFFSET 0
1277 #define CSR_ETRIGGER_ACTION_LENGTH 6
1278 #define CSR_ETRIGGER_ACTION (0x3fULL << CSR_ETRIGGER_ACTION_OFFSET)
1279 #define CSR_TMEXTTRIGGER 0x7a1
1280 #define CSR_TMEXTTRIGGER_TYPE_OFFSET (XLEN-4)
1281 #define CSR_TMEXTTRIGGER_TYPE_LENGTH 4
1282 #define CSR_TMEXTTRIGGER_TYPE (0xfULL << CSR_TMEXTTRIGGER_TYPE_OFFSET)
1283 #define CSR_TMEXTTRIGGER_DMODE_OFFSET (XLEN-5)
1284 #define CSR_TMEXTTRIGGER_DMODE_LENGTH 1
1285 #define CSR_TMEXTTRIGGER_DMODE (0x1ULL << CSR_TMEXTTRIGGER_DMODE_OFFSET)
1287 * If this bit is implemented, the hardware sets it when this
1288 * trigger matches. The trigger's user can set or clear it at any
1289 * time. It is used to determine which
1290 * trigger(s) matched. If the bit is not implemented, it is always 0
1291 * and writing it has no effect.
1293 #define CSR_TMEXTTRIGGER_HIT_OFFSET (XLEN-6)
1294 #define CSR_TMEXTTRIGGER_HIT_LENGTH 1
1295 #define CSR_TMEXTTRIGGER_HIT (0x1ULL << CSR_TMEXTTRIGGER_HIT_OFFSET)
1297 * This optional bit, when set, causes this trigger to fire whenever an attached
1298 * interrupt controller signals a trigger.
1300 #define CSR_TMEXTTRIGGER_INTCTL_OFFSET 22
1301 #define CSR_TMEXTTRIGGER_INTCTL_LENGTH 1
1302 #define CSR_TMEXTTRIGGER_INTCTL (0x1ULL << CSR_TMEXTTRIGGER_INTCTL_OFFSET)
1304 * Selects any combination of up to 16 external debug trigger inputs
1305 * that cause this trigger to fire.
1307 #define CSR_TMEXTTRIGGER_SELECT_OFFSET 6
1308 #define CSR_TMEXTTRIGGER_SELECT_LENGTH 16
1309 #define CSR_TMEXTTRIGGER_SELECT (0xffffULL << CSR_TMEXTTRIGGER_SELECT_OFFSET)
1311 * The action to take when the trigger fires. The values are explained
1312 * in Table~\ref{tab:action}.
1314 #define CSR_TMEXTTRIGGER_ACTION_OFFSET 0
1315 #define CSR_TMEXTTRIGGER_ACTION_LENGTH 6
1316 #define CSR_TMEXTTRIGGER_ACTION (0x3fULL << CSR_TMEXTTRIGGER_ACTION_OFFSET)
1317 #define CSR_TEXTRA32 0x7a3
1319 * Data used together with \FcsrTextraThirtytwoMhselect.
1321 #define CSR_TEXTRA32_MHVALUE_OFFSET 26
1322 #define CSR_TEXTRA32_MHVALUE_LENGTH 6
1323 #define CSR_TEXTRA32_MHVALUE (0x3fU << CSR_TEXTRA32_MHVALUE_OFFSET)
1325 * 0: Ignore \FcsrTextraThirtytwoMhvalue.
1327 * 4: This trigger will only match if the low bits of
1328 * \RcsrMcontext/\RcsrHcontext equal \FcsrTextraThirtytwoMhvalue.
1330 * 1, 5: This trigger will only match if the low bits of
1331 * \RcsrMcontext/\RcsrHcontext equal \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.
1333 * 2, 6: This trigger will only match if VMID in hgatp equals the lower VMIDMAX
1334 * (defined in the Privileged Spec) bits of \{\FcsrTextraThirtytwoMhvalue, mhselect[2]\}.
1338 * If the H extension is not supported, the only legal values are 0 and 4.
1340 #define CSR_TEXTRA32_MHSELECT_OFFSET 23
1341 #define CSR_TEXTRA32_MHSELECT_LENGTH 3
1342 #define CSR_TEXTRA32_MHSELECT (0x7U << CSR_TEXTRA32_MHSELECT_OFFSET)
1344 * When the least significant bit of this field is 1, it causes bits 7:0
1345 * in the comparison to be ignored, when \FcsrTextraThirtytwoSselect=1.
1346 * When the next most significant bit of this field is 1, it causes bits 15:8
1347 * to be ignored in the comparison, when \FcsrTextraThirtytwoSselect=1.
1349 #define CSR_TEXTRA32_SBYTEMASK_OFFSET 18
1350 #define CSR_TEXTRA32_SBYTEMASK_LENGTH 2
1351 #define CSR_TEXTRA32_SBYTEMASK (0x3U << CSR_TEXTRA32_SBYTEMASK_OFFSET)
1353 * Data used together with \FcsrTextraThirtytwoSselect.
1355 * This field should be tied to 0 when S-mode is not supported.
1357 #define CSR_TEXTRA32_SVALUE_OFFSET 2
1358 #define CSR_TEXTRA32_SVALUE_LENGTH 16
1359 #define CSR_TEXTRA32_SVALUE (0xffffU << CSR_TEXTRA32_SVALUE_OFFSET)
1361 * 0: Ignore \FcsrTextraThirtytwoSvalue.
1363 * 1: This trigger will only match if the low bits of
1364 * \RcsrScontext equal \FcsrTextraThirtytwoSvalue.
1366 * 2: This trigger will only match if:
1367 * \begin{itemize}[noitemsep,nolistsep]
1368 * \item the mode is VS-mode or VU-mode and ASID in \Rvsatp
1369 * equals the lower ASIDMAX (defined in the Privileged Spec) bits
1370 * of \FcsrTextraThirtytwoSvalue.
1371 * \item in all other modes, ASID in \Rsatp equals the lower
1372 * ASIDMAX (defined in the Privileged Spec) bits of
1373 * \FcsrTextraThirtytwoSvalue.
1376 * This field should be tied to 0 when S-mode is not supported.
1378 #define CSR_TEXTRA32_SSELECT_OFFSET 0
1379 #define CSR_TEXTRA32_SSELECT_LENGTH 2
1380 #define CSR_TEXTRA32_SSELECT (0x3U << CSR_TEXTRA32_SSELECT_OFFSET)
1381 #define CSR_TEXTRA64 0x7a3
1382 #define CSR_TEXTRA64_MHVALUE_OFFSET 51
1383 #define CSR_TEXTRA64_MHVALUE_LENGTH 13
1384 #define CSR_TEXTRA64_MHVALUE (0x1fffULL << CSR_TEXTRA64_MHVALUE_OFFSET)
1385 #define CSR_TEXTRA64_MHSELECT_OFFSET 48
1386 #define CSR_TEXTRA64_MHSELECT_LENGTH 3
1387 #define CSR_TEXTRA64_MHSELECT (0x7ULL << CSR_TEXTRA64_MHSELECT_OFFSET)
1389 * When the least significant bit of this field is 1, it causes bits 7:0
1390 * in the comparison to be ignored, when \FcsrTextraSixtyfourSselect=1.
1391 * Likewise, the second bit controls the comparison of bits 15:8,
1392 * third bit controls the comparison of bits 23:16,
1393 * fourth bit controls the comparison of bits 31:24, and
1394 * fifth bit controls the comparison of bits 33:32.
1396 #define CSR_TEXTRA64_SBYTEMASK_OFFSET 36
1397 #define CSR_TEXTRA64_SBYTEMASK_LENGTH 5
1398 #define CSR_TEXTRA64_SBYTEMASK (0x1fULL << CSR_TEXTRA64_SBYTEMASK_OFFSET)
1399 #define CSR_TEXTRA64_SVALUE_OFFSET 2
1400 #define CSR_TEXTRA64_SVALUE_LENGTH 34
1401 #define CSR_TEXTRA64_SVALUE (0x3ffffffffULL << CSR_TEXTRA64_SVALUE_OFFSET)
1402 #define CSR_TEXTRA64_SSELECT_OFFSET 0
1403 #define CSR_TEXTRA64_SSELECT_LENGTH 2
1404 #define CSR_TEXTRA64_SSELECT (0x3ULL << CSR_TEXTRA64_SSELECT_OFFSET)
1405 #define DM_DMSTATUS 0x11
1407 * 0: Unimplemented, or \FdmDmcontrolNdmreset is zero and no ndmreset is currently
1410 * 1: \FdmDmcontrolNdmreset is currently nonzero, or there is an ndmreset in progress.
1412 #define DM_DMSTATUS_NDMRESETPENDING_OFFSET 24
1413 #define DM_DMSTATUS_NDMRESETPENDING_LENGTH 1
1414 #define DM_DMSTATUS_NDMRESETPENDING (0x1U << DM_DMSTATUS_NDMRESETPENDING_OFFSET)
1416 * 0: The per-hart {\tt unavail} bits reflect the current state of the hart.
1418 * 1: The per-hart {\tt unavail} bits are sticky. Once they are set, they will
1419 * not clear until the debugger acknowledges them using \FdmDmcontrolAckunavail.
1421 #define DM_DMSTATUS_STICKYUNAVAIL_OFFSET 23
1422 #define DM_DMSTATUS_STICKYUNAVAIL_LENGTH 1
1423 #define DM_DMSTATUS_STICKYUNAVAIL (0x1U << DM_DMSTATUS_STICKYUNAVAIL_OFFSET)
1425 * If 1, then there is an implicit {\tt ebreak} instruction at the
1426 * non-existent word immediately after the Program Buffer. This saves
1427 * the debugger from having to write the {\tt ebreak} itself, and
1428 * allows the Program Buffer to be one word smaller.
1430 * This must be 1 when \FdmAbstractcsProgbufsize is 1.
1432 #define DM_DMSTATUS_IMPEBREAK_OFFSET 22
1433 #define DM_DMSTATUS_IMPEBREAK_LENGTH 1
1434 #define DM_DMSTATUS_IMPEBREAK (0x1U << DM_DMSTATUS_IMPEBREAK_OFFSET)
1436 * This field is 1 when all currently selected harts have been reset
1437 * and reset has not been acknowledged for any of them.
1439 #define DM_DMSTATUS_ALLHAVERESET_OFFSET 19
1440 #define DM_DMSTATUS_ALLHAVERESET_LENGTH 1
1441 #define DM_DMSTATUS_ALLHAVERESET (0x1U << DM_DMSTATUS_ALLHAVERESET_OFFSET)
1443 * This field is 1 when at least one currently selected hart has been
1444 * reset and reset has not been acknowledged for that hart.
1446 #define DM_DMSTATUS_ANYHAVERESET_OFFSET 18
1447 #define DM_DMSTATUS_ANYHAVERESET_LENGTH 1
1448 #define DM_DMSTATUS_ANYHAVERESET (0x1U << DM_DMSTATUS_ANYHAVERESET_OFFSET)
1450 * This field is 1 when all currently selected harts have acknowledged
1451 * their last resume request.
1453 #define DM_DMSTATUS_ALLRESUMEACK_OFFSET 17
1454 #define DM_DMSTATUS_ALLRESUMEACK_LENGTH 1
1455 #define DM_DMSTATUS_ALLRESUMEACK (0x1U << DM_DMSTATUS_ALLRESUMEACK_OFFSET)
1457 * This field is 1 when any currently selected hart has acknowledged
1458 * its last resume request.
1460 #define DM_DMSTATUS_ANYRESUMEACK_OFFSET 16
1461 #define DM_DMSTATUS_ANYRESUMEACK_LENGTH 1
1462 #define DM_DMSTATUS_ANYRESUMEACK (0x1U << DM_DMSTATUS_ANYRESUMEACK_OFFSET)
1464 * This field is 1 when all currently selected harts do not exist in
1465 * this hardware platform.
1467 #define DM_DMSTATUS_ALLNONEXISTENT_OFFSET 15
1468 #define DM_DMSTATUS_ALLNONEXISTENT_LENGTH 1
1469 #define DM_DMSTATUS_ALLNONEXISTENT (0x1U << DM_DMSTATUS_ALLNONEXISTENT_OFFSET)
1471 * This field is 1 when any currently selected hart does not exist in
1472 * this hardware platform.
1474 #define DM_DMSTATUS_ANYNONEXISTENT_OFFSET 14
1475 #define DM_DMSTATUS_ANYNONEXISTENT_LENGTH 1
1476 #define DM_DMSTATUS_ANYNONEXISTENT (0x1U << DM_DMSTATUS_ANYNONEXISTENT_OFFSET)
1478 * This field is 1 when all currently selected harts are
1479 * unavailable, or (if \FdmDmstatusStickyunavail is 1) were
1480 * unavailable without that being acknowledged.
1482 #define DM_DMSTATUS_ALLUNAVAIL_OFFSET 13
1483 #define DM_DMSTATUS_ALLUNAVAIL_LENGTH 1
1484 #define DM_DMSTATUS_ALLUNAVAIL (0x1U << DM_DMSTATUS_ALLUNAVAIL_OFFSET)
1486 * This field is 1 when any currently selected hart is unavailable,
1487 * or (if \FdmDmstatusStickyunavail is 1) was unavailable without
1488 * that being acknowledged.
1490 #define DM_DMSTATUS_ANYUNAVAIL_OFFSET 12
1491 #define DM_DMSTATUS_ANYUNAVAIL_LENGTH 1
1492 #define DM_DMSTATUS_ANYUNAVAIL (0x1U << DM_DMSTATUS_ANYUNAVAIL_OFFSET)
1494 * This field is 1 when all currently selected harts are running.
1496 #define DM_DMSTATUS_ALLRUNNING_OFFSET 11
1497 #define DM_DMSTATUS_ALLRUNNING_LENGTH 1
1498 #define DM_DMSTATUS_ALLRUNNING (0x1U << DM_DMSTATUS_ALLRUNNING_OFFSET)
1500 * This field is 1 when any currently selected hart is running.
1502 #define DM_DMSTATUS_ANYRUNNING_OFFSET 10
1503 #define DM_DMSTATUS_ANYRUNNING_LENGTH 1
1504 #define DM_DMSTATUS_ANYRUNNING (0x1U << DM_DMSTATUS_ANYRUNNING_OFFSET)
1506 * This field is 1 when all currently selected harts are halted.
1508 #define DM_DMSTATUS_ALLHALTED_OFFSET 9
1509 #define DM_DMSTATUS_ALLHALTED_LENGTH 1
1510 #define DM_DMSTATUS_ALLHALTED (0x1U << DM_DMSTATUS_ALLHALTED_OFFSET)
1512 * This field is 1 when any currently selected hart is halted.
1514 #define DM_DMSTATUS_ANYHALTED_OFFSET 8
1515 #define DM_DMSTATUS_ANYHALTED_LENGTH 1
1516 #define DM_DMSTATUS_ANYHALTED (0x1U << DM_DMSTATUS_ANYHALTED_OFFSET)
1518 * 0: Authentication is required before using the DM.
1520 * 1: The authentication check has passed.
1522 * On components that don't implement authentication, this bit must be
1525 #define DM_DMSTATUS_AUTHENTICATED_OFFSET 7
1526 #define DM_DMSTATUS_AUTHENTICATED_LENGTH 1
1527 #define DM_DMSTATUS_AUTHENTICATED (0x1U << DM_DMSTATUS_AUTHENTICATED_OFFSET)
1529 * 0: The authentication module is ready to process the next
1530 * read/write to \RdmAuthdata.
1532 * 1: The authentication module is busy. Accessing \RdmAuthdata results
1533 * in unspecified behavior.
1535 * \FdmDmstatusAuthbusy only becomes set in immediate response to an access to
1538 #define DM_DMSTATUS_AUTHBUSY_OFFSET 6
1539 #define DM_DMSTATUS_AUTHBUSY_LENGTH 1
1540 #define DM_DMSTATUS_AUTHBUSY (0x1U << DM_DMSTATUS_AUTHBUSY_OFFSET)
1542 * 1 if this Debug Module supports halt-on-reset functionality
1543 * controllable by the \FdmDmcontrolSetresethaltreq and \FdmDmcontrolClrresethaltreq bits.
1546 #define DM_DMSTATUS_HASRESETHALTREQ_OFFSET 5
1547 #define DM_DMSTATUS_HASRESETHALTREQ_LENGTH 1
1548 #define DM_DMSTATUS_HASRESETHALTREQ (0x1U << DM_DMSTATUS_HASRESETHALTREQ_OFFSET)
1550 * 0: \RdmConfstrptrZero--\RdmConfstrptrThree hold information which
1551 * is not relevant to the configuration string.
1553 * 1: \RdmConfstrptrZero--\RdmConfstrptrThree hold the address of the
1554 * configuration string.
1556 #define DM_DMSTATUS_CONFSTRPTRVALID_OFFSET 4
1557 #define DM_DMSTATUS_CONFSTRPTRVALID_LENGTH 1
1558 #define DM_DMSTATUS_CONFSTRPTRVALID (0x1U << DM_DMSTATUS_CONFSTRPTRVALID_OFFSET)
1560 * 0: There is no Debug Module present.
1562 * 1: There is a Debug Module and it conforms to version 0.11 of this
1565 * 2: There is a Debug Module and it conforms to version 0.13 of this
1568 * 3: There is a Debug Module and it conforms to version 1.0 of this
1571 * 15: There is a Debug Module but it does not conform to any
1572 * available version of this spec.
1574 #define DM_DMSTATUS_VERSION_OFFSET 0
1575 #define DM_DMSTATUS_VERSION_LENGTH 4
1576 #define DM_DMSTATUS_VERSION (0xfU << DM_DMSTATUS_VERSION_OFFSET)
1577 #define DM_DMCONTROL 0x10
1579 * Writing 0 clears the halt request bit for all currently selected
1580 * harts. This may cancel outstanding halt requests for those harts.
1582 * Writing 1 sets the halt request bit for all currently selected
1583 * harts. Running harts will halt whenever their halt request bit is
1586 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1588 #define DM_DMCONTROL_HALTREQ_OFFSET 31
1589 #define DM_DMCONTROL_HALTREQ_LENGTH 1
1590 #define DM_DMCONTROL_HALTREQ (0x1U << DM_DMCONTROL_HALTREQ_OFFSET)
1592 * Writing 1 causes the currently selected harts to resume once, if
1593 * they are halted when the write occurs. It also clears the resume
1594 * ack bit for those harts.
1596 * \FdmDmcontrolResumereq is ignored if \FdmDmcontrolHaltreq is set.
1598 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1600 #define DM_DMCONTROL_RESUMEREQ_OFFSET 30
1601 #define DM_DMCONTROL_RESUMEREQ_LENGTH 1
1602 #define DM_DMCONTROL_RESUMEREQ (0x1U << DM_DMCONTROL_RESUMEREQ_OFFSET)
1604 * This optional field writes the reset bit for all the currently
1605 * selected harts. To perform a reset the debugger writes 1, and then
1606 * writes 0 to deassert the reset signal.
1608 * While this bit is 1, the debugger must not change which harts are
1611 * If this feature is not implemented, the bit always stays 0, so
1612 * after writing 1 the debugger can read the register back to see if
1613 * the feature is supported.
1615 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1617 #define DM_DMCONTROL_HARTRESET_OFFSET 29
1618 #define DM_DMCONTROL_HARTRESET_LENGTH 1
1619 #define DM_DMCONTROL_HARTRESET (0x1U << DM_DMCONTROL_HARTRESET_OFFSET)
1623 * 1: Clears {\tt havereset} for any selected harts.
1625 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1627 #define DM_DMCONTROL_ACKHAVERESET_OFFSET 28
1628 #define DM_DMCONTROL_ACKHAVERESET_LENGTH 1
1629 #define DM_DMCONTROL_ACKHAVERESET (0x1U << DM_DMCONTROL_ACKHAVERESET_OFFSET)
1633 * 1: Clears {\tt unavail} for any selected harts.
1635 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1637 #define DM_DMCONTROL_ACKUNAVAIL_OFFSET 27
1638 #define DM_DMCONTROL_ACKUNAVAIL_LENGTH 1
1639 #define DM_DMCONTROL_ACKUNAVAIL (0x1U << DM_DMCONTROL_ACKUNAVAIL_OFFSET)
1641 * Selects the definition of currently selected harts.
1643 * 0: There is a single currently selected hart, that is selected by \Fhartsel.
1645 * 1: There may be multiple currently selected harts -- the hart
1646 * selected by \Fhartsel, plus those selected by the hart array mask
1649 * An implementation which does not implement the hart array mask register
1650 * must tie this field to 0. A debugger which wishes to use the hart array
1651 * mask register feature should set this bit and read back to see if the functionality
1654 #define DM_DMCONTROL_HASEL_OFFSET 26
1655 #define DM_DMCONTROL_HASEL_LENGTH 1
1656 #define DM_DMCONTROL_HASEL (0x1U << DM_DMCONTROL_HASEL_OFFSET)
1658 * The low 10 bits of \Fhartsel: the DM-specific index of the hart to
1659 * select. This hart is always part of the currently selected harts.
1661 #define DM_DMCONTROL_HARTSELLO_OFFSET 16
1662 #define DM_DMCONTROL_HARTSELLO_LENGTH 10
1663 #define DM_DMCONTROL_HARTSELLO (0x3ffU << DM_DMCONTROL_HARTSELLO_OFFSET)
1665 * The high 10 bits of \Fhartsel: the DM-specific index of the hart to
1666 * select. This hart is always part of the currently selected harts.
1668 #define DM_DMCONTROL_HARTSELHI_OFFSET 6
1669 #define DM_DMCONTROL_HARTSELHI_LENGTH 10
1670 #define DM_DMCONTROL_HARTSELHI (0x3ffU << DM_DMCONTROL_HARTSELHI_OFFSET)
1672 * This optional field sets \Fkeepalive for all currently selected
1673 * harts, unless \FdmDmcontrolClrkeepalive is simultaneously set to
1676 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1678 #define DM_DMCONTROL_SETKEEPALIVE_OFFSET 5
1679 #define DM_DMCONTROL_SETKEEPALIVE_LENGTH 1
1680 #define DM_DMCONTROL_SETKEEPALIVE (0x1U << DM_DMCONTROL_SETKEEPALIVE_OFFSET)
1682 * This optional field clears \Fkeepalive for all currently selected
1685 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1687 #define DM_DMCONTROL_CLRKEEPALIVE_OFFSET 4
1688 #define DM_DMCONTROL_CLRKEEPALIVE_LENGTH 1
1689 #define DM_DMCONTROL_CLRKEEPALIVE (0x1U << DM_DMCONTROL_CLRKEEPALIVE_OFFSET)
1691 * This optional field writes the halt-on-reset request bit for all
1692 * currently selected harts, unless \FdmDmcontrolClrresethaltreq is
1693 * simultaneously set to 1.
1694 * When set to 1, each selected hart will halt upon the next deassertion
1695 * of its reset. The halt-on-reset request bit is not automatically
1696 * cleared. The debugger must write to \FdmDmcontrolClrresethaltreq to clear it.
1698 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1700 * If \FdmDmstatusHasresethaltreq is 0, this field is not implemented.
1702 #define DM_DMCONTROL_SETRESETHALTREQ_OFFSET 3
1703 #define DM_DMCONTROL_SETRESETHALTREQ_LENGTH 1
1704 #define DM_DMCONTROL_SETRESETHALTREQ (0x1U << DM_DMCONTROL_SETRESETHALTREQ_OFFSET)
1706 * This optional field clears the halt-on-reset request bit for all
1707 * currently selected harts.
1709 * Writes apply to the new value of \Fhartsel and \FdmDmcontrolHasel.
1711 #define DM_DMCONTROL_CLRRESETHALTREQ_OFFSET 2
1712 #define DM_DMCONTROL_CLRRESETHALTREQ_LENGTH 1
1713 #define DM_DMCONTROL_CLRRESETHALTREQ (0x1U << DM_DMCONTROL_CLRRESETHALTREQ_OFFSET)
1715 * This bit controls the reset signal from the DM to the rest of the
1716 * hardware platform. The signal should reset every part of the hardware platform, including
1717 * every hart, except for the DM and any logic required to access the
1719 * To perform a hardware platform reset the debugger writes 1,
1721 * to deassert the reset.
1723 #define DM_DMCONTROL_NDMRESET_OFFSET 1
1724 #define DM_DMCONTROL_NDMRESET_LENGTH 1
1725 #define DM_DMCONTROL_NDMRESET (0x1U << DM_DMCONTROL_NDMRESET_OFFSET)
1727 * This bit serves as a reset signal for the Debug Module itself.
1728 * After changing the value of this bit, the debugger must poll
1729 * \RdmDmcontrol until \FdmDmcontrolDmactive has taken the requested value
1730 * before performing any action that assumes the requested \FdmDmcontrolDmactive
1731 * state change has completed. Hardware may
1732 * take an arbitrarily long time to complete activation or deactivation and will
1733 * indicate completion by setting \FdmDmcontrolDmactive to the requested value.
1735 * 0: The module's state, including authentication mechanism,
1736 * takes its reset values (the \FdmDmcontrolDmactive bit is the only bit which can
1737 * be written to something other than its reset value). Any accesses
1738 * to the module may fail. Specifically, \FdmDmstatusVersion might not return
1741 * 1: The module functions normally.
1743 * No other mechanism should exist that may result in resetting the
1744 * Debug Module after power up.
1746 * To place the Debug Module into a known state, a debugger may write 0 to \FdmDmcontrolDmactive,
1747 * poll until \FdmDmcontrolDmactive is observed 0, write 1 to \FdmDmcontrolDmactive, and
1748 * poll until \FdmDmcontrolDmactive is observed 1.
1750 * Implementations may pay attention to this bit to further aid
1751 * debugging, for example by preventing the Debug Module from being
1752 * power gated while debugging is active.
1754 #define DM_DMCONTROL_DMACTIVE_OFFSET 0
1755 #define DM_DMCONTROL_DMACTIVE_LENGTH 1
1756 #define DM_DMCONTROL_DMACTIVE (0x1U << DM_DMCONTROL_DMACTIVE_OFFSET)
1757 #define DM_HARTINFO 0x12
1759 * Number of {\tt dscratch} registers available for the debugger
1760 * to use during program buffer execution, starting from \RcsrDscratchZero.
1761 * The debugger can make no assumptions about the contents of these
1762 * registers between commands.
1764 #define DM_HARTINFO_NSCRATCH_OFFSET 20
1765 #define DM_HARTINFO_NSCRATCH_LENGTH 4
1766 #define DM_HARTINFO_NSCRATCH (0xfU << DM_HARTINFO_NSCRATCH_OFFSET)
1768 * 0: The {\tt data} registers are shadowed in the hart by CSRs.
1769 * Each CSR is DXLEN bits in size, and corresponds
1770 * to a single argument, per Table~\ref{tab:datareg}.
1772 * 1: The {\tt data} registers are shadowed in the hart's memory map.
1773 * Each register takes up 4 bytes in the memory map.
1775 #define DM_HARTINFO_DATAACCESS_OFFSET 16
1776 #define DM_HARTINFO_DATAACCESS_LENGTH 1
1777 #define DM_HARTINFO_DATAACCESS (0x1U << DM_HARTINFO_DATAACCESS_OFFSET)
1779 * If \FdmHartinfoDataaccess is 0: Number of CSRs dedicated to
1780 * shadowing the {\tt data} registers.
1782 * If \FdmHartinfoDataaccess is 1: Number of 32-bit words in the memory map
1783 * dedicated to shadowing the {\tt data} registers.
1785 * Since there are at most 12 {\tt data} registers, the value in this
1786 * register must be 12 or smaller.
1788 #define DM_HARTINFO_DATASIZE_OFFSET 12
1789 #define DM_HARTINFO_DATASIZE_LENGTH 4
1790 #define DM_HARTINFO_DATASIZE (0xfU << DM_HARTINFO_DATASIZE_OFFSET)
1792 * If \FdmHartinfoDataaccess is 0: The number of the first CSR dedicated to
1793 * shadowing the {\tt data} registers.
1795 * If \FdmHartinfoDataaccess is 1: Address of RAM where the data
1796 * registers are shadowed. This address is sign extended giving a
1797 * range of -2048 to 2047, easily addressed with a load or store using
1798 * \Xzero as the address register.
1800 #define DM_HARTINFO_DATAADDR_OFFSET 0
1801 #define DM_HARTINFO_DATAADDR_LENGTH 12
1802 #define DM_HARTINFO_DATAADDR (0xfffU << DM_HARTINFO_DATAADDR_OFFSET)
1803 #define DM_HAWINDOWSEL 0x14
1805 * The high bits of this field may be tied to 0, depending on how large
1806 * the array mask register is. E.g.\ on a hardware platform with 48 harts only bit 0
1807 * of this field may actually be writable.
1809 #define DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET 0
1810 #define DM_HAWINDOWSEL_HAWINDOWSEL_LENGTH 15
1811 #define DM_HAWINDOWSEL_HAWINDOWSEL (0x7fffU << DM_HAWINDOWSEL_HAWINDOWSEL_OFFSET)
1812 #define DM_HAWINDOW 0x15
1813 #define DM_HAWINDOW_MASKDATA_OFFSET 0
1814 #define DM_HAWINDOW_MASKDATA_LENGTH 32
1815 #define DM_HAWINDOW_MASKDATA (0xffffffffU << DM_HAWINDOW_MASKDATA_OFFSET)
1816 #define DM_ABSTRACTCS 0x16
1818 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
1820 #define DM_ABSTRACTCS_PROGBUFSIZE_OFFSET 24
1821 #define DM_ABSTRACTCS_PROGBUFSIZE_LENGTH 5
1822 #define DM_ABSTRACTCS_PROGBUFSIZE (0x1fU << DM_ABSTRACTCS_PROGBUFSIZE_OFFSET)
1824 * 1: An abstract command is currently being executed.
1826 * This bit is set as soon as \RdmCommand is written, and is
1827 * not cleared until that command has completed.
1829 #define DM_ABSTRACTCS_BUSY_OFFSET 12
1830 #define DM_ABSTRACTCS_BUSY_LENGTH 1
1831 #define DM_ABSTRACTCS_BUSY (0x1U << DM_ABSTRACTCS_BUSY_OFFSET)
1833 * This optional bit controls whether program buffer and abstract
1834 * memory accesses are performed with the exact and full set of
1835 * permission checks that apply based on the current architectural
1836 * state of the hart performing the access, or with a relaxed set of
1837 * permission checks (e.g. PMP restrictions are ignored). The
1838 * details of the latter are implementation-specific. When set to 0,
1839 * full permissions apply; when set to 1, relaxed permissions apply.
1841 #define DM_ABSTRACTCS_RELAXEDPRIV_OFFSET 11
1842 #define DM_ABSTRACTCS_RELAXEDPRIV_LENGTH 1
1843 #define DM_ABSTRACTCS_RELAXEDPRIV (0x1U << DM_ABSTRACTCS_RELAXEDPRIV_OFFSET)
1845 * Gets set if an abstract command fails. The bits in this field remain set until
1846 * they are cleared by writing 1 to them. No abstract command is
1847 * started until the value is reset to 0.
1849 * This field only contains a valid value if \FdmAbstractcsBusy is 0.
1851 * 0 (none): No error.
1853 * 1 (busy): An abstract command was executing while \RdmCommand,
1854 * \RdmAbstractcs, or \RdmAbstractauto was written, or when one
1855 * of the {\tt data} or {\tt progbuf} registers was read or written.
1856 * This status is only written if \FdmAbstractcsCmderr contains 0.
1858 * 2 (not supported): The command in \RdmCommand is not supported. It
1859 * may be supported with different options set, but it will not be
1860 * supported at a later time when the hart or system state are
1863 * 3 (exception): An exception occurred while executing the command
1864 * (e.g.\ while executing the Program Buffer).
1866 * 4 (halt/resume): The abstract command couldn't execute because the
1867 * hart wasn't in the required state (running/halted), or unavailable.
1869 * 5 (bus): The abstract command failed due to a bus error (e.g.\
1870 * alignment, access size, or timeout).
1872 * 6: Reserved for future use.
1874 * 7 (other): The command failed for another reason.
1876 #define DM_ABSTRACTCS_CMDERR_OFFSET 8
1877 #define DM_ABSTRACTCS_CMDERR_LENGTH 3
1878 #define DM_ABSTRACTCS_CMDERR (0x7U << DM_ABSTRACTCS_CMDERR_OFFSET)
1880 * Number of {\tt data} registers that are implemented as part of the
1881 * abstract command interface. Valid sizes are 1 -- 12.
1883 #define DM_ABSTRACTCS_DATACOUNT_OFFSET 0
1884 #define DM_ABSTRACTCS_DATACOUNT_LENGTH 4
1885 #define DM_ABSTRACTCS_DATACOUNT (0xfU << DM_ABSTRACTCS_DATACOUNT_OFFSET)
1886 #define DM_COMMAND 0x17
1888 * The type determines the overall functionality of this
1891 #define DM_COMMAND_CMDTYPE_OFFSET 24
1892 #define DM_COMMAND_CMDTYPE_LENGTH 8
1893 #define DM_COMMAND_CMDTYPE (0xffU << DM_COMMAND_CMDTYPE_OFFSET)
1895 * This field is interpreted in a command-specific manner,
1896 * described for each abstract command.
1898 #define DM_COMMAND_CONTROL_OFFSET 0
1899 #define DM_COMMAND_CONTROL_LENGTH 24
1900 #define DM_COMMAND_CONTROL (0xffffffU << DM_COMMAND_CONTROL_OFFSET)
1901 #define DM_ABSTRACTAUTO 0x18
1903 * When a bit in this field is 1, read or write accesses to the
1904 * corresponding {\tt progbuf} word cause the command in \RdmCommand to
1905 * be executed again.
1907 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET 16
1908 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LENGTH 16
1909 #define DM_ABSTRACTAUTO_AUTOEXECPROGBUF (0xffffU << DM_ABSTRACTAUTO_AUTOEXECPROGBUF_OFFSET)
1911 * When a bit in this field is 1, read or write accesses to the
1912 * corresponding {\tt data} word cause the command in \RdmCommand to be
1915 #define DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET 0
1916 #define DM_ABSTRACTAUTO_AUTOEXECDATA_LENGTH 12
1917 #define DM_ABSTRACTAUTO_AUTOEXECDATA (0xfffU << DM_ABSTRACTAUTO_AUTOEXECDATA_OFFSET)
1918 #define DM_CONFSTRPTR0 0x19
1919 #define DM_CONFSTRPTR0_ADDR_OFFSET 0
1920 #define DM_CONFSTRPTR0_ADDR_LENGTH 32
1921 #define DM_CONFSTRPTR0_ADDR (0xffffffffU << DM_CONFSTRPTR0_ADDR_OFFSET)
1922 #define DM_CONFSTRPTR1 0x1a
1923 #define DM_CONFSTRPTR1_ADDR_OFFSET 0
1924 #define DM_CONFSTRPTR1_ADDR_LENGTH 32
1925 #define DM_CONFSTRPTR1_ADDR (0xffffffffU << DM_CONFSTRPTR1_ADDR_OFFSET)
1926 #define DM_CONFSTRPTR2 0x1b
1927 #define DM_CONFSTRPTR2_ADDR_OFFSET 0
1928 #define DM_CONFSTRPTR2_ADDR_LENGTH 32
1929 #define DM_CONFSTRPTR2_ADDR (0xffffffffU << DM_CONFSTRPTR2_ADDR_OFFSET)
1930 #define DM_CONFSTRPTR3 0x1c
1931 #define DM_CONFSTRPTR3_ADDR_OFFSET 0
1932 #define DM_CONFSTRPTR3_ADDR_LENGTH 32
1933 #define DM_CONFSTRPTR3_ADDR (0xffffffffU << DM_CONFSTRPTR3_ADDR_OFFSET)
1934 #define DM_NEXTDM 0x1d
1935 #define DM_NEXTDM_ADDR_OFFSET 0
1936 #define DM_NEXTDM_ADDR_LENGTH 32
1937 #define DM_NEXTDM_ADDR (0xffffffffU << DM_NEXTDM_ADDR_OFFSET)
1938 #define DM_DATA0 0x04
1939 #define DM_DATA0_DATA_OFFSET 0
1940 #define DM_DATA0_DATA_LENGTH 32
1941 #define DM_DATA0_DATA (0xffffffffU << DM_DATA0_DATA_OFFSET)
1942 #define DM_DATA1 0x05
1943 #define DM_DATA2 0x06
1944 #define DM_DATA3 0x07
1945 #define DM_DATA4 0x08
1946 #define DM_DATA5 0x09
1947 #define DM_DATA6 0x0a
1948 #define DM_DATA7 0x0b
1949 #define DM_DATA8 0x0c
1950 #define DM_DATA9 0x0d
1951 #define DM_DATA10 0x0e
1952 #define DM_DATA11 0x0f
1953 #define DM_PROGBUF0 0x20
1954 #define DM_PROGBUF0_DATA_OFFSET 0
1955 #define DM_PROGBUF0_DATA_LENGTH 32
1956 #define DM_PROGBUF0_DATA (0xffffffffU << DM_PROGBUF0_DATA_OFFSET)
1957 #define DM_PROGBUF1 0x21
1958 #define DM_PROGBUF2 0x22
1959 #define DM_PROGBUF3 0x23
1960 #define DM_PROGBUF4 0x24
1961 #define DM_PROGBUF5 0x25
1962 #define DM_PROGBUF6 0x26
1963 #define DM_PROGBUF7 0x27
1964 #define DM_PROGBUF8 0x28
1965 #define DM_PROGBUF9 0x29
1966 #define DM_PROGBUF10 0x2a
1967 #define DM_PROGBUF11 0x2b
1968 #define DM_PROGBUF12 0x2c
1969 #define DM_PROGBUF13 0x2d
1970 #define DM_PROGBUF14 0x2e
1971 #define DM_PROGBUF15 0x2f
1972 #define DM_AUTHDATA 0x30
1973 #define DM_AUTHDATA_DATA_OFFSET 0
1974 #define DM_AUTHDATA_DATA_LENGTH 32
1975 #define DM_AUTHDATA_DATA (0xffffffffU << DM_AUTHDATA_DATA_OFFSET)
1976 #define DM_DMCS2 0x32
1978 * 0: The remaining fields in this register configure halt groups.
1980 * 1: The remaining fields in this register configure resume groups.
1982 #define DM_DMCS2_GROUPTYPE_OFFSET 11
1983 #define DM_DMCS2_GROUPTYPE_LENGTH 1
1984 #define DM_DMCS2_GROUPTYPE (0x1U << DM_DMCS2_GROUPTYPE_OFFSET)
1986 * This field contains the currently selected DM external trigger.
1988 * If a non-existent trigger value is written here, the hardware will
1989 * change it to a valid one or 0 if no DM external triggers exist.
1991 #define DM_DMCS2_DMEXTTRIGGER_OFFSET 7
1992 #define DM_DMCS2_DMEXTTRIGGER_LENGTH 4
1993 #define DM_DMCS2_DMEXTTRIGGER (0xfU << DM_DMCS2_DMEXTTRIGGER_OFFSET)
1995 * When \FdmDmcsTwoHgselect is 0, contains the group of the hart
1996 * specified by \Fhartsel.
1998 * When \FdmDmcsTwoHgselect is 1, contains the group of the DM external
1999 * trigger selected by \FdmDmcsTwoDmexttrigger.
2001 * Writes only have an effect if \FdmDmcsTwoHgwrite is also written 1.
2003 * Group numbers are contiguous starting at 0, with the highest number
2004 * being implementation-dependent, and possibly different between
2005 * different group types. Debuggers should read back this field after
2006 * writing to confirm they are using a hart group that is supported.
2008 * If groups aren't implemented, then this entire field is 0.
2010 #define DM_DMCS2_GROUP_OFFSET 2
2011 #define DM_DMCS2_GROUP_LENGTH 5
2012 #define DM_DMCS2_GROUP (0x1fU << DM_DMCS2_GROUP_OFFSET)
2014 * When 1 is written and \FdmDmcsTwoHgselect is 0, for every selected
2015 * hart the DM will change its group to the value written to \FdmDmcsTwoGroup,
2016 * if the hardware supports that group for that hart.
2017 * Implementations may also change the group of a minimal set of
2018 * unselected harts in the same way, if that is necessary due to
2019 * a hardware limitation.
2021 * When 1 is written and \FdmDmcsTwoHgselect is 1, the DM will change
2022 * the group of the DM external trigger selected by \FdmDmcsTwoDmexttrigger
2023 * to the value written to \FdmDmcsTwoGroup, if the hardware supports
2024 * that group for that trigger.
2026 * Writing 0 has no effect.
2028 #define DM_DMCS2_HGWRITE_OFFSET 1
2029 #define DM_DMCS2_HGWRITE_LENGTH 1
2030 #define DM_DMCS2_HGWRITE (0x1U << DM_DMCS2_HGWRITE_OFFSET)
2032 * 0: Operate on harts.
2034 * 1: Operate on DM external triggers.
2036 * If there are no DM external triggers, this field must be tied to 0.
2038 #define DM_DMCS2_HGSELECT_OFFSET 0
2039 #define DM_DMCS2_HGSELECT_LENGTH 1
2040 #define DM_DMCS2_HGSELECT (0x1U << DM_DMCS2_HGSELECT_OFFSET)
2041 #define DM_HALTSUM0 0x40
2042 #define DM_HALTSUM0_HALTSUM0_OFFSET 0
2043 #define DM_HALTSUM0_HALTSUM0_LENGTH 32
2044 #define DM_HALTSUM0_HALTSUM0 (0xffffffffU << DM_HALTSUM0_HALTSUM0_OFFSET)
2045 #define DM_HALTSUM1 0x13
2046 #define DM_HALTSUM1_HALTSUM1_OFFSET 0
2047 #define DM_HALTSUM1_HALTSUM1_LENGTH 32
2048 #define DM_HALTSUM1_HALTSUM1 (0xffffffffU << DM_HALTSUM1_HALTSUM1_OFFSET)
2049 #define DM_HALTSUM2 0x34
2050 #define DM_HALTSUM2_HALTSUM2_OFFSET 0
2051 #define DM_HALTSUM2_HALTSUM2_LENGTH 32
2052 #define DM_HALTSUM2_HALTSUM2 (0xffffffffU << DM_HALTSUM2_HALTSUM2_OFFSET)
2053 #define DM_HALTSUM3 0x35
2054 #define DM_HALTSUM3_HALTSUM3_OFFSET 0
2055 #define DM_HALTSUM3_HALTSUM3_LENGTH 32
2056 #define DM_HALTSUM3_HALTSUM3 (0xffffffffU << DM_HALTSUM3_HALTSUM3_OFFSET)
2057 #define DM_SBCS 0x38
2059 * 0: The System Bus interface conforms to mainline drafts of this
2060 * spec older than 1 January, 2018.
2062 * 1: The System Bus interface conforms to this version of the spec.
2064 * Other values are reserved for future versions.
2066 #define DM_SBCS_SBVERSION_OFFSET 29
2067 #define DM_SBCS_SBVERSION_LENGTH 3
2068 #define DM_SBCS_SBVERSION (0x7U << DM_SBCS_SBVERSION_OFFSET)
2070 * Set when the debugger attempts to read data while a read is in
2071 * progress, or when the debugger initiates a new access while one is
2072 * already in progress (while \FdmSbcsSbbusy is set). It remains set until
2073 * it's explicitly cleared by the debugger.
2075 * While this field is set, no more system bus accesses can be
2076 * initiated by the Debug Module.
2078 #define DM_SBCS_SBBUSYERROR_OFFSET 22
2079 #define DM_SBCS_SBBUSYERROR_LENGTH 1
2080 #define DM_SBCS_SBBUSYERROR (0x1U << DM_SBCS_SBBUSYERROR_OFFSET)
2082 * When 1, indicates the system bus master is busy. (Whether the
2083 * system bus itself is busy is related, but not the same thing.) This
2084 * bit goes high immediately when a read or write is requested for any
2085 * reason, and does not go low until the access is fully completed.
2087 * Writes to \RdmSbcs while \FdmSbcsSbbusy is high result in undefined
2088 * behavior. A debugger must not write to \RdmSbcs until it reads
2089 * \FdmSbcsSbbusy as 0.
2091 #define DM_SBCS_SBBUSY_OFFSET 21
2092 #define DM_SBCS_SBBUSY_LENGTH 1
2093 #define DM_SBCS_SBBUSY (0x1U << DM_SBCS_SBBUSY_OFFSET)
2095 * When 1, every write to \RdmSbaddressZero automatically triggers a
2096 * system bus read at the new address.
2098 #define DM_SBCS_SBREADONADDR_OFFSET 20
2099 #define DM_SBCS_SBREADONADDR_LENGTH 1
2100 #define DM_SBCS_SBREADONADDR (0x1U << DM_SBCS_SBREADONADDR_OFFSET)
2102 * Select the access size to use for system bus accesses.
2114 * If \FdmSbcsSbaccess has an unsupported value when the DM starts a bus
2115 * access, the access is not performed and \FdmSbcsSberror is set to 4.
2117 #define DM_SBCS_SBACCESS_OFFSET 17
2118 #define DM_SBCS_SBACCESS_LENGTH 3
2119 #define DM_SBCS_SBACCESS (0x7U << DM_SBCS_SBACCESS_OFFSET)
2121 * When 1, {\tt sbaddress} is incremented by the access size (in
2122 * bytes) selected in \FdmSbcsSbaccess after every system bus access.
2124 #define DM_SBCS_SBAUTOINCREMENT_OFFSET 16
2125 #define DM_SBCS_SBAUTOINCREMENT_LENGTH 1
2126 #define DM_SBCS_SBAUTOINCREMENT (0x1U << DM_SBCS_SBAUTOINCREMENT_OFFSET)
2128 * When 1, every read from \RdmSbdataZero automatically triggers a
2129 * system bus read at the (possibly auto-incremented) address.
2131 #define DM_SBCS_SBREADONDATA_OFFSET 15
2132 #define DM_SBCS_SBREADONDATA_LENGTH 1
2133 #define DM_SBCS_SBREADONDATA (0x1U << DM_SBCS_SBREADONDATA_OFFSET)
2135 * When the Debug Module's system bus
2136 * master encounters an error, this field gets set. The bits in this
2137 * field remain set until they are cleared by writing 1 to them.
2138 * While this field is non-zero, no more system bus accesses can be
2139 * initiated by the Debug Module.
2141 * An implementation may report ``Other'' (7) for any error condition.
2143 * 0: There was no bus error.
2145 * 1: There was a timeout.
2147 * 2: A bad address was accessed.
2149 * 3: There was an alignment error.
2151 * 4: An access of unsupported size was requested.
2155 #define DM_SBCS_SBERROR_OFFSET 12
2156 #define DM_SBCS_SBERROR_LENGTH 3
2157 #define DM_SBCS_SBERROR (0x7U << DM_SBCS_SBERROR_OFFSET)
2159 * Width of system bus addresses in bits. (0 indicates there is no bus
2162 #define DM_SBCS_SBASIZE_OFFSET 5
2163 #define DM_SBCS_SBASIZE_LENGTH 7
2164 #define DM_SBCS_SBASIZE (0x7fU << DM_SBCS_SBASIZE_OFFSET)
2166 * 1 when 128-bit system bus accesses are supported.
2168 #define DM_SBCS_SBACCESS128_OFFSET 4
2169 #define DM_SBCS_SBACCESS128_LENGTH 1
2170 #define DM_SBCS_SBACCESS128 (0x1U << DM_SBCS_SBACCESS128_OFFSET)
2172 * 1 when 64-bit system bus accesses are supported.
2174 #define DM_SBCS_SBACCESS64_OFFSET 3
2175 #define DM_SBCS_SBACCESS64_LENGTH 1
2176 #define DM_SBCS_SBACCESS64 (0x1U << DM_SBCS_SBACCESS64_OFFSET)
2178 * 1 when 32-bit system bus accesses are supported.
2180 #define DM_SBCS_SBACCESS32_OFFSET 2
2181 #define DM_SBCS_SBACCESS32_LENGTH 1
2182 #define DM_SBCS_SBACCESS32 (0x1U << DM_SBCS_SBACCESS32_OFFSET)
2184 * 1 when 16-bit system bus accesses are supported.
2186 #define DM_SBCS_SBACCESS16_OFFSET 1
2187 #define DM_SBCS_SBACCESS16_LENGTH 1
2188 #define DM_SBCS_SBACCESS16 (0x1U << DM_SBCS_SBACCESS16_OFFSET)
2190 * 1 when 8-bit system bus accesses are supported.
2192 #define DM_SBCS_SBACCESS8_OFFSET 0
2193 #define DM_SBCS_SBACCESS8_LENGTH 1
2194 #define DM_SBCS_SBACCESS8 (0x1U << DM_SBCS_SBACCESS8_OFFSET)
2195 #define DM_SBADDRESS0 0x39
2197 * Accesses bits 31:0 of the physical address in {\tt sbaddress}.
2199 #define DM_SBADDRESS0_ADDRESS_OFFSET 0
2200 #define DM_SBADDRESS0_ADDRESS_LENGTH 32
2201 #define DM_SBADDRESS0_ADDRESS (0xffffffffU << DM_SBADDRESS0_ADDRESS_OFFSET)
2202 #define DM_SBADDRESS1 0x3a
2204 * Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
2205 * the system address bus is that wide).
2207 #define DM_SBADDRESS1_ADDRESS_OFFSET 0
2208 #define DM_SBADDRESS1_ADDRESS_LENGTH 32
2209 #define DM_SBADDRESS1_ADDRESS (0xffffffffU << DM_SBADDRESS1_ADDRESS_OFFSET)
2210 #define DM_SBADDRESS2 0x3b
2212 * Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
2213 * the system address bus is that wide).
2215 #define DM_SBADDRESS2_ADDRESS_OFFSET 0
2216 #define DM_SBADDRESS2_ADDRESS_LENGTH 32
2217 #define DM_SBADDRESS2_ADDRESS (0xffffffffU << DM_SBADDRESS2_ADDRESS_OFFSET)
2218 #define DM_SBADDRESS3 0x37
2220 * Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
2221 * the system address bus is that wide).
2223 #define DM_SBADDRESS3_ADDRESS_OFFSET 0
2224 #define DM_SBADDRESS3_ADDRESS_LENGTH 32
2225 #define DM_SBADDRESS3_ADDRESS (0xffffffffU << DM_SBADDRESS3_ADDRESS_OFFSET)
2226 #define DM_SBDATA0 0x3c
2228 * Accesses bits 31:0 of {\tt sbdata}.
2230 #define DM_SBDATA0_DATA_OFFSET 0
2231 #define DM_SBDATA0_DATA_LENGTH 32
2232 #define DM_SBDATA0_DATA (0xffffffffU << DM_SBDATA0_DATA_OFFSET)
2233 #define DM_SBDATA1 0x3d
2235 * Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
2238 #define DM_SBDATA1_DATA_OFFSET 0
2239 #define DM_SBDATA1_DATA_LENGTH 32
2240 #define DM_SBDATA1_DATA (0xffffffffU << DM_SBDATA1_DATA_OFFSET)
2241 #define DM_SBDATA2 0x3e
2243 * Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
2246 #define DM_SBDATA2_DATA_OFFSET 0
2247 #define DM_SBDATA2_DATA_LENGTH 32
2248 #define DM_SBDATA2_DATA (0xffffffffU << DM_SBDATA2_DATA_OFFSET)
2249 #define DM_SBDATA3 0x3f
2251 * Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
2254 #define DM_SBDATA3_DATA_OFFSET 0
2255 #define DM_SBDATA3_DATA_LENGTH 32
2256 #define DM_SBDATA3_DATA (0xffffffffU << DM_SBDATA3_DATA_OFFSET)
2257 #define DM_CUSTOM 0x1f
2258 #define DM_CUSTOM0 0x70
2259 #define DM_CUSTOM1 0x71
2260 #define DM_CUSTOM2 0x72
2261 #define DM_CUSTOM3 0x73
2262 #define DM_CUSTOM4 0x74
2263 #define DM_CUSTOM5 0x75
2264 #define DM_CUSTOM6 0x76
2265 #define DM_CUSTOM7 0x77
2266 #define DM_CUSTOM8 0x78
2267 #define DM_CUSTOM9 0x79
2268 #define DM_CUSTOM10 0x7a
2269 #define DM_CUSTOM11 0x7b
2270 #define DM_CUSTOM12 0x7c
2271 #define DM_CUSTOM13 0x7d
2272 #define DM_CUSTOM14 0x7e
2273 #define DM_CUSTOM15 0x7f
2274 #define SHORTNAME 0x123
2276 * Description of what this field is used for.
2278 #define SHORTNAME_FIELD_OFFSET 0
2279 #define SHORTNAME_FIELD_LENGTH 8
2280 #define SHORTNAME_FIELD (0xffU << SHORTNAME_FIELD_OFFSET)
2282 * This is 0 to indicate Access Register Command.
2284 #define AC_ACCESS_REGISTER_CMDTYPE_OFFSET 24
2285 #define AC_ACCESS_REGISTER_CMDTYPE_LENGTH 8
2286 #define AC_ACCESS_REGISTER_CMDTYPE (0xffU << AC_ACCESS_REGISTER_CMDTYPE_OFFSET)
2288 * 2: Access the lowest 32 bits of the register.
2290 * 3: Access the lowest 64 bits of the register.
2292 * 4: Access the lowest 128 bits of the register.
2294 * If \FacAccessregisterAarsize specifies a size larger than the register's actual size,
2295 * then the access must fail. If a register is accessible, then reads of \FacAccessregisterAarsize
2296 * less than or equal to the register's actual size must be supported.
2298 * This field controls the Argument Width as referenced in
2299 * Table~\ref{tab:datareg}.
2301 #define AC_ACCESS_REGISTER_AARSIZE_OFFSET 20
2302 #define AC_ACCESS_REGISTER_AARSIZE_LENGTH 3
2303 #define AC_ACCESS_REGISTER_AARSIZE (0x7U << AC_ACCESS_REGISTER_AARSIZE_OFFSET)
2305 * 0: No effect. This variant must be supported.
2307 * 1: After a successful register access, \FacAccessregisterRegno is
2308 * incremented. Incrementing past the highest supported value
2309 * causes \FacAccessregisterRegno to become \unspecified. Supporting
2310 * this variant is optional. It is undefined whether the increment
2311 * happens when \FacAccessregisterTransfer is 0.
2313 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET 19
2314 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT_LENGTH 1
2315 #define AC_ACCESS_REGISTER_AARPOSTINCREMENT (0x1U << AC_ACCESS_REGISTER_AARPOSTINCREMENT_OFFSET)
2317 * 0: No effect. This variant must be supported, and is the only
2318 * supported one if \FdmAbstractcsProgbufsize is 0.
2320 * 1: Execute the program in the Program Buffer exactly once after
2321 * performing the transfer, if any. Supporting this variant is
2324 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET 18
2325 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH 1
2326 #define AC_ACCESS_REGISTER_POSTEXEC (0x1U << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
2328 * 0: Don't do the operation specified by \FacAccessregisterWrite.
2330 * 1: Do the operation specified by \FacAccessregisterWrite.
2332 * This bit can be used to just execute the Program Buffer without
2333 * having to worry about placing valid values into \FacAccessregisterAarsize or \FacAccessregisterRegno.
2335 #define AC_ACCESS_REGISTER_TRANSFER_OFFSET 17
2336 #define AC_ACCESS_REGISTER_TRANSFER_LENGTH 1
2337 #define AC_ACCESS_REGISTER_TRANSFER (0x1U << AC_ACCESS_REGISTER_TRANSFER_OFFSET)
2339 * When \FacAccessregisterTransfer is set:
2340 * 0: Copy data from the specified register into {\tt arg0} portion
2343 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
2344 * specified register.
2346 #define AC_ACCESS_REGISTER_WRITE_OFFSET 16
2347 #define AC_ACCESS_REGISTER_WRITE_LENGTH 1
2348 #define AC_ACCESS_REGISTER_WRITE (0x1U << AC_ACCESS_REGISTER_WRITE_OFFSET)
2350 * Number of the register to access, as described in
2351 * Table~\ref{tab:regno}.
2352 * \RcsrDpc may be used as an alias for PC if this command is
2353 * supported on a non-halted hart.
2355 #define AC_ACCESS_REGISTER_REGNO_OFFSET 0
2356 #define AC_ACCESS_REGISTER_REGNO_LENGTH 16
2357 #define AC_ACCESS_REGISTER_REGNO (0xffffU << AC_ACCESS_REGISTER_REGNO_OFFSET)
2359 * This is 1 to indicate Quick Access command.
2361 #define AC_QUICK_ACCESS_CMDTYPE_OFFSET 24
2362 #define AC_QUICK_ACCESS_CMDTYPE_LENGTH 8
2363 #define AC_QUICK_ACCESS_CMDTYPE (0xffU << AC_QUICK_ACCESS_CMDTYPE_OFFSET)
2365 * This is 2 to indicate Access Memory Command.
2367 #define AC_ACCESS_MEMORY_CMDTYPE_OFFSET 24
2368 #define AC_ACCESS_MEMORY_CMDTYPE_LENGTH 8
2369 #define AC_ACCESS_MEMORY_CMDTYPE (0xffU << AC_ACCESS_MEMORY_CMDTYPE_OFFSET)
2371 * An implementation does not have to implement both virtual and
2372 * physical accesses, but it must fail accesses that it doesn't
2375 * 0: Addresses are physical (to the hart they are performed on).
2377 * 1: Addresses are virtual, and translated the way they would be from
2378 * M-mode, with \FcsrMstatusMprv set.
2380 * Debug Modules on systems without address translation (i.e. virtual addresses equal physical)
2381 * may optionally allow \FacAccessmemoryAamvirtual set to 1, which would produce the same result as
2382 * that same abstract command with \FacAccessmemoryAamvirtual cleared.
2384 #define AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET 23
2385 #define AC_ACCESS_MEMORY_AAMVIRTUAL_LENGTH 1
2386 #define AC_ACCESS_MEMORY_AAMVIRTUAL (0x1U << AC_ACCESS_MEMORY_AAMVIRTUAL_OFFSET)
2388 * 0: Access the lowest 8 bits of the memory location.
2390 * 1: Access the lowest 16 bits of the memory location.
2392 * 2: Access the lowest 32 bits of the memory location.
2394 * 3: Access the lowest 64 bits of the memory location.
2396 * 4: Access the lowest 128 bits of the memory location.
2398 #define AC_ACCESS_MEMORY_AAMSIZE_OFFSET 20
2399 #define AC_ACCESS_MEMORY_AAMSIZE_LENGTH 3
2400 #define AC_ACCESS_MEMORY_AAMSIZE (0x7U << AC_ACCESS_MEMORY_AAMSIZE_OFFSET)
2402 * After a memory access has completed, if this bit is 1, increment
2403 * {\tt arg1} (which contains the address used) by the number of bytes
2404 * encoded in \FacAccessmemoryAamsize.
2406 * Supporting this variant is optional, but highly recommended for
2407 * performance reasons.
2409 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET 19
2410 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT_LENGTH 1
2411 #define AC_ACCESS_MEMORY_AAMPOSTINCREMENT (0x1U << AC_ACCESS_MEMORY_AAMPOSTINCREMENT_OFFSET)
2413 * 0: Copy data from the memory location specified in {\tt arg1} into
2414 * the low bits of {\tt arg0}. Any remaining bits of {\tt arg0} now
2415 * have an undefined value.
2417 * 1: Copy data from the low bits of {\tt arg0} into the memory
2418 * location specified in {\tt arg1}.
2420 #define AC_ACCESS_MEMORY_WRITE_OFFSET 16
2421 #define AC_ACCESS_MEMORY_WRITE_LENGTH 1
2422 #define AC_ACCESS_MEMORY_WRITE (0x1U << AC_ACCESS_MEMORY_WRITE_OFFSET)
2424 * These bits are reserved for target-specific uses.
2426 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET 14
2427 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC_LENGTH 2
2428 #define AC_ACCESS_MEMORY_TARGET_SPECIFIC (0x3U << AC_ACCESS_MEMORY_TARGET_SPECIFIC_OFFSET)
2429 #define VIRT_PRIV virtual
2431 * Contains the virtualization mode the hart was operating in when Debug
2432 * Mode was entered. The encoding is described in Table \ref{tab:privlevel},
2433 * and matches the virtualization mode encoding from the Privileged Spec.
2434 * A user can write this value to change the hart's virtualization mode
2435 * when exiting Debug Mode.
2437 #define VIRT_PRIV_V_OFFSET 2
2438 #define VIRT_PRIV_V_LENGTH 1
2439 #define VIRT_PRIV_V (0x1U << VIRT_PRIV_V_OFFSET)
2441 * Contains the privilege level the hart was operating in when Debug
2442 * Mode was entered. The encoding is described in Table
2443 * \ref{tab:privlevel}, and matches the privilege level encoding from
2444 * the Privileged Spec. A user can write this
2445 * value to change the hart's privilege level when exiting Debug Mode.
2447 #define VIRT_PRIV_PRV_OFFSET 0
2448 #define VIRT_PRIV_PRV_LENGTH 2
2449 #define VIRT_PRIV_PRV (0x3U << VIRT_PRIV_PRV_OFFSET)
2450 #define DMI_SERCS 0x34
2452 * Number of supported serial ports.
2454 #define DMI_SERCS_SERIALCOUNT_OFFSET 28
2455 #define DMI_SERCS_SERIALCOUNT_LENGTH 4
2456 #define DMI_SERCS_SERIALCOUNT (0xfU << DMI_SERCS_SERIALCOUNT_OFFSET)
2458 * Select which serial port is accessed by \RdmiSerrx and \RdmiSertx.
2460 #define DMI_SERCS_SERIAL_OFFSET 24
2461 #define DMI_SERCS_SERIAL_LENGTH 3
2462 #define DMI_SERCS_SERIAL (0x7U << DMI_SERCS_SERIAL_OFFSET)
2463 #define DMI_SERCS_ERROR7_OFFSET 23
2464 #define DMI_SERCS_ERROR7_LENGTH 1
2465 #define DMI_SERCS_ERROR7 (0x1U << DMI_SERCS_ERROR7_OFFSET)
2466 #define DMI_SERCS_VALID7_OFFSET 22
2467 #define DMI_SERCS_VALID7_LENGTH 1
2468 #define DMI_SERCS_VALID7 (0x1U << DMI_SERCS_VALID7_OFFSET)
2469 #define DMI_SERCS_FULL7_OFFSET 21
2470 #define DMI_SERCS_FULL7_LENGTH 1
2471 #define DMI_SERCS_FULL7 (0x1U << DMI_SERCS_FULL7_OFFSET)
2472 #define DMI_SERCS_ERROR6_OFFSET 20
2473 #define DMI_SERCS_ERROR6_LENGTH 1
2474 #define DMI_SERCS_ERROR6 (0x1U << DMI_SERCS_ERROR6_OFFSET)
2475 #define DMI_SERCS_VALID6_OFFSET 19
2476 #define DMI_SERCS_VALID6_LENGTH 1
2477 #define DMI_SERCS_VALID6 (0x1U << DMI_SERCS_VALID6_OFFSET)
2478 #define DMI_SERCS_FULL6_OFFSET 18
2479 #define DMI_SERCS_FULL6_LENGTH 1
2480 #define DMI_SERCS_FULL6 (0x1U << DMI_SERCS_FULL6_OFFSET)
2481 #define DMI_SERCS_ERROR5_OFFSET 17
2482 #define DMI_SERCS_ERROR5_LENGTH 1
2483 #define DMI_SERCS_ERROR5 (0x1U << DMI_SERCS_ERROR5_OFFSET)
2484 #define DMI_SERCS_VALID5_OFFSET 16
2485 #define DMI_SERCS_VALID5_LENGTH 1
2486 #define DMI_SERCS_VALID5 (0x1U << DMI_SERCS_VALID5_OFFSET)
2487 #define DMI_SERCS_FULL5_OFFSET 15
2488 #define DMI_SERCS_FULL5_LENGTH 1
2489 #define DMI_SERCS_FULL5 (0x1U << DMI_SERCS_FULL5_OFFSET)
2490 #define DMI_SERCS_ERROR4_OFFSET 14
2491 #define DMI_SERCS_ERROR4_LENGTH 1
2492 #define DMI_SERCS_ERROR4 (0x1U << DMI_SERCS_ERROR4_OFFSET)
2493 #define DMI_SERCS_VALID4_OFFSET 13
2494 #define DMI_SERCS_VALID4_LENGTH 1
2495 #define DMI_SERCS_VALID4 (0x1U << DMI_SERCS_VALID4_OFFSET)
2496 #define DMI_SERCS_FULL4_OFFSET 12
2497 #define DMI_SERCS_FULL4_LENGTH 1
2498 #define DMI_SERCS_FULL4 (0x1U << DMI_SERCS_FULL4_OFFSET)
2499 #define DMI_SERCS_ERROR3_OFFSET 11
2500 #define DMI_SERCS_ERROR3_LENGTH 1
2501 #define DMI_SERCS_ERROR3 (0x1U << DMI_SERCS_ERROR3_OFFSET)
2502 #define DMI_SERCS_VALID3_OFFSET 10
2503 #define DMI_SERCS_VALID3_LENGTH 1
2504 #define DMI_SERCS_VALID3 (0x1U << DMI_SERCS_VALID3_OFFSET)
2505 #define DMI_SERCS_FULL3_OFFSET 9
2506 #define DMI_SERCS_FULL3_LENGTH 1
2507 #define DMI_SERCS_FULL3 (0x1U << DMI_SERCS_FULL3_OFFSET)
2508 #define DMI_SERCS_ERROR2_OFFSET 8
2509 #define DMI_SERCS_ERROR2_LENGTH 1
2510 #define DMI_SERCS_ERROR2 (0x1U << DMI_SERCS_ERROR2_OFFSET)
2511 #define DMI_SERCS_VALID2_OFFSET 7
2512 #define DMI_SERCS_VALID2_LENGTH 1
2513 #define DMI_SERCS_VALID2 (0x1U << DMI_SERCS_VALID2_OFFSET)
2514 #define DMI_SERCS_FULL2_OFFSET 6
2515 #define DMI_SERCS_FULL2_LENGTH 1
2516 #define DMI_SERCS_FULL2 (0x1U << DMI_SERCS_FULL2_OFFSET)
2517 #define DMI_SERCS_ERROR1_OFFSET 5
2518 #define DMI_SERCS_ERROR1_LENGTH 1
2519 #define DMI_SERCS_ERROR1 (0x1U << DMI_SERCS_ERROR1_OFFSET)
2520 #define DMI_SERCS_VALID1_OFFSET 4
2521 #define DMI_SERCS_VALID1_LENGTH 1
2522 #define DMI_SERCS_VALID1 (0x1U << DMI_SERCS_VALID1_OFFSET)
2523 #define DMI_SERCS_FULL1_OFFSET 3
2524 #define DMI_SERCS_FULL1_LENGTH 1
2525 #define DMI_SERCS_FULL1 (0x1U << DMI_SERCS_FULL1_OFFSET)
2527 * 1 when the debugger-to-core queue for serial port 0 has
2528 * over or underflowed. This bit will remain set until it is reset by
2529 * writing 1 to this bit.
2531 #define DMI_SERCS_ERROR0_OFFSET 2
2532 #define DMI_SERCS_ERROR0_LENGTH 1
2533 #define DMI_SERCS_ERROR0 (0x1U << DMI_SERCS_ERROR0_OFFSET)
2535 * 1 when the core-to-debugger queue for serial port 0 is not empty.
2537 #define DMI_SERCS_VALID0_OFFSET 1
2538 #define DMI_SERCS_VALID0_LENGTH 1
2539 #define DMI_SERCS_VALID0 (0x1U << DMI_SERCS_VALID0_OFFSET)
2541 * 1 when the debugger-to-core queue for serial port 0 is full.
2543 #define DMI_SERCS_FULL0_OFFSET 0
2544 #define DMI_SERCS_FULL0_LENGTH 1
2545 #define DMI_SERCS_FULL0 (0x1U << DMI_SERCS_FULL0_OFFSET)
2546 #define DMI_SERTX 0x35
2547 #define DMI_SERTX_DATA_OFFSET 0
2548 #define DMI_SERTX_DATA_LENGTH 32
2549 #define DMI_SERTX_DATA (0xffffffffU << DMI_SERTX_DATA_OFFSET)
2550 #define DMI_SERRX 0x36
2551 #define DMI_SERRX_DATA_OFFSET 0
2552 #define DMI_SERRX_DATA_LENGTH 32
2553 #define DMI_SERRX_DATA (0xffffffffU << DMI_SERRX_DATA_OFFSET)