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   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Julius Baxter                                   *
   3  *   julius@opencores.org                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2013 by Marek Czerski                                   *
   6  *   ma.czerski@gmail.com                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2013 by Franck Jullien                                  *
   9  *   elec4fun@gmail.com                                                    *
  10  *                                                                         *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  24  ***************************************************************************/
  25
  26 #ifndef OPENOCD_TARGET_OPENRISC_OR1K_H
  27 #define OPENOCD_TARGET_OPENRISC_OR1K_H
  28
  29 #ifdef HAVE_CONFIG_H
  30 #include "config.h"
  31 #endif
  32
  33 #include <target/target.h>
  34
  35 /* SPR groups start address */
  36 #define GROUP0          (0  << 11)
  37 #define GROUP1          (1  << 11)
  38 #define GROUP2          (2  << 11)
  39 #define GROUP3          (3  << 11)
  40 #define GROUP4          (4  << 11)
  41 #define GROUP5          (5  << 11)
  42 #define GROUP6          (6  << 11)
  43 #define GROUP7          (7  << 11)
  44 #define GROUP8          (8  << 11)
  45 #define GROUP9          (9  << 11)
  46 #define GROUP10         (10 << 11)
  47
  48 /* OR1K registers */
  49 enum or1k_reg_nums {
  50         OR1K_REG_R0 = 0,
  51         OR1K_REG_R1,
  52         OR1K_REG_R2,
  53         OR1K_REG_R3,
  54         OR1K_REG_R4,
  55         OR1K_REG_R5,
  56         OR1K_REG_R6,
  57         OR1K_REG_R7,
  58         OR1K_REG_R8,
  59         OR1K_REG_R9,
  60         OR1K_REG_R10,
  61         OR1K_REG_R11,
  62         OR1K_REG_R12,
  63         OR1K_REG_R13,
  64         OR1K_REG_R14,
  65         OR1K_REG_R15,
  66         OR1K_REG_R16,
  67         OR1K_REG_R17,
  68         OR1K_REG_R18,
  69         OR1K_REG_R19,
  70         OR1K_REG_R20,
  71         OR1K_REG_R21,
  72         OR1K_REG_R22,
  73         OR1K_REG_R23,
  74         OR1K_REG_R24,
  75         OR1K_REG_R25,
  76         OR1K_REG_R26,
  77         OR1K_REG_R27,
  78         OR1K_REG_R28,
  79         OR1K_REG_R29,
  80         OR1K_REG_R30,
  81         OR1K_REG_R31,
  82         OR1K_REG_PPC,
  83         OR1K_REG_NPC,
  84         OR1K_REG_SR,
  85         OR1KNUMCOREREGS
  86 };
  87
  88 struct or1k_jtag {
  89         struct jtag_tap *tap;
  90         int or1k_jtag_inited;
  91         int or1k_jtag_module_selected;
  92         uint8_t *current_reg_idx;
  93         struct or1k_tap_ip *tap_ip;
  94         struct or1k_du *du_core;
  95         struct target *target;
  96 };
  97
  98 struct or1k_common {
  99         struct or1k_jtag jtag;
 100         struct reg_cache *core_cache;
 101         uint32_t core_regs[OR1KNUMCOREREGS];
 102         int nb_regs;
 103         struct or1k_core_reg *arch_info;
 104 };
 105
 106 static inline struct or1k_common *
 107 target_to_or1k(struct target *target)
 108 {
 109         return (struct or1k_common *)target->arch_info;
 110 }
 111
 112 struct or1k_core_reg {
 113         const char *name;
 114         uint32_t list_num;   /* Index in register cache */
 115         uint32_t spr_num;    /* Number in architecture's SPR space */
 116         struct target *target;
 117         struct or1k_common *or1k_common;
 118         const char *feature; /* feature name in XML tdesc file */
 119         const char *group;   /* register group in XML tdesc file */
 120 };
 121
 122 struct or1k_core_reg_init {
 123         const char *name;
 124         uint32_t spr_num;    /* Number in architecture's SPR space */
 125         const char *feature; /* feature name in XML tdesc file */
 126         const char *group;   /* register group in XML tdesc file */
 127 };
 128
 129 /* ORBIS32 Trap instruction */
 130 #define OR1K_TRAP_INSTR  0x21000001
 131
 132 enum or1k_debug_reg_nums {
 133         OR1K_DEBUG_REG_DMR1 = 0,
 134         OR1K_DEBUG_REG_DMR2,
 135         OR1K_DEBUG_REG_DCWR0,
 136         OR1K_DEBUG_REG_DCWR1,
 137         OR1K_DEBUG_REG_DSR,
 138         OR1K_DEBUG_REG_DRR,
 139         OR1K_DEBUG_REG_NUM
 140 };
 141
 142 #define NO_SINGLE_STEP          0
 143 #define SINGLE_STEP             1
 144
 145 /* OR1K Debug registers and bits needed for resuming */
 146 #define OR1K_DEBUG_REG_BASE     GROUP6                     /* Debug registers Base address */
 147 #define OR1K_DMR1_CPU_REG_ADD   (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
 148 #define OR1K_DMR1_ST            0x00400000                 /* Single-step trace */
 149 #define OR1K_DMR1_BT            0x00800000                 /* Branch trace */
 150 #define OR1K_DMR2_WGB           0x003ff000                 /* Watchpoints generating breakpoint */
 151 #define OR1K_DSR_TE             0x00002000                 /* Trap exception */
 152
 153 /* OR1K Instruction cache registers needed for invalidating instruction
 154  * memory during adding and removing breakpoints.
 155  */
 156 #define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2)             /* IC Block Invalidate Register 0x2002 */
 157
 158 #endif /* OPENOCD_TARGET_OPENRISC_OR1K_H */