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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2011 by Julius Baxter                                   *
   5  *   julius@opencores.org                                                  *
   6  *                                                                         *
   7  *   Copyright (C) 2013 by Marek Czerski                                   *
   8  *   ma.czerski@gmail.com                                                  *
   9  *                                                                         *
  10  *   Copyright (C) 2013 by Franck Jullien                                  *
  11  *   elec4fun@gmail.com                                                    *
  12  *                                                                         *
  13  ***************************************************************************/
  14
  15 #ifndef OPENOCD_TARGET_OPENRISC_OR1K_H
  16 #define OPENOCD_TARGET_OPENRISC_OR1K_H
  17
  18 #ifdef HAVE_CONFIG_H
  19 #include "config.h"
  20 #endif
  21
  22 #include <target/target.h>
  23
  24 /* SPR groups start address */
  25 #define GROUP0          (0  << 11)
  26 #define GROUP1          (1  << 11)
  27 #define GROUP2          (2  << 11)
  28 #define GROUP3          (3  << 11)
  29 #define GROUP4          (4  << 11)
  30 #define GROUP5          (5  << 11)
  31 #define GROUP6          (6  << 11)
  32 #define GROUP7          (7  << 11)
  33 #define GROUP8          (8  << 11)
  34 #define GROUP9          (9  << 11)
  35 #define GROUP10         (10 << 11)
  36
  37 /* OR1K registers */
  38 enum or1k_reg_nums {
  39         OR1K_REG_R0 = 0,
  40         OR1K_REG_R1,
  41         OR1K_REG_R2,
  42         OR1K_REG_R3,
  43         OR1K_REG_R4,
  44         OR1K_REG_R5,
  45         OR1K_REG_R6,
  46         OR1K_REG_R7,
  47         OR1K_REG_R8,
  48         OR1K_REG_R9,
  49         OR1K_REG_R10,
  50         OR1K_REG_R11,
  51         OR1K_REG_R12,
  52         OR1K_REG_R13,
  53         OR1K_REG_R14,
  54         OR1K_REG_R15,
  55         OR1K_REG_R16,
  56         OR1K_REG_R17,
  57         OR1K_REG_R18,
  58         OR1K_REG_R19,
  59         OR1K_REG_R20,
  60         OR1K_REG_R21,
  61         OR1K_REG_R22,
  62         OR1K_REG_R23,
  63         OR1K_REG_R24,
  64         OR1K_REG_R25,
  65         OR1K_REG_R26,
  66         OR1K_REG_R27,
  67         OR1K_REG_R28,
  68         OR1K_REG_R29,
  69         OR1K_REG_R30,
  70         OR1K_REG_R31,
  71         OR1K_REG_PPC,
  72         OR1K_REG_NPC,
  73         OR1K_REG_SR,
  74         OR1KNUMCOREREGS
  75 };
  76
  77 struct or1k_jtag {
  78         struct jtag_tap *tap;
  79         int or1k_jtag_inited;
  80         int or1k_jtag_module_selected;
  81         uint8_t *current_reg_idx;
  82         struct or1k_tap_ip *tap_ip;
  83         struct or1k_du *du_core;
  84         struct target *target;
  85 };
  86
  87 struct or1k_common {
  88         struct or1k_jtag jtag;
  89         struct reg_cache *core_cache;
  90         uint32_t core_regs[OR1KNUMCOREREGS];
  91         int nb_regs;
  92         struct or1k_core_reg *arch_info;
  93 };
  94
  95 static inline struct or1k_common *
  96 target_to_or1k(struct target *target)
  97 {
  98         return (struct or1k_common *)target->arch_info;
  99 }
 100
 101 struct or1k_core_reg {
 102         const char *name;
 103         uint32_t list_num;   /* Index in register cache */
 104         uint32_t spr_num;    /* Number in architecture's SPR space */
 105         struct target *target;
 106         struct or1k_common *or1k_common;
 107         const char *feature; /* feature name in XML tdesc file */
 108         const char *group;   /* register group in XML tdesc file */
 109 };
 110
 111 struct or1k_core_reg_init {
 112         const char *name;
 113         uint32_t spr_num;    /* Number in architecture's SPR space */
 114         const char *feature; /* feature name in XML tdesc file */
 115         const char *group;   /* register group in XML tdesc file */
 116 };
 117
 118 /* ORBIS32 Trap instruction */
 119 #define OR1K_TRAP_INSTR  0x21000001
 120
 121 enum or1k_debug_reg_nums {
 122         OR1K_DEBUG_REG_DMR1 = 0,
 123         OR1K_DEBUG_REG_DMR2,
 124         OR1K_DEBUG_REG_DCWR0,
 125         OR1K_DEBUG_REG_DCWR1,
 126         OR1K_DEBUG_REG_DSR,
 127         OR1K_DEBUG_REG_DRR,
 128         OR1K_DEBUG_REG_NUM
 129 };
 130
 131 #define NO_SINGLE_STEP          0
 132 #define SINGLE_STEP             1
 133
 134 /* OR1K Debug registers and bits needed for resuming */
 135 #define OR1K_DEBUG_REG_BASE     GROUP6                     /* Debug registers Base address */
 136 #define OR1K_DMR1_CPU_REG_ADD   (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
 137 #define OR1K_DMR1_ST            0x00400000                 /* Single-step trace */
 138 #define OR1K_DMR1_BT            0x00800000                 /* Branch trace */
 139 #define OR1K_DMR2_WGB           0x003ff000                 /* Watchpoints generating breakpoint */
 140 #define OR1K_DSR_TE             0x00002000                 /* Trap exception */
 141
 142 /* OR1K Instruction cache registers needed for invalidating instruction
 143  * memory during adding and removing breakpoints.
 144  */
 145 #define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2)             /* IC Block Invalidate Register 0x2002 */
 146
 147 #endif /* OPENOCD_TARGET_OPENRISC_OR1K_H */