git.gag.com Git - fw/openocd/blob - src/target/openrisc/or1k.c

   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Julius Baxter                                   *
   3  *   julius@opencores.org                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2013 by Marek Czerski                                   *
   6  *   ma.czerski@gmail.com                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2013 by Franck Jullien                                  *
   9  *   elec4fun@gmail.com                                                    *
  10  *                                                                         *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program; if not, write to the                         *
  24  *   Free Software Foundation, Inc.,                                       *
  25  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  26  ***************************************************************************/
  27
  28 #ifdef HAVE_CONFIG_H
  29 #include "config.h"
  30 #endif
  31
  32 #include <jtag/jtag.h>
  33 #include <target/register.h>
  34 #include <target/target.h>
  35 #include <target/breakpoints.h>
  36 #include <target/target_type.h>
  37 #include <helper/fileio.h>
  38 #include "or1k_tap.h"
  39 #include "or1k.h"
  40 #include "or1k_du.h"
  41
  42 LIST_HEAD(tap_list);
  43 LIST_HEAD(du_list);
  44
  45 static int or1k_remove_breakpoint(struct target *target,
  46                                   struct breakpoint *breakpoint);
  47
  48 static int or1k_read_core_reg(struct target *target, int num);
  49 static int or1k_write_core_reg(struct target *target, int num);
  50
  51 static struct or1k_core_reg *or1k_core_reg_list_arch_info;
  52
  53 static const struct or1k_core_reg_init or1k_init_reg_list[] = {
  54         {"r0"       , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
  55         {"r1"       , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
  56         {"r2"       , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
  57         {"r3"       , GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
  58         {"r4"       , GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
  59         {"r5"       , GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
  60         {"r6"       , GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
  61         {"r7"       , GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
  62         {"r8"       , GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
  63         {"r9"       , GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
  64         {"r10"      , GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
  65         {"r11"      , GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
  66         {"r12"      , GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
  67         {"r13"      , GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
  68         {"r14"      , GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
  69         {"r15"      , GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
  70         {"r16"      , GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
  71         {"r17"      , GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
  72         {"r18"      , GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
  73         {"r19"      , GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
  74         {"r20"      , GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
  75         {"r21"      , GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
  76         {"r22"      , GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
  77         {"r23"      , GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
  78         {"r24"      , GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
  79         {"r25"      , GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
  80         {"r26"      , GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
  81         {"r27"      , GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
  82         {"r28"      , GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
  83         {"r29"      , GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
  84         {"r30"      , GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
  85         {"r31"      , GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
  86         {"ppc"      , GROUP0 + 18,   "org.gnu.gdb.or1k.group0", NULL},
  87         {"npc"      , GROUP0 + 16,   "org.gnu.gdb.or1k.group0", NULL},
  88         {"sr"       , GROUP0 + 17,   "org.gnu.gdb.or1k.group0", NULL},
  89         {"vr"       , GROUP0 + 0,    "org.gnu.gdb.or1k.group0", "system"},
  90         {"upr"      , GROUP0 + 1,    "org.gnu.gdb.or1k.group0", "system"},
  91         {"cpucfgr"  , GROUP0 + 2,    "org.gnu.gdb.or1k.group0", "system"},
  92         {"dmmucfgr" , GROUP0 + 3,    "org.gnu.gdb.or1k.group0", "system"},
  93         {"immucfgr" , GROUP0 + 4,    "org.gnu.gdb.or1k.group0", "system"},
  94         {"dccfgr"   , GROUP0 + 5,    "org.gnu.gdb.or1k.group0", "system"},
  95         {"iccfgr"   , GROUP0 + 6,    "org.gnu.gdb.or1k.group0", "system"},
  96         {"dcfgr"    , GROUP0 + 7,    "org.gnu.gdb.or1k.group0", "system"},
  97         {"pccfgr"   , GROUP0 + 8,    "org.gnu.gdb.or1k.group0", "system"},
  98         {"fpcsr"    , GROUP0 + 20,   "org.gnu.gdb.or1k.group0", "system"},
  99         {"epcr0"    , GROUP0 + 32,   "org.gnu.gdb.or1k.group0", "system"},
 100         {"epcr1"    , GROUP0 + 33,   "org.gnu.gdb.or1k.group0", "system"},
 101         {"epcr2"    , GROUP0 + 34,   "org.gnu.gdb.or1k.group0", "system"},
 102         {"epcr3"    , GROUP0 + 35,   "org.gnu.gdb.or1k.group0", "system"},
 103         {"epcr4"    , GROUP0 + 36,   "org.gnu.gdb.or1k.group0", "system"},
 104         {"epcr5"    , GROUP0 + 37,   "org.gnu.gdb.or1k.group0", "system"},
 105         {"epcr6"    , GROUP0 + 38,   "org.gnu.gdb.or1k.group0", "system"},
 106         {"epcr7"    , GROUP0 + 39,   "org.gnu.gdb.or1k.group0", "system"},
 107         {"epcr8"    , GROUP0 + 40,   "org.gnu.gdb.or1k.group0", "system"},
 108         {"epcr9"    , GROUP0 + 41,   "org.gnu.gdb.or1k.group0", "system"},
 109         {"epcr10"   , GROUP0 + 42,   "org.gnu.gdb.or1k.group0", "system"},
 110         {"epcr11"   , GROUP0 + 43,   "org.gnu.gdb.or1k.group0", "system"},
 111         {"epcr12"   , GROUP0 + 44,   "org.gnu.gdb.or1k.group0", "system"},
 112         {"epcr13"   , GROUP0 + 45,   "org.gnu.gdb.or1k.group0", "system"},
 113         {"epcr14"   , GROUP0 + 46,   "org.gnu.gdb.or1k.group0", "system"},
 114         {"epcr15"   , GROUP0 + 47,   "org.gnu.gdb.or1k.group0", "system"},
 115         {"eear0"    , GROUP0 + 48,   "org.gnu.gdb.or1k.group0", "system"},
 116         {"eear1"    , GROUP0 + 49,   "org.gnu.gdb.or1k.group0", "system"},
 117         {"eear2"    , GROUP0 + 50,   "org.gnu.gdb.or1k.group0", "system"},
 118         {"eear3"    , GROUP0 + 51,   "org.gnu.gdb.or1k.group0", "system"},
 119         {"eear4"    , GROUP0 + 52,   "org.gnu.gdb.or1k.group0", "system"},
 120         {"eear5"    , GROUP0 + 53,   "org.gnu.gdb.or1k.group0", "system"},
 121         {"eear6"    , GROUP0 + 54,   "org.gnu.gdb.or1k.group0", "system"},
 122         {"eear7"    , GROUP0 + 55,   "org.gnu.gdb.or1k.group0", "system"},
 123         {"eear8"    , GROUP0 + 56,   "org.gnu.gdb.or1k.group0", "system"},
 124         {"eear9"    , GROUP0 + 57,   "org.gnu.gdb.or1k.group0", "system"},
 125         {"eear10"   , GROUP0 + 58,   "org.gnu.gdb.or1k.group0", "system"},
 126         {"eear11"   , GROUP0 + 59,   "org.gnu.gdb.or1k.group0", "system"},
 127         {"eear12"   , GROUP0 + 60,   "org.gnu.gdb.or1k.group0", "system"},
 128         {"eear13"   , GROUP0 + 61,   "org.gnu.gdb.or1k.group0", "system"},
 129         {"eear14"   , GROUP0 + 62,   "org.gnu.gdb.or1k.group0", "system"},
 130         {"eear15"   , GROUP0 + 63,   "org.gnu.gdb.or1k.group0", "system"},
 131         {"esr0"     , GROUP0 + 64,   "org.gnu.gdb.or1k.group0", "system"},
 132         {"esr1"     , GROUP0 + 65,   "org.gnu.gdb.or1k.group0", "system"},
 133         {"esr2"     , GROUP0 + 66,   "org.gnu.gdb.or1k.group0", "system"},
 134         {"esr3"     , GROUP0 + 67,   "org.gnu.gdb.or1k.group0", "system"},
 135         {"esr4"     , GROUP0 + 68,   "org.gnu.gdb.or1k.group0", "system"},
 136         {"esr5"     , GROUP0 + 69,   "org.gnu.gdb.or1k.group0", "system"},
 137         {"esr6"     , GROUP0 + 70,   "org.gnu.gdb.or1k.group0", "system"},
 138         {"esr7"     , GROUP0 + 71,   "org.gnu.gdb.or1k.group0", "system"},
 139         {"esr8"     , GROUP0 + 72,   "org.gnu.gdb.or1k.group0", "system"},
 140         {"esr9"     , GROUP0 + 73,   "org.gnu.gdb.or1k.group0", "system"},
 141         {"esr10"    , GROUP0 + 74,   "org.gnu.gdb.or1k.group0", "system"},
 142         {"esr11"    , GROUP0 + 75,   "org.gnu.gdb.or1k.group0", "system"},
 143         {"esr12"    , GROUP0 + 76,   "org.gnu.gdb.or1k.group0", "system"},
 144         {"esr13"    , GROUP0 + 77,   "org.gnu.gdb.or1k.group0", "system"},
 145         {"esr14"    , GROUP0 + 78,   "org.gnu.gdb.or1k.group0", "system"},
 146         {"esr15"    , GROUP0 + 79,   "org.gnu.gdb.or1k.group0", "system"},
 147
 148         {"dmmuucr"  , GROUP1 + 0,    "org.gnu.gdb.or1k.group1", "dmmu"},
 149         {"dmmuupr"  , GROUP1 + 1,    "org.gnu.gdb.or1k.group1", "dmmu"},
 150         {"dtlbeir"  , GROUP1 + 2,    "org.gnu.gdb.or1k.group1", "dmmu"},
 151         {"datbmr0"  , GROUP1 + 4,    "org.gnu.gdb.or1k.group1", "dmmu"},
 152         {"datbmr1"  , GROUP1 + 5,    "org.gnu.gdb.or1k.group1", "dmmu"},
 153         {"datbmr2"  , GROUP1 + 6,    "org.gnu.gdb.or1k.group1", "dmmu"},
 154         {"datbmr3"  , GROUP1 + 7,    "org.gnu.gdb.or1k.group1", "dmmu"},
 155         {"datbtr0"  , GROUP1 + 8,    "org.gnu.gdb.or1k.group1", "dmmu"},
 156         {"datbtr1"  , GROUP1 + 9,    "org.gnu.gdb.or1k.group1", "dmmu"},
 157         {"datbtr2"  , GROUP1 + 10,   "org.gnu.gdb.or1k.group1", "dmmu"},
 158         {"datbtr3"  , GROUP1 + 11,   "org.gnu.gdb.or1k.group1", "dmmu"},
 159
 160         {"immucr"   , GROUP2 + 0,    "org.gnu.gdb.or1k.group2", "immu"},
 161         {"immupr"   , GROUP2 + 1,    "org.gnu.gdb.or1k.group2", "immu"},
 162         {"itlbeir"  , GROUP2 + 2,    "org.gnu.gdb.or1k.group2", "immu"},
 163         {"iatbmr0"  , GROUP2 + 4,    "org.gnu.gdb.or1k.group2", "immu"},
 164         {"iatbmr1"  , GROUP2 + 5,    "org.gnu.gdb.or1k.group2", "immu"},
 165         {"iatbmr2"  , GROUP2 + 6,    "org.gnu.gdb.or1k.group2", "immu"},
 166         {"iatbmr3"  , GROUP2 + 7,    "org.gnu.gdb.or1k.group2", "immu"},
 167         {"iatbtr0"  , GROUP2 + 8,    "org.gnu.gdb.or1k.group2", "immu"},
 168         {"iatbtr1"  , GROUP2 + 9,    "org.gnu.gdb.or1k.group2", "immu"},
 169         {"iatbtr2"  , GROUP2 + 10,   "org.gnu.gdb.or1k.group2", "immu"},
 170         {"iatbtr3"  , GROUP2 + 11,   "org.gnu.gdb.or1k.group2", "immu"},
 171
 172         {"dccr"     , GROUP3 + 0,    "org.gnu.gdb.or1k.group3", "dcache"},
 173         {"dcbpr"    , GROUP3 + 1,    "org.gnu.gdb.or1k.group3", "dcache"},
 174         {"dcbfr"    , GROUP3 + 2,    "org.gnu.gdb.or1k.group3", "dcache"},
 175         {"dcbir"    , GROUP3 + 3,    "org.gnu.gdb.or1k.group3", "dcache"},
 176         {"dcbwr"    , GROUP3 + 4,    "org.gnu.gdb.or1k.group3", "dcache"},
 177         {"dcblr"    , GROUP3 + 5,    "org.gnu.gdb.or1k.group3", "dcache"},
 178
 179         {"iccr"     , GROUP4 + 0,    "org.gnu.gdb.or1k.group4", "icache"},
 180         {"icbpr"    , GROUP4 + 1,    "org.gnu.gdb.or1k.group4", "icache"},
 181         {"icbir"    , GROUP4 + 2,    "org.gnu.gdb.or1k.group4", "icache"},
 182         {"icblr"    , GROUP4 + 3,    "org.gnu.gdb.or1k.group4", "icache"},
 183
 184         {"maclo"    , GROUP5 + 0,    "org.gnu.gdb.or1k.group5", "mac"},
 185         {"machi"    , GROUP5 + 1,    "org.gnu.gdb.or1k.group5", "mac"},
 186
 187         {"dvr0"     , GROUP6 + 0,    "org.gnu.gdb.or1k.group6", "debug"},
 188         {"dvr1"     , GROUP6 + 1,    "org.gnu.gdb.or1k.group6", "debug"},
 189         {"dvr2"     , GROUP6 + 2,    "org.gnu.gdb.or1k.group6", "debug"},
 190         {"dvr3"     , GROUP6 + 3,    "org.gnu.gdb.or1k.group6", "debug"},
 191         {"dvr4"     , GROUP6 + 4,    "org.gnu.gdb.or1k.group6", "debug"},
 192         {"dvr5"     , GROUP6 + 5,    "org.gnu.gdb.or1k.group6", "debug"},
 193         {"dvr6"     , GROUP6 + 6,    "org.gnu.gdb.or1k.group6", "debug"},
 194         {"dvr7"     , GROUP6 + 7,    "org.gnu.gdb.or1k.group6", "debug"},
 195         {"dcr0"     , GROUP6 + 8,    "org.gnu.gdb.or1k.group6", "debug"},
 196         {"dcr1"     , GROUP6 + 9,    "org.gnu.gdb.or1k.group6", "debug"},
 197         {"dcr2"     , GROUP6 + 10,   "org.gnu.gdb.or1k.group6", "debug"},
 198         {"dcr3"     , GROUP6 + 11,   "org.gnu.gdb.or1k.group6", "debug"},
 199         {"dcr4"     , GROUP6 + 12,   "org.gnu.gdb.or1k.group6", "debug"},
 200         {"dcr5"     , GROUP6 + 13,   "org.gnu.gdb.or1k.group6", "debug"},
 201         {"dcr6"     , GROUP6 + 14,   "org.gnu.gdb.or1k.group6", "debug"},
 202         {"dcr7"     , GROUP6 + 15,   "org.gnu.gdb.or1k.group6", "debug"},
 203         {"dmr1"     , GROUP6 + 16,   "org.gnu.gdb.or1k.group6", "debug"},
 204         {"dmr2"     , GROUP6 + 17,   "org.gnu.gdb.or1k.group6", "debug"},
 205         {"dcwr0"    , GROUP6 + 18,   "org.gnu.gdb.or1k.group6", "debug"},
 206         {"dcwr1"    , GROUP6 + 19,   "org.gnu.gdb.or1k.group6", "debug"},
 207         {"dsr"      , GROUP6 + 20,   "org.gnu.gdb.or1k.group6", "debug"},
 208         {"drr"      , GROUP6 + 21,   "org.gnu.gdb.or1k.group6", "debug"},
 209
 210         {"pccr0"    , GROUP7 + 0,    "org.gnu.gdb.or1k.group7", "perf"},
 211         {"pccr1"    , GROUP7 + 1,    "org.gnu.gdb.or1k.group7", "perf"},
 212         {"pccr2"    , GROUP7 + 2,    "org.gnu.gdb.or1k.group7", "perf"},
 213         {"pccr3"    , GROUP7 + 3,    "org.gnu.gdb.or1k.group7", "perf"},
 214         {"pccr4"    , GROUP7 + 4,    "org.gnu.gdb.or1k.group7", "perf"},
 215         {"pccr5"    , GROUP7 + 5,    "org.gnu.gdb.or1k.group7", "perf"},
 216         {"pccr6"    , GROUP7 + 6,    "org.gnu.gdb.or1k.group7", "perf"},
 217         {"pccr7"    , GROUP7 + 7,    "org.gnu.gdb.or1k.group7", "perf"},
 218         {"pcmr0"    , GROUP7 + 8,    "org.gnu.gdb.or1k.group7", "perf"},
 219         {"pcmr1"    , GROUP7 + 9,    "org.gnu.gdb.or1k.group7", "perf"},
 220         {"pcmr2"    , GROUP7 + 10,   "org.gnu.gdb.or1k.group7", "perf"},
 221         {"pcmr3"    , GROUP7 + 11,   "org.gnu.gdb.or1k.group7", "perf"},
 222         {"pcmr4"    , GROUP7 + 12,   "org.gnu.gdb.or1k.group7", "perf"},
 223         {"pcmr5"    , GROUP7 + 13,   "org.gnu.gdb.or1k.group7", "perf"},
 224         {"pcmr6"    , GROUP7 + 14,   "org.gnu.gdb.or1k.group7", "perf"},
 225         {"pcmr7"    , GROUP7 + 15,   "org.gnu.gdb.or1k.group7", "perf"},
 226
 227         {"pmr"      , GROUP8 + 0,    "org.gnu.gdb.or1k.group8", "power"},
 228
 229         {"picmr"    , GROUP9 + 0,    "org.gnu.gdb.or1k.group9", "pic"},
 230         {"picsr"    , GROUP9 + 2,    "org.gnu.gdb.or1k.group9", "pic"},
 231
 232         {"ttmr"     , GROUP10 + 0,   "org.gnu.gdb.or1k.group10", "timer"},
 233         {"ttcr"     , GROUP10 + 1,   "org.gnu.gdb.or1k.group10", "timer"},
 234 };
 235
 236 static int or1k_add_reg(struct target *target, struct or1k_core_reg *new_reg)
 237 {
 238         struct or1k_common *or1k = target_to_or1k(target);
 239         int reg_list_size = or1k->nb_regs * sizeof(struct or1k_core_reg);
 240
 241         or1k_core_reg_list_arch_info = realloc(or1k_core_reg_list_arch_info,
 242                                 reg_list_size + sizeof(struct or1k_core_reg));
 243
 244         memcpy(&or1k_core_reg_list_arch_info[or1k->nb_regs], new_reg,
 245                 sizeof(struct or1k_core_reg));
 246
 247         or1k_core_reg_list_arch_info[or1k->nb_regs].list_num = or1k->nb_regs;
 248
 249         or1k->nb_regs++;
 250
 251         return ERROR_OK;
 252 }
 253
 254 static int or1k_create_reg_list(struct target *target)
 255 {
 256         struct or1k_common *or1k = target_to_or1k(target);
 257
 258         LOG_DEBUG("-");
 259
 260         or1k_core_reg_list_arch_info = malloc(ARRAY_SIZE(or1k_init_reg_list) *
 261                                        sizeof(struct or1k_core_reg));
 262
 263         for (int i = 0; i < (int)ARRAY_SIZE(or1k_init_reg_list); i++) {
 264                 or1k_core_reg_list_arch_info[i].name = or1k_init_reg_list[i].name;
 265                 or1k_core_reg_list_arch_info[i].spr_num = or1k_init_reg_list[i].spr_num;
 266                 or1k_core_reg_list_arch_info[i].group = or1k_init_reg_list[i].group;
 267                 or1k_core_reg_list_arch_info[i].feature = or1k_init_reg_list[i].feature;
 268                 or1k_core_reg_list_arch_info[i].list_num = i;
 269                 or1k_core_reg_list_arch_info[i].target = NULL;
 270                 or1k_core_reg_list_arch_info[i].or1k_common = NULL;
 271         }
 272
 273         or1k->nb_regs = ARRAY_SIZE(or1k_init_reg_list);
 274
 275         struct or1k_core_reg new_reg;
 276         new_reg.target = NULL;
 277         new_reg.or1k_common = NULL;
 278
 279         char name[32];
 280         for (int way = 0; way < 4; way++) {
 281                 for (int i = 0; i < 128; i++) {
 282
 283                         sprintf(name, "dtlbw%dmr%d", way, i);
 284                         new_reg.name = strdup(name);
 285                         new_reg.spr_num = GROUP1 + 512 + i + (way * 256);
 286                         new_reg.feature = "org.gnu.gdb.or1k.group1";
 287                         new_reg.group = "dmmu";
 288                         or1k_add_reg(target, &new_reg);
 289
 290                         sprintf(name, "dtlbw%dtr%d", way, i);
 291                         new_reg.name = strdup(name);
 292                         new_reg.spr_num = GROUP1 + 640 + i + (way * 256);
 293                         new_reg.feature = "org.gnu.gdb.or1k.group1";
 294                         new_reg.group = "dmmu";
 295                         or1k_add_reg(target, &new_reg);
 296
 297
 298                         sprintf(name, "itlbw%dmr%d", way, i);
 299                         new_reg.name = strdup(name);
 300                         new_reg.spr_num = GROUP2 + 512 + i + (way * 256);
 301                         new_reg.feature = "org.gnu.gdb.or1k.group2";
 302                         new_reg.group = "immu";
 303                         or1k_add_reg(target, &new_reg);
 304
 305
 306                         sprintf(name, "itlbw%dtr%d", way, i);
 307                         new_reg.name = strdup(name);
 308                         new_reg.spr_num = GROUP2 + 640 + i + (way * 256);
 309                         new_reg.feature = "org.gnu.gdb.or1k.group2";
 310                         new_reg.group = "immu";
 311                         or1k_add_reg(target, &new_reg);
 312
 313                 }
 314         }
 315
 316         return ERROR_OK;
 317 }
 318
 319 static int or1k_jtag_read_regs(struct or1k_common *or1k, uint32_t *regs)
 320 {
 321         struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
 322
 323         LOG_DEBUG("-");
 324
 325         return du_core->or1k_jtag_read_cpu(&or1k->jtag,
 326                         or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
 327                         regs + OR1K_REG_R0);
 328 }
 329
 330 static int or1k_jtag_write_regs(struct or1k_common *or1k, uint32_t *regs)
 331 {
 332         struct or1k_du *du_core = or1k_jtag_to_du(&or1k->jtag);
 333
 334         LOG_DEBUG("-");
 335
 336         return du_core->or1k_jtag_write_cpu(&or1k->jtag,
 337                         or1k->arch_info[OR1K_REG_R0].spr_num, OR1K_REG_R31 + 1,
 338                         &regs[OR1K_REG_R0]);
 339 }
 340
 341 static int or1k_save_context(struct target *target)
 342 {
 343         struct or1k_common *or1k = target_to_or1k(target);
 344         struct or1k_du *du_core = or1k_to_du(or1k);
 345         int regs_read = 0;
 346         int retval;
 347
 348         LOG_DEBUG("-");
 349
 350         for (int i = 0; i < OR1KNUMCOREREGS; i++) {
 351                 if (!or1k->core_cache->reg_list[i].valid) {
 352                         if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
 353                                 retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
 354                                                 or1k->arch_info[i].spr_num, 1,
 355                                                 &or1k->core_regs[i]);
 356                                 if (retval != ERROR_OK)
 357                                         return retval;
 358                         } else if (!regs_read) {
 359                                 /* read gpr registers at once (but only one time in this loop) */
 360                                 retval = or1k_jtag_read_regs(or1k, or1k->core_regs);
 361                                 if (retval != ERROR_OK)
 362                                         return retval;
 363                                 /* prevent next reads in this loop */
 364                                 regs_read = 1;
 365                         }
 366                         /* We've just updated the core_reg[i], now update
 367                            the core cache */
 368                         or1k_read_core_reg(target, i);
 369                 }
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 static int or1k_restore_context(struct target *target)
 376 {
 377         struct or1k_common *or1k = target_to_or1k(target);
 378         struct or1k_du *du_core = or1k_to_du(or1k);
 379         int reg_write = 0;
 380         int retval;
 381
 382         LOG_DEBUG("-");
 383
 384         for (int i = 0; i < OR1KNUMCOREREGS; i++) {
 385                 if (or1k->core_cache->reg_list[i].dirty) {
 386                         or1k_write_core_reg(target, i);
 387
 388                         if (i == OR1K_REG_PPC || i == OR1K_REG_NPC || i == OR1K_REG_SR) {
 389                                 retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 390                                                 or1k->arch_info[i].spr_num, 1,
 391                                                 &or1k->core_regs[i]);
 392                                 if (retval != ERROR_OK) {
 393                                         LOG_ERROR("Error while restoring context");
 394                                         return retval;
 395                                 }
 396                         } else
 397                                 reg_write = 1;
 398                 }
 399         }
 400
 401         if (reg_write) {
 402                 /* read gpr registers at once (but only one time in this loop) */
 403                 retval = or1k_jtag_write_regs(or1k, or1k->core_regs);
 404                 if (retval != ERROR_OK) {
 405                         LOG_ERROR("Error while restoring context");
 406                         return retval;
 407                 }
 408         }
 409
 410         return ERROR_OK;
 411 }
 412
 413 static int or1k_read_core_reg(struct target *target, int num)
 414 {
 415         struct or1k_common *or1k = target_to_or1k(target);
 416         struct or1k_du *du_core = or1k_to_du(or1k);
 417         uint32_t reg_value;
 418
 419         LOG_DEBUG("-");
 420
 421         if ((num < 0) || (num >= or1k->nb_regs))
 422                 return ERROR_COMMAND_SYNTAX_ERROR;
 423
 424         if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
 425                 reg_value = or1k->core_regs[num];
 426                 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
 427                 LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
 428                 or1k->core_cache->reg_list[num].valid = 1;
 429                 or1k->core_cache->reg_list[num].dirty = 0;
 430         } else {
 431                 /* This is an spr, always read value from HW */
 432                 int retval = du_core->or1k_jtag_read_cpu(&or1k->jtag,
 433                                                          or1k->arch_info[num].spr_num, 1, &reg_value);
 434                 if (retval != ERROR_OK) {
 435                         LOG_ERROR("Error while reading spr 0x%08" PRIx32, or1k->arch_info[num].spr_num);
 436                         return retval;
 437                 }
 438                 buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
 439                 LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
 440         }
 441
 442         return ERROR_OK;
 443 }
 444
 445 static int or1k_write_core_reg(struct target *target, int num)
 446 {
 447         struct or1k_common *or1k = target_to_or1k(target);
 448
 449         LOG_DEBUG("-");
 450
 451         if ((num < 0) || (num >= OR1KNUMCOREREGS))
 452                 return ERROR_COMMAND_SYNTAX_ERROR;
 453
 454         uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
 455         or1k->core_regs[num] = reg_value;
 456         LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
 457         or1k->core_cache->reg_list[num].valid = 1;
 458         or1k->core_cache->reg_list[num].dirty = 0;
 459
 460         return ERROR_OK;
 461 }
 462
 463 static int or1k_get_core_reg(struct reg *reg)
 464 {
 465         struct or1k_core_reg *or1k_reg = reg->arch_info;
 466         struct target *target = or1k_reg->target;
 467
 468         LOG_DEBUG("-");
 469
 470         if (target->state != TARGET_HALTED)
 471                 return ERROR_TARGET_NOT_HALTED;
 472
 473         return or1k_read_core_reg(target, or1k_reg->list_num);
 474 }
 475
 476 static int or1k_set_core_reg(struct reg *reg, uint8_t *buf)
 477 {
 478         struct or1k_core_reg *or1k_reg = reg->arch_info;
 479         struct target *target = or1k_reg->target;
 480         struct or1k_common *or1k = target_to_or1k(target);
 481         struct or1k_du *du_core = or1k_to_du(or1k);
 482         uint32_t value = buf_get_u32(buf, 0, 32);
 483
 484         LOG_DEBUG("-");
 485
 486         if (target->state != TARGET_HALTED)
 487                 return ERROR_TARGET_NOT_HALTED;
 488
 489         if (or1k_reg->list_num < OR1KNUMCOREREGS) {
 490                 buf_set_u32(reg->value, 0, 32, value);
 491                 reg->dirty = 1;
 492                 reg->valid = 1;
 493         } else {
 494                 /* This is an spr, write it to the HW */
 495                 int retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 496                                                           or1k_reg->spr_num, 1, &value);
 497                 if (retval != ERROR_OK) {
 498                         LOG_ERROR("Error while writing spr 0x%08" PRIx32, or1k_reg->spr_num);
 499                         return retval;
 500                 }
 501         }
 502
 503         return ERROR_OK;
 504 }
 505
 506 static const struct reg_arch_type or1k_reg_type = {
 507         .get = or1k_get_core_reg,
 508         .set = or1k_set_core_reg,
 509 };
 510
 511 static struct reg_cache *or1k_build_reg_cache(struct target *target)
 512 {
 513         struct or1k_common *or1k = target_to_or1k(target);
 514         struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 515         struct reg_cache *cache = malloc(sizeof(struct reg_cache));
 516         struct reg *reg_list = calloc(or1k->nb_regs, sizeof(struct reg));
 517         struct or1k_core_reg *arch_info =
 518                 malloc((or1k->nb_regs) * sizeof(struct or1k_core_reg));
 519         struct reg_feature *feature;
 520
 521         LOG_DEBUG("-");
 522
 523         /* Build the process context cache */
 524         cache->name = "OpenRISC 1000 registers";
 525         cache->next = NULL;
 526         cache->reg_list = reg_list;
 527         cache->num_regs = or1k->nb_regs;
 528         (*cache_p) = cache;
 529         or1k->core_cache = cache;
 530         or1k->arch_info = arch_info;
 531
 532         for (int i = 0; i < or1k->nb_regs; i++) {
 533                 arch_info[i] = or1k_core_reg_list_arch_info[i];
 534                 arch_info[i].target = target;
 535                 arch_info[i].or1k_common = or1k;
 536                 reg_list[i].name = or1k_core_reg_list_arch_info[i].name;
 537
 538                 feature = malloc(sizeof(struct reg_feature));
 539                 feature->name = or1k_core_reg_list_arch_info[i].feature;
 540                 reg_list[i].feature = feature;
 541
 542                 reg_list[i].group = or1k_core_reg_list_arch_info[i].group;
 543                 reg_list[i].size = 32;
 544                 reg_list[i].value = calloc(1, 4);
 545                 reg_list[i].dirty = 0;
 546                 reg_list[i].valid = 0;
 547                 reg_list[i].type = &or1k_reg_type;
 548                 reg_list[i].arch_info = &arch_info[i];
 549                 reg_list[i].number = i;
 550                 reg_list[i].exist = true;
 551         }
 552
 553         return cache;
 554 }
 555
 556 static int or1k_debug_entry(struct target *target)
 557 {
 558         LOG_DEBUG("-");
 559
 560         int retval = or1k_save_context(target);
 561         if (retval != ERROR_OK) {
 562                 LOG_ERROR("Error while calling or1k_save_context");
 563                 return retval;
 564         }
 565
 566         struct or1k_common *or1k = target_to_or1k(target);
 567         uint32_t addr = or1k->core_regs[OR1K_REG_NPC];
 568
 569         if (breakpoint_find(target, addr))
 570                 /* Halted on a breakpoint, step back to permit executing the instruction there */
 571                 retval = or1k_set_core_reg(&or1k->core_cache->reg_list[OR1K_REG_NPC],
 572                                            (uint8_t *)&addr);
 573
 574         return retval;
 575 }
 576
 577 static int or1k_halt(struct target *target)
 578 {
 579         struct or1k_common *or1k = target_to_or1k(target);
 580         struct or1k_du *du_core = or1k_to_du(or1k);
 581
 582         LOG_DEBUG("target->state: %s",
 583                   target_state_name(target));
 584
 585         if (target->state == TARGET_HALTED) {
 586                 LOG_DEBUG("Target was already halted");
 587                 return ERROR_OK;
 588         }
 589
 590         if (target->state == TARGET_UNKNOWN)
 591                 LOG_WARNING("Target was in unknown state when halt was requested");
 592
 593         if (target->state == TARGET_RESET) {
 594                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) &&
 595                     jtag_get_srst()) {
 596                         LOG_ERROR("Can't request a halt while in reset if nSRST pulls nTRST");
 597                         return ERROR_TARGET_FAILURE;
 598                 } else {
 599                         target->debug_reason = DBG_REASON_DBGRQ;
 600                         return ERROR_OK;
 601                 }
 602         }
 603
 604         int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
 605         if (retval != ERROR_OK) {
 606                 LOG_ERROR("Impossible to stall the CPU");
 607                 return retval;
 608         }
 609
 610         target->debug_reason = DBG_REASON_DBGRQ;
 611
 612         return ERROR_OK;
 613 }
 614
 615 static int or1k_is_cpu_running(struct target *target, int *running)
 616 {
 617         struct or1k_common *or1k = target_to_or1k(target);
 618         struct or1k_du *du_core = or1k_to_du(or1k);
 619         int retval;
 620         int tries = 0;
 621         const int RETRIES_MAX = 5;
 622
 623         /* Have a retry loop to determine of the CPU is running.
 624            If target has been hard reset for any reason, it might take a couple
 625            of goes before it's ready again.
 626         */
 627         while (tries < RETRIES_MAX) {
 628
 629                 tries++;
 630
 631                 retval = du_core->or1k_is_cpu_running(&or1k->jtag, running);
 632                 if (retval != ERROR_OK) {
 633                         LOG_WARNING("Debug IF CPU control reg read failure.");
 634                         /* Try once to restart the JTAG infrastructure -
 635                            quite possibly the board has just been reset. */
 636                         LOG_WARNING("Resetting JTAG TAP state and reconnectiong to debug IF.");
 637                         du_core->or1k_jtag_init(&or1k->jtag);
 638
 639                         LOG_WARNING("...attempt %d of %d", tries, RETRIES_MAX);
 640
 641                         alive_sleep(2);
 642
 643                         continue;
 644                 } else
 645                         return ERROR_OK;
 646         }
 647
 648         LOG_ERROR("Could not re-establish communication with target");
 649         return retval;
 650 }
 651
 652 static int or1k_poll(struct target *target)
 653 {
 654         int retval;
 655         int running;
 656
 657         retval = or1k_is_cpu_running(target, &running);
 658         if (retval != ERROR_OK) {
 659                 LOG_ERROR("Error while calling or1k_is_cpu_running");
 660                 return retval;
 661         }
 662
 663         /* check for processor halted */
 664         if (!running) {
 665                 /* It's actually stalled, so update our software's state */
 666                 if ((target->state == TARGET_RUNNING) ||
 667                     (target->state == TARGET_RESET)) {
 668
 669                         target->state = TARGET_HALTED;
 670
 671                         retval = or1k_debug_entry(target);
 672                         if (retval != ERROR_OK) {
 673                                 LOG_ERROR("Error while calling or1k_debug_entry");
 674                                 return retval;
 675                         }
 676
 677                         target_call_event_callbacks(target,
 678                                                     TARGET_EVENT_HALTED);
 679                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 680                         target->state = TARGET_HALTED;
 681
 682                         retval = or1k_debug_entry(target);
 683                         if (retval != ERROR_OK) {
 684                                 LOG_ERROR("Error while calling or1k_debug_entry");
 685                                 return retval;
 686                         }
 687
 688                         target_call_event_callbacks(target,
 689                                                     TARGET_EVENT_DEBUG_HALTED);
 690                 }
 691         } else { /* ... target is running */
 692
 693                 /* If target was supposed to be stalled, stall it again */
 694                 if  (target->state == TARGET_HALTED) {
 695
 696                         target->state = TARGET_RUNNING;
 697
 698                         retval = or1k_halt(target);
 699                         if (retval != ERROR_OK) {
 700                                 LOG_ERROR("Error while calling or1k_halt");
 701                                 return retval;
 702                         }
 703
 704                         retval = or1k_debug_entry(target);
 705                         if (retval != ERROR_OK) {
 706                                 LOG_ERROR("Error while calling or1k_debug_entry");
 707                                 return retval;
 708                         }
 709
 710                         target_call_event_callbacks(target,
 711                                                     TARGET_EVENT_DEBUG_HALTED);
 712                 }
 713
 714                 target->state = TARGET_RUNNING;
 715
 716         }
 717
 718         return ERROR_OK;
 719 }
 720
 721 static int or1k_assert_reset(struct target *target)
 722 {
 723         struct or1k_common *or1k = target_to_or1k(target);
 724         struct or1k_du *du_core = or1k_to_du(or1k);
 725
 726         LOG_DEBUG("-");
 727
 728         int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_RESET);
 729         if (retval != ERROR_OK) {
 730                 LOG_ERROR("Error while asserting RESET");
 731                 return retval;
 732         }
 733
 734         return ERROR_OK;
 735 }
 736
 737 static int or1k_deassert_reset(struct target *target)
 738 {
 739         struct or1k_common *or1k = target_to_or1k(target);
 740         struct or1k_du *du_core = or1k_to_du(or1k);
 741
 742         LOG_DEBUG("-");
 743
 744         int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_NOT_RESET);
 745         if (retval != ERROR_OK) {
 746                 LOG_ERROR("Error while desasserting RESET");
 747                 return retval;
 748         }
 749
 750         return ERROR_OK;
 751 }
 752
 753 static int or1k_soft_reset_halt(struct target *target)
 754 {
 755         struct or1k_common *or1k = target_to_or1k(target);
 756         struct or1k_du *du_core = or1k_to_du(or1k);
 757
 758         LOG_DEBUG("-");
 759
 760         int retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_STALL);
 761         if (retval != ERROR_OK) {
 762                 LOG_ERROR("Error while stalling the CPU");
 763                 return retval;
 764         }
 765
 766         retval = or1k_assert_reset(target);
 767         if (retval != ERROR_OK)
 768                 return retval;
 769
 770         retval = or1k_deassert_reset(target);
 771         if (retval != ERROR_OK)
 772                 return retval;
 773
 774         return ERROR_OK;
 775 }
 776
 777 static bool is_any_soft_breakpoint(struct target *target)
 778 {
 779         struct breakpoint *breakpoint = target->breakpoints;
 780
 781         LOG_DEBUG("-");
 782
 783         while (breakpoint)
 784                 if (breakpoint->type == BKPT_SOFT)
 785                         return true;
 786
 787         return false;
 788 }
 789
 790 static int or1k_resume_or_step(struct target *target, int current,
 791                                uint32_t address, int handle_breakpoints,
 792                                int debug_execution, int step)
 793 {
 794         struct or1k_common *or1k = target_to_or1k(target);
 795         struct or1k_du *du_core = or1k_to_du(or1k);
 796         struct breakpoint *breakpoint = NULL;
 797         uint32_t resume_pc;
 798         uint32_t debug_reg_list[OR1K_DEBUG_REG_NUM];
 799
 800         LOG_DEBUG("Addr: 0x%" PRIx32 ", stepping: %s, handle breakpoints %s\n",
 801                   address, step ? "yes" : "no", handle_breakpoints ? "yes" : "no");
 802
 803         if (target->state != TARGET_HALTED) {
 804                 LOG_ERROR("Target not halted");
 805                 return ERROR_TARGET_NOT_HALTED;
 806         }
 807
 808         if (!debug_execution)
 809                 target_free_all_working_areas(target);
 810
 811         /* current ? continue on current pc : continue at <address> */
 812         if (!current)
 813                 buf_set_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value, 0,
 814                             32, address);
 815
 816         int retval = or1k_restore_context(target);
 817         if (retval != ERROR_OK) {
 818                 LOG_ERROR("Error while calling or1k_restore_context");
 819                 return retval;
 820         }
 821
 822         /* read debug registers (starting from DMR1 register) */
 823         retval = du_core->or1k_jtag_read_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
 824                                              OR1K_DEBUG_REG_NUM, debug_reg_list);
 825         if (retval != ERROR_OK) {
 826                 LOG_ERROR("Error while reading debug registers");
 827                 return retval;
 828         }
 829
 830         /* Clear Debug Reason Register (DRR) */
 831         debug_reg_list[OR1K_DEBUG_REG_DRR] = 0;
 832
 833         /* Clear watchpoint break generation in Debug Mode Register 2 (DMR2) */
 834         debug_reg_list[OR1K_DEBUG_REG_DMR2] &= ~OR1K_DMR2_WGB;
 835         if (step)
 836                 /* Set the single step trigger in Debug Mode Register 1 (DMR1) */
 837                 debug_reg_list[OR1K_DEBUG_REG_DMR1] |= OR1K_DMR1_ST | OR1K_DMR1_BT;
 838         else
 839                 /* Clear the single step trigger in Debug Mode Register 1 (DMR1) */
 840                 debug_reg_list[OR1K_DEBUG_REG_DMR1] &= ~(OR1K_DMR1_ST | OR1K_DMR1_BT);
 841
 842         /* Set traps to be handled by the debug unit in the Debug Stop
 843            Register (DSR). Check if we have any software breakpoints in
 844            place before setting this value - the kernel, for instance,
 845            relies on l.trap instructions not stalling the processor ! */
 846         if (is_any_soft_breakpoint(target) == true)
 847                 debug_reg_list[OR1K_DEBUG_REG_DSR] |= OR1K_DSR_TE;
 848
 849         /* Write debug registers (starting from DMR1 register) */
 850         retval = du_core->or1k_jtag_write_cpu(&or1k->jtag, OR1K_DMR1_CPU_REG_ADD,
 851                                               OR1K_DEBUG_REG_NUM, debug_reg_list);
 852         if (retval != ERROR_OK) {
 853                 LOG_ERROR("Error while writing back debug registers");
 854                 return retval;
 855         }
 856
 857         resume_pc = buf_get_u32(or1k->core_cache->reg_list[OR1K_REG_NPC].value,
 858                                 0, 32);
 859
 860         /* The front-end may request us not to handle breakpoints */
 861         if (handle_breakpoints) {
 862                 /* Single step past breakpoint at current address */
 863                 breakpoint = breakpoint_find(target, resume_pc);
 864                 if (breakpoint) {
 865                         LOG_DEBUG("Unset breakpoint at 0x%08" PRIx32, breakpoint->address);
 866                         retval = or1k_remove_breakpoint(target, breakpoint);
 867                         if (retval != ERROR_OK)
 868                                 return retval;
 869                 }
 870         }
 871
 872         /* Unstall time */
 873         retval = du_core->or1k_cpu_stall(&or1k->jtag, CPU_UNSTALL);
 874         if (retval != ERROR_OK) {
 875                 LOG_ERROR("Error while unstalling the CPU");
 876                 return retval;
 877         }
 878
 879         if (step)
 880                 target->debug_reason = DBG_REASON_SINGLESTEP;
 881         else
 882                 target->debug_reason = DBG_REASON_NOTHALTED;
 883
 884         /* Registers are now invalid */
 885         register_cache_invalidate(or1k->core_cache);
 886
 887         if (!debug_execution) {
 888                 target->state = TARGET_RUNNING;
 889                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 890                 LOG_DEBUG("Target resumed at 0x%08" PRIx32, resume_pc);
 891         } else {
 892                 target->state = TARGET_DEBUG_RUNNING;
 893                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 894                 LOG_DEBUG("Target debug resumed at 0x%08" PRIx32, resume_pc);
 895         }
 896
 897         return ERROR_OK;
 898 }
 899
 900 static int or1k_resume(struct target *target, int current,
 901                 uint32_t address, int handle_breakpoints, int debug_execution)
 902 {
 903         return or1k_resume_or_step(target, current, address,
 904                                    handle_breakpoints,
 905                                    debug_execution,
 906                                    NO_SINGLE_STEP);
 907 }
 908
 909 static int or1k_step(struct target *target, int current,
 910                      uint32_t address, int handle_breakpoints)
 911 {
 912         return or1k_resume_or_step(target, current, address,
 913                                    handle_breakpoints,
 914                                    0,
 915                                    SINGLE_STEP);
 916
 917 }
 918
 919 static int or1k_add_breakpoint(struct target *target,
 920                                struct breakpoint *breakpoint)
 921 {
 922         struct or1k_common *or1k = target_to_or1k(target);
 923         struct or1k_du *du_core = or1k_to_du(or1k);
 924         uint8_t data;
 925
 926         LOG_DEBUG("Adding breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
 927                   breakpoint->address, breakpoint->length, breakpoint->type,
 928                   breakpoint->set, breakpoint->unique_id);
 929
 930         /* Only support SW breakpoints for now. */
 931         if (breakpoint->type == BKPT_HARD)
 932                 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
 933
 934         /* Read and save the instruction */
 935         int retval = du_core->or1k_jtag_read_memory(&or1k->jtag,
 936                                          breakpoint->address,
 937                                          4,
 938                                          1,
 939                                          &data);
 940         if (retval != ERROR_OK) {
 941                 LOG_ERROR("Error while reading the instruction at 0x%08" PRIx32,
 942                            breakpoint->address);
 943                 return retval;
 944         }
 945
 946         if (breakpoint->orig_instr != NULL)
 947                 free(breakpoint->orig_instr);
 948
 949         breakpoint->orig_instr = malloc(breakpoint->length);
 950         memcpy(breakpoint->orig_instr, &data, breakpoint->length);
 951
 952         /* Sub in the OR1K trap instruction */
 953         uint8_t or1k_trap_insn[4];
 954         target_buffer_set_u32(target, or1k_trap_insn, OR1K_TRAP_INSTR);
 955         retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
 956                                           breakpoint->address,
 957                                           4,
 958                                           1,
 959                                           or1k_trap_insn);
 960
 961         if (retval != ERROR_OK) {
 962                 LOG_ERROR("Error while writing OR1K_TRAP_INSTR at 0x%08" PRIx32,
 963                            breakpoint->address);
 964                 return retval;
 965         }
 966
 967         /* invalidate instruction cache */
 968         retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
 969                         OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
 970         if (retval != ERROR_OK) {
 971                 LOG_ERROR("Error while invalidating the ICACHE");
 972                 return retval;
 973         }
 974
 975         return ERROR_OK;
 976 }
 977
 978 static int or1k_remove_breakpoint(struct target *target,
 979                                   struct breakpoint *breakpoint)
 980 {
 981         struct or1k_common *or1k = target_to_or1k(target);
 982         struct or1k_du *du_core = or1k_to_du(or1k);
 983
 984         LOG_DEBUG("Removing breakpoint: addr 0x%08" PRIx32 ", len %d, type %d, set: %d, id: %" PRId32,
 985                   breakpoint->address, breakpoint->length, breakpoint->type,
 986                   breakpoint->set, breakpoint->unique_id);
 987
 988         /* Only support SW breakpoints for now. */
 989         if (breakpoint->type == BKPT_HARD)
 990                 LOG_ERROR("HW breakpoints not supported for now. Doing SW breakpoint.");
 991
 992         /* Replace the removed instruction */
 993         int retval = du_core->or1k_jtag_write_memory(&or1k->jtag,
 994                                           breakpoint->address,
 995                                           4,
 996                                           1,
 997                                           breakpoint->orig_instr);
 998
 999         if (retval != ERROR_OK) {
1000                 LOG_ERROR("Error while writing back the instruction at 0x%08" PRIx32,
1001                            breakpoint->address);
1002                 return retval;
1003         }
1004
1005         /* invalidate instruction cache */
1006         retval = du_core->or1k_jtag_write_cpu(&or1k->jtag,
1007                         OR1K_ICBIR_CPU_REG_ADD, 1, &breakpoint->address);
1008         if (retval != ERROR_OK) {
1009                 LOG_ERROR("Error while invalidating the ICACHE");
1010                 return retval;
1011         }
1012
1013         return ERROR_OK;
1014 }
1015
1016 static int or1k_add_watchpoint(struct target *target,
1017                                struct watchpoint *watchpoint)
1018 {
1019         LOG_ERROR("%s: implement me", __func__);
1020         return ERROR_OK;
1021 }
1022
1023 static int or1k_remove_watchpoint(struct target *target,
1024                                   struct watchpoint *watchpoint)
1025 {
1026         LOG_ERROR("%s: implement me", __func__);
1027         return ERROR_OK;
1028 }
1029
1030 static int or1k_read_memory(struct target *target, uint32_t address,
1031                 uint32_t size, uint32_t count, uint8_t *buffer)
1032 {
1033         struct or1k_common *or1k = target_to_or1k(target);
1034         struct or1k_du *du_core = or1k_to_du(or1k);
1035
1036         LOG_DEBUG("Read memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1037
1038         if (target->state != TARGET_HALTED) {
1039                 LOG_ERROR("Target not halted");
1040                 return ERROR_TARGET_NOT_HALTED;
1041         }
1042
1043         /* Sanitize arguments */
1044         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1045                 LOG_ERROR("Bad arguments");
1046                 return ERROR_COMMAND_SYNTAX_ERROR;
1047         }
1048
1049         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1050                 LOG_ERROR("Can't handle unaligned memory access");
1051                 return ERROR_TARGET_UNALIGNED_ACCESS;
1052         }
1053
1054         return du_core->or1k_jtag_read_memory(&or1k->jtag, address, size, count, buffer);
1055 }
1056
1057 static int or1k_write_memory(struct target *target, uint32_t address,
1058                 uint32_t size, uint32_t count, const uint8_t *buffer)
1059 {
1060         struct or1k_common *or1k = target_to_or1k(target);
1061         struct or1k_du *du_core = or1k_to_du(or1k);
1062
1063         LOG_DEBUG("Write memory at 0x%08" PRIx32 ", size: %" PRIu32 ", count: 0x%08" PRIx32, address, size, count);
1064
1065         if (target->state != TARGET_HALTED) {
1066                 LOG_WARNING("Target not halted");
1067                 return ERROR_TARGET_NOT_HALTED;
1068         }
1069
1070         /* Sanitize arguments */
1071         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !buffer) {
1072                 LOG_ERROR("Bad arguments");
1073                 return ERROR_COMMAND_SYNTAX_ERROR;
1074         }
1075
1076         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) {
1077                 LOG_ERROR("Can't handle unaligned memory access");
1078                 return ERROR_TARGET_UNALIGNED_ACCESS;
1079         }
1080
1081         return du_core->or1k_jtag_write_memory(&or1k->jtag, address, size, count, buffer);
1082 }
1083
1084 static int or1k_init_target(struct command_context *cmd_ctx,
1085                 struct target *target)
1086 {
1087         struct or1k_common *or1k = target_to_or1k(target);
1088         struct or1k_du *du_core = or1k_to_du(or1k);
1089         struct or1k_jtag *jtag = &or1k->jtag;
1090
1091         if (du_core == NULL) {
1092                 LOG_ERROR("No debug unit selected");
1093                 return ERROR_FAIL;
1094         }
1095
1096         if (jtag->tap_ip == NULL) {
1097                 LOG_ERROR("No tap selected");
1098                 return ERROR_FAIL;
1099         }
1100
1101         or1k->jtag.tap = target->tap;
1102         or1k->jtag.or1k_jtag_inited = 0;
1103         or1k->jtag.or1k_jtag_module_selected = -1;
1104         or1k->jtag.target = target;
1105
1106         or1k_build_reg_cache(target);
1107
1108         return ERROR_OK;
1109 }
1110
1111 static int or1k_target_create(struct target *target, Jim_Interp *interp)
1112 {
1113         if (target->tap == NULL)
1114                 return ERROR_FAIL;
1115
1116         struct or1k_common *or1k = calloc(1, sizeof(struct or1k_common));
1117
1118         target->arch_info = or1k;
1119
1120         or1k_create_reg_list(target);
1121
1122         or1k_tap_vjtag_register();
1123         or1k_tap_xilinx_bscan_register();
1124         or1k_tap_mohor_register();
1125
1126         or1k_du_adv_register();
1127
1128         return ERROR_OK;
1129 }
1130
1131 static int or1k_examine(struct target *target)
1132 {
1133         struct or1k_common *or1k = target_to_or1k(target);
1134         struct or1k_du *du_core = or1k_to_du(or1k);
1135
1136         if (!target_was_examined(target)) {
1137
1138                 target_set_examined(target);
1139
1140                 int running;
1141
1142                 int retval = du_core->or1k_is_cpu_running(&or1k->jtag, &running);
1143                 if (retval != ERROR_OK) {
1144                         LOG_ERROR("Couldn't read the CPU state");
1145                         return retval;
1146                 } else {
1147                         if (running)
1148                                 target->state = TARGET_RUNNING;
1149                         else {
1150                                 LOG_DEBUG("Target is halted");
1151
1152                                 /* This is the first time we examine the target,
1153                                  * it is stalled and we don't know why. Let's
1154                                  * assume this is because of a debug reason.
1155                                  */
1156                                 if (target->state == TARGET_UNKNOWN)
1157                                         target->debug_reason = DBG_REASON_DBGRQ;
1158
1159                                 target->state = TARGET_HALTED;
1160                         }
1161                 }
1162         }
1163
1164         return ERROR_OK;
1165 }
1166
1167 static int or1k_arch_state(struct target *target)
1168 {
1169         return ERROR_OK;
1170 }
1171
1172 static int or1k_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
1173                           int *reg_list_size, enum target_register_class reg_class)
1174 {
1175         struct or1k_common *or1k = target_to_or1k(target);
1176
1177         if (reg_class == REG_CLASS_GENERAL) {
1178                 /* We will have this called whenever GDB connects. */
1179                 int retval = or1k_save_context(target);
1180                 if (retval != ERROR_OK) {
1181                         LOG_ERROR("Error while calling or1k_save_context");
1182                         return retval;
1183                 }
1184                 *reg_list_size = OR1KNUMCOREREGS;
1185                 /* this is free()'d back in gdb_server.c's gdb_get_register_packet() */
1186                 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1187
1188                 for (int i = 0; i < OR1KNUMCOREREGS; i++)
1189                         (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1190         } else {
1191                 *reg_list_size = or1k->nb_regs;
1192                 *reg_list = malloc((*reg_list_size) * sizeof(struct reg *));
1193
1194                 for (int i = 0; i < or1k->nb_regs; i++)
1195                         (*reg_list)[i] = &or1k->core_cache->reg_list[i];
1196         }
1197
1198         return ERROR_OK;
1199
1200 }
1201
1202 int or1k_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info)
1203 {
1204         return ERROR_FAIL;
1205 }
1206
1207 static int or1k_checksum_memory(struct target *target, uint32_t address,
1208                 uint32_t count, uint32_t *checksum) {
1209
1210         return ERROR_FAIL;
1211 }
1212
1213 COMMAND_HANDLER(or1k_tap_select_command_handler)
1214 {
1215         struct target *target = get_current_target(CMD_CTX);
1216         struct or1k_common *or1k = target_to_or1k(target);
1217         struct or1k_jtag *jtag = &or1k->jtag;
1218         struct or1k_tap_ip *or1k_tap;
1219
1220         if (CMD_ARGC != 1)
1221                 return ERROR_COMMAND_SYNTAX_ERROR;
1222
1223         list_for_each_entry(or1k_tap, &tap_list, list) {
1224                 if (or1k_tap->name) {
1225                         if (!strcmp(CMD_ARGV[0], or1k_tap->name)) {
1226                                 jtag->tap_ip = or1k_tap;
1227                                 LOG_INFO("%s tap selected", or1k_tap->name);
1228                                 return ERROR_OK;
1229                         }
1230                 }
1231         }
1232
1233         LOG_ERROR("%s unknown, no tap selected", CMD_ARGV[0]);
1234         return ERROR_COMMAND_SYNTAX_ERROR;
1235 }
1236
1237 COMMAND_HANDLER(or1k_tap_list_command_handler)
1238 {
1239         struct or1k_tap_ip *or1k_tap;
1240
1241         if (CMD_ARGC != 0)
1242                 return ERROR_COMMAND_SYNTAX_ERROR;
1243
1244         list_for_each_entry(or1k_tap, &tap_list, list) {
1245                 if (or1k_tap->name)
1246                         command_print(CMD_CTX, "%s", or1k_tap->name);
1247         }
1248
1249         return ERROR_OK;
1250 }
1251
1252 COMMAND_HANDLER(or1k_du_select_command_handler)
1253 {
1254         struct target *target = get_current_target(CMD_CTX);
1255         struct or1k_common *or1k = target_to_or1k(target);
1256         struct or1k_jtag *jtag = &or1k->jtag;
1257         struct or1k_du *or1k_du;
1258
1259         if (CMD_ARGC > 2)
1260                 return ERROR_COMMAND_SYNTAX_ERROR;
1261
1262         list_for_each_entry(or1k_du, &du_list, list) {
1263                 if (or1k_du->name) {
1264                         if (!strcmp(CMD_ARGV[0], or1k_du->name)) {
1265                                 jtag->du_core = or1k_du;
1266                                 LOG_INFO("%s debug unit selected", or1k_du->name);
1267
1268                                 if (CMD_ARGC == 2) {
1269                                         int options;
1270                                         COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], options);
1271                                         or1k_du->options = options;
1272                                         LOG_INFO("Option %x is passed to %s debug unit"
1273                                                  , options, or1k_du->name);
1274                                 }
1275
1276                                 return ERROR_OK;
1277                         }
1278                 }
1279         }
1280
1281         LOG_ERROR("%s unknown, no debug unit selected", CMD_ARGV[0]);
1282         return ERROR_COMMAND_SYNTAX_ERROR;
1283 }
1284
1285 COMMAND_HANDLER(or1k_du_list_command_handler)
1286 {
1287         struct or1k_du *or1k_du;
1288
1289         if (CMD_ARGC != 0)
1290                 return ERROR_COMMAND_SYNTAX_ERROR;
1291
1292         list_for_each_entry(or1k_du, &du_list, list) {
1293                 if (or1k_du->name)
1294                         command_print(CMD_CTX, "%s", or1k_du->name);
1295         }
1296
1297         return ERROR_OK;
1298 }
1299
1300 COMMAND_HANDLER(or1k_addreg_command_handler)
1301 {
1302         struct target *target = get_current_target(CMD_CTX);
1303         struct or1k_core_reg new_reg;
1304
1305         if (CMD_ARGC != 4)
1306                 return ERROR_COMMAND_SYNTAX_ERROR;
1307
1308         new_reg.target = NULL;
1309         new_reg.or1k_common = NULL;
1310
1311         uint32_t addr;
1312         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], addr);
1313
1314         new_reg.name = strdup(CMD_ARGV[0]);
1315         new_reg.spr_num = addr;
1316         new_reg.feature = strdup(CMD_ARGV[2]);
1317         new_reg.group = strdup(CMD_ARGV[3]);
1318
1319         or1k_add_reg(target, &new_reg);
1320
1321         LOG_DEBUG("Add reg \"%s\" @ 0x%08" PRIx32 ", group \"%s\", feature \"%s\"",
1322                   new_reg.name, addr, new_reg.group, new_reg.feature);
1323
1324         return ERROR_OK;
1325 }
1326
1327 static const struct command_registration or1k_hw_ip_command_handlers[] = {
1328         {
1329                 "tap_select",
1330                 .handler = or1k_tap_select_command_handler,
1331                 .mode = COMMAND_ANY,
1332                 .usage = "tap_select name",
1333                 .help = "Select the TAP core to use",
1334         },
1335         {
1336                 "tap_list",
1337                 .handler = or1k_tap_list_command_handler,
1338                 .mode = COMMAND_ANY,
1339                 .usage = "tap_list",
1340                 .help = "Display available TAP core",
1341         },
1342         {
1343                 "du_select",
1344                 .handler = or1k_du_select_command_handler,
1345                 .mode = COMMAND_ANY,
1346                 .usage = "du_select name",
1347                 .help = "Select the Debug Unit core to use",
1348         },
1349         {
1350                 "du_list",
1351                 .handler = or1k_du_list_command_handler,
1352                 .mode = COMMAND_ANY,
1353                 .usage = "select_tap name",
1354                 .help = "Display available Debug Unit core",
1355         },
1356         COMMAND_REGISTRATION_DONE
1357 };
1358
1359 static const struct command_registration or1k_reg_command_handlers[] = {
1360         {
1361                 "addreg",
1362                 .handler = or1k_addreg_command_handler,
1363                 .mode = COMMAND_ANY,
1364                 .usage = "addreg name addr feature group",
1365                 .help = "Add a register to the register list",
1366         },
1367         COMMAND_REGISTRATION_DONE
1368 };
1369
1370 static const struct command_registration or1k_command_handlers[] = {
1371         {
1372                 .chain = or1k_reg_command_handlers,
1373         },
1374         {
1375                 .chain = or1k_hw_ip_command_handlers,
1376         },
1377         COMMAND_REGISTRATION_DONE
1378 };
1379
1380
1381 struct target_type or1k_target = {
1382         .name = "or1k",
1383
1384         .poll = or1k_poll,
1385         .arch_state = or1k_arch_state,
1386
1387         .target_request_data = NULL,
1388
1389         .halt = or1k_halt,
1390         .resume = or1k_resume,
1391         .step = or1k_step,
1392
1393         .assert_reset = or1k_assert_reset,
1394         .deassert_reset = or1k_deassert_reset,
1395         .soft_reset_halt = or1k_soft_reset_halt,
1396
1397         .get_gdb_reg_list = or1k_get_gdb_reg_list,
1398
1399         .read_memory = or1k_read_memory,
1400         .write_memory = or1k_write_memory,
1401         .checksum_memory = or1k_checksum_memory,
1402
1403         .commands = or1k_command_handlers,
1404         .add_breakpoint = or1k_add_breakpoint,
1405         .remove_breakpoint = or1k_remove_breakpoint,
1406         .add_watchpoint = or1k_add_watchpoint,
1407         .remove_watchpoint = or1k_remove_watchpoint,
1408
1409         .target_create = or1k_target_create,
1410         .init_target = or1k_init_target,
1411         .examine = or1k_examine,
1412
1413         .get_gdb_fileio_info = or1k_get_gdb_fileio_info,
1414 };