git.gag.com Git - fw/openocd/blob - src/target/nds32_cmd.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2013 Andes Technology                                   *
   5  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
   6  ***************************************************************************/
   7
   8 #ifdef HAVE_CONFIG_H
   9 #include "config.h"
  10 #endif
  11
  12 #include <helper/command.h>
  13 #include "nds32.h"
  14 #include "nds32_aice.h"
  15 #include "nds32_disassembler.h"
  16
  17 extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
  18 extern uint32_t nds32_edm_ops_num;
  19
  20 static const char *const nds_memory_access_name[] = {
  21         "BUS",
  22         "CPU",
  23 };
  24
  25 static const char *const nds_memory_select_name[] = {
  26         "AUTO",
  27         "MEM",
  28         "ILM",
  29         "DLM",
  30 };
  31
  32 COMMAND_HANDLER(handle_nds32_dssim_command)
  33 {
  34         struct target *target = get_current_target(CMD_CTX);
  35         struct nds32 *nds32 = target_to_nds32(target);
  36
  37         if (!is_nds32(nds32)) {
  38                 command_print(CMD, "current target isn't an Andes core");
  39                 return ERROR_FAIL;
  40         }
  41
  42         if (CMD_ARGC > 0) {
  43                 if (strcmp(CMD_ARGV[0], "on") == 0)
  44                         nds32->step_isr_enable = true;
  45                 if (strcmp(CMD_ARGV[0], "off") == 0)
  46                         nds32->step_isr_enable = false;
  47         }
  48
  49         command_print(CMD, "%s: $INT_MASK.DSSIM: %d", target_name(target),
  50                         nds32->step_isr_enable);
  51
  52         return ERROR_OK;
  53 }
  54
  55 COMMAND_HANDLER(handle_nds32_memory_access_command)
  56 {
  57         struct target *target = get_current_target(CMD_CTX);
  58         struct nds32 *nds32 = target_to_nds32(target);
  59         struct aice_port_s *aice = target_to_aice(target);
  60         struct nds32_memory *memory = &(nds32->memory);
  61
  62         if (!is_nds32(nds32)) {
  63                 command_print(CMD, "current target isn't an Andes core");
  64                 return ERROR_FAIL;
  65         }
  66
  67         if (CMD_ARGC > 0) {
  68                 if (strcmp(CMD_ARGV[0], "bus") == 0)
  69                         memory->access_channel = NDS_MEMORY_ACC_BUS;
  70                 else if (strcmp(CMD_ARGV[0], "cpu") == 0)
  71                         memory->access_channel = NDS_MEMORY_ACC_CPU;
  72                 else /* default access channel is NDS_MEMORY_ACC_CPU */
  73                         memory->access_channel = NDS_MEMORY_ACC_CPU;
  74
  75                 LOG_DEBUG("memory access channel is changed to %s",
  76                                 nds_memory_access_name[memory->access_channel]);
  77
  78                 aice_memory_access(aice, memory->access_channel);
  79         } else {
  80                 command_print(CMD, "%s: memory access channel: %s",
  81                                 target_name(target),
  82                                 nds_memory_access_name[memory->access_channel]);
  83         }
  84
  85         return ERROR_OK;
  86 }
  87
  88 COMMAND_HANDLER(handle_nds32_memory_mode_command)
  89 {
  90         struct target *target = get_current_target(CMD_CTX);
  91         struct nds32 *nds32 = target_to_nds32(target);
  92         struct aice_port_s *aice = target_to_aice(target);
  93
  94         if (!is_nds32(nds32)) {
  95                 command_print(CMD, "current target isn't an Andes core");
  96                 return ERROR_FAIL;
  97         }
  98
  99         if (CMD_ARGC > 0) {
 100
 101                 if (nds32->edm.access_control == false) {
 102                         command_print(CMD, "%s does not support ACC_CTL. "
 103                                         "Set memory mode to MEMORY", target_name(target));
 104                         nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
 105                 } else if (nds32->edm.direct_access_local_memory == false) {
 106                         command_print(CMD, "%s does not support direct access "
 107                                         "local memory. Set memory mode to MEMORY",
 108                                         target_name(target));
 109                         nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
 110
 111                         /* set to ACC_CTL */
 112                         aice_memory_mode(aice, nds32->memory.mode);
 113                 } else {
 114                         if (strcmp(CMD_ARGV[0], "auto") == 0) {
 115                                 nds32->memory.mode = NDS_MEMORY_SELECT_AUTO;
 116                         } else if (strcmp(CMD_ARGV[0], "mem") == 0) {
 117                                 nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
 118                         } else if (strcmp(CMD_ARGV[0], "ilm") == 0) {
 119                                 if (nds32->memory.ilm_base == 0)
 120                                         command_print(CMD, "%s does not support ILM",
 121                                                         target_name(target));
 122                                 else
 123                                         nds32->memory.mode = NDS_MEMORY_SELECT_ILM;
 124                         } else if (strcmp(CMD_ARGV[0], "dlm") == 0) {
 125                                 if (nds32->memory.dlm_base == 0)
 126                                         command_print(CMD, "%s does not support DLM",
 127                                                         target_name(target));
 128                                 else
 129                                         nds32->memory.mode = NDS_MEMORY_SELECT_DLM;
 130                         }
 131
 132                         /* set to ACC_CTL */
 133                         aice_memory_mode(aice, nds32->memory.mode);
 134                 }
 135         }
 136
 137         command_print(CMD, "%s: memory mode: %s",
 138                         target_name(target),
 139                         nds_memory_select_name[nds32->memory.mode]);
 140
 141         return ERROR_OK;
 142 }
 143
 144 COMMAND_HANDLER(handle_nds32_cache_command)
 145 {
 146         struct target *target = get_current_target(CMD_CTX);
 147         struct nds32 *nds32 = target_to_nds32(target);
 148         struct aice_port_s *aice = target_to_aice(target);
 149         struct nds32_cache *icache = &(nds32->memory.icache);
 150         struct nds32_cache *dcache = &(nds32->memory.dcache);
 151         int result;
 152
 153         if (!is_nds32(nds32)) {
 154                 command_print(CMD, "current target isn't an Andes core");
 155                 return ERROR_FAIL;
 156         }
 157
 158         if (CMD_ARGC > 0) {
 159
 160                 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
 161                         if ((dcache->line_size != 0) && (dcache->enable == true)) {
 162                                 /* D$ write back */
 163                                 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
 164                                 if (result != ERROR_OK) {
 165                                         command_print(CMD, "%s: Write back data cache...failed",
 166                                                         target_name(target));
 167                                         return result;
 168                                 }
 169
 170                                 command_print(CMD, "%s: Write back data cache...done",
 171                                                 target_name(target));
 172
 173                                 /* D$ invalidate */
 174                                 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
 175                                 if (result != ERROR_OK) {
 176                                         command_print(CMD, "%s: Invalidate data cache...failed",
 177                                                         target_name(target));
 178                                         return result;
 179                                 }
 180
 181                                 command_print(CMD, "%s: Invalidate data cache...done",
 182                                                 target_name(target));
 183                         } else {
 184                                 if (dcache->line_size == 0)
 185                                         command_print(CMD, "%s: No data cache",
 186                                                         target_name(target));
 187                                 else
 188                                         command_print(CMD, "%s: Data cache disabled",
 189                                                         target_name(target));
 190                         }
 191
 192                         if ((icache->line_size != 0) && (icache->enable == true)) {
 193                                 /* I$ invalidate */
 194                                 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
 195                                 if (result != ERROR_OK) {
 196                                         command_print(CMD, "%s: Invalidate instruction cache...failed",
 197                                                         target_name(target));
 198                                         return result;
 199                                 }
 200
 201                                 command_print(CMD, "%s: Invalidate instruction cache...done",
 202                                                 target_name(target));
 203                         } else {
 204                                 if (icache->line_size == 0)
 205                                         command_print(CMD, "%s: No instruction cache",
 206                                                         target_name(target));
 207                                 else
 208                                         command_print(CMD, "%s: Instruction cache disabled",
 209                                                         target_name(target));
 210                         }
 211                 } else
 212                         command_print(CMD, "No valid parameter");
 213         }
 214
 215         return ERROR_OK;
 216 }
 217
 218 COMMAND_HANDLER(handle_nds32_icache_command)
 219 {
 220         struct target *target = get_current_target(CMD_CTX);
 221         struct nds32 *nds32 = target_to_nds32(target);
 222         struct aice_port_s *aice = target_to_aice(target);
 223         struct nds32_cache *icache = &(nds32->memory.icache);
 224         int result;
 225
 226         if (!is_nds32(nds32)) {
 227                 command_print(CMD, "current target isn't an Andes core");
 228                 return ERROR_FAIL;
 229         }
 230
 231         if (CMD_ARGC > 0) {
 232
 233                 if (icache->line_size == 0) {
 234                         command_print(CMD, "%s: No instruction cache",
 235                                         target_name(target));
 236                         return ERROR_OK;
 237                 }
 238
 239                 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
 240                         if (icache->enable == true) {
 241                                 /* I$ invalidate */
 242                                 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1I_INVALALL, 0);
 243                                 if (result != ERROR_OK) {
 244                                         command_print(CMD, "%s: Invalidate instruction cache...failed",
 245                                                         target_name(target));
 246                                         return result;
 247                                 }
 248
 249                                 command_print(CMD, "%s: Invalidate instruction cache...done",
 250                                                 target_name(target));
 251                         } else {
 252                                 command_print(CMD, "%s: Instruction cache disabled",
 253                                                 target_name(target));
 254                         }
 255                 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
 256                         uint32_t value;
 257                         nds32_get_mapped_reg(nds32, IR8, &value);
 258                         nds32_set_mapped_reg(nds32, IR8, value | 0x1);
 259                 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
 260                         uint32_t value;
 261                         nds32_get_mapped_reg(nds32, IR8, &value);
 262                         nds32_set_mapped_reg(nds32, IR8, value & ~0x1);
 263                 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
 264                         /* TODO: dump cache content */
 265                 } else {
 266                         command_print(CMD, "%s: No valid parameter", target_name(target));
 267                 }
 268         }
 269
 270         return ERROR_OK;
 271 }
 272
 273 COMMAND_HANDLER(handle_nds32_dcache_command)
 274 {
 275         struct target *target = get_current_target(CMD_CTX);
 276         struct nds32 *nds32 = target_to_nds32(target);
 277         struct aice_port_s *aice = target_to_aice(target);
 278         struct nds32_cache *dcache = &(nds32->memory.dcache);
 279         int result;
 280
 281         if (!is_nds32(nds32)) {
 282                 command_print(CMD, "current target isn't an Andes core");
 283                 return ERROR_FAIL;
 284         }
 285
 286         if (CMD_ARGC > 0) {
 287
 288                 if (dcache->line_size == 0) {
 289                         command_print(CMD, "%s: No data cache", target_name(target));
 290                         return ERROR_OK;
 291                 }
 292
 293                 if (strcmp(CMD_ARGV[0], "invalidate") == 0) {
 294                         if (dcache->enable == true) {
 295                                 /* D$ write back */
 296                                 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_WBALL, 0);
 297                                 if (result != ERROR_OK) {
 298                                         command_print(CMD, "%s: Write back data cache...failed",
 299                                                         target_name(target));
 300                                         return result;
 301                                 }
 302
 303                                 command_print(CMD, "%s: Write back data cache...done",
 304                                                 target_name(target));
 305
 306                                 /* D$ invalidate */
 307                                 result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_INVALALL, 0);
 308                                 if (result != ERROR_OK) {
 309                                         command_print(CMD, "%s: Invalidate data cache...failed",
 310                                                         target_name(target));
 311                                         return result;
 312                                 }
 313
 314                                 command_print(CMD, "%s: Invalidate data cache...done",
 315                                                 target_name(target));
 316                         } else {
 317                                 command_print(CMD, "%s: Data cache disabled",
 318                                                 target_name(target));
 319                         }
 320                 } else if (strcmp(CMD_ARGV[0], "enable") == 0) {
 321                         uint32_t value;
 322                         nds32_get_mapped_reg(nds32, IR8, &value);
 323                         nds32_set_mapped_reg(nds32, IR8, value | 0x2);
 324                 } else if (strcmp(CMD_ARGV[0], "disable") == 0) {
 325                         uint32_t value;
 326                         nds32_get_mapped_reg(nds32, IR8, &value);
 327                         nds32_set_mapped_reg(nds32, IR8, value & ~0x2);
 328                 } else if (strcmp(CMD_ARGV[0], "dump") == 0) {
 329                         /* TODO: dump cache content */
 330                 } else {
 331                         command_print(CMD, "%s: No valid parameter", target_name(target));
 332                 }
 333         }
 334
 335         return ERROR_OK;
 336 }
 337
 338 COMMAND_HANDLER(handle_nds32_auto_break_command)
 339 {
 340         struct target *target = get_current_target(CMD_CTX);
 341         struct nds32 *nds32 = target_to_nds32(target);
 342
 343         if (!is_nds32(nds32)) {
 344                 command_print(CMD, "current target isn't an Andes core");
 345                 return ERROR_FAIL;
 346         }
 347
 348         if (CMD_ARGC > 0) {
 349                 if (strcmp(CMD_ARGV[0], "on") == 0)
 350                         nds32->auto_convert_hw_bp = true;
 351                 if (strcmp(CMD_ARGV[0], "off") == 0)
 352                         nds32->auto_convert_hw_bp = false;
 353         }
 354
 355         if (nds32->auto_convert_hw_bp)
 356                 command_print(CMD, "%s: convert sw break to hw break on ROM: on",
 357                                 target_name(target));
 358         else
 359                 command_print(CMD, "%s: convert sw break to hw break on ROM: off",
 360                                 target_name(target));
 361
 362         return ERROR_OK;
 363 }
 364
 365 COMMAND_HANDLER(handle_nds32_virtual_hosting_command)
 366 {
 367         struct target *target = get_current_target(CMD_CTX);
 368         struct nds32 *nds32 = target_to_nds32(target);
 369
 370         if (!is_nds32(nds32)) {
 371                 command_print(CMD, "current target isn't an Andes core");
 372                 return ERROR_FAIL;
 373         }
 374
 375         if (CMD_ARGC > 0) {
 376                 if (strcmp(CMD_ARGV[0], "on") == 0)
 377                         nds32->virtual_hosting = true;
 378                 if (strcmp(CMD_ARGV[0], "off") == 0)
 379                         nds32->virtual_hosting = false;
 380         }
 381
 382         if (nds32->virtual_hosting)
 383                 command_print(CMD, "%s: virtual hosting: on", target_name(target));
 384         else
 385                 command_print(CMD, "%s: virtual hosting: off", target_name(target));
 386
 387         return ERROR_OK;
 388 }
 389
 390 COMMAND_HANDLER(handle_nds32_global_stop_command)
 391 {
 392         struct target *target = get_current_target(CMD_CTX);
 393         struct nds32 *nds32 = target_to_nds32(target);
 394
 395         if (!is_nds32(nds32)) {
 396                 command_print(CMD, "current target isn't an Andes core");
 397                 return ERROR_FAIL;
 398         }
 399
 400         if (CMD_ARGC > 0) {
 401                 if (strcmp(CMD_ARGV[0], "on") == 0)
 402                         nds32->global_stop = true;
 403                 if (strcmp(CMD_ARGV[0], "off") == 0)
 404                         nds32->global_stop = false;
 405         }
 406
 407         if (nds32->global_stop)
 408                 LOG_INFO("%s: global stop: on", target_name(target));
 409         else
 410                 LOG_INFO("%s: global stop: off", target_name(target));
 411
 412         return ERROR_OK;
 413 }
 414
 415 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command)
 416 {
 417         struct target *target = get_current_target(CMD_CTX);
 418         struct nds32 *nds32 = target_to_nds32(target);
 419
 420         if (!is_nds32(nds32)) {
 421                 command_print(CMD, "current target isn't an Andes core");
 422                 return ERROR_FAIL;
 423         }
 424
 425         if (CMD_ARGC > 0) {
 426                 if (strcmp(CMD_ARGV[0], "on") == 0)
 427                         nds32->soft_reset_halt = true;
 428                 if (strcmp(CMD_ARGV[0], "off") == 0)
 429                         nds32->soft_reset_halt = false;
 430         }
 431
 432         if (nds32->soft_reset_halt)
 433                 LOG_INFO("%s: soft-reset-halt: on", target_name(target));
 434         else
 435                 LOG_INFO("%s: soft-reset-halt: off", target_name(target));
 436
 437         return ERROR_OK;
 438 }
 439
 440 COMMAND_HANDLER(handle_nds32_boot_time_command)
 441 {
 442         struct target *target = get_current_target(CMD_CTX);
 443         struct nds32 *nds32 = target_to_nds32(target);
 444
 445         if (!is_nds32(nds32)) {
 446                 command_print(CMD, "current target isn't an Andes core");
 447                 return ERROR_FAIL;
 448         }
 449
 450         if (CMD_ARGC > 0)
 451                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], nds32->boot_time);
 452
 453         return ERROR_OK;
 454 }
 455
 456 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command)
 457 {
 458         struct target *target = get_current_target(CMD_CTX);
 459         struct nds32 *nds32 = target_to_nds32(target);
 460
 461         if (!is_nds32(nds32)) {
 462                 command_print(CMD, "current target isn't an Andes core");
 463                 return ERROR_FAIL;
 464         }
 465
 466         nds32->edm_passcode = strdup(CMD_ARGV[0]);
 467
 468         return ERROR_OK;
 469 }
 470
 471 COMMAND_HANDLER(handle_nds32_login_edm_operation_command)
 472 {
 473         struct target *target = get_current_target(CMD_CTX);
 474         struct nds32 *nds32 = target_to_nds32(target);
 475
 476         if (!is_nds32(nds32)) {
 477                 command_print(CMD, "current target isn't an Andes core");
 478                 return ERROR_FAIL;
 479         }
 480
 481         if (CMD_ARGC > 1) {
 482
 483                 uint32_t misc_reg_no;
 484                 uint32_t data;
 485
 486                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], misc_reg_no);
 487                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], data);
 488
 489                 if (nds32_edm_ops_num >= NDS32_EDM_OPERATION_MAX_NUM)
 490                         return ERROR_FAIL;
 491
 492                 /* Just save the operation. Execute it in nds32_login() */
 493                 nds32_edm_ops[nds32_edm_ops_num].reg_no = misc_reg_no;
 494                 nds32_edm_ops[nds32_edm_ops_num].value = data;
 495                 nds32_edm_ops_num++;
 496         } else
 497                 return ERROR_FAIL;
 498
 499         return ERROR_OK;
 500 }
 501
 502 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command)
 503 {
 504         struct target *target = get_current_target(CMD_CTX);
 505         struct nds32 *nds32 = target_to_nds32(target);
 506
 507         if (!is_nds32(nds32)) {
 508                 command_print(CMD, "current target isn't an Andes core");
 509                 return ERROR_FAIL;
 510         }
 511
 512         if (CMD_ARGC > 0) {
 513                 if (strcmp(CMD_ARGV[0], "on") == 0)
 514                         nds32->reset_halt_as_examine = true;
 515                 if (strcmp(CMD_ARGV[0], "off") == 0)
 516                         nds32->reset_halt_as_examine = false;
 517         }
 518
 519         return ERROR_OK;
 520 }
 521
 522 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command)
 523 {
 524         struct target *target = get_current_target(CMD_CTX);
 525         struct nds32 *nds32 = target_to_nds32(target);
 526
 527         if (!is_nds32(nds32)) {
 528                 command_print(CMD, "current target isn't an Andes core");
 529                 return ERROR_FAIL;
 530         }
 531
 532         if (CMD_ARGC > 0) {
 533                 if (strcmp(CMD_ARGV[0], "on") == 0)
 534                         nds32->keep_target_edm_ctl = true;
 535                 if (strcmp(CMD_ARGV[0], "off") == 0)
 536                         nds32->keep_target_edm_ctl = false;
 537         }
 538
 539         return ERROR_OK;
 540 }
 541
 542 COMMAND_HANDLER(handle_nds32_decode_command)
 543 {
 544         struct target *target = get_current_target(CMD_CTX);
 545         struct nds32 *nds32 = target_to_nds32(target);
 546
 547         if (!is_nds32(nds32)) {
 548                 command_print(CMD, "current target isn't an Andes core");
 549                 return ERROR_FAIL;
 550         }
 551
 552         if (CMD_ARGC > 1) {
 553
 554                 uint32_t addr;
 555                 uint32_t insn_count;
 556                 uint32_t opcode;
 557                 uint32_t read_addr;
 558                 uint32_t i;
 559                 struct nds32_instruction instruction;
 560
 561                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
 562                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], insn_count);
 563
 564                 read_addr = addr;
 565                 i = 0;
 566                 while (i < insn_count) {
 567                         if (nds32_read_opcode(nds32, read_addr, &opcode) != ERROR_OK)
 568                                 return ERROR_FAIL;
 569                         if (nds32_evaluate_opcode(nds32, opcode, read_addr, &instruction) != ERROR_OK)
 570                                 return ERROR_FAIL;
 571
 572                         command_print(CMD, "%s", instruction.text);
 573
 574                         read_addr += instruction.instruction_size;
 575                         i++;
 576                 }
 577         } else if (CMD_ARGC == 1) {
 578
 579                 uint32_t addr;
 580                 uint32_t opcode;
 581                 struct nds32_instruction instruction;
 582
 583                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], addr);
 584
 585                 if (nds32_read_opcode(nds32, addr, &opcode) != ERROR_OK)
 586                         return ERROR_FAIL;
 587                 if (nds32_evaluate_opcode(nds32, opcode, addr, &instruction) != ERROR_OK)
 588                         return ERROR_FAIL;
 589
 590                 command_print(CMD, "%s", instruction.text);
 591         } else
 592                 return ERROR_FAIL;
 593
 594         return ERROR_OK;
 595 }
 596
 597 COMMAND_HANDLER(handle_nds32_word_access_mem_command)
 598 {
 599         struct target *target = get_current_target(CMD_CTX);
 600         struct nds32 *nds32 = target_to_nds32(target);
 601
 602         if (!is_nds32(nds32)) {
 603                 command_print(CMD, "current target isn't an Andes core");
 604                 return ERROR_FAIL;
 605         }
 606
 607         if (CMD_ARGC > 0) {
 608                 if (strcmp(CMD_ARGV[0], "on") == 0)
 609                         nds32->word_access_mem = true;
 610                 if (strcmp(CMD_ARGV[0], "off") == 0)
 611                         nds32->word_access_mem = false;
 612         }
 613
 614         return ERROR_OK;
 615 }
 616
 617 COMMAND_HANDLER(handle_nds32_query_target_command)
 618 {
 619         struct target *target = get_current_target(CMD_CTX);
 620         struct nds32 *nds32 = target_to_nds32(target);
 621
 622         if (!is_nds32(nds32)) {
 623                 command_print(CMD, "current target isn't an Andes core");
 624                 return ERROR_FAIL;
 625         }
 626
 627         command_print(CMD, "OCD");
 628
 629         return ERROR_OK;
 630 }
 631
 632 COMMAND_HANDLER(handle_nds32_query_endian_command)
 633 {
 634         struct target *target = get_current_target(CMD_CTX);
 635         struct nds32 *nds32 = target_to_nds32(target);
 636
 637         if (!is_nds32(nds32)) {
 638                 command_print(CMD, "current target isn't an Andes core");
 639                 return ERROR_FAIL;
 640         }
 641
 642         uint32_t value_psw;
 643         nds32_get_mapped_reg(nds32, IR0, &value_psw);
 644
 645         if (value_psw & 0x20)
 646                 command_print(CMD, "%s: BE", target_name(target));
 647         else
 648                 command_print(CMD, "%s: LE", target_name(target));
 649
 650         return ERROR_OK;
 651 }
 652
 653 COMMAND_HANDLER(handle_nds32_query_cpuid_command)
 654 {
 655         struct target *target = get_current_target(CMD_CTX);
 656         struct nds32 *nds32 = target_to_nds32(target);
 657
 658         if (!is_nds32(nds32)) {
 659                 command_print(CMD, "current target isn't an Andes core");
 660                 return ERROR_FAIL;
 661         }
 662
 663         command_print(CMD, "CPUID: %s", target_name(target));
 664
 665         return ERROR_OK;
 666 }
 667
 668 static int jim_nds32_bulk_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 669 {
 670         const char *cmd_name = Jim_GetString(argv[0], NULL);
 671
 672         struct jim_getopt_info goi;
 673         jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
 674
 675         if (goi.argc < 3) {
 676                 Jim_SetResultFormatted(goi.interp,
 677                                 "usage: %s <address> <count> <data>", cmd_name);
 678                 return JIM_ERR;
 679         }
 680
 681         int e;
 682         jim_wide address;
 683         e = jim_getopt_wide(&goi, &address);
 684         if (e != JIM_OK)
 685                 return e;
 686
 687         jim_wide count;
 688         e = jim_getopt_wide(&goi, &count);
 689         if (e != JIM_OK)
 690                 return e;
 691
 692         uint32_t *data = malloc(count * sizeof(uint32_t));
 693         if (!data)
 694                 return JIM_ERR;
 695
 696         jim_wide i;
 697         for (i = 0; i < count; i++) {
 698                 jim_wide tmp;
 699                 e = jim_getopt_wide(&goi, &tmp);
 700                 if (e != JIM_OK) {
 701                         free(data);
 702                         return e;
 703                 }
 704                 data[i] = (uint32_t)tmp;
 705         }
 706
 707         /* all args must be consumed */
 708         if (goi.argc != 0) {
 709                 free(data);
 710                 return JIM_ERR;
 711         }
 712
 713         struct command_context *cmd_ctx = current_command_context(interp);
 714         assert(cmd_ctx);
 715         struct target *target = get_current_target(cmd_ctx);
 716         int result;
 717
 718         result = target_write_buffer(target, address, count * 4, (const uint8_t *)data);
 719
 720         free(data);
 721
 722         return result;
 723 }
 724
 725 static int jim_nds32_multi_write(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 726 {
 727         const char *cmd_name = Jim_GetString(argv[0], NULL);
 728
 729         struct jim_getopt_info goi;
 730         jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
 731
 732         if (goi.argc < 3) {
 733                 Jim_SetResultFormatted(goi.interp,
 734                                 "usage: %s # of pairs [<address> <data>]+", cmd_name);
 735                 return JIM_ERR;
 736         }
 737
 738         int e;
 739         jim_wide num_of_pairs;
 740         e = jim_getopt_wide(&goi, &num_of_pairs);
 741         if (e != JIM_OK)
 742                 return e;
 743
 744         struct command_context *cmd_ctx = current_command_context(interp);
 745         assert(cmd_ctx);
 746         struct target *target = get_current_target(cmd_ctx);
 747         struct aice_port_s *aice = target_to_aice(target);
 748         int result;
 749         uint32_t address;
 750         uint32_t data;
 751         jim_wide i;
 752
 753         aice_set_command_mode(aice, AICE_COMMAND_MODE_PACK);
 754         for (i = 0; i < num_of_pairs; i++) {
 755                 jim_wide tmp;
 756                 e = jim_getopt_wide(&goi, &tmp);
 757                 if (e != JIM_OK)
 758                         break;
 759                 address = (uint32_t)tmp;
 760
 761                 e = jim_getopt_wide(&goi, &tmp);
 762                 if (e != JIM_OK)
 763                         break;
 764                 data = (uint32_t)tmp;
 765
 766                 result = target_write_buffer(target, address, 4, (const uint8_t *)&data);
 767                 if (result != ERROR_OK)
 768                         break;
 769         }
 770         aice_set_command_mode(aice, AICE_COMMAND_MODE_NORMAL);
 771
 772         /* all args must be consumed */
 773         if (goi.argc != 0)
 774                 return JIM_ERR;
 775
 776         return ERROR_OK;
 777 }
 778
 779 static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 780 {
 781         const char *cmd_name = Jim_GetString(argv[0], NULL);
 782
 783         struct jim_getopt_info goi;
 784         jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
 785
 786         if (goi.argc < 2) {
 787                 Jim_SetResultFormatted(goi.interp,
 788                                 "usage: %s <address> <count>", cmd_name);
 789                 return JIM_ERR;
 790         }
 791
 792         int e;
 793         jim_wide address;
 794         e = jim_getopt_wide(&goi, &address);
 795         if (e != JIM_OK)
 796                 return e;
 797
 798         jim_wide count;
 799         e = jim_getopt_wide(&goi, &count);
 800         if (e != JIM_OK)
 801                 return e;
 802
 803         /* all args must be consumed */
 804         if (goi.argc != 0)
 805                 return JIM_ERR;
 806
 807         struct command_context *cmd_ctx = current_command_context(interp);
 808         assert(cmd_ctx);
 809         struct target *target = get_current_target(cmd_ctx);
 810         uint32_t *data = malloc(count * sizeof(uint32_t));
 811         int result;
 812         result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
 813         char data_str[12];
 814
 815         jim_wide i;
 816         Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
 817         for (i = 0; i < count; i++) {
 818                 sprintf(data_str, "0x%08" PRIx32 " ", data[i]);
 819                 Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
 820         }
 821
 822         free(data);
 823
 824         return result;
 825 }
 826
 827 static int jim_nds32_read_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 828 {
 829         const char *cmd_name = Jim_GetString(argv[0], NULL);
 830
 831         struct jim_getopt_info goi;
 832         jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
 833
 834         if (goi.argc < 1) {
 835                 Jim_SetResultFormatted(goi.interp,
 836                                 "usage: %s <edm_sr_name>", cmd_name);
 837                 return JIM_ERR;
 838         }
 839
 840         int e;
 841         const char *edm_sr_name;
 842         int edm_sr_name_len;
 843         e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len);
 844         if (e != JIM_OK)
 845                 return e;
 846
 847         /* all args must be consumed */
 848         if (goi.argc != 0)
 849                 return JIM_ERR;
 850
 851         uint32_t edm_sr_number;
 852         uint32_t edm_sr_value;
 853         if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
 854                 edm_sr_number = NDS_EDM_SR_EDM_DTR;
 855         else if (strncmp(edm_sr_name, "edmsw", edm_sr_name_len) == 0)
 856                 edm_sr_number = NDS_EDM_SR_EDMSW;
 857         else
 858                 return ERROR_FAIL;
 859
 860         struct command_context *cmd_ctx = current_command_context(interp);
 861         assert(cmd_ctx);
 862         struct target *target = get_current_target(cmd_ctx);
 863         struct aice_port_s *aice = target_to_aice(target);
 864         char data_str[11];
 865
 866         aice_read_debug_reg(aice, edm_sr_number, &edm_sr_value);
 867
 868         sprintf(data_str, "0x%08" PRIx32, edm_sr_value);
 869         Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
 870         Jim_AppendStrings(interp, Jim_GetResult(interp), data_str, NULL);
 871
 872         return ERROR_OK;
 873 }
 874
 875 static int jim_nds32_write_edm_sr(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 876 {
 877         const char *cmd_name = Jim_GetString(argv[0], NULL);
 878
 879         struct jim_getopt_info goi;
 880         jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
 881
 882         if (goi.argc < 2) {
 883                 Jim_SetResultFormatted(goi.interp,
 884                                 "usage: %s <edm_sr_name> <value>", cmd_name);
 885                 return JIM_ERR;
 886         }
 887
 888         int e;
 889         const char *edm_sr_name;
 890         int edm_sr_name_len;
 891         e = jim_getopt_string(&goi, &edm_sr_name, &edm_sr_name_len);
 892         if (e != JIM_OK)
 893                 return e;
 894
 895         jim_wide value;
 896         e = jim_getopt_wide(&goi, &value);
 897         if (e != JIM_OK)
 898                 return e;
 899
 900         /* all args must be consumed */
 901         if (goi.argc != 0)
 902                 return JIM_ERR;
 903
 904         uint32_t edm_sr_number;
 905         if (strncmp(edm_sr_name, "edm_dtr", edm_sr_name_len) == 0)
 906                 edm_sr_number = NDS_EDM_SR_EDM_DTR;
 907         else
 908                 return ERROR_FAIL;
 909
 910         struct command_context *cmd_ctx = current_command_context(interp);
 911         assert(cmd_ctx);
 912         struct target *target = get_current_target(cmd_ctx);
 913         struct aice_port_s *aice = target_to_aice(target);
 914
 915         aice_write_debug_reg(aice, edm_sr_number, value);
 916
 917         return ERROR_OK;
 918 }
 919
 920 static const struct command_registration nds32_query_command_handlers[] = {
 921         {
 922                 .name = "target",
 923                 .handler = handle_nds32_query_target_command,
 924                 .mode = COMMAND_EXEC,
 925                 .usage = "",
 926                 .help = "reply 'OCD' for gdb to identify server-side is OpenOCD",
 927         },
 928         {
 929                 .name = "endian",
 930                 .handler = handle_nds32_query_endian_command,
 931                 .mode = COMMAND_EXEC,
 932                 .usage = "",
 933                 .help = "query target endian",
 934         },
 935         {
 936                 .name = "cpuid",
 937                 .handler = handle_nds32_query_cpuid_command,
 938                 .mode = COMMAND_EXEC,
 939                 .usage = "",
 940                 .help = "query CPU ID",
 941         },
 942
 943         COMMAND_REGISTRATION_DONE
 944 };
 945
 946 static const struct command_registration nds32_exec_command_handlers[] = {
 947         {
 948                 .name = "dssim",
 949                 .handler = handle_nds32_dssim_command,
 950                 .mode = COMMAND_EXEC,
 951                 .usage = "['on'|'off']",
 952                 .help = "display/change $INT_MASK.DSSIM status",
 953         },
 954         {
 955                 .name = "mem_access",
 956                 .handler = handle_nds32_memory_access_command,
 957                 .mode = COMMAND_EXEC,
 958                 .usage = "['bus'|'cpu']",
 959                 .help = "display/change memory access channel",
 960         },
 961         {
 962                 .name = "mem_mode",
 963                 .handler = handle_nds32_memory_mode_command,
 964                 .mode = COMMAND_EXEC,
 965                 .usage = "['auto'|'mem'|'ilm'|'dlm']",
 966                 .help = "display/change memory mode",
 967         },
 968         {
 969                 .name = "cache",
 970                 .handler = handle_nds32_cache_command,
 971                 .mode = COMMAND_EXEC,
 972                 .usage = "['invalidate']",
 973                 .help = "cache control",
 974         },
 975         {
 976                 .name = "icache",
 977                 .handler = handle_nds32_icache_command,
 978                 .mode = COMMAND_EXEC,
 979                 .usage = "['invalidate'|'enable'|'disable'|'dump']",
 980                 .help = "icache control",
 981         },
 982         {
 983                 .name = "dcache",
 984                 .handler = handle_nds32_dcache_command,
 985                 .mode = COMMAND_EXEC,
 986                 .usage = "['invalidate'|'enable'|'disable'|'dump']",
 987                 .help = "dcache control",
 988         },
 989         {
 990                 .name = "auto_break",
 991                 .handler = handle_nds32_auto_break_command,
 992                 .mode = COMMAND_EXEC,
 993                 .usage = "['on'|'off']",
 994                 .help = "convert software breakpoints to hardware breakpoints if needed",
 995         },
 996         {
 997                 .name = "virtual_hosting",
 998                 .handler = handle_nds32_virtual_hosting_command,
 999                 .mode = COMMAND_ANY,
1000                 .usage = "['on'|'off']",
1001                 .help = "turn on/off virtual hosting",
1002         },
1003         {
1004                 .name = "global_stop",
1005                 .handler = handle_nds32_global_stop_command,
1006                 .mode = COMMAND_ANY,
1007                 .usage = "['on'|'off']",
1008                 .help = "turn on/off global stop. After turning on, every load/store "
1009                          "instructions will be stopped to check memory access.",
1010         },
1011         {
1012                 .name = "soft_reset_halt",
1013                 .handler = handle_nds32_soft_reset_halt_command,
1014                 .mode = COMMAND_ANY,
1015                 .usage = "['on'|'off']",
1016                 .help = "as issuing rest-halt, to use soft-reset-halt or not."
1017                          "the feature is for backward-compatible.",
1018         },
1019         {
1020                 .name = "boot_time",
1021                 .handler = handle_nds32_boot_time_command,
1022                 .mode = COMMAND_CONFIG,
1023                 .usage = "milliseconds",
1024                 .help = "set the period to wait after srst.",
1025         },
1026         {
1027                 .name = "login_edm_passcode",
1028                 .handler = handle_nds32_login_edm_passcode_command,
1029                 .mode = COMMAND_CONFIG,
1030                 .usage = "passcode",
1031                 .help = "set EDM passcode for secure MCU debugging.",
1032         },
1033         {
1034                 .name = "login_edm_operation",
1035                 .handler = handle_nds32_login_edm_operation_command,
1036                 .mode = COMMAND_CONFIG,
1037                 .usage = "misc_reg_no value",
1038                 .help = "add EDM operations for secure MCU debugging.",
1039         },
1040         {
1041                 .name = "reset_halt_as_init",
1042                 .handler = handle_nds32_reset_halt_as_init_command,
1043                 .mode = COMMAND_CONFIG,
1044                 .usage = "['on'|'off']",
1045                 .help = "reset halt as openocd init.",
1046         },
1047         {
1048                 .name = "keep_target_edm_ctl",
1049                 .handler = handle_nds32_keep_target_edm_ctl_command,
1050                 .mode = COMMAND_CONFIG,
1051                 .usage = "['on'|'off']",
1052                 .help = "Backup/Restore target EDM_CTL register.",
1053         },
1054         {
1055                 .name = "decode",
1056                 .handler = handle_nds32_decode_command,
1057                 .mode = COMMAND_EXEC,
1058                 .usage = "address icount",
1059                 .help = "decode instruction.",
1060         },
1061         {
1062                 .name = "word_access_mem",
1063                 .handler = handle_nds32_word_access_mem_command,
1064                 .mode = COMMAND_ANY,
1065                 .usage = "['on'|'off']",
1066                 .help = "Always use word-aligned address to access memory.",
1067         },
1068         {
1069                 .name = "bulk_write",
1070                 .jim_handler = jim_nds32_bulk_write,
1071                 .mode = COMMAND_EXEC,
1072                 .help = "Write multiple 32-bit words to target memory",
1073                 .usage = "address count data",
1074         },
1075         {
1076                 .name = "multi_write",
1077                 .jim_handler = jim_nds32_multi_write,
1078                 .mode = COMMAND_EXEC,
1079                 .help = "Write multiple addresses/words to target memory",
1080                 .usage = "num_of_pairs [address data]+",
1081         },
1082         {
1083                 .name = "bulk_read",
1084                 .jim_handler = jim_nds32_bulk_read,
1085                 .mode = COMMAND_EXEC,
1086                 .help = "Read multiple 32-bit words from target memory",
1087                 .usage = "address count",
1088         },
1089         {
1090                 .name = "read_edmsr",
1091                 .jim_handler = jim_nds32_read_edm_sr,
1092                 .mode = COMMAND_EXEC,
1093                 .help = "Read EDM system register",
1094                 .usage = "['edmsw'|'edm_dtr']",
1095         },
1096         {
1097                 .name = "write_edmsr",
1098                 .jim_handler = jim_nds32_write_edm_sr,
1099                 .mode = COMMAND_EXEC,
1100                 .help = "Write EDM system register",
1101                 .usage = "['edm_dtr'] value",
1102         },
1103         {
1104                 .name = "query",
1105                 .mode = COMMAND_EXEC,
1106                 .help = "Andes query command group",
1107                 .usage = "",
1108                 .chain = nds32_query_command_handlers,
1109         },
1110
1111         COMMAND_REGISTRATION_DONE
1112 };
1113
1114 const struct command_registration nds32_command_handlers[] = {
1115         {
1116                 .name = "nds",
1117                 .mode = COMMAND_ANY,
1118                 .help = "Andes command group",
1119                 .usage = "",
1120                 .chain = nds32_exec_command_handlers,
1121         },
1122         COMMAND_REGISTRATION_DONE
1123 };