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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "mips32.h"
  27 #include "mips_m4k.h"
  28 #include "mips32_dmaacc.h"
  29 #include "jtag.h"
  30 #include "log.h"
  31
  32 #include <stdlib.h>
  33 #include <string.h>
  34
  35 /* cli handling */
  36
  37 /* forward declarations */
  38 int mips_m4k_poll(target_t *target);
  39 int mips_m4k_halt(struct target_s *target);
  40 int mips_m4k_soft_reset_halt(struct target_s *target);
  41 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
  42 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
  43 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  44 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  45 int mips_m4k_register_commands(struct command_context_s *cmd_ctx);
  46 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  47 int mips_m4k_quit(void);
  48 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp);
  49
  50 int mips_m4k_examine(struct target_s *target);
  51 int mips_m4k_assert_reset(target_t *target);
  52 int mips_m4k_deassert_reset(target_t *target);
  53
  54 target_type_t mips_m4k_target =
  55 {
  56         .name = "mips_m4k",
  57
  58         .poll = mips_m4k_poll,
  59         .arch_state = mips32_arch_state,
  60
  61         .target_request_data = NULL,
  62
  63         .halt = mips_m4k_halt,
  64         .resume = mips_m4k_resume,
  65         .step = mips_m4k_step,
  66
  67         .assert_reset = mips_m4k_assert_reset,
  68         .deassert_reset = mips_m4k_deassert_reset,
  69         .soft_reset_halt = mips_m4k_soft_reset_halt,
  70
  71         .get_gdb_reg_list = mips32_get_gdb_reg_list,
  72
  73         .read_memory = mips_m4k_read_memory,
  74         .write_memory = mips_m4k_write_memory,
  75         .bulk_write_memory = mips_m4k_bulk_write_memory,
  76         .checksum_memory = NULL,
  77         .blank_check_memory = NULL,
  78
  79         .run_algorithm = mips32_run_algorithm,
  80
  81         .add_breakpoint = mips_m4k_add_breakpoint,
  82         .remove_breakpoint = mips_m4k_remove_breakpoint,
  83         .add_watchpoint = mips_m4k_add_watchpoint,
  84         .remove_watchpoint = mips_m4k_remove_watchpoint,
  85
  86         .register_commands = mips_m4k_register_commands,
  87         .target_create = mips_m4k_target_create,
  88         .init_target = mips_m4k_init_target,
  89         .examine = mips_m4k_examine,
  90         .quit = mips_m4k_quit
  91 };
  92
  93 int mips_m4k_examine_debug_reason(target_t *target)
  94 {
  95         int break_status;
  96         int retval;
  97
  98         if ((target->debug_reason != DBG_REASON_DBGRQ)
  99                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 100         {
 101                 /* get info about inst breakpoint support */
 102                 if ((retval = target_read_u32(target, EJTAG_IBS, &break_status)) != ERROR_OK)
 103                         return retval;
 104                 if (break_status & 0x1f)
 105                 {
 106                         /* we have halted on a  breakpoint */
 107                         if ((retval = target_write_u32(target, EJTAG_IBS, 0)) != ERROR_OK)
 108                                 return retval;
 109                         target->debug_reason = DBG_REASON_BREAKPOINT;
 110                 }
 111
 112                 /* get info about data breakpoint support */
 113                 if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
 114                         return retval;
 115                 if (break_status & 0x1f)
 116                 {
 117                         /* we have halted on a  breakpoint */
 118                         if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
 119                                 return retval;
 120                         target->debug_reason = DBG_REASON_WATCHPOINT;
 121                 }
 122         }
 123
 124         return ERROR_OK;
 125 }
 126
 127 int mips_m4k_debug_entry(target_t *target)
 128 {
 129         mips32_common_t *mips32 = target->arch_info;
 130         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 131         u32 debug_reg;
 132
 133         /* read debug register */
 134         mips_ejtag_read_debug(ejtag_info, &debug_reg);
 135
 136         /* make sure break uit configured */
 137         mips32_configure_break_unit(target);
 138
 139         /* attempt to find halt reason */
 140         mips_m4k_examine_debug_reason(target);
 141
 142         /* clear single step if active */
 143         if (debug_reg & EJTAG_DEBUG_DSS)
 144         {
 145                 /* stopped due to single step - clear step bit */
 146                 mips_ejtag_config_step(ejtag_info, 0);
 147         }
 148
 149         mips32_save_context(target);
 150
 151         LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s",
 152                 *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value),
 153                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 154
 155         return ERROR_OK;
 156 }
 157
 158 int mips_m4k_poll(target_t *target)
 159 {
 160         int retval;
 161         mips32_common_t *mips32 = target->arch_info;
 162         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 163         u32 ejtag_ctrl = ejtag_info->ejtag_ctrl;
 164
 165         /* read ejtag control reg */
 166         jtag_add_end_state(TAP_IDLE);
 167         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 168         mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 169
 170         /* clear this bit before handling polling
 171          * as after reset registers will read zero */
 172         if (ejtag_ctrl & EJTAG_CTRL_ROCC)
 173         {
 174                 /* we have detected a reset, clear flag
 175                  * otherwise ejtag will not work */
 176                 jtag_add_end_state(TAP_IDLE);
 177                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 178
 179                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 180                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 181                 LOG_DEBUG("Reset Detected");
 182         }
 183
 184         /* check for processor halted */
 185         if (ejtag_ctrl & EJTAG_CTRL_BRKST)
 186         {
 187                 if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 188                 {
 189                         jtag_add_end_state(TAP_IDLE);
 190                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 191
 192                         target->state = TARGET_HALTED;
 193
 194                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 195                                 return retval;
 196
 197                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 198                 }
 199                 else if (target->state == TARGET_DEBUG_RUNNING)
 200                 {
 201                         target->state = TARGET_HALTED;
 202
 203                         if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK)
 204                                 return retval;
 205
 206                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 207                 }
 208         }
 209         else
 210         {
 211                 target->state = TARGET_RUNNING;
 212         }
 213
 214 //      LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
 215
 216         return ERROR_OK;
 217 }
 218
 219 int mips_m4k_halt(struct target_s *target)
 220 {
 221         mips32_common_t *mips32 = target->arch_info;
 222         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 223
 224         LOG_DEBUG("target->state: %s",
 225                   Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 226
 227         if (target->state == TARGET_HALTED)
 228         {
 229                 LOG_DEBUG("target was already halted");
 230                 return ERROR_OK;
 231         }
 232
 233         if (target->state == TARGET_UNKNOWN)
 234         {
 235                 LOG_WARNING("target was in unknown state when halt was requested");
 236         }
 237
 238         if (target->state == TARGET_RESET)
 239         {
 240                 if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
 241                 {
 242                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 243                         return ERROR_TARGET_FAILURE;
 244                 }
 245                 else
 246                 {
 247                         /* we came here in a reset_halt or reset_init sequence
 248                          * debug entry was already prepared in mips32_prepare_reset_halt()
 249                          */
 250                         target->debug_reason = DBG_REASON_DBGRQ;
 251
 252                         return ERROR_OK;
 253                 }
 254         }
 255
 256         /* break processor */
 257         mips_ejtag_enter_debug(ejtag_info);
 258
 259         target->debug_reason = DBG_REASON_DBGRQ;
 260
 261         return ERROR_OK;
 262 }
 263
 264 int mips_m4k_assert_reset(target_t *target)
 265 {
 266         mips32_common_t *mips32 = target->arch_info;
 267         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 268
 269         LOG_DEBUG("target->state: %s",
 270                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 271
 272         if (!(jtag_reset_config & RESET_HAS_SRST))
 273         {
 274                 LOG_ERROR("Can't assert SRST");
 275                 return ERROR_FAIL;
 276         }
 277
 278         if (target->reset_halt)
 279         {
 280                 /* use hardware to catch reset */
 281                 jtag_add_end_state(TAP_IDLE);
 282                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
 283         }
 284         else
 285         {
 286                 jtag_add_end_state(TAP_IDLE);
 287                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 288         }
 289
 290         if (strcmp(target->variant, "ejtag_srst") == 0)
 291         {
 292                 u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 293                 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 294                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 295                 mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 296         }
 297         else
 298         {
 299                 /* here we should issue a srst only, but we may have to assert trst as well */
 300                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 301                 {
 302                         jtag_add_reset(1, 1);
 303                 }
 304                 else
 305                 {
 306                         jtag_add_reset(0, 1);
 307                 }
 308         }
 309
 310         target->state = TARGET_RESET;
 311         jtag_add_sleep(50000);
 312
 313         mips32_invalidate_core_regs(target);
 314
 315         if (target->reset_halt)
 316         {
 317                 int retval;
 318                 if ((retval = target_halt(target))!=ERROR_OK)
 319                         return retval;
 320         }
 321
 322         return ERROR_OK;
 323 }
 324
 325 int mips_m4k_deassert_reset(target_t *target)
 326 {
 327         LOG_DEBUG("target->state: %s",
 328                 Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
 329
 330         /* deassert reset lines */
 331         jtag_add_reset(0, 0);
 332
 333         return ERROR_OK;
 334 }
 335
 336 int mips_m4k_soft_reset_halt(struct target_s *target)
 337 {
 338         /* TODO */
 339         return ERROR_OK;
 340 }
 341
 342 int mips_m4k_single_step_core(target_t *target)
 343 {
 344         mips32_common_t *mips32 = target->arch_info;
 345         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 346
 347         /* configure single step mode */
 348         mips_ejtag_config_step(ejtag_info, 1);
 349
 350         /* exit debug mode */
 351         mips_ejtag_exit_debug(ejtag_info, 1);
 352
 353         mips_m4k_debug_entry(target);
 354
 355         return ERROR_OK;
 356 }
 357
 358 int mips_m4k_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
 359 {
 360         mips32_common_t *mips32 = target->arch_info;
 361         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 362         breakpoint_t *breakpoint = NULL;
 363         u32 resume_pc;
 364
 365         if (target->state != TARGET_HALTED)
 366         {
 367                 LOG_WARNING("target not halted");
 368                 return ERROR_TARGET_NOT_HALTED;
 369         }
 370
 371         if (!debug_execution)
 372         {
 373                 target_free_all_working_areas(target);
 374                 mips_m4k_enable_breakpoints(target);
 375                 mips_m4k_enable_watchpoints(target);
 376         }
 377
 378         /* current = 1: continue on current pc, otherwise continue at <address> */
 379         if (!current)
 380         {
 381                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 382                 mips32->core_cache->reg_list[MIPS32_PC].dirty = 1;
 383                 mips32->core_cache->reg_list[MIPS32_PC].valid = 1;
 384         }
 385
 386         resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 387
 388         mips32_restore_context(target);
 389
 390         /* the front-end may request us not to handle breakpoints */
 391         if (handle_breakpoints)
 392         {
 393                 /* Single step past breakpoint at current address */
 394                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 395                 {
 396                         LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
 397                         mips_m4k_unset_breakpoint(target, breakpoint);
 398                         mips_m4k_single_step_core(target);
 399                         mips_m4k_set_breakpoint(target, breakpoint);
 400                 }
 401         }
 402
 403         /* exit debug mode - enable interrupts if required */
 404         mips_ejtag_exit_debug(ejtag_info, !debug_execution);
 405         target->debug_reason = DBG_REASON_NOTHALTED;
 406
 407         /* registers are now invalid */
 408         mips32_invalidate_core_regs(target);
 409
 410         if (!debug_execution)
 411         {
 412                 target->state = TARGET_RUNNING;
 413                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 414                 LOG_DEBUG("target resumed at 0x%x", resume_pc);
 415         }
 416         else
 417         {
 418                 target->state = TARGET_DEBUG_RUNNING;
 419                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 420                 LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
 421         }
 422
 423         return ERROR_OK;
 424 }
 425
 426 int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
 427 {
 428         /* get pointers to arch-specific information */
 429         mips32_common_t *mips32 = target->arch_info;
 430         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 431         breakpoint_t *breakpoint = NULL;
 432
 433         if (target->state != TARGET_HALTED)
 434         {
 435                 LOG_WARNING("target not halted");
 436                 return ERROR_TARGET_NOT_HALTED;
 437         }
 438
 439         /* current = 1: continue on current pc, otherwise continue at <address> */
 440         if (!current)
 441                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 442
 443         /* the front-end may request us not to handle breakpoints */
 444         if (handle_breakpoints)
 445                 if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32))))
 446                         mips_m4k_unset_breakpoint(target, breakpoint);
 447
 448         /* restore context */
 449         mips32_restore_context(target);
 450
 451         /* configure single step mode */
 452         mips_ejtag_config_step(ejtag_info, 1);
 453
 454         target->debug_reason = DBG_REASON_SINGLESTEP;
 455
 456         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 457
 458         /* exit debug mode */
 459         mips_ejtag_exit_debug(ejtag_info, 1);
 460
 461         /* registers are now invalid */
 462         mips32_invalidate_core_regs(target);
 463
 464         if (breakpoint)
 465                 mips_m4k_set_breakpoint(target, breakpoint);
 466
 467         LOG_DEBUG("target stepped ");
 468
 469         mips_m4k_debug_entry(target);
 470         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 471
 472         return ERROR_OK;
 473 }
 474
 475 void mips_m4k_enable_breakpoints(struct target_s *target)
 476 {
 477         breakpoint_t *breakpoint = target->breakpoints;
 478
 479         /* set any pending breakpoints */
 480         while (breakpoint)
 481         {
 482                 if (breakpoint->set == 0)
 483                         mips_m4k_set_breakpoint(target, breakpoint);
 484                 breakpoint = breakpoint->next;
 485         }
 486 }
 487
 488 int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 489 {
 490         mips32_common_t *mips32 = target->arch_info;
 491         mips32_comparator_t * comparator_list = mips32->inst_break_list;
 492
 493         if (breakpoint->set)
 494         {
 495                 LOG_WARNING("breakpoint already set");
 496                 return ERROR_OK;
 497         }
 498
 499         if (breakpoint->type == BKPT_HARD)
 500         {
 501                 int bp_num = 0;
 502
 503                 while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 504                         bp_num++;
 505                 if (bp_num >= mips32->num_inst_bpoints)
 506                 {
 507                         LOG_DEBUG("ERROR Can not find free FP Comparator");
 508                         LOG_WARNING("ERROR Can not find free FP Comparator");
 509                         exit(-1);
 510                 }
 511                 breakpoint->set = bp_num + 1;
 512                 comparator_list[bp_num].used = 1;
 513                 comparator_list[bp_num].bp_value = breakpoint->address;
 514                 target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
 515                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
 516                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
 517                 LOG_DEBUG("bp_num %i bp_value 0x%x", bp_num, comparator_list[bp_num].bp_value);
 518         }
 519         else if (breakpoint->type == BKPT_SOFT)
 520         {
 521
 522         }
 523
 524         return ERROR_OK;
 525 }
 526
 527 int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 528 {
 529         /* get pointers to arch-specific information */
 530         mips32_common_t *mips32 = target->arch_info;
 531         mips32_comparator_t * comparator_list = mips32->inst_break_list;
 532
 533         if (!breakpoint->set)
 534         {
 535                 LOG_WARNING("breakpoint not set");
 536                 return ERROR_OK;
 537         }
 538
 539         if (breakpoint->type == BKPT_HARD)
 540         {
 541                 int bp_num = breakpoint->set - 1;
 542                 if ((bp_num < 0) || (bp_num >= mips32->num_inst_bpoints))
 543                 {
 544                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
 545                         return ERROR_OK;
 546                 }
 547                 comparator_list[bp_num].used = 0;
 548                 comparator_list[bp_num].bp_value = 0;
 549                 target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
 550         }
 551         else
 552         {
 553
 554         }
 555         breakpoint->set = 0;
 556
 557         return ERROR_OK;
 558 }
 559
 560 int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 561 {
 562         mips32_common_t *mips32 = target->arch_info;
 563
 564         if (mips32->num_inst_bpoints_avail < 1)
 565         {
 566                 LOG_INFO("no hardware breakpoint available");
 567                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 568         }
 569
 570         /* default to hardware for now */
 571         breakpoint->type = BKPT_HARD;
 572
 573         mips32->num_inst_bpoints_avail--;
 574         mips_m4k_set_breakpoint(target, breakpoint);
 575
 576         return ERROR_OK;
 577 }
 578
 579 int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 580 {
 581         /* get pointers to arch-specific information */
 582         mips32_common_t *mips32 = target->arch_info;
 583
 584         if (target->state != TARGET_HALTED)
 585         {
 586                 LOG_WARNING("target not halted");
 587                 return ERROR_TARGET_NOT_HALTED;
 588         }
 589
 590         if (breakpoint->set)
 591         {
 592                 mips_m4k_unset_breakpoint(target, breakpoint);
 593         }
 594
 595         if (breakpoint->type == BKPT_HARD)
 596                 mips32->num_inst_bpoints_avail++;
 597
 598         return ERROR_OK;
 599 }
 600
 601 int mips_m4k_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 602 {
 603         /* TODO */
 604         return ERROR_OK;
 605 }
 606
 607 int mips_m4k_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 608 {
 609         /* TODO */
 610         return ERROR_OK;
 611 }
 612
 613 int mips_m4k_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 614 {
 615         /* TODO */
 616         return ERROR_OK;
 617 }
 618
 619 int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 620 {
 621         /* TODO */
 622         return ERROR_OK;
 623 }
 624
 625 void mips_m4k_enable_watchpoints(struct target_s *target)
 626 {
 627         watchpoint_t *watchpoint = target->watchpoints;
 628
 629         /* set any pending watchpoints */
 630         while (watchpoint)
 631         {
 632                 if (watchpoint->set == 0)
 633                         mips_m4k_set_watchpoint(target, watchpoint);
 634                 watchpoint = watchpoint->next;
 635         }
 636 }
 637
 638 int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 639 {
 640         mips32_common_t *mips32 = target->arch_info;
 641         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 642
 643         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 644
 645         if (target->state != TARGET_HALTED)
 646         {
 647                 LOG_WARNING("target not halted");
 648                 return ERROR_TARGET_NOT_HALTED;
 649         }
 650
 651         /* sanitize arguments */
 652         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 653                 return ERROR_INVALID_ARGUMENTS;
 654
 655         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 656                 return ERROR_TARGET_UNALIGNED_ACCESS;
 657
 658         switch (size)
 659         {
 660                 case 4:
 661                 case 2:
 662                 case 1:
 663                         /* if noDMA off, use DMAACC mode for memory read */
 664                         if(ejtag_info->impcode & EJTAG_IMP_NODMA)
 665                                 return mips32_pracc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 666                         else
 667                                 return mips32_dmaacc_read_mem(ejtag_info, address, size, count, (void *)buffer);
 668                 default:
 669                         LOG_ERROR("BUG: we shouldn't get here");
 670                         exit(-1);
 671                         break;
 672         }
 673
 674         return ERROR_OK;
 675 }
 676
 677 int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 678 {
 679         mips32_common_t *mips32 = target->arch_info;
 680         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 681
 682         LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 683
 684         if (target->state != TARGET_HALTED)
 685         {
 686                 LOG_WARNING("target not halted");
 687                 return ERROR_TARGET_NOT_HALTED;
 688         }
 689
 690         /* sanitize arguments */
 691         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 692                 return ERROR_INVALID_ARGUMENTS;
 693
 694         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 695                 return ERROR_TARGET_UNALIGNED_ACCESS;
 696
 697         switch (size)
 698         {
 699                 case 4:
 700                 case 2:
 701                 case 1:
 702                         /* if noDMA off, use DMAACC mode for memory write */
 703                         if(ejtag_info->impcode & EJTAG_IMP_NODMA)
 704                                 mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 705                         else
 706                                 mips32_dmaacc_write_mem(ejtag_info, address, size, count, (void *)buffer);
 707                         break;
 708                 default:
 709                         LOG_ERROR("BUG: we shouldn't get here");
 710                         exit(-1);
 711                         break;
 712         }
 713
 714         return ERROR_OK;
 715 }
 716
 717 int mips_m4k_register_commands(struct command_context_s *cmd_ctx)
 718 {
 719         int retval;
 720
 721         retval = mips32_register_commands(cmd_ctx);
 722         return retval;
 723 }
 724
 725 int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 726 {
 727         mips32_build_reg_cache(target);
 728
 729         return ERROR_OK;
 730 }
 731
 732 int mips_m4k_quit(void)
 733 {
 734         return ERROR_OK;
 735 }
 736
 737 int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap)
 738 {
 739         mips32_common_t *mips32 = &mips_m4k->mips32_common;
 740
 741         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 742
 743         /* initialize mips4k specific info */
 744         mips32_init_arch_info(target, mips32, tap);
 745         mips32->arch_info = mips_m4k;
 746
 747         return ERROR_OK;
 748 }
 749
 750 int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp)
 751 {
 752         mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t));
 753
 754         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
 755
 756         return ERROR_OK;
 757 }
 758
 759 int mips_m4k_examine(struct target_s *target)
 760 {
 761         int retval;
 762         mips32_common_t *mips32 = target->arch_info;
 763         mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
 764         u32 idcode = 0;
 765
 766         if (!target->type->examined)
 767         {
 768                 mips_ejtag_get_idcode(ejtag_info, &idcode, NULL);
 769
 770                 if (((idcode >> 1) & 0x7FF) == 0x29)
 771                 {
 772                         /* we are using a pic32mx so select ejtag port
 773                          * as it is not selected by default */
 774                         mips_ejtag_set_instr(ejtag_info, 0x05, NULL);
 775                         LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 776                 }
 777         }
 778
 779         /* init rest of ejtag interface */
 780         if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK)
 781                 return retval;
 782
 783         if ((retval = mips32_examine(target)) != ERROR_OK)
 784                 return retval;
 785
 786         return ERROR_OK;
 787 }
 788
 789 int mips_m4k_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer)
 790 {
 791         return mips_m4k_write_memory(target, address, 4, count, buffer);
 792 }