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   1 /***************************************************************************
   2  *   Copyright (C) 2008 by Spencer Oliver                                  *
   3  *   spen@spen-soft.co.uk                                                  *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by David T.L. Wong                                 *
   6  *                                                                         *
   7  *   Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com>          *
   8  *                                                                         *
   9  *   Copyright (C) 2011 by Drasko DRASKOVIC                                *
  10  *   drasko.draskovic@gmail.com                                            *
  11  *                                                                         *
  12  *   This program is free software; you can redistribute it and/or modify  *
  13  *   it under the terms of the GNU General Public License as published by  *
  14  *   the Free Software Foundation; either version 2 of the License, or     *
  15  *   (at your option) any later version.                                   *
  16  *                                                                         *
  17  *   This program is distributed in the hope that it will be useful,       *
  18  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  19  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  20  *   GNU General Public License for more details.                          *
  21  *                                                                         *
  22  *   You should have received a copy of the GNU General Public License     *
  23  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  24  ***************************************************************************/
  25
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "breakpoints.h"
  31 #include "mips32.h"
  32 #include "mips_m4k.h"
  33 #include "mips32_dmaacc.h"
  34 #include "target_type.h"
  35 #include "register.h"
  36 #include "smp.h"
  37
  38 static void mips_m4k_enable_breakpoints(struct target *target);
  39 static void mips_m4k_enable_watchpoints(struct target *target);
  40 static int mips_m4k_set_breakpoint(struct target *target,
  41                 struct breakpoint *breakpoint);
  42 static int mips_m4k_unset_breakpoint(struct target *target,
  43                 struct breakpoint *breakpoint);
  44 static int mips_m4k_internal_restore(struct target *target, int current,
  45                 target_addr_t address, int handle_breakpoints,
  46                 int debug_execution);
  47 static int mips_m4k_halt(struct target *target);
  48 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
  49                 uint32_t count, const uint8_t *buffer);
  50
  51 static int mips_m4k_examine_debug_reason(struct target *target)
  52 {
  53         struct mips32_common *mips32 = target_to_mips32(target);
  54         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
  55         uint32_t break_status;
  56         int retval;
  57
  58         if ((target->debug_reason != DBG_REASON_DBGRQ)
  59                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
  60                 if (ejtag_info->debug_caps & EJTAG_DCR_IB) {
  61                         /* get info about inst breakpoint support */
  62                         retval = target_read_u32(target,
  63                                 ejtag_info->ejtag_ibs_addr, &break_status);
  64                         if (retval != ERROR_OK)
  65                                 return retval;
  66                         if (break_status & 0x1f) {
  67                                 /* we have halted on a  breakpoint */
  68                                 retval = target_write_u32(target,
  69                                         ejtag_info->ejtag_ibs_addr, 0);
  70                                 if (retval != ERROR_OK)
  71                                         return retval;
  72                                 target->debug_reason = DBG_REASON_BREAKPOINT;
  73                         }
  74                 }
  75
  76                 if (ejtag_info->debug_caps & EJTAG_DCR_DB) {
  77                         /* get info about data breakpoint support */
  78                         retval = target_read_u32(target,
  79                                 ejtag_info->ejtag_dbs_addr, &break_status);
  80                         if (retval != ERROR_OK)
  81                                 return retval;
  82                         if (break_status & 0x1f) {
  83                                 /* we have halted on a  breakpoint */
  84                                 retval = target_write_u32(target,
  85                                         ejtag_info->ejtag_dbs_addr, 0);
  86                                 if (retval != ERROR_OK)
  87                                         return retval;
  88                                 target->debug_reason = DBG_REASON_WATCHPOINT;
  89                         }
  90                 }
  91         }
  92
  93         return ERROR_OK;
  94 }
  95
  96 static int mips_m4k_debug_entry(struct target *target)
  97 {
  98         struct mips32_common *mips32 = target_to_mips32(target);
  99         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 100
 101         mips32_save_context(target);
 102
 103         /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
 104         mips_ejtag_config_step(ejtag_info, 0);
 105
 106         /* make sure break unit configured */
 107         mips32_configure_break_unit(target);
 108
 109         /* attempt to find halt reason */
 110         mips_m4k_examine_debug_reason(target);
 111
 112         mips32_read_config_regs(target);
 113
 114         /* default to mips32 isa, it will be changed below if required */
 115         mips32->isa_mode = MIPS32_ISA_MIPS32;
 116
 117         /* other than mips32 only and isa bit set ? */
 118         if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1))
 119                 mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;
 120
 121         LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
 122                         buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
 123                         target_state_name(target));
 124
 125         return ERROR_OK;
 126 }
 127
 128 static struct target *get_mips_m4k(struct target *target, int32_t coreid)
 129 {
 130         struct target_list *head;
 131
 132         foreach_smp_target(head, target->smp_targets) {
 133                 struct target *curr = head->target;
 134                 if ((curr->coreid == coreid) && (curr->state == TARGET_HALTED))
 135                         return curr;
 136         }
 137         return target;
 138 }
 139
 140 static int mips_m4k_halt_smp(struct target *target)
 141 {
 142         int retval = ERROR_OK;
 143         struct target_list *head;
 144
 145         foreach_smp_target(head, target->smp_targets) {
 146                 int ret = ERROR_OK;
 147                 struct target *curr = head->target;
 148                 if ((curr != target) && (curr->state != TARGET_HALTED))
 149                         ret = mips_m4k_halt(curr);
 150
 151                 if (ret != ERROR_OK) {
 152                         LOG_ERROR("halt failed target->coreid: %" PRId32, curr->coreid);
 153                         retval = ret;
 154                 }
 155         }
 156         return retval;
 157 }
 158
 159 static int update_halt_gdb(struct target *target)
 160 {
 161         int retval = ERROR_OK;
 162         if (target->gdb_service->core[0] == -1) {
 163                 target->gdb_service->target = target;
 164                 target->gdb_service->core[0] = target->coreid;
 165                 retval = mips_m4k_halt_smp(target);
 166         }
 167         return retval;
 168 }
 169
 170 static int mips_m4k_poll(struct target *target)
 171 {
 172         int retval = ERROR_OK;
 173         struct mips32_common *mips32 = target_to_mips32(target);
 174         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 175         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 176         enum target_state prev_target_state = target->state;
 177
 178         /*  toggle to another core is done by gdb as follow */
 179         /*  maint packet J core_id */
 180         /*  continue */
 181         /*  the next polling trigger an halt event sent to gdb */
 182         if ((target->state == TARGET_HALTED) && (target->smp) &&
 183                 (target->gdb_service) &&
 184                 (!target->gdb_service->target)) {
 185                 target->gdb_service->target =
 186                         get_mips_m4k(target, target->gdb_service->core[1]);
 187                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 188                 return retval;
 189         }
 190
 191         /* read ejtag control reg */
 192         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 193         retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 194         if (retval != ERROR_OK)
 195                 return retval;
 196
 197         ejtag_info->isa = (ejtag_ctrl & EJTAG_CTRL_DBGISA) ? 1 : 0;
 198
 199         /* clear this bit before handling polling
 200          * as after reset registers will read zero */
 201         if (ejtag_ctrl & EJTAG_CTRL_ROCC) {
 202                 /* we have detected a reset, clear flag
 203                  * otherwise ejtag will not work */
 204                 ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 205
 206                 mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 207                 retval = mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 208                 if (retval != ERROR_OK)
 209                         return retval;
 210                 LOG_DEBUG("Reset Detected");
 211         }
 212
 213         /* check for processor halted */
 214         if (ejtag_ctrl & EJTAG_CTRL_BRKST) {
 215                 if ((target->state != TARGET_HALTED)
 216                     && (target->state != TARGET_DEBUG_RUNNING)) {
 217                         if (target->state == TARGET_UNKNOWN)
 218                                 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
 219
 220                         /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
 221                          * (maybe put on by HALT-ing the board in the previous session).
 222                          *
 223                          * Force enable debug entry for this session.
 224                          */
 225                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 226                         target->state = TARGET_HALTED;
 227                         retval = mips_m4k_debug_entry(target);
 228                         if (retval != ERROR_OK)
 229                                 return retval;
 230
 231                         if (target->smp &&
 232                                 ((prev_target_state == TARGET_RUNNING)
 233                              || (prev_target_state == TARGET_RESET))) {
 234                                 retval = update_halt_gdb(target);
 235                                 if (retval != ERROR_OK)
 236                                         return retval;
 237                         }
 238                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 239                 } else if (target->state == TARGET_DEBUG_RUNNING) {
 240                         target->state = TARGET_HALTED;
 241
 242                         retval = mips_m4k_debug_entry(target);
 243                         if (retval != ERROR_OK)
 244                                 return retval;
 245
 246                         if (target->smp) {
 247                                 retval = update_halt_gdb(target);
 248                                 if (retval != ERROR_OK)
 249                                         return retval;
 250                         }
 251
 252                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 253                 }
 254         } else
 255                 target->state = TARGET_RUNNING;
 256
 257 /*      LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
 258
 259         return ERROR_OK;
 260 }
 261
 262 static int mips_m4k_halt(struct target *target)
 263 {
 264         struct mips32_common *mips32 = target_to_mips32(target);
 265         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 266
 267         LOG_DEBUG("target->state: %s", target_state_name(target));
 268
 269         if (target->state == TARGET_HALTED) {
 270                 LOG_DEBUG("target was already halted");
 271                 return ERROR_OK;
 272         }
 273
 274         if (target->state == TARGET_UNKNOWN)
 275                 LOG_WARNING("target was in unknown state when halt was requested");
 276
 277         if (target->state == TARGET_RESET) {
 278                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 279                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 280                         return ERROR_TARGET_FAILURE;
 281                 } else {
 282                         /* we came here in a reset_halt or reset_init sequence
 283                          * debug entry was already prepared in mips_m4k_assert_reset()
 284                          */
 285                         target->debug_reason = DBG_REASON_DBGRQ;
 286
 287                         return ERROR_OK;
 288                 }
 289         }
 290
 291         /* break processor */
 292         mips_ejtag_enter_debug(ejtag_info);
 293
 294         target->debug_reason = DBG_REASON_DBGRQ;
 295
 296         return ERROR_OK;
 297 }
 298
 299 static int mips_m4k_assert_reset(struct target *target)
 300 {
 301         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
 302         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 303
 304         /* TODO: apply hw reset signal in not examined state */
 305         if (!(target_was_examined(target))) {
 306                 LOG_WARNING("Reset is not asserted because the target is not examined.");
 307                 LOG_WARNING("Use a reset button or power cycle the target.");
 308                 return ERROR_TARGET_NOT_EXAMINED;
 309         }
 310
 311         LOG_DEBUG("target->state: %s",
 312                 target_state_name(target));
 313
 314         enum reset_types jtag_reset_config = jtag_get_reset_config();
 315
 316         /* some cores support connecting while srst is asserted
 317          * use that mode is it has been configured */
 318
 319         bool srst_asserted = false;
 320
 321         if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
 322                         (jtag_reset_config & RESET_SRST_NO_GATING)) {
 323                 jtag_add_reset(0, 1);
 324                 srst_asserted = true;
 325         }
 326
 327
 328         /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
 329         if (ejtag_info->ejtag_version != EJTAG_VERSION_20) {
 330                 if (target->reset_halt) {
 331                         /* use hardware to catch reset */
 332                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 333                 } else
 334                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 335         }
 336
 337         if (jtag_reset_config & RESET_HAS_SRST) {
 338                 /* here we should issue a srst only, but we may have to assert trst as well */
 339                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 340                         jtag_add_reset(1, 1);
 341                 else if (!srst_asserted)
 342                         jtag_add_reset(0, 1);
 343         } else if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 344                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 345         } else {
 346                 if (mips_m4k->is_pic32mx) {
 347                         LOG_DEBUG("Using MTAP reset to reset processor...");
 348
 349                         /* use microchip specific MTAP reset */
 350                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
 351                         mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 352
 353                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_ASERT_RST);
 354                         mips_ejtag_drscan_8_out(ejtag_info, MCHP_DE_ASSERT_RST);
 355                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 356                 } else {
 357                         /* use ejtag reset - not supported by all cores */
 358                         uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 359                         LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 360                         mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 361                         mips_ejtag_drscan_32_out(ejtag_info, ejtag_ctrl);
 362                 }
 363         }
 364
 365         target->state = TARGET_RESET;
 366         jtag_add_sleep(50000);
 367
 368         register_cache_invalidate(mips_m4k->mips32.core_cache);
 369
 370         if (target->reset_halt) {
 371                 int retval = target_halt(target);
 372                 if (retval != ERROR_OK)
 373                         return retval;
 374         }
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int mips_m4k_deassert_reset(struct target *target)
 380 {
 381         LOG_DEBUG("target->state: %s", target_state_name(target));
 382
 383         /* deassert reset lines */
 384         jtag_add_reset(0, 0);
 385
 386         return ERROR_OK;
 387 }
 388
 389 static int mips_m4k_single_step_core(struct target *target)
 390 {
 391         struct mips32_common *mips32 = target_to_mips32(target);
 392         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 393
 394         /* configure single step mode */
 395         mips_ejtag_config_step(ejtag_info, 1);
 396
 397         /* disable interrupts while stepping */
 398         mips32_enable_interrupts(target, 0);
 399
 400         /* exit debug mode */
 401         mips_ejtag_exit_debug(ejtag_info);
 402
 403         mips_m4k_debug_entry(target);
 404
 405         return ERROR_OK;
 406 }
 407
 408 static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
 409 {
 410         int retval = ERROR_OK;
 411         struct target_list *head;
 412
 413         foreach_smp_target(head, target->smp_targets) {
 414                 int ret = ERROR_OK;
 415                 struct target *curr = head->target;
 416                 if ((curr != target) && (curr->state != TARGET_RUNNING)) {
 417                         /*  resume current address , not in step mode */
 418                         ret = mips_m4k_internal_restore(curr, 1, address,
 419                                                    handle_breakpoints, 0);
 420
 421                         if (ret != ERROR_OK) {
 422                                 LOG_ERROR("target->coreid :%" PRId32 " failed to resume at address :0x%" PRIx32,
 423                                                   curr->coreid, address);
 424                                 retval = ret;
 425                         }
 426                 }
 427         }
 428         return retval;
 429 }
 430
 431 static int mips_m4k_internal_restore(struct target *target, int current,
 432                 target_addr_t address, int handle_breakpoints, int debug_execution)
 433 {
 434         struct mips32_common *mips32 = target_to_mips32(target);
 435         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 436         struct breakpoint *breakpoint = NULL;
 437         uint32_t resume_pc;
 438
 439         if (target->state != TARGET_HALTED) {
 440                 LOG_WARNING("target not halted");
 441                 return ERROR_TARGET_NOT_HALTED;
 442         }
 443
 444         if (!debug_execution) {
 445                 target_free_all_working_areas(target);
 446                 mips_m4k_enable_breakpoints(target);
 447                 mips_m4k_enable_watchpoints(target);
 448         }
 449
 450         /* current = 1: continue on current pc, otherwise continue at <address> */
 451         if (!current) {
 452                 mips_m4k_isa_filter(mips32->isa_imp, &address);
 453                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 454                 mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
 455                 mips32->core_cache->reg_list[MIPS32_PC].valid = true;
 456         }
 457
 458         if ((mips32->isa_imp > 1) &&  debug_execution)  /* if more than one isa supported */
 459                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
 460
 461         if (!current)
 462                 resume_pc = address;
 463         else
 464                 resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
 465
 466         mips32_restore_context(target);
 467
 468         /* the front-end may request us not to handle breakpoints */
 469         if (handle_breakpoints) {
 470                 /* Single step past breakpoint at current address */
 471                 breakpoint = breakpoint_find(target, resume_pc);
 472                 if (breakpoint) {
 473                         LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT "",
 474                                           breakpoint->address);
 475                         mips_m4k_unset_breakpoint(target, breakpoint);
 476                         mips_m4k_single_step_core(target);
 477                         mips_m4k_set_breakpoint(target, breakpoint);
 478                 }
 479         }
 480
 481         /* enable interrupts if we are running */
 482         mips32_enable_interrupts(target, !debug_execution);
 483
 484         /* exit debug mode */
 485         mips_ejtag_exit_debug(ejtag_info);
 486         target->debug_reason = DBG_REASON_NOTHALTED;
 487
 488         /* registers are now invalid */
 489         register_cache_invalidate(mips32->core_cache);
 490
 491         if (!debug_execution) {
 492                 target->state = TARGET_RUNNING;
 493                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 494                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 495         } else {
 496                 target->state = TARGET_DEBUG_RUNNING;
 497                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 498                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 499         }
 500
 501         return ERROR_OK;
 502 }
 503
 504 static int mips_m4k_resume(struct target *target, int current,
 505                 target_addr_t address, int handle_breakpoints, int debug_execution)
 506 {
 507         int retval = ERROR_OK;
 508
 509         /* dummy resume for smp toggle in order to reduce gdb impact  */
 510         if ((target->smp) && (target->gdb_service->core[1] != -1)) {
 511                 /*   simulate a start and halt of target */
 512                 target->gdb_service->target = NULL;
 513                 target->gdb_service->core[0] = target->gdb_service->core[1];
 514                 /*  fake resume at next poll we play the  target core[1], see poll*/
 515                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 516                 return retval;
 517         }
 518
 519         retval = mips_m4k_internal_restore(target, current, address,
 520                                 handle_breakpoints,
 521                                 debug_execution);
 522
 523         if (retval == ERROR_OK && target->smp) {
 524                 target->gdb_service->core[0] = -1;
 525                 retval = mips_m4k_restore_smp(target, address, handle_breakpoints);
 526         }
 527
 528         return retval;
 529 }
 530
 531 static int mips_m4k_step(struct target *target, int current,
 532                 target_addr_t address, int handle_breakpoints)
 533 {
 534         /* get pointers to arch-specific information */
 535         struct mips32_common *mips32 = target_to_mips32(target);
 536         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 537         struct breakpoint *breakpoint = NULL;
 538
 539         if (target->state != TARGET_HALTED) {
 540                 LOG_WARNING("target not halted");
 541                 return ERROR_TARGET_NOT_HALTED;
 542         }
 543
 544         /* current = 1: continue on current pc, otherwise continue at <address> */
 545         if (!current) {
 546                 mips_m4k_isa_filter(mips32->isa_imp, &address);
 547                 buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
 548                 mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
 549                 mips32->core_cache->reg_list[MIPS32_PC].valid = true;
 550         }
 551
 552         /* the front-end may request us not to handle breakpoints */
 553         if (handle_breakpoints) {
 554                 breakpoint = breakpoint_find(target,
 555                                 buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 556                 if (breakpoint)
 557                         mips_m4k_unset_breakpoint(target, breakpoint);
 558         }
 559
 560         /* restore context */
 561         mips32_restore_context(target);
 562
 563         /* configure single step mode */
 564         mips_ejtag_config_step(ejtag_info, 1);
 565
 566         target->debug_reason = DBG_REASON_SINGLESTEP;
 567
 568         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 569
 570         /* disable interrupts while stepping */
 571         mips32_enable_interrupts(target, 0);
 572
 573         /* exit debug mode */
 574         mips_ejtag_exit_debug(ejtag_info);
 575
 576         /* registers are now invalid */
 577         register_cache_invalidate(mips32->core_cache);
 578
 579         LOG_DEBUG("target stepped ");
 580         mips_m4k_debug_entry(target);
 581
 582         if (breakpoint)
 583                 mips_m4k_set_breakpoint(target, breakpoint);
 584
 585         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 586
 587         return ERROR_OK;
 588 }
 589
 590 static void mips_m4k_enable_breakpoints(struct target *target)
 591 {
 592         struct breakpoint *breakpoint = target->breakpoints;
 593
 594         /* set any pending breakpoints */
 595         while (breakpoint) {
 596                 if (!breakpoint->is_set)
 597                         mips_m4k_set_breakpoint(target, breakpoint);
 598                 breakpoint = breakpoint->next;
 599         }
 600 }
 601
 602 static int mips_m4k_set_breakpoint(struct target *target,
 603                 struct breakpoint *breakpoint)
 604 {
 605         struct mips32_common *mips32 = target_to_mips32(target);
 606         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 607         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 608         int retval;
 609
 610         if (breakpoint->is_set) {
 611                 LOG_WARNING("breakpoint already set");
 612                 return ERROR_OK;
 613         }
 614
 615         if (breakpoint->type == BKPT_HARD) {
 616                 int bp_num = 0;
 617
 618                 while (comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints))
 619                         bp_num++;
 620                 if (bp_num >= mips32->num_inst_bpoints) {
 621                         LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32 ")",
 622                                         breakpoint->unique_id);
 623                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 624                 }
 625                 breakpoint_hw_set(breakpoint, bp_num);
 626                 comparator_list[bp_num].used = 1;
 627                 comparator_list[bp_num].bp_value = breakpoint->address;
 628
 629                 if (breakpoint->length != 4)                    /* make sure isa bit set */
 630                         comparator_list[bp_num].bp_value |= 1;
 631                 else                                            /* make sure isa bit cleared */
 632                         comparator_list[bp_num].bp_value &= ~1;
 633
 634                 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
 635                  * Warning: there is no IB ASID registers in 2.0.
 636                  * Do not set it! :) */
 637                 if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 638                         comparator_list[bp_num].bp_value &= 0xFFFFFFFC;
 639
 640                 target_write_u32(target, comparator_list[bp_num].reg_address,
 641                                 comparator_list[bp_num].bp_value);
 642                 target_write_u32(target, comparator_list[bp_num].reg_address +
 643                                  ejtag_info->ejtag_ibm_offs, 0x00000000);
 644                 target_write_u32(target, comparator_list[bp_num].reg_address +
 645                                  ejtag_info->ejtag_ibc_offs, 1);
 646                 LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
 647                                   breakpoint->unique_id,
 648                                   bp_num, comparator_list[bp_num].bp_value);
 649         } else if (breakpoint->type == BKPT_SOFT) {
 650                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 651
 652                 uint32_t isa_req = breakpoint->length & 1;      /* micro mips request bit */
 653                 uint32_t bplength = breakpoint->length & ~1;    /* drop micro mips request bit for length */
 654                 uint32_t bpaddr = breakpoint->address & ~1;     /* drop isa bit from address, if set */
 655
 656                 if (bplength == 4) {
 657                         uint32_t verify = 0xffffffff;
 658                         uint32_t sdbbp32_instr = MIPS32_SDBBP(isa_req);
 659                         if (ejtag_info->endianness && isa_req)
 660                                 sdbbp32_instr = SWAP16(sdbbp32_instr);
 661
 662                         if ((breakpoint->address & 3) == 0) {   /* word aligned */
 663
 664                                 retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
 665                                 if (retval != ERROR_OK)
 666                                         return retval;
 667
 668                                 retval = target_write_u32(target, bpaddr, sdbbp32_instr);
 669                                 if (retval != ERROR_OK)
 670                                         return retval;
 671
 672                                 retval = target_read_u32(target, bpaddr, &verify);
 673                                 if (retval != ERROR_OK)
 674                                         return retval;
 675
 676                                 if (verify != sdbbp32_instr)
 677                                         verify = 0;
 678
 679                         } else {        /* 16 bit aligned */
 680                                 retval = target_read_memory(target, bpaddr, 2, 2, breakpoint->orig_instr);
 681                                 if (retval != ERROR_OK)
 682                                         return retval;
 683
 684                                 uint8_t sdbbp_buf[4];
 685                                 target_buffer_set_u32(target, sdbbp_buf, sdbbp32_instr);
 686
 687                                 retval = target_write_memory(target, bpaddr, 2, 2, sdbbp_buf);
 688                                 if (retval != ERROR_OK)
 689                                         return retval;
 690
 691                                 retval = target_read_memory(target, bpaddr, 2, 2, sdbbp_buf);
 692                                 if (retval != ERROR_OK)
 693                                         return retval;
 694
 695                                 if (target_buffer_get_u32(target, sdbbp_buf) != sdbbp32_instr)
 696                                         verify = 0;
 697                         }
 698
 699                         if (verify == 0) {
 700                                 LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
 701                                         " - check that memory is read/writable", breakpoint->address);
 702                                 return ERROR_OK;
 703                         }
 704
 705                 } else {
 706                         uint16_t verify = 0xffff;
 707
 708                         retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
 709                         if (retval != ERROR_OK)
 710                                 return retval;
 711
 712                         retval = target_write_u16(target, bpaddr, MIPS16_SDBBP(isa_req));
 713                         if (retval != ERROR_OK)
 714                                 return retval;
 715
 716                         retval = target_read_u16(target, bpaddr, &verify);
 717                         if (retval != ERROR_OK)
 718                                 return retval;
 719
 720                         if (verify != MIPS16_SDBBP(isa_req)) {
 721                                 LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
 722                                                 " - check that memory is read/writable", breakpoint->address);
 723                                 return ERROR_OK;
 724                         }
 725                 }
 726
 727                 breakpoint->is_set = true;
 728         }
 729
 730         return ERROR_OK;
 731 }
 732
 733 static int mips_m4k_unset_breakpoint(struct target *target,
 734                 struct breakpoint *breakpoint)
 735 {
 736         /* get pointers to arch-specific information */
 737         struct mips32_common *mips32 = target_to_mips32(target);
 738         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 739         struct mips32_comparator *comparator_list = mips32->inst_break_list;
 740         int retval;
 741
 742         if (!breakpoint->is_set) {
 743                 LOG_WARNING("breakpoint not set");
 744                 return ERROR_OK;
 745         }
 746
 747         if (breakpoint->type == BKPT_HARD) {
 748                 int bp_num = breakpoint->number;
 749                 if (bp_num >= mips32->num_inst_bpoints) {
 750                         LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
 751                                           breakpoint->unique_id);
 752                         return ERROR_OK;
 753                 }
 754                 LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d",
 755                                 breakpoint->unique_id,
 756                                 bp_num);
 757                 comparator_list[bp_num].used = 0;
 758                 comparator_list[bp_num].bp_value = 0;
 759                 target_write_u32(target, comparator_list[bp_num].reg_address +
 760                                  ejtag_info->ejtag_ibc_offs, 0);
 761
 762         } else {
 763                 /* restore original instruction (kept in target endianness) */
 764                 uint32_t isa_req = breakpoint->length & 1;
 765                 uint32_t bplength = breakpoint->length & ~1;
 766                 uint8_t current_instr[4];
 767                 LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
 768                 if (bplength == 4) {
 769                         uint32_t sdbbp32_instr =  MIPS32_SDBBP(isa_req);
 770                         if (ejtag_info->endianness && isa_req)
 771                                 sdbbp32_instr = SWAP16(sdbbp32_instr);
 772
 773                         if ((breakpoint->address & 3) == 0) {           /* 32bit aligned */
 774                                 /* check that user program has not modified breakpoint instruction */
 775                                 retval = target_read_memory(target, breakpoint->address, 4, 1, current_instr);
 776                                 if (retval != ERROR_OK)
 777                                         return retval;
 778                                 /**
 779                                 * target_read_memory() gets us data in _target_ endianness.
 780                                 * If we want to use this data on the host for comparisons with some macros
 781                                 * we must first transform it to _host_ endianness using target_buffer_get_u16().
 782                                 */
 783                                 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
 784                                         retval = target_write_memory(target, breakpoint->address, 4, 1,
 785                                                                                 breakpoint->orig_instr);
 786                                         if (retval != ERROR_OK)
 787                                                 return retval;
 788                                 }
 789                         } else {        /* 16bit aligned */
 790                                 retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
 791                                 if (retval != ERROR_OK)
 792                                         return retval;
 793
 794                                 if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
 795                                         retval = target_write_memory(target, breakpoint->address, 2, 2,
 796                                                                                 breakpoint->orig_instr);
 797                                         if (retval != ERROR_OK)
 798                                                 return retval;
 799                                 }
 800                         }
 801                 } else {
 802                         /* check that user program has not modified breakpoint instruction */
 803                         retval = target_read_memory(target, breakpoint->address, 2, 1, current_instr);
 804                         if (retval != ERROR_OK)
 805                                 return retval;
 806
 807                         if (target_buffer_get_u16(target, current_instr) == MIPS16_SDBBP(isa_req)) {
 808                                 retval = target_write_memory(target, breakpoint->address, 2, 1,
 809                                                                         breakpoint->orig_instr);
 810                                 if (retval != ERROR_OK)
 811                                         return retval;
 812                         }
 813                 }
 814         }
 815
 816         breakpoint->is_set = false;
 817
 818         return ERROR_OK;
 819 }
 820
 821 static int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 822 {
 823         struct mips32_common *mips32 = target_to_mips32(target);
 824
 825         if ((breakpoint->length > 5 || breakpoint->length < 2) ||               /* out of range */
 826                 (breakpoint->length == 4 && (breakpoint->address & 2)) ||       /* mips32 unaligned */
 827                 (mips32->isa_imp == MIPS32_ONLY && breakpoint->length != 4) ||  /* misp32 specific */
 828                 ((mips32->isa_imp & 1) != (breakpoint->length & 1)))            /* isa not implemented */
 829                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 830
 831         if (breakpoint->type == BKPT_HARD) {
 832                 if (mips32->num_inst_bpoints_avail < 1) {
 833                         LOG_INFO("no hardware breakpoint available");
 834                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 835                 }
 836
 837                 mips32->num_inst_bpoints_avail--;
 838         }
 839
 840         return mips_m4k_set_breakpoint(target, breakpoint);
 841 }
 842
 843 static int mips_m4k_remove_breakpoint(struct target *target,
 844                 struct breakpoint *breakpoint)
 845 {
 846         /* get pointers to arch-specific information */
 847         struct mips32_common *mips32 = target_to_mips32(target);
 848
 849         if (target->state != TARGET_HALTED) {
 850                 LOG_WARNING("target not halted");
 851                 return ERROR_TARGET_NOT_HALTED;
 852         }
 853
 854         if (breakpoint->is_set)
 855                 mips_m4k_unset_breakpoint(target, breakpoint);
 856
 857         if (breakpoint->type == BKPT_HARD)
 858                 mips32->num_inst_bpoints_avail++;
 859
 860         return ERROR_OK;
 861 }
 862
 863 static int mips_m4k_set_watchpoint(struct target *target,
 864                 struct watchpoint *watchpoint)
 865 {
 866         struct mips32_common *mips32 = target_to_mips32(target);
 867         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 868         struct mips32_comparator *comparator_list = mips32->data_break_list;
 869         int wp_num = 0;
 870         /*
 871          * watchpoint enabled, ignore all byte lanes in value register
 872          * and exclude both load and store accesses from  watchpoint
 873          * condition evaluation
 874         */
 875         int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
 876                         (0xff << EJTAG_DBCN_BLM_SHIFT);
 877
 878         if (watchpoint->is_set) {
 879                 LOG_WARNING("watchpoint already set");
 880                 return ERROR_OK;
 881         }
 882
 883         while (comparator_list[wp_num].used && (wp_num < mips32->num_data_bpoints))
 884                 wp_num++;
 885         if (wp_num >= mips32->num_data_bpoints) {
 886                 LOG_ERROR("Can not find free FP Comparator");
 887                 return ERROR_FAIL;
 888         }
 889
 890         if (watchpoint->length != 4) {
 891                 LOG_ERROR("Only watchpoints of length 4 are supported");
 892                 return ERROR_TARGET_UNALIGNED_ACCESS;
 893         }
 894
 895         if (watchpoint->address % 4) {
 896                 LOG_ERROR("Watchpoints address should be word aligned");
 897                 return ERROR_TARGET_UNALIGNED_ACCESS;
 898         }
 899
 900         switch (watchpoint->rw) {
 901                 case WPT_READ:
 902                         enable &= ~EJTAG_DBCN_NOLB;
 903                         break;
 904                 case WPT_WRITE:
 905                         enable &= ~EJTAG_DBCN_NOSB;
 906                         break;
 907                 case WPT_ACCESS:
 908                         enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
 909                         break;
 910                 default:
 911                         LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
 912         }
 913
 914         watchpoint->number = wp_num;
 915         comparator_list[wp_num].used = 1;
 916         comparator_list[wp_num].bp_value = watchpoint->address;
 917
 918         /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
 919          * There is as well no ASID register support. */
 920         if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
 921                 comparator_list[wp_num].bp_value &= 0xFFFFFFF8;
 922         else
 923                 target_write_u32(target, comparator_list[wp_num].reg_address +
 924                          ejtag_info->ejtag_dbasid_offs, 0x00000000);
 925
 926         target_write_u32(target, comparator_list[wp_num].reg_address,
 927                          comparator_list[wp_num].bp_value);
 928         target_write_u32(target, comparator_list[wp_num].reg_address +
 929                          ejtag_info->ejtag_dbm_offs, 0x00000000);
 930
 931         target_write_u32(target, comparator_list[wp_num].reg_address +
 932                          ejtag_info->ejtag_dbc_offs, enable);
 933         /* TODO: probably this value is ignored on 2.0 */
 934         target_write_u32(target, comparator_list[wp_num].reg_address +
 935                          ejtag_info->ejtag_dbv_offs, 0);
 936         LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
 937
 938         return ERROR_OK;
 939 }
 940
 941 static int mips_m4k_unset_watchpoint(struct target *target,
 942                 struct watchpoint *watchpoint)
 943 {
 944         /* get pointers to arch-specific information */
 945         struct mips32_common *mips32 = target_to_mips32(target);
 946         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
 947         struct mips32_comparator *comparator_list = mips32->data_break_list;
 948
 949         if (!watchpoint->is_set) {
 950                 LOG_WARNING("watchpoint not set");
 951                 return ERROR_OK;
 952         }
 953
 954         int wp_num = watchpoint->number;
 955         if (wp_num >= mips32->num_data_bpoints) {
 956                 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
 957                 return ERROR_OK;
 958         }
 959         comparator_list[wp_num].used = 0;
 960         comparator_list[wp_num].bp_value = 0;
 961         target_write_u32(target, comparator_list[wp_num].reg_address +
 962                          ejtag_info->ejtag_dbc_offs, 0);
 963         watchpoint->is_set = false;
 964
 965         return ERROR_OK;
 966 }
 967
 968 static int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 969 {
 970         struct mips32_common *mips32 = target_to_mips32(target);
 971
 972         if (mips32->num_data_bpoints_avail < 1) {
 973                 LOG_INFO("no hardware watchpoints available");
 974                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 975         }
 976
 977         mips32->num_data_bpoints_avail--;
 978
 979         mips_m4k_set_watchpoint(target, watchpoint);
 980         return ERROR_OK;
 981 }
 982
 983 static int mips_m4k_remove_watchpoint(struct target *target,
 984                 struct watchpoint *watchpoint)
 985 {
 986         /* get pointers to arch-specific information */
 987         struct mips32_common *mips32 = target_to_mips32(target);
 988
 989         if (target->state != TARGET_HALTED) {
 990                 LOG_WARNING("target not halted");
 991                 return ERROR_TARGET_NOT_HALTED;
 992         }
 993
 994         if (watchpoint->is_set)
 995                 mips_m4k_unset_watchpoint(target, watchpoint);
 996
 997         mips32->num_data_bpoints_avail++;
 998
 999         return ERROR_OK;
1000 }
1001
1002 static void mips_m4k_enable_watchpoints(struct target *target)
1003 {
1004         struct watchpoint *watchpoint = target->watchpoints;
1005
1006         /* set any pending watchpoints */
1007         while (watchpoint) {
1008                 if (!watchpoint->is_set)
1009                         mips_m4k_set_watchpoint(target, watchpoint);
1010                 watchpoint = watchpoint->next;
1011         }
1012 }
1013
1014 static int mips_m4k_read_memory(struct target *target, target_addr_t address,
1015                 uint32_t size, uint32_t count, uint8_t *buffer)
1016 {
1017         struct mips32_common *mips32 = target_to_mips32(target);
1018         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1019
1020         LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1021                         address, size, count);
1022
1023         if (target->state != TARGET_HALTED) {
1024                 LOG_WARNING("target not halted");
1025                 return ERROR_TARGET_NOT_HALTED;
1026         }
1027
1028         /* sanitize arguments */
1029         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1030                 return ERROR_COMMAND_SYNTAX_ERROR;
1031
1032         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1033                 return ERROR_TARGET_UNALIGNED_ACCESS;
1034
1035         /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1036         void *t = NULL;
1037
1038         if (size > 1) {
1039                 t = malloc(count * size * sizeof(uint8_t));
1040                 if (!t) {
1041                         LOG_ERROR("Out of memory");
1042                         return ERROR_FAIL;
1043                 }
1044         } else
1045                 t = buffer;
1046
1047         /* if noDMA off, use DMAACC mode for memory read */
1048         int retval;
1049         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1050                 retval = mips32_pracc_read_mem(ejtag_info, address, size, count, t);
1051         else
1052                 retval = mips32_dmaacc_read_mem(ejtag_info, address, size, count, t);
1053
1054         /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1055         /* endianness, but byte array should represent target endianness       */
1056         if (retval == ERROR_OK) {
1057                 switch (size) {
1058                 case 4:
1059                         target_buffer_set_u32_array(target, buffer, count, t);
1060                         break;
1061                 case 2:
1062                         target_buffer_set_u16_array(target, buffer, count, t);
1063                         break;
1064                 }
1065         }
1066
1067         if (size > 1)
1068                 free(t);
1069
1070         return retval;
1071 }
1072
1073 static int mips_m4k_write_memory(struct target *target, target_addr_t address,
1074                 uint32_t size, uint32_t count, const uint8_t *buffer)
1075 {
1076         struct mips32_common *mips32 = target_to_mips32(target);
1077         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1078
1079         LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
1080                         address, size, count);
1081
1082         if (target->state != TARGET_HALTED) {
1083                 LOG_WARNING("target not halted");
1084                 return ERROR_TARGET_NOT_HALTED;
1085         }
1086
1087         if (size == 4 && count > 32) {
1088                 int retval = mips_m4k_bulk_write_memory(target, address, count, buffer);
1089                 if (retval == ERROR_OK)
1090                         return ERROR_OK;
1091                 LOG_WARNING("Falling back to non-bulk write");
1092         }
1093
1094         /* sanitize arguments */
1095         if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
1096                 return ERROR_COMMAND_SYNTAX_ERROR;
1097
1098         if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
1099                 return ERROR_TARGET_UNALIGNED_ACCESS;
1100
1101         /** correct endianness if we have word or hword access */
1102         void *t = NULL;
1103         if (size > 1) {
1104                 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1105                 /* endianness, but byte array represents target endianness               */
1106                 t = malloc(count * size * sizeof(uint8_t));
1107                 if (!t) {
1108                         LOG_ERROR("Out of memory");
1109                         return ERROR_FAIL;
1110                 }
1111
1112                 switch (size) {
1113                 case 4:
1114                         target_buffer_get_u32_array(target, buffer, count, (uint32_t *)t);
1115                         break;
1116                 case 2:
1117                         target_buffer_get_u16_array(target, buffer, count, (uint16_t *)t);
1118                         break;
1119                 }
1120                 buffer = t;
1121         }
1122
1123         /* if noDMA off, use DMAACC mode for memory write */
1124         int retval;
1125         if (ejtag_info->impcode & EJTAG_IMP_NODMA)
1126                 retval = mips32_pracc_write_mem(ejtag_info, address, size, count, buffer);
1127         else
1128                 retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
1129
1130         free(t);
1131
1132         if (retval != ERROR_OK)
1133                 return retval;
1134
1135         return ERROR_OK;
1136 }
1137
1138 static int mips_m4k_init_target(struct command_context *cmd_ctx,
1139                 struct target *target)
1140 {
1141         mips32_build_reg_cache(target);
1142
1143         return ERROR_OK;
1144 }
1145
1146 static int mips_m4k_init_arch_info(struct target *target,
1147                 struct mips_m4k_common *mips_m4k, struct jtag_tap *tap)
1148 {
1149         struct mips32_common *mips32 = &mips_m4k->mips32;
1150
1151         mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
1152
1153         /* initialize mips4k specific info */
1154         mips32_init_arch_info(target, mips32, tap);
1155         mips32->arch_info = mips_m4k;
1156
1157         return ERROR_OK;
1158 }
1159
1160 static int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
1161 {
1162         struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
1163
1164         mips_m4k_init_arch_info(target, mips_m4k, target->tap);
1165
1166         return ERROR_OK;
1167 }
1168
1169 static int mips_m4k_examine(struct target *target)
1170 {
1171         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1172         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1173
1174         if (!target_was_examined(target)) {
1175                 int retval = mips_ejtag_get_idcode(ejtag_info);
1176                 if (retval != ERROR_OK) {
1177                         LOG_ERROR("idcode read failed");
1178                         return retval;
1179                 }
1180                 if (((ejtag_info->idcode >> 1) & 0x7FF) == 0x29) {
1181                         /* we are using a pic32mx so select ejtag port
1182                          * as it is not selected by default */
1183                         mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
1184                         LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
1185                         mips_m4k->is_pic32mx = true;
1186                 }
1187         }
1188
1189         /* init rest of ejtag interface */
1190         int retval = mips_ejtag_init(ejtag_info);
1191         if (retval != ERROR_OK)
1192                 return retval;
1193
1194         return mips32_examine(target);
1195 }
1196
1197 static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
1198                 uint32_t count, const uint8_t *buffer)
1199 {
1200         struct mips32_common *mips32 = target_to_mips32(target);
1201         struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
1202         struct working_area *fast_data_area;
1203         int retval;
1204         int write_t = 1;
1205
1206         LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
1207                           address, count);
1208
1209         /* check alignment */
1210         if (address & 0x3u)
1211                 return ERROR_TARGET_UNALIGNED_ACCESS;
1212
1213         if (!mips32->fast_data_area) {
1214                 /* Get memory for block write handler
1215                  * we preserve this area between calls and gain a speed increase
1216                  * of about 3kb/sec when writing flash
1217                  * this will be released/nulled by the system when the target is resumed or reset */
1218                 retval = target_alloc_working_area(target,
1219                                 MIPS32_FASTDATA_HANDLER_SIZE,
1220                                 &mips32->fast_data_area);
1221                 if (retval != ERROR_OK) {
1222                         LOG_ERROR("No working area available");
1223                         return retval;
1224                 }
1225
1226                 /* reset fastadata state so the algo get reloaded */
1227                 ejtag_info->fast_access_save = -1;
1228         }
1229
1230         fast_data_area = mips32->fast_data_area;
1231
1232         if (address <= fast_data_area->address + fast_data_area->size &&
1233                         fast_data_area->address <= address + count) {
1234                 LOG_ERROR("fast_data (" TARGET_ADDR_FMT ") is within write area "
1235                           "(" TARGET_ADDR_FMT "-" TARGET_ADDR_FMT ").",
1236                           fast_data_area->address, address, address + count);
1237                 LOG_ERROR("Change work-area-phys or load_image address!");
1238                 return ERROR_FAIL;
1239         }
1240
1241         /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1242         /* but byte array represents target endianness                      */
1243         uint32_t *t = NULL;
1244         t = malloc(count * sizeof(uint32_t));
1245         if (!t) {
1246                 LOG_ERROR("Out of memory");
1247                 return ERROR_FAIL;
1248         }
1249
1250         target_buffer_get_u32_array(target, buffer, count, t);
1251
1252         retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
1253                         count, t);
1254
1255         free(t);
1256
1257         if (retval != ERROR_OK)
1258                 LOG_ERROR("Fastdata access Failed");
1259
1260         return retval;
1261 }
1262
1263 static int mips_m4k_verify_pointer(struct command_invocation *cmd,
1264                 struct mips_m4k_common *mips_m4k)
1265 {
1266         if (mips_m4k->common_magic != MIPSM4K_COMMON_MAGIC) {
1267                 command_print(cmd, "target is not an MIPS_M4K");
1268                 return ERROR_TARGET_INVALID;
1269         }
1270         return ERROR_OK;
1271 }
1272
1273 COMMAND_HANDLER(mips_m4k_handle_cp0_command)
1274 {
1275         int retval;
1276         struct target *target = get_current_target(CMD_CTX);
1277         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1278         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1279
1280         retval = mips_m4k_verify_pointer(CMD, mips_m4k);
1281         if (retval != ERROR_OK)
1282                 return retval;
1283
1284         if (target->state != TARGET_HALTED) {
1285                 command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
1286                 return ERROR_OK;
1287         }
1288
1289         /* two or more argument, access a single register/select (write if third argument is given) */
1290         if (CMD_ARGC < 2)
1291                 return ERROR_COMMAND_SYNTAX_ERROR;
1292         else {
1293                 uint32_t cp0_reg, cp0_sel;
1294                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], cp0_reg);
1295                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], cp0_sel);
1296
1297                 if (CMD_ARGC == 2) {
1298                         uint32_t value;
1299                         retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
1300                         if (retval != ERROR_OK) {
1301                                 command_print(CMD,
1302                                                 "couldn't access reg %" PRIu32,
1303                                                 cp0_reg);
1304                                 return ERROR_OK;
1305                         }
1306                         command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1307                                         cp0_reg, cp0_sel, value);
1308
1309                 } else if (CMD_ARGC == 3) {
1310                         uint32_t value;
1311                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1312                         retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
1313                         if (retval != ERROR_OK) {
1314                                 command_print(CMD,
1315                                                 "couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
1316                                                 cp0_reg,  cp0_sel);
1317                                 return ERROR_OK;
1318                         }
1319                         command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
1320                                         cp0_reg, cp0_sel, value);
1321                 }
1322         }
1323
1324         return ERROR_OK;
1325 }
1326
1327 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
1328 {
1329         struct target *target = get_current_target(CMD_CTX);
1330         struct mips_m4k_common *mips_m4k = target_to_m4k(target);
1331         struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
1332
1333         if (CMD_ARGC == 1)
1334                 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
1335         else if (CMD_ARGC > 1)
1336                         return ERROR_COMMAND_SYNTAX_ERROR;
1337
1338         command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
1339         if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {
1340                 ejtag_info->mode = 0;
1341                 command_print(CMD, "running in legacy mode");
1342         } else {
1343                 ejtag_info->mode = 1;
1344                 command_print(CMD, "running in fast queued mode");
1345         }
1346
1347         return ERROR_OK;
1348 }
1349
1350 static const struct command_registration mips_m4k_exec_command_handlers[] = {
1351         {
1352                 .name = "cp0",
1353                 .handler = mips_m4k_handle_cp0_command,
1354                 .mode = COMMAND_EXEC,
1355                 .usage = "regnum [value]",
1356                 .help = "display/modify cp0 register",
1357         },
1358         {
1359                 .name = "scan_delay",
1360                 .handler = mips_m4k_handle_scan_delay_command,
1361                 .mode = COMMAND_ANY,
1362                 .help = "display/set scan delay in nano seconds",
1363                 .usage = "[value]",
1364         },
1365         {
1366                 .chain = smp_command_handlers,
1367         },
1368         COMMAND_REGISTRATION_DONE
1369 };
1370
1371 const struct command_registration mips_m4k_command_handlers[] = {
1372         {
1373                 .chain = mips32_command_handlers,
1374         },
1375         {
1376                 .name = "mips_m4k",
1377                 .mode = COMMAND_ANY,
1378                 .help = "mips_m4k command group",
1379                 .usage = "",
1380                 .chain = mips_m4k_exec_command_handlers,
1381         },
1382         COMMAND_REGISTRATION_DONE
1383 };
1384
1385 struct target_type mips_m4k_target = {
1386         .name = "mips_m4k",
1387
1388         .poll = mips_m4k_poll,
1389         .arch_state = mips32_arch_state,
1390
1391         .halt = mips_m4k_halt,
1392         .resume = mips_m4k_resume,
1393         .step = mips_m4k_step,
1394
1395         .assert_reset = mips_m4k_assert_reset,
1396         .deassert_reset = mips_m4k_deassert_reset,
1397
1398         .get_gdb_reg_list = mips32_get_gdb_reg_list,
1399
1400         .read_memory = mips_m4k_read_memory,
1401         .write_memory = mips_m4k_write_memory,
1402         .checksum_memory = mips32_checksum_memory,
1403         .blank_check_memory = mips32_blank_check_memory,
1404
1405         .run_algorithm = mips32_run_algorithm,
1406
1407         .add_breakpoint = mips_m4k_add_breakpoint,
1408         .remove_breakpoint = mips_m4k_remove_breakpoint,
1409         .add_watchpoint = mips_m4k_add_watchpoint,
1410         .remove_watchpoint = mips_m4k_remove_watchpoint,
1411
1412         .commands = mips_m4k_command_handlers,
1413         .target_create = mips_m4k_target_create,
1414         .init_target = mips_m4k_init_target,
1415         .examine = mips_m4k_examine,
1416 };