git.gag.com Git - fw/openocd/blob - src/target/etm.c

   1 /***************************************************************************\r
   2  *   Copyright (C) 2005 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #include "config.h"\r
  21 \r
  22 #include "etm.h"\r
  23 \r
  24 #include "armv4_5.h"\r
  25 #include "arm7_9_common.h"\r
  26 \r
  27 #include "log.h"\r
  28 #include "arm_jtag.h"\r
  29 #include "types.h"\r
  30 #include "binarybuffer.h"\r
  31 #include "target.h"\r
  32 #include "register.h"\r
  33 #include "jtag.h"\r
  34 \r
  35 #include <stdlib.h>\r
  36 \r
  37 bitfield_desc_t etm_comms_ctrl_bitfield_desc[] = \r
  38 {\r
  39         {"R", 1},\r
  40         {"W", 1},\r
  41         {"reserved", 26},\r
  42         {"version", 4}\r
  43 };\r
  44 \r
  45 int etm_reg_arch_info[] =\r
  46 {\r
  47         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,\r
  48         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\r
  49         0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, \r
  50         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, \r
  51         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,\r
  52         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, \r
  53         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,\r
  54         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,\r
  55         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, \r
  56         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, \r
  57         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,\r
  58         0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,\r
  59         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67, \r
  60         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, \r
  61 };\r
  62 \r
  63 int etm_reg_arch_size_info[] =\r
  64 {\r
  65         32, 32, 17, 8, 3, 9, 32, 17,\r
  66         26, 16, 25, 8, 17, 32, 32, 17,\r
  67         32, 32, 32, 32, 32, 32, 32, 32, \r
  68         32, 32, 32, 32, 32, 32, 32, 32, \r
  69         7, 7, 7, 7, 7, 7, 7, 7, \r
  70         7, 7, 7, 7, 7, 7, 7, 7, \r
  71         32, 32, 32, 32, 32, 32, 32, 32, \r
  72         32, 32, 32, 32, 32, 32, 32, 32, \r
  73         32, 32, 32, 32, 32, 32, 32, 32, \r
  74         32, 32, 32, 32, 32, 32, 32, 32, \r
  75         16, 16, 16, 16, 18, 18, 18, 18,\r
  76         17, 17, 17, 17, 16, 16, 16, 16,\r
  77         17, 17, 17, 17, 17, 17, 2, \r
  78         17, 17, 17, 17, 32, 32, 32, 32 \r
  79 };\r
  80 \r
  81 char* etm_reg_list[] =\r
  82 {\r
  83         "ETM_CTRL",\r
  84         "ETM_CONFIG",\r
  85         "ETM_TRIG_EVENT",\r
  86         "ETM_MMD_CTRL",\r
  87         "ETM_STATUS",\r
  88         "ETM_SYS_CONFIG",\r
  89         "ETM_TRACE_RESOURCE_CTRL",\r
  90         "ETM_TRACE_EN_CTRL2",\r
  91         "ETM_TRACE_EN_EVENT",\r
  92         "ETM_TRACE_EN_CTRL1",\r
  93         "ETM_FIFOFULL_REGION",\r
  94         "ETM_FIFOFULL_LEVEL",\r
  95         "ETM_VIEWDATA_EVENT",\r
  96         "ETM_VIEWDATA_CTRL1",\r
  97         "ETM_VIEWDATA_CTRL2",\r
  98         "ETM_VIEWDATA_CTRL3",\r
  99         "ETM_ADDR_COMPARATOR_VALUE1",\r
 100         "ETM_ADDR_COMPARATOR_VALUE2",\r
 101         "ETM_ADDR_COMPARATOR_VALUE3",\r
 102         "ETM_ADDR_COMPARATOR_VALUE4",\r
 103         "ETM_ADDR_COMPARATOR_VALUE5",\r
 104         "ETM_ADDR_COMPARATOR_VALUE6",\r
 105         "ETM_ADDR_COMPARATOR_VALUE7",\r
 106         "ETM_ADDR_COMPARATOR_VALUE8",\r
 107         "ETM_ADDR_COMPARATOR_VALUE9",\r
 108         "ETM_ADDR_COMPARATOR_VALUE10",\r
 109         "ETM_ADDR_COMPARATOR_VALUE11",\r
 110         "ETM_ADDR_COMPARATOR_VALUE12",\r
 111         "ETM_ADDR_COMPARATOR_VALUE13",\r
 112         "ETM_ADDR_COMPARATOR_VALUE14",\r
 113         "ETM_ADDR_COMPARATOR_VALUE15",\r
 114         "ETM_ADDR_COMPARATOR_VALUE16",\r
 115         "ETM_ADDR_ACCESS_TYPE1",\r
 116         "ETM_ADDR_ACCESS_TYPE2",\r
 117         "ETM_ADDR_ACCESS_TYPE3",\r
 118         "ETM_ADDR_ACCESS_TYPE4",\r
 119         "ETM_ADDR_ACCESS_TYPE5",\r
 120         "ETM_ADDR_ACCESS_TYPE6",\r
 121         "ETM_ADDR_ACCESS_TYPE7",\r
 122         "ETM_ADDR_ACCESS_TYPE8",\r
 123         "ETM_ADDR_ACCESS_TYPE9",\r
 124         "ETM_ADDR_ACCESS_TYPE10",\r
 125         "ETM_ADDR_ACCESS_TYPE11",\r
 126         "ETM_ADDR_ACCESS_TYPE12",\r
 127         "ETM_ADDR_ACCESS_TYPE13",\r
 128         "ETM_ADDR_ACCESS_TYPE14",\r
 129         "ETM_ADDR_ACCESS_TYPE15",\r
 130         "ETM_ADDR_ACCESS_TYPE16",\r
 131         "ETM_DATA_COMPARATOR_VALUE1",\r
 132         "ETM_DATA_COMPARATOR_VALUE2",\r
 133         "ETM_DATA_COMPARATOR_VALUE3",\r
 134         "ETM_DATA_COMPARATOR_VALUE4",\r
 135         "ETM_DATA_COMPARATOR_VALUE5",\r
 136         "ETM_DATA_COMPARATOR_VALUE6",\r
 137         "ETM_DATA_COMPARATOR_VALUE7",\r
 138         "ETM_DATA_COMPARATOR_VALUE8",\r
 139         "ETM_DATA_COMPARATOR_VALUE9",\r
 140         "ETM_DATA_COMPARATOR_VALUE10",\r
 141         "ETM_DATA_COMPARATOR_VALUE11",\r
 142         "ETM_DATA_COMPARATOR_VALUE12",\r
 143         "ETM_DATA_COMPARATOR_VALUE13",\r
 144         "ETM_DATA_COMPARATOR_VALUE14",\r
 145         "ETM_DATA_COMPARATOR_VALUE15",\r
 146         "ETM_DATA_COMPARATOR_VALUE16",\r
 147         "ETM_DATA_COMPARATOR_MASK1",\r
 148         "ETM_DATA_COMPARATOR_MASK2",\r
 149         "ETM_DATA_COMPARATOR_MASK3",\r
 150         "ETM_DATA_COMPARATOR_MASK4",\r
 151         "ETM_DATA_COMPARATOR_MASK5",\r
 152         "ETM_DATA_COMPARATOR_MASK6",\r
 153         "ETM_DATA_COMPARATOR_MASK7",\r
 154         "ETM_DATA_COMPARATOR_MASK8",\r
 155         "ETM_DATA_COMPARATOR_MASK9",\r
 156         "ETM_DATA_COMPARATOR_MASK10",\r
 157         "ETM_DATA_COMPARATOR_MASK11",\r
 158         "ETM_DATA_COMPARATOR_MASK12",\r
 159         "ETM_DATA_COMPARATOR_MASK13",\r
 160         "ETM_DATA_COMPARATOR_MASK14",\r
 161         "ETM_DATA_COMPARATOR_MASK15",\r
 162         "ETM_DATA_COMPARATOR_MASK16",\r
 163         "ETM_COUNTER_INITAL_VALUE1",\r
 164         "ETM_COUNTER_INITAL_VALUE2",\r
 165         "ETM_COUNTER_INITAL_VALUE3",\r
 166         "ETM_COUNTER_INITAL_VALUE4",\r
 167         "ETM_COUNTER_ENABLE1",\r
 168         "ETM_COUNTER_ENABLE2",\r
 169         "ETM_COUNTER_ENABLE3",\r
 170         "ETM_COUNTER_ENABLE4",\r
 171         "ETM_COUNTER_RELOAD_VALUE1",\r
 172         "ETM_COUNTER_RELOAD_VALUE2",\r
 173         "ETM_COUNTER_RELOAD_VALUE3",\r
 174         "ETM_COUNTER_RELOAD_VALUE4",\r
 175         "ETM_COUNTER_VALUE1",\r
 176         "ETM_COUNTER_VALUE2",\r
 177         "ETM_COUNTER_VALUE3",\r
 178         "ETM_COUNTER_VALUE4",\r
 179         "ETM_SEQUENCER_CTRL1",\r
 180         "ETM_SEQUENCER_CTRL2",\r
 181         "ETM_SEQUENCER_CTRL3",\r
 182         "ETM_SEQUENCER_CTRL4",\r
 183         "ETM_SEQUENCER_CTRL5",\r
 184         "ETM_SEQUENCER_CTRL6",\r
 185         "ETM_SEQUENCER_STATE",\r
 186         "ETM_EXTERNAL_OUTPUT1",\r
 187         "ETM_EXTERNAL_OUTPUT2",\r
 188         "ETM_EXTERNAL_OUTPUT3",\r
 189         "ETM_EXTERNAL_OUTPUT4",\r
 190         "ETM_CONTEXTID_COMPARATOR_VALUE1",\r
 191         "ETM_CONTEXTID_COMPARATOR_VALUE2",\r
 192         "ETM_CONTEXTID_COMPARATOR_VALUE3",\r
 193         "ETM_CONTEXTID_COMPARATOR_MASK"\r
 194 };  \r
 195 \r
 196 int etm_reg_arch_type = -1;\r
 197 \r
 198 int etm_get_reg(reg_t *reg);\r
 199 int etm_set_reg(reg_t *reg, u32 value);\r
 200 \r
 201 int etm_write_reg(reg_t *reg, u32 value);\r
 202 int etm_read_reg(reg_t *reg);\r
 203 \r
 204 reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg)\r
 205 {\r
 206         reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));\r
 207         reg_t *reg_list = NULL;\r
 208         etm_reg_t *arch_info = NULL;\r
 209         int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);\r
 210         int i;\r
 211         \r
 212         /* register a register arch-type for etm registers only once */\r
 213         if (etm_reg_arch_type == -1)\r
 214                 etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);\r
 215         \r
 216         /* the actual registers are kept in two arrays */\r
 217         reg_list = calloc(num_regs, sizeof(reg_t));\r
 218         arch_info = calloc(num_regs, sizeof(etm_reg_t));\r
 219         \r
 220         /* fill in values for the reg cache */\r
 221         reg_cache->name = "etm registers";\r
 222         reg_cache->next = NULL;\r
 223         reg_cache->reg_list = reg_list;\r
 224         reg_cache->num_regs = num_regs;\r
 225         \r
 226         /* set up registers */\r
 227         for (i = 0; i < num_regs; i++)\r
 228         {\r
 229                 reg_list[i].name = etm_reg_list[i];\r
 230                 reg_list[i].size = 32;\r
 231                 reg_list[i].dirty = 0;\r
 232                 reg_list[i].valid = 0;\r
 233                 reg_list[i].bitfield_desc = NULL;\r
 234                 reg_list[i].num_bitfields = 0;\r
 235                 reg_list[i].value = calloc(1, 4);\r
 236                 reg_list[i].arch_info = &arch_info[i];\r
 237                 reg_list[i].arch_type = etm_reg_arch_type;\r
 238                 reg_list[i].size = etm_reg_arch_size_info[i];\r
 239                 arch_info[i].addr = etm_reg_arch_info[i];\r
 240                 arch_info[i].jtag_info = jtag_info;\r
 241         }\r
 242         return reg_cache;\r
 243 }\r
 244 \r
 245 int etm_get_reg(reg_t *reg)\r
 246 {\r
 247         if (etm_read_reg(reg) != ERROR_OK)\r
 248         {\r
 249                 ERROR("BUG: error scheduling etm register read");\r
 250                 exit(-1);\r
 251         }\r
 252         \r
 253         if (jtag_execute_queue() != ERROR_OK)\r
 254         {\r
 255                 ERROR("register read failed");\r
 256         }\r
 257         \r
 258         return ERROR_OK;\r
 259 }\r
 260 \r
 261 int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)\r
 262 {\r
 263         etm_reg_t *etm_reg = reg->arch_info;\r
 264         u8 reg_addr = etm_reg->addr & 0x7f;\r
 265         scan_field_t fields[3];\r
 266         \r
 267         DEBUG("%i", etm_reg->addr);\r
 268 \r
 269         jtag_add_end_state(TAP_RTI);\r
 270         arm_jtag_scann(etm_reg->jtag_info, 0x6);\r
 271         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr);\r
 272         \r
 273         fields[0].device = etm_reg->jtag_info->chain_pos;\r
 274         fields[0].num_bits = 32;\r
 275         fields[0].out_value = reg->value;\r
 276         fields[0].out_mask = NULL;\r
 277         fields[0].in_value = NULL;\r
 278         fields[0].in_check_value = NULL;\r
 279         fields[0].in_check_mask = NULL;\r
 280         fields[0].in_handler = NULL;\r
 281         fields[0].in_handler_priv = NULL;\r
 282         \r
 283         fields[1].device = etm_reg->jtag_info->chain_pos;\r
 284         fields[1].num_bits = 7;\r
 285         fields[1].out_value = malloc(1);\r
 286         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);\r
 287         fields[1].out_mask = NULL;\r
 288         fields[1].in_value = NULL;\r
 289         fields[1].in_check_value = NULL;\r
 290         fields[1].in_check_mask = NULL;\r
 291         fields[1].in_handler = NULL;\r
 292         fields[1].in_handler_priv = NULL;\r
 293 \r
 294         fields[2].device = etm_reg->jtag_info->chain_pos;\r
 295         fields[2].num_bits = 1;\r
 296         fields[2].out_value = malloc(1);\r
 297         buf_set_u32(fields[2].out_value, 0, 1, 0);\r
 298         fields[2].out_mask = NULL;\r
 299         fields[2].in_value = NULL;\r
 300         fields[2].in_check_value = NULL;\r
 301         fields[2].in_check_mask = NULL;\r
 302         fields[2].in_handler = NULL;\r
 303         fields[2].in_handler_priv = NULL;\r
 304         \r
 305         jtag_add_dr_scan(3, fields, -1);\r
 306         \r
 307         fields[0].in_value = reg->value;\r
 308         fields[0].in_check_value = check_value;\r
 309         fields[0].in_check_mask = check_mask;\r
 310                 \r
 311         jtag_add_dr_scan(3, fields, -1);\r
 312 \r
 313         free(fields[1].out_value);\r
 314         free(fields[2].out_value);\r
 315         \r
 316         return ERROR_OK;\r
 317 }\r
 318 \r
 319 int etm_read_reg(reg_t *reg)\r
 320 {\r
 321         return etm_read_reg_w_check(reg, NULL, NULL);   \r
 322 }\r
 323 \r
 324 int etm_set_reg(reg_t *reg, u32 value)\r
 325 {\r
 326         if (etm_write_reg(reg, value) != ERROR_OK)\r
 327         {\r
 328                 ERROR("BUG: error scheduling etm register write");\r
 329                 exit(-1);\r
 330         }\r
 331         \r
 332         buf_set_u32(reg->value, 0, reg->size, value);\r
 333         reg->valid = 1;\r
 334         reg->dirty = 0;\r
 335         \r
 336         return ERROR_OK;\r
 337 }\r
 338 \r
 339 int etm_set_reg_w_exec(reg_t *reg, u32 value)\r
 340 {\r
 341         etm_set_reg(reg, value);\r
 342         \r
 343         if (jtag_execute_queue() != ERROR_OK)\r
 344         {\r
 345                 ERROR("register write failed");\r
 346                 exit(-1);\r
 347         }\r
 348         return ERROR_OK;\r
 349 }\r
 350 \r
 351 int etm_write_reg(reg_t *reg, u32 value)\r
 352 {\r
 353         etm_reg_t *etm_reg = reg->arch_info;\r
 354         u8 reg_addr = etm_reg->addr & 0x7f;\r
 355         scan_field_t fields[3];\r
 356         \r
 357         DEBUG("%i: 0x%8.8x", etm_reg->addr, value);\r
 358         \r
 359         jtag_add_end_state(TAP_RTI);\r
 360         arm_jtag_scann(etm_reg->jtag_info, 0x6);\r
 361         arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr);\r
 362         \r
 363         fields[0].device = etm_reg->jtag_info->chain_pos;\r
 364         fields[0].num_bits = 32;\r
 365         fields[0].out_value = malloc(4);\r
 366         buf_set_u32(fields[0].out_value, 0, 32, value);\r
 367         fields[0].out_mask = NULL;\r
 368         fields[0].in_value = NULL;\r
 369         fields[0].in_check_value = NULL;\r
 370         fields[0].in_check_mask = NULL;\r
 371         fields[0].in_handler = NULL;\r
 372         fields[0].in_handler_priv = NULL;\r
 373         \r
 374         fields[1].device = etm_reg->jtag_info->chain_pos;\r
 375         fields[1].num_bits = 7;\r
 376         fields[1].out_value = malloc(1);\r
 377         buf_set_u32(fields[1].out_value, 0, 7, reg_addr);\r
 378         fields[1].out_mask = NULL;\r
 379         fields[1].in_value = NULL;\r
 380         fields[1].in_check_value = NULL;\r
 381         fields[1].in_check_mask = NULL;\r
 382         fields[1].in_handler = NULL;\r
 383         fields[1].in_handler_priv = NULL;\r
 384 \r
 385         fields[2].device = etm_reg->jtag_info->chain_pos;\r
 386         fields[2].num_bits = 1;\r
 387         fields[2].out_value = malloc(1);\r
 388         buf_set_u32(fields[2].out_value, 0, 1, 1);\r
 389         fields[2].out_mask = NULL;\r
 390         fields[2].in_value = NULL;\r
 391         fields[2].in_check_value = NULL;\r
 392         fields[2].in_check_mask = NULL;\r
 393         fields[2].in_handler = NULL;\r
 394         fields[2].in_handler_priv = NULL;\r
 395         \r
 396         jtag_add_dr_scan(3, fields, -1);\r
 397         \r
 398         free(fields[0].out_value);\r
 399         free(fields[1].out_value);\r
 400         free(fields[2].out_value);\r
 401         \r
 402         return ERROR_OK;\r
 403 }\r
 404 \r
 405 int etm_store_reg(reg_t *reg)\r
 406 {\r
 407         return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));\r
 408 }\r
 409 \r