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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2018 by Square, Inc.                                    *
   5  *   Steven Stallion <stallion@squareup.com>                               *
   6  *   James Zhao <hjz@squareup.com>                                         *
   7  ***************************************************************************/
   8
   9 #ifndef OPENOCD_TARGET_ESIRISC_REGS_H
  10 #define OPENOCD_TARGET_ESIRISC_REGS_H
  11
  12 enum esirisc_reg_num {
  13         ESIRISC_SP,
  14         ESIRISC_RA,
  15         ESIRISC_R2,
  16         ESIRISC_R3,
  17         ESIRISC_R4,
  18         ESIRISC_R5,
  19         ESIRISC_R6,
  20         ESIRISC_R7,
  21         ESIRISC_R8,
  22         ESIRISC_R9,
  23         ESIRISC_R10,
  24         ESIRISC_R11,
  25         ESIRISC_R12,
  26         ESIRISC_R13,
  27         ESIRISC_R14,
  28         ESIRISC_R15,
  29         ESIRISC_R16,
  30         ESIRISC_R17,
  31         ESIRISC_R18,
  32         ESIRISC_R19,
  33         ESIRISC_R20,
  34         ESIRISC_R21,
  35         ESIRISC_R22,
  36         ESIRISC_R23,
  37         ESIRISC_R24,
  38         ESIRISC_R25,
  39         ESIRISC_R26,
  40         ESIRISC_R27,
  41         ESIRISC_R28,
  42         ESIRISC_R29,
  43         ESIRISC_R30,
  44         ESIRISC_R31,
  45
  46         ESIRISC_V0,
  47         ESIRISC_V1,
  48         ESIRISC_V2,
  49         ESIRISC_V3,
  50         ESIRISC_V4,
  51         ESIRISC_V5,
  52         ESIRISC_V6,
  53         ESIRISC_V7,
  54         ESIRISC_V8,
  55         ESIRISC_V9,
  56         ESIRISC_V10,
  57         ESIRISC_V11,
  58         ESIRISC_V12,
  59         ESIRISC_V13,
  60         ESIRISC_V14,
  61         ESIRISC_V15,
  62         ESIRISC_V16,
  63         ESIRISC_V17,
  64         ESIRISC_V18,
  65         ESIRISC_V19,
  66         ESIRISC_V20,
  67         ESIRISC_V21,
  68         ESIRISC_V22,
  69         ESIRISC_V23,
  70         ESIRISC_V24,
  71         ESIRISC_V25,
  72         ESIRISC_V26,
  73         ESIRISC_V27,
  74         ESIRISC_V28,
  75         ESIRISC_V29,
  76         ESIRISC_V30,
  77         ESIRISC_V31,
  78
  79         ESIRISC_A0,
  80         ESIRISC_A1,
  81         ESIRISC_A2,
  82         ESIRISC_A3,
  83         ESIRISC_A4,
  84         ESIRISC_A5,
  85         ESIRISC_A6,
  86         ESIRISC_A7,
  87
  88         ESIRISC_PC,
  89         ESIRISC_CAS,
  90         ESIRISC_TC,
  91         ESIRISC_ETA,
  92         ESIRISC_ETC,
  93         ESIRISC_EPC,
  94         ESIRISC_ECAS,
  95         ESIRISC_EID,
  96         ESIRISC_ED,
  97         ESIRISC_IP,
  98         ESIRISC_IM,
  99         ESIRISC_IS,
 100         ESIRISC_IT,
 101
 102         ESIRISC_NUM_REGS,
 103 };
 104
 105 /* CSR Banks */
 106 #define CSR_THREAD                                      0x00
 107 #define CSR_INTERRUPT                           0x01
 108 #define CSR_DEBUG                                       0x04
 109 #define CSR_CONFIG                                      0x05
 110 #define CSR_TRACE                                       0x09
 111
 112 /* Thread CSRs */
 113 #define CSR_THREAD_TC                           0x00    /* Thread Control */
 114 #define CSR_THREAD_PC                           0x01    /* Program Counter */
 115 #define CSR_THREAD_CAS                          0x02    /* Comparison & Arithmetic Status */
 116 #define CSR_THREAD_AC                           0x03    /* Arithmetic Control */
 117 #define CSR_THREAD_LF                           0x04    /* Locked Flag */
 118 #define CSR_THREAD_LA                           0x05    /* Locked Address */
 119 #define CSR_THREAD_ETA                          0x07    /* Exception Table Address */
 120 #define CSR_THREAD_ETC                          0x08    /* Exception TC */
 121 #define CSR_THREAD_EPC                          0x09    /* Exception PC */
 122 #define CSR_THREAD_ECAS                         0x0a    /* Exception CAS */
 123 #define CSR_THREAD_EID                          0x0b    /* Exception ID */
 124 #define CSR_THREAD_ED                           0x0c    /* Exception Data */
 125
 126 /* Interrupt CSRs */
 127 #define CSR_INTERRUPT_IP                        0x00    /* Interrupt Pending */
 128 #define CSR_INTERRUPT_IA                        0x01    /* Interrupt Acknowledge */
 129 #define CSR_INTERRUPT_IM                        0x02    /* Interrupt Mask */
 130 #define CSR_INTERRUPT_IS                        0x03    /* Interrupt Sense */
 131 #define CSR_INTERRUPT_IT                        0x04    /* Interrupt Trigger */
 132
 133 /* Debug CSRs */
 134 #define CSR_DEBUG_DC                            0x00    /* Debug Control */
 135 #define CSR_DEBUG_IBC                           0x01    /* Instruction Breakpoint Control */
 136 #define CSR_DEBUG_DBC                           0x02    /* Data Breakpoint Control */
 137 #define CSR_DEBUG_HWDC                          0x03    /* Hardware Debug Control */
 138 #define CSR_DEBUG_DBS                           0x04    /* Data Breakpoint Size */
 139 #define CSR_DEBUG_DBR                           0x05    /* Data Breakpoint Range */
 140 #define CSR_DEBUG_IBA_N                         0x08    /* Instruction Breakpoint Address [0..7] */
 141 #define CSR_DEBUG_DBA_N                         0x10    /* Data Breakpoint Address [0..7] */
 142
 143 /* Configuration CSRs */
 144 #define CSR_CONFIG_ARCH0                        0x00    /* Architectural Configuration 0 */
 145 #define CSR_CONFIG_ARCH1                        0x01    /* Architectural Configuration 1 */
 146 #define CSR_CONFIG_ARCH2                        0x02    /* Architectural Configuration 2 */
 147 #define CSR_CONFIG_ARCH3                        0x03    /* Architectural Configuration 3 */
 148 #define CSR_CONFIG_MEM                          0x04    /* Memory Configuration */
 149 #define CSR_CONFIG_IC                           0x05    /* Instruction Cache Configuration */
 150 #define CSR_CONFIG_DC                           0x06    /* Data Cache Configuration */
 151 #define CSR_CONFIG_INT                          0x07    /* Interrupt Configuration */
 152 #define CSR_CONFIG_ISA_N                        0x08    /* Instruction Set Configuration [0..6] */
 153 #define CSR_CONFIG_DBG                          0x0f    /* Debug Configuration */
 154 #define CSR_CONFIG_MID                          0x10    /* Manufacturer ID */
 155 #define CSR_CONFIG_REV                          0x11    /* Revision Number */
 156 #define CSR_CONFIG_MPID                         0x12    /* Multiprocessor ID */
 157 #define CSR_CONFIG_FREQ_N                       0x13    /* Frequency [0..2] */
 158 #define CSR_CONFIG_TRACE                        0x16    /* Trace Configuration */
 159
 160 /* Trace CSRs */
 161 #define CSR_TRACE_CONTROL                       0x00
 162 #define CSR_TRACE_STATUS                        0x01
 163 #define CSR_TRACE_BUFFER_START          0x02
 164 #define CSR_TRACE_BUFFER_END            0x03
 165 #define CSR_TRACE_BUFFER_CUR            0x04
 166 #define CSR_TRACE_TRIGGER                       0x05
 167 #define CSR_TRACE_START_DATA            0x06
 168 #define CSR_TRACE_START_MASK            0x07
 169 #define CSR_TRACE_STOP_DATA                     0x08
 170 #define CSR_TRACE_STOP_MASK                     0x09
 171 #define CSR_TRACE_DELAY                         0x0a
 172
 173 #endif /* OPENOCD_TARGET_ESIRISC_REGS_H */