git.gag.com Git - fw/openocd/blob - src/target/embeddedice.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifndef EMBEDDED_ICE_H
  21 #define EMBEDDED_ICE_H
  22
  23 #include "target.h"
  24 #include "register.h"
  25 #include "arm_jtag.h"
  26
  27 enum
  28 {
  29         EICE_DBG_CTRL = 0,
  30         EICE_DBG_STAT = 1,
  31         EICE_COMMS_CTRL = 2,
  32         EICE_COMMS_DATA = 3,
  33         EICE_W0_ADDR_VALUE = 4,
  34         EICE_W0_ADDR_MASK = 5,
  35         EICE_W0_DATA_VALUE  = 6,
  36         EICE_W0_DATA_MASK = 7,
  37         EICE_W0_CONTROL_VALUE = 8,
  38         EICE_W0_CONTROL_MASK = 9,
  39         EICE_W1_ADDR_VALUE = 10,
  40         EICE_W1_ADDR_MASK = 11,
  41         EICE_W1_DATA_VALUE = 12,
  42         EICE_W1_DATA_MASK = 13,
  43         EICE_W1_CONTROL_VALUE = 14,
  44         EICE_W1_CONTROL_MASK = 15
  45 };
  46
  47 enum
  48 {
  49         EICE_DBG_CONTROL_INTDIS = 2,
  50         EICE_DBG_CONTROL_DBGRQ = 1,
  51         EICE_DBG_CONTROL_DBGACK = 0,
  52 };
  53
  54 enum
  55 {
  56         EICE_DBG_STATUS_ITBIT = 4,
  57         EICE_DBG_STATUS_SYSCOMP = 3,
  58         EICE_DBG_STATUS_IFEN = 2,
  59         EICE_DBG_STATUS_DBGRQ = 1,
  60         EICE_DBG_STATUS_DBGACK = 0
  61 };
  62
  63 enum
  64 {
  65         EICE_W_CTRL_ENABLE = 0x100,
  66         EICE_W_CTRL_RANGE = 0x80,
  67         EICE_W_CTRL_CHAIN = 0x40,
  68         EICE_W_CTRL_EXTERN = 0x20,
  69         EICE_W_CTRL_nTRANS = 0x10,
  70         EICE_W_CTRL_nOPC = 0x8,
  71         EICE_W_CTRL_MAS = 0x6,
  72         EICE_W_CTRL_ITBIT = 0x2,
  73         EICE_W_CTRL_nRW = 0x1
  74 };
  75
  76 typedef struct embeddedice_reg_s
  77 {
  78         int addr;
  79         arm_jtag_t *jtag_info;
  80 } embeddedice_reg_t;
  81
  82 extern reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg);
  83 extern int embeddedice_read_reg(reg_t *reg);
  84 extern int embeddedice_write_reg(reg_t *reg, u32 value);
  85 extern int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
  86 extern int embeddedice_store_reg(reg_t *reg);
  87 extern int embeddedice_set_reg(reg_t *reg, u32 value);
  88 extern int embeddedice_set_reg_w_exec(reg_t *reg, u32 value);
  89
  90 #endif /* EMBEDDED_ICE_H */