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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41 #include "arm_semihosting.h"
  42 #include <helper/time_support.h>
  43
  44 /* NOTE:  most of this should work fine for the Cortex-M1 and
  45  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  46  * Some differences:  M0/M1 doesn't have FBP remapping or the
  47  * DWT tracing/profiling support.  (So the cycle counter will
  48  * not be usable; the other stuff isn't currently used here.)
  49  *
  50  * Although there are some workarounds for errata seen only in r0p0
  51  * silicon, such old parts are hard to find and thus not much tested
  52  * any longer.
  53  */
  54
  55 /**
  56  * Returns the type of a break point required by address location
  57  */
  58 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
  59
  60
  61 /* forward declarations */
  62 static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
  63 static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
  64 static void cortex_m3_enable_watchpoints(struct target *target);
  65 static int cortex_m3_store_core_reg_u32(struct target *target,
  66                 enum armv7m_regtype type, uint32_t num, uint32_t value);
  67
  68 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  69                 uint32_t *value, int regnum)
  70 {
  71         int retval;
  72         uint32_t dcrdr;
  73
  74         /* because the DCB_DCRDR is used for the emulated dcc channel
  75          * we have to save/restore the DCB_DCRDR when used */
  76
  77         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  78         if (retval != ERROR_OK)
  79                 return retval;
  80
  81         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  82         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  83         if (retval != ERROR_OK)
  84                 return retval;
  85         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  86         if (retval != ERROR_OK)
  87                 return retval;
  88
  89         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  90         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  91         if (retval != ERROR_OK)
  92                 return retval;
  93         retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  94         if (retval != ERROR_OK)
  95                 return retval;
  96
  97         retval = dap_run(swjdp);
  98         if (retval != ERROR_OK)
  99                 return retval;
 100
 101         /* restore DCB_DCRDR - this needs to be in a seperate
 102          * transaction otherwise the emulated DCC channel breaks */
 103         if (retval == ERROR_OK)
 104                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 105
 106         return retval;
 107 }
 108
 109 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 110                 uint32_t value, int regnum)
 111 {
 112         int retval;
 113         uint32_t dcrdr;
 114
 115         /* because the DCB_DCRDR is used for the emulated dcc channel
 116          * we have to save/restore the DCB_DCRDR when used */
 117
 118         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 119         if (retval != ERROR_OK)
 120                 return retval;
 121
 122         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 123         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 124         if (retval != ERROR_OK)
 125                 return retval;
 126         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 127         if (retval != ERROR_OK)
 128                 return retval;
 129
 130         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 131         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 132         if (retval != ERROR_OK)
 133                 return retval;
 134         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 135         if (retval != ERROR_OK)
 136                 return retval;
 137
 138         retval = dap_run(swjdp);
 139         if (retval != ERROR_OK)
 140                 return retval;
 141
 142         /* restore DCB_DCRDR - this needs to be in a seperate
 143          * transaction otherwise the emulated DCC channel breaks */
 144         if (retval == ERROR_OK)
 145                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 146
 147         return retval;
 148 }
 149
 150 static int cortex_m3_write_debug_halt_mask(struct target *target,
 151                 uint32_t mask_on, uint32_t mask_off)
 152 {
 153         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 154         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 155
 156         /* mask off status bits */
 157         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 158         /* create new register mask */
 159         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 160
 161         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 162 }
 163
 164 static int cortex_m3_clear_halt(struct target *target)
 165 {
 166         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 167         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 168         int retval;
 169
 170         /* clear step if any */
 171         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 172
 173         /* Read Debug Fault Status Register */
 174         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 175         if (retval != ERROR_OK)
 176                 return retval;
 177
 178         /* Clear Debug Fault Status */
 179         retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 180         if (retval != ERROR_OK)
 181                 return retval;
 182         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 183
 184         return ERROR_OK;
 185 }
 186
 187 static int cortex_m3_single_step_core(struct target *target)
 188 {
 189         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 190         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 191         uint32_t dhcsr_save;
 192         int retval;
 193
 194         /* backup dhcsr reg */
 195         dhcsr_save = cortex_m3->dcb_dhcsr;
 196
 197         /* Mask interrupts before clearing halt, if done already.  This avoids
 198          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 199          * HALT can put the core into an unknown state.
 200          */
 201         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
 202         {
 203                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 204                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 205                 if (retval != ERROR_OK)
 206                         return retval;
 207         }
 208         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 209                                 DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212         LOG_DEBUG(" ");
 213
 214         /* restore dhcsr reg */
 215         cortex_m3->dcb_dhcsr = dhcsr_save;
 216         cortex_m3_clear_halt(target);
 217
 218         return ERROR_OK;
 219 }
 220
 221 static int cortex_m3_endreset_event(struct target *target)
 222 {
 223         int i;
 224         int retval;
 225         uint32_t dcb_demcr;
 226         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 227         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 228         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 229         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 230         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 231
 232         /* REVISIT The four debug monitor bits are currently ignored... */
 233         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 234         if (retval != ERROR_OK)
 235                 return retval;
 236         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 237
 238         /* this register is used for emulated dcc channel */
 239         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 240         if (retval != ERROR_OK)
 241                 return retval;
 242
 243         /* Enable debug requests */
 244         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 245         if (retval != ERROR_OK)
 246                 return retval;
 247         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
 248         {
 249                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 250                 if (retval != ERROR_OK)
 251                         return retval;
 252         }
 253
 254         /* clear any interrupt masking */
 255         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 256
 257         /* Enable features controlled by ITM and DWT blocks, and catch only
 258          * the vectors we were told to pay attention to.
 259          *
 260          * Target firmware is responsible for all fault handling policy
 261          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 262          * or manual updates to the NVIC SHCSR and CCR registers.
 263          */
 264         retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 265         if (retval != ERROR_OK)
 266                 return retval;
 267
 268         /* Paranoia: evidently some (early?) chips don't preserve all the
 269          * debug state (including FBP, DWT, etc) across reset...
 270          */
 271
 272         /* Enable FPB */
 273         retval = target_write_u32(target, FP_CTRL, 3);
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         cortex_m3->fpb_enabled = 1;
 278
 279         /* Restore FPB registers */
 280         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
 281         {
 282                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 283                 if (retval != ERROR_OK)
 284                         return retval;
 285         }
 286
 287         /* Restore DWT registers */
 288         for (i = 0; i < cortex_m3->dwt_num_comp; i++)
 289         {
 290                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 291                                 dwt_list[i].comp);
 292                 if (retval != ERROR_OK)
 293                         return retval;
 294                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 295                                 dwt_list[i].mask);
 296                 if (retval != ERROR_OK)
 297                         return retval;
 298                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 299                                 dwt_list[i].function);
 300                 if (retval != ERROR_OK)
 301                         return retval;
 302         }
 303         retval = dap_run(swjdp);
 304         if (retval != ERROR_OK)
 305                 return retval;
 306
 307         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 308
 309         /* make sure we have latest dhcsr flags */
 310         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 311
 312         return retval;
 313 }
 314
 315 static int cortex_m3_examine_debug_reason(struct target *target)
 316 {
 317         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 318
 319         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
 320         /* only check the debug reason if we don't know it already */
 321
 322         if ((target->debug_reason != DBG_REASON_DBGRQ)
 323                 && (target->debug_reason != DBG_REASON_SINGLESTEP))
 324         {
 325                 if (cortex_m3->nvic_dfsr & DFSR_BKPT)
 326                 {
 327                         target->debug_reason = DBG_REASON_BREAKPOINT;
 328                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 329                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 330                 }
 331                 else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 332                         target->debug_reason = DBG_REASON_WATCHPOINT;
 333                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 334                         target->debug_reason = DBG_REASON_BREAKPOINT;
 335                 else /* EXTERNAL, HALTED */
 336                         target->debug_reason = DBG_REASON_UNDEFINED;
 337         }
 338
 339         return ERROR_OK;
 340 }
 341
 342 static int cortex_m3_examine_exception_reason(struct target *target)
 343 {
 344         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 345         struct armv7m_common *armv7m = target_to_armv7m(target);
 346         struct adiv5_dap *swjdp = &armv7m->dap;
 347         int retval;
 348
 349         retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 350         if (retval != ERROR_OK)
 351                 return retval;
 352         switch (armv7m->exception_number)
 353         {
 354                 case 2: /* NMI */
 355                         break;
 356                 case 3: /* Hard Fault */
 357                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 358                         if (retval != ERROR_OK)
 359                                 return retval;
 360                         if (except_sr & 0x40000000)
 361                         {
 362                                 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 363                                 if (retval != ERROR_OK)
 364                                         return retval;
 365                         }
 366                         break;
 367                 case 4: /* Memory Management */
 368                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 369                         if (retval != ERROR_OK)
 370                                 return retval;
 371                         retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 372                         if (retval != ERROR_OK)
 373                                 return retval;
 374                         break;
 375                 case 5: /* Bus Fault */
 376                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 377                         if (retval != ERROR_OK)
 378                                 return retval;
 379                         retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 380                         if (retval != ERROR_OK)
 381                                 return retval;
 382                         break;
 383                 case 6: /* Usage Fault */
 384                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 385                         if (retval != ERROR_OK)
 386                                 return retval;
 387                         break;
 388                 case 11:        /* SVCall */
 389                         break;
 390                 case 12:        /* Debug Monitor */
 391                         retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 392                         if (retval != ERROR_OK)
 393                                 return retval;
 394                         break;
 395                 case 14:        /* PendSV */
 396                         break;
 397                 case 15:        /* SysTick */
 398                         break;
 399                 default:
 400                         except_sr = 0;
 401                         break;
 402         }
 403         retval = dap_run(swjdp);
 404         if (retval == ERROR_OK)
 405                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 406                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 407                         armv7m_exception_string(armv7m->exception_number),
 408                         shcsr, except_sr, cfsr, except_ar);
 409         return retval;
 410 }
 411
 412 /* PSP is used in some thread modes */
 413 static const int armv7m_psp_reg_map[17] = {
 414         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 415         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 416         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 417         ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
 418         ARMV7M_xPSR,
 419 };
 420
 421 /* MSP is used in handler and some thread modes */
 422 static const int armv7m_msp_reg_map[17] = {
 423         ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
 424         ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
 425         ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
 426         ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
 427         ARMV7M_xPSR,
 428 };
 429
 430 static int cortex_m3_debug_entry(struct target *target)
 431 {
 432         int i;
 433         uint32_t xPSR;
 434         int retval;
 435         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 436         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 437         struct arm *arm = &armv7m->arm;
 438         struct adiv5_dap *swjdp = &armv7m->dap;
 439         struct reg *r;
 440
 441         LOG_DEBUG(" ");
 442
 443         cortex_m3_clear_halt(target);
 444         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 445         if (retval != ERROR_OK)
 446                 return retval;
 447
 448         if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
 449                 return retval;
 450
 451         /* Examine target state and mode */
 452         /* First load register acessible through core debug port*/
 453         int num_regs = armv7m->core_cache->num_regs;
 454
 455         for (i = 0; i < num_regs; i++)
 456         {
 457                 if (!armv7m->core_cache->reg_list[i].valid)
 458                         armv7m->read_core_reg(target, i);
 459         }
 460
 461         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 462         xPSR = buf_get_u32(r->value, 0, 32);
 463
 464 #ifdef ARMV7_GDB_HACKS
 465         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 466          * Instead, each CM3 should have its own dummy value...
 467          */
 468         /* copy real xpsr reg for gdb, setting thumb bit */
 469         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 470         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 471         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 472         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 473 #endif
 474
 475         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 476         if (xPSR & 0xf00)
 477         {
 478                 r->dirty = r->valid;
 479                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
 480         }
 481
 482         /* Are we in an exception handler */
 483         if (xPSR & 0x1FF)
 484         {
 485                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 486                 armv7m->exception_number = (xPSR & 0x1FF);
 487
 488                 arm->core_mode = ARM_MODE_HANDLER;
 489                 arm->map = armv7m_msp_reg_map;
 490         }
 491         else
 492         {
 493                 unsigned control = buf_get_u32(armv7m->core_cache
 494                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 495
 496                 /* is this thread privileged? */
 497                 armv7m->core_mode = control & 1;
 498                 arm->core_mode = armv7m->core_mode
 499                                 ? ARM_MODE_USER_THREAD
 500                                 : ARM_MODE_THREAD;
 501
 502                 /* which stack is it using? */
 503                 if (control & 2)
 504                         arm->map = armv7m_psp_reg_map;
 505                 else
 506                         arm->map = armv7m_msp_reg_map;
 507
 508                 armv7m->exception_number = 0;
 509         }
 510
 511         if (armv7m->exception_number)
 512         {
 513                 cortex_m3_examine_exception_reason(target);
 514         }
 515
 516         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 517                 armv7m_mode_strings[armv7m->core_mode],
 518                 *(uint32_t*)(arm->pc->value),
 519                 target_state_name(target));
 520
 521         if (armv7m->post_debug_entry)
 522         {
 523                 retval = armv7m->post_debug_entry(target);
 524                 if (retval != ERROR_OK)
 525                         return retval;
 526         }
 527
 528         return ERROR_OK;
 529 }
 530
 531 static int cortex_m3_poll(struct target *target)
 532 {
 533         int detected_failure = ERROR_OK;
 534         int retval = ERROR_OK;
 535         enum target_state prev_target_state = target->state;
 536         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 537         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 538
 539         /* Read from Debug Halting Control and Status Register */
 540         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 541         if (retval != ERROR_OK)
 542         {
 543                 target->state = TARGET_UNKNOWN;
 544                 return retval;
 545         }
 546
 547         /* Recover from lockup.  See ARMv7-M architecture spec,
 548          * section B1.5.15 "Unrecoverable exception cases".
 549          */
 550         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 551                 LOG_ERROR("%s -- clearing lockup after double fault",
 552                                 target_name(target));
 553                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 554                 target->debug_reason = DBG_REASON_DBGRQ;
 555
 556                 /* We have to execute the rest (the "finally" equivalent, but
 557                  * still throw this exception again).
 558                  */
 559                 detected_failure = ERROR_FAIL;
 560
 561                 /* refresh status bits */
 562                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 563                 if (retval != ERROR_OK)
 564                         return retval;
 565         }
 566
 567         if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 568         {
 569                 /* check if still in reset */
 570                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 571                 if (retval != ERROR_OK)
 572                         return retval;
 573
 574                 if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 575                 {
 576                         target->state = TARGET_RESET;
 577                         return ERROR_OK;
 578                 }
 579         }
 580
 581         if (target->state == TARGET_RESET)
 582         {
 583                 /* Cannot switch context while running so endreset is
 584                  * called with target->state == TARGET_RESET
 585                  */
 586                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 587                                 cortex_m3->dcb_dhcsr);
 588                 cortex_m3_endreset_event(target);
 589                 target->state = TARGET_RUNNING;
 590                 prev_target_state = TARGET_RUNNING;
 591         }
 592
 593         if (cortex_m3->dcb_dhcsr & S_HALT)
 594         {
 595                 target->state = TARGET_HALTED;
 596
 597                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET))
 598                 {
 599                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 600                                 return retval;
 601
 602                         if (arm_semihosting(target, &retval) != 0)
 603                                 return retval;
 604
 605                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 606                 }
 607                 if (prev_target_state == TARGET_DEBUG_RUNNING)
 608                 {
 609                         LOG_DEBUG(" ");
 610                         if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
 611                                 return retval;
 612
 613                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 614                 }
 615         }
 616
 617         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 618          * How best to model low power modes?
 619          */
 620
 621         if (target->state == TARGET_UNKNOWN)
 622         {
 623                 /* check if processor is retiring instructions */
 624                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST)
 625                 {
 626                         target->state = TARGET_RUNNING;
 627                         retval = ERROR_OK;
 628                 }
 629         }
 630
 631         /* Did we detect a failure condition that we cleared? */
 632         if (detected_failure != ERROR_OK)
 633                 retval = detected_failure;
 634         return retval;
 635 }
 636
 637 static int cortex_m3_halt(struct target *target)
 638 {
 639         LOG_DEBUG("target->state: %s",
 640                 target_state_name(target));
 641
 642         if (target->state == TARGET_HALTED)
 643         {
 644                 LOG_DEBUG("target was already halted");
 645                 return ERROR_OK;
 646         }
 647
 648         if (target->state == TARGET_UNKNOWN)
 649         {
 650                 LOG_WARNING("target was in unknown state when halt was requested");
 651         }
 652
 653         if (target->state == TARGET_RESET)
 654         {
 655                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst())
 656                 {
 657                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 658                         return ERROR_TARGET_FAILURE;
 659                 }
 660                 else
 661                 {
 662                         /* we came here in a reset_halt or reset_init sequence
 663                          * debug entry was already prepared in cortex_m3_prepare_reset_halt()
 664                          */
 665                         target->debug_reason = DBG_REASON_DBGRQ;
 666
 667                         return ERROR_OK;
 668                 }
 669         }
 670
 671         /* Write to Debug Halting Control and Status Register */
 672         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 673
 674         target->debug_reason = DBG_REASON_DBGRQ;
 675
 676         return ERROR_OK;
 677 }
 678
 679 static int cortex_m3_soft_reset_halt(struct target *target)
 680 {
 681         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 682         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 683         uint32_t dcb_dhcsr = 0;
 684         int retval, timeout = 0;
 685
 686         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 687         retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
 688                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 689         if (retval != ERROR_OK)
 690                 return retval;
 691
 692         /* Request a core-only reset */
 693         retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 694                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 695         if (retval != ERROR_OK)
 696                 return retval;
 697         target->state = TARGET_RESET;
 698
 699         /* registers are now invalid */
 700         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 701
 702         while (timeout < 100)
 703         {
 704                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 705                 if (retval == ERROR_OK)
 706                 {
 707                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 708                                         &cortex_m3->nvic_dfsr);
 709                         if (retval != ERROR_OK)
 710                                 return retval;
 711                         if ((dcb_dhcsr & S_HALT)
 712                                         && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 713                         {
 714                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 715                                         "DFSR 0x%08x",
 716                                         (unsigned) dcb_dhcsr,
 717                                         (unsigned) cortex_m3->nvic_dfsr);
 718                                 cortex_m3_poll(target);
 719                                 /* FIXME restore user's vector catch config */
 720                                 return ERROR_OK;
 721                         }
 722                         else
 723                                 LOG_DEBUG("waiting for system reset-halt, "
 724                                         "DHCSR 0x%08x, %d ms",
 725                                         (unsigned) dcb_dhcsr, timeout);
 726                 }
 727                 timeout++;
 728                 alive_sleep(1);
 729         }
 730
 731         return ERROR_OK;
 732 }
 733
 734 static void cortex_m3_enable_breakpoints(struct target *target)
 735 {
 736         struct breakpoint *breakpoint = target->breakpoints;
 737
 738         /* set any pending breakpoints */
 739         while (breakpoint)
 740         {
 741                 if (!breakpoint->set)
 742                         cortex_m3_set_breakpoint(target, breakpoint);
 743                 breakpoint = breakpoint->next;
 744         }
 745 }
 746
 747 static int cortex_m3_resume(struct target *target, int current,
 748                 uint32_t address, int handle_breakpoints, int debug_execution)
 749 {
 750         struct armv7m_common *armv7m = target_to_armv7m(target);
 751         struct breakpoint *breakpoint = NULL;
 752         uint32_t resume_pc;
 753         struct reg *r;
 754
 755         if (target->state != TARGET_HALTED)
 756         {
 757                 LOG_WARNING("target not halted");
 758                 return ERROR_TARGET_NOT_HALTED;
 759         }
 760
 761         if (!debug_execution)
 762         {
 763                 target_free_all_working_areas(target);
 764                 cortex_m3_enable_breakpoints(target);
 765                 cortex_m3_enable_watchpoints(target);
 766         }
 767
 768         if (debug_execution)
 769         {
 770                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 771
 772                 /* Disable interrupts */
 773                 /* We disable interrupts in the PRIMASK register instead of
 774                  * masking with C_MASKINTS.  This is probably the same issue
 775                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 776                  * in parallel with disabled interrupts can cause local faults
 777                  * to not be taken.
 778                  *
 779                  * REVISIT this clearly breaks non-debug execution, since the
 780                  * PRIMASK register state isn't saved/restored...  workaround
 781                  * by never resuming app code after debug execution.
 782                  */
 783                 buf_set_u32(r->value, 0, 1, 1);
 784                 r->dirty = true;
 785                 r->valid = true;
 786
 787                 /* Make sure we are in Thumb mode */
 788                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 789                 buf_set_u32(r->value, 24, 1, 1);
 790                 r->dirty = true;
 791                 r->valid = true;
 792         }
 793
 794         /* current = 1: continue on current pc, otherwise continue at <address> */
 795         r = armv7m->arm.pc;
 796         if (!current)
 797         {
 798                 buf_set_u32(r->value, 0, 32, address);
 799                 r->dirty = true;
 800                 r->valid = true;
 801         }
 802
 803         /* if we halted last time due to a bkpt instruction
 804          * then we have to manually step over it, otherwise
 805          * the core will break again */
 806
 807         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 808                         && !debug_execution)
 809         {
 810                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 811         }
 812
 813         resume_pc = buf_get_u32(r->value, 0, 32);
 814
 815         armv7m_restore_context(target);
 816
 817         /* the front-end may request us not to handle breakpoints */
 818         if (handle_breakpoints)
 819         {
 820                 /* Single step past breakpoint at current address */
 821                 if ((breakpoint = breakpoint_find(target, resume_pc)))
 822                 {
 823                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 824                                           breakpoint->address,
 825                                           breakpoint->unique_id);
 826                         cortex_m3_unset_breakpoint(target, breakpoint);
 827                         cortex_m3_single_step_core(target);
 828                         cortex_m3_set_breakpoint(target, breakpoint);
 829                 }
 830         }
 831
 832         /* Restart core */
 833         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 834
 835         target->debug_reason = DBG_REASON_NOTHALTED;
 836
 837         /* registers are now invalid */
 838         register_cache_invalidate(armv7m->core_cache);
 839
 840         if (!debug_execution)
 841         {
 842                 target->state = TARGET_RUNNING;
 843                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 844                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 845         }
 846         else
 847         {
 848                 target->state = TARGET_DEBUG_RUNNING;
 849                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 850                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 851         }
 852
 853         return ERROR_OK;
 854 }
 855
 856 /* int irqstepcount = 0; */
 857 static int cortex_m3_step(struct target *target, int current,
 858                 uint32_t address, int handle_breakpoints)
 859 {
 860         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 861         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 862         struct adiv5_dap *swjdp = &armv7m->dap;
 863         struct breakpoint *breakpoint = NULL;
 864         struct reg *pc = armv7m->arm.pc;
 865         bool bkpt_inst_found = false;
 866         int retval;
 867         bool isr_timed_out = false;
 868
 869         if (target->state != TARGET_HALTED)
 870         {
 871                 LOG_WARNING("target not halted");
 872                 return ERROR_TARGET_NOT_HALTED;
 873         }
 874
 875         /* current = 1: continue on current pc, otherwise continue at <address> */
 876         if (!current)
 877                 buf_set_u32(pc->value, 0, 32, address);
 878
 879         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 880
 881         /* the front-end may request us not to handle breakpoints */
 882         if (handle_breakpoints) {
 883                 breakpoint = breakpoint_find(target, pc_value);
 884                 if (breakpoint)
 885                         cortex_m3_unset_breakpoint(target, breakpoint);
 886         }
 887
 888         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 889
 890         target->debug_reason = DBG_REASON_SINGLESTEP;
 891
 892         armv7m_restore_context(target);
 893
 894         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 895
 896         /* if no bkpt instruction is found at pc then we can perform
 897          * a normal step, otherwise we have to manually step over the bkpt
 898          * instruction - as such simulate a step */
 899         if (bkpt_inst_found == false)
 900         {
 901                 /* Automatic ISR masking mode off: Just step over the next instruction */
 902                 if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
 903                 {
 904                         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 905                 }
 906                 else
 907                 {
 908                         /* Process interrupts during stepping in a way they don't interfere
 909                          * debugging.
 910                          *
 911                          * Principle:
 912                          *
 913                          * Set a temporary break point at the current pc and let the core run
 914                          * with interrupts enabled. Pending interrupts get served and we run
 915                          * into the breakpoint again afterwards. Then we step over the next
 916                          * instruction with interrupts disabled.
 917                          *
 918                          * If the pending interrupts don't complete within time, we leave the
 919                          * core running. This may happen if the interrupts trigger faster
 920                          * than the core can process them or the handler doesn't return.
 921                          *
 922                          * If no more breakpoints are available we simply do a step with
 923                          * interrupts enabled.
 924                          *
 925                          */
 926
 927                         /* Set a temporary break point */
 928                         retval = breakpoint_add(target, pc_value , 2, BKPT_TYPE_BY_ADDR(pc_value));
 929                         bool tmp_bp_set = (retval == ERROR_OK);
 930
 931                         /* No more breakpoints left, just do a step */
 932                         if (!tmp_bp_set)
 933                         {
 934                                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 935                         }
 936                         else
 937                         {
 938                                 /* Start the core */
 939                                 LOG_DEBUG("Starting core to serve pending interrupts");
 940                                 int64_t t_start = timeval_ms();
 941                                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 942
 943                                 /* Wait for pending handlers to complete or timeout */
 944                                 do {
 945                                         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 946                                         if (retval != ERROR_OK)
 947                                         {
 948                                                 target->state = TARGET_UNKNOWN;
 949                                                 return retval;
 950                                         }
 951                                         isr_timed_out = ((timeval_ms() - t_start) > 500);
 952                                 } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
 953
 954                                 /* Remove the temporary breakpoint */
 955                                 breakpoint_remove(target, pc_value);
 956
 957                                 if (isr_timed_out)
 958                                 {
 959                                         LOG_DEBUG("Interrupt handlers didn't complete within time, "
 960                                                         "leaving target running");
 961                                 }
 962                                 else
 963                                 {
 964                                         /* Step over next instruction with interrupts disabled */
 965                                         cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
 966                                         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 967                                         /* Re-enable interrupts */
 968                                         cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 969                                 }
 970                         }
 971                 }
 972         }
 973
 974         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 975         if (retval != ERROR_OK)
 976                 return retval;
 977
 978         /* registers are now invalid */
 979         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 980
 981         if (breakpoint)
 982                 cortex_m3_set_breakpoint(target, breakpoint);
 983
 984         if (isr_timed_out) {
 985                 /* Leave the core running. The user has to stop execution manually. */
 986                 target->debug_reason = DBG_REASON_NOTHALTED;
 987                 target->state = TARGET_RUNNING;
 988                 return ERROR_OK;
 989         }
 990
 991         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 992                         " nvic_icsr = 0x%" PRIx32,
 993                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 994
 995         retval = cortex_m3_debug_entry(target);
 996         if (retval != ERROR_OK)
 997                 return retval;
 998         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 999
1000         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1001                         " nvic_icsr = 0x%" PRIx32,
1002                         cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
1003
1004         return ERROR_OK;
1005 }
1006
1007 static int cortex_m3_assert_reset(struct target *target)
1008 {
1009         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1010         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1011         enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
1012
1013         LOG_DEBUG("target->state: %s",
1014                 target_state_name(target));
1015
1016         enum reset_types jtag_reset_config = jtag_get_reset_config();
1017
1018         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
1019                 /* allow scripts to override the reset event */
1020
1021                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
1022                 register_cache_invalidate(cortex_m3->armv7m.core_cache);
1023                 target->state = TARGET_RESET;
1024
1025                 return ERROR_OK;
1026         }
1027
1028         /* Enable debug requests */
1029         int retval;
1030         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
1031         if (retval != ERROR_OK)
1032                 return retval;
1033         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
1034         {
1035                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
1036                 if (retval != ERROR_OK)
1037                         return retval;
1038         }
1039
1040         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
1041         if (retval != ERROR_OK)
1042                 return retval;
1043
1044         if (!target->reset_halt)
1045         {
1046                 /* Set/Clear C_MASKINTS in a separate operation */
1047                 if (cortex_m3->dcb_dhcsr & C_MASKINTS)
1048                 {
1049                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
1050                                         DBGKEY | C_DEBUGEN | C_HALT);
1051                         if (retval != ERROR_OK)
1052                                 return retval;
1053                 }
1054
1055                 /* clear any debug flags before resuming */
1056                 cortex_m3_clear_halt(target);
1057
1058                 /* clear C_HALT in dhcsr reg */
1059                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
1060         }
1061         else
1062         {
1063                 /* Halt in debug on reset; endreset_event() restores DEMCR.
1064                  *
1065                  * REVISIT catching BUSERR presumably helps to defend against
1066                  * bad vector table entries.  Should this include MMERR or
1067                  * other flags too?
1068                  */
1069                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
1070                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
1071                 if (retval != ERROR_OK)
1072                         return retval;
1073         }
1074
1075         if (jtag_reset_config & RESET_HAS_SRST)
1076         {
1077                 /* default to asserting srst */
1078                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1079                 {
1080                         jtag_add_reset(1, 1);
1081                 }
1082                 else
1083                 {
1084                         jtag_add_reset(0, 1);
1085                 }
1086         }
1087         else
1088         {
1089                 /* Use a standard Cortex-M3 software reset mechanism.
1090                  * We default to using VECRESET as it is supported on all current cores.
1091                  * This has the disadvantage of not resetting the peripherals, so a
1092                  * reset-init event handler is needed to perform any peripheral resets.
1093                  */
1094                 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1095                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1096                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1097                 if (retval != ERROR_OK)
1098                         return retval;
1099
1100                 LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1101                                 ? "SYSRESETREQ" : "VECTRESET");
1102
1103                 if (reset_config == CORTEX_M3_RESET_VECTRESET) {
1104                         LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1105                                         "handler to reset any peripherals");
1106                 }
1107
1108                 {
1109                         /* I do not know why this is necessary, but it
1110                          * fixes strange effects (step/resume cause NMI
1111                          * after reset) on LM3S6918 -- Michael Schwingen
1112                          */
1113                         uint32_t tmp;
1114                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1115                         if (retval != ERROR_OK)
1116                                 return retval;
1117                 }
1118         }
1119
1120         target->state = TARGET_RESET;
1121         jtag_add_sleep(50000);
1122
1123         register_cache_invalidate(cortex_m3->armv7m.core_cache);
1124
1125         if (target->reset_halt)
1126         {
1127                 if ((retval = target_halt(target)) != ERROR_OK)
1128                         return retval;
1129         }
1130
1131         return ERROR_OK;
1132 }
1133
1134 static int cortex_m3_deassert_reset(struct target *target)
1135 {
1136         LOG_DEBUG("target->state: %s",
1137                 target_state_name(target));
1138
1139         /* deassert reset lines */
1140         jtag_add_reset(0, 0);
1141
1142         return ERROR_OK;
1143 }
1144
1145 static int
1146 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1147 {
1148         int retval;
1149         int fp_num = 0;
1150         uint32_t hilo;
1151         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1152         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1153
1154         if (breakpoint->set)
1155         {
1156                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1157                 return ERROR_OK;
1158         }
1159
1160         if (cortex_m3->auto_bp_type)
1161         {
1162                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1163         }
1164
1165         if (breakpoint->type == BKPT_HARD)
1166         {
1167                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1168                         fp_num++;
1169                 if (fp_num >= cortex_m3->fp_num_code)
1170                 {
1171                         LOG_ERROR("Can not find free FPB Comparator!");
1172                         return ERROR_FAIL;
1173                 }
1174                 breakpoint->set = fp_num + 1;
1175                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1176                 comparator_list[fp_num].used = 1;
1177                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1178                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1179                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
1180                 if (!cortex_m3->fpb_enabled)
1181                 {
1182                         LOG_DEBUG("FPB wasn't enabled, do it now");
1183                         target_write_u32(target, FP_CTRL, 3);
1184                 }
1185         }
1186         else if (breakpoint->type == BKPT_SOFT)
1187         {
1188                 uint8_t code[4];
1189
1190                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1191                  * semihosting; don't use that.  Otherwise the BKPT
1192                  * parameter is arbitrary.
1193                  */
1194                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1195                 retval = target_read_memory(target,
1196                                 breakpoint->address & 0xFFFFFFFE,
1197                                 breakpoint->length, 1,
1198                                 breakpoint->orig_instr);
1199                 if (retval != ERROR_OK)
1200                         return retval;
1201                 retval = target_write_memory(target,
1202                                 breakpoint->address & 0xFFFFFFFE,
1203                                 breakpoint->length, 1,
1204                                 code);
1205                 if (retval != ERROR_OK)
1206                         return retval;
1207                 breakpoint->set = true;
1208         }
1209
1210         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1211                           breakpoint->unique_id,
1212                           (int)(breakpoint->type),
1213                           breakpoint->address,
1214                           breakpoint->length,
1215                           breakpoint->set);
1216
1217         return ERROR_OK;
1218 }
1219
1220 static int
1221 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1222 {
1223         int retval;
1224         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1225         struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
1226
1227         if (!breakpoint->set)
1228         {
1229                 LOG_WARNING("breakpoint not set");
1230                 return ERROR_OK;
1231         }
1232
1233         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1234                           breakpoint->unique_id,
1235                           (int)(breakpoint->type),
1236                           breakpoint->address,
1237                           breakpoint->length,
1238                           breakpoint->set);
1239
1240         if (breakpoint->type == BKPT_HARD)
1241         {
1242                 int fp_num = breakpoint->set - 1;
1243                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
1244                 {
1245                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1246                         return ERROR_OK;
1247                 }
1248                 comparator_list[fp_num].used = 0;
1249                 comparator_list[fp_num].fpcr_value = 0;
1250                 target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
1251         }
1252         else
1253         {
1254                 /* restore original instruction (kept in target endianness) */
1255                 if (breakpoint->length == 4)
1256                 {
1257                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
1258                         {
1259                                 return retval;
1260                         }
1261                 }
1262                 else
1263                 {
1264                         if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
1265                         {
1266                                 return retval;
1267                         }
1268                 }
1269         }
1270         breakpoint->set = false;
1271
1272         return ERROR_OK;
1273 }
1274
1275 static int
1276 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1277 {
1278         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1279
1280         if (cortex_m3->auto_bp_type)
1281         {
1282                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1283 #ifdef ARMV7_GDB_HACKS
1284                 if (breakpoint->length != 2) {
1285                         /* XXX Hack: Replace all breakpoints with length != 2 with
1286                          * a hardware breakpoint. */
1287                         breakpoint->type = BKPT_HARD;
1288                         breakpoint->length = 2;
1289                 }
1290 #endif
1291         }
1292
1293         if(breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1294                 if (breakpoint->type == BKPT_HARD)
1295                 {
1296                         LOG_INFO("flash patch comparator requested outside code memory region");
1297                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1298                 }
1299
1300                 if (breakpoint->type == BKPT_SOFT)
1301                 {
1302                         LOG_INFO("soft breakpoint requested in code (flash) memory region");
1303                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1304                 }
1305         }
1306
1307         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
1308         {
1309                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1310                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1311         }
1312
1313         if ((breakpoint->length != 2))
1314         {
1315                 LOG_INFO("only breakpoints of two bytes length supported");
1316                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1317         }
1318
1319         if (breakpoint->type == BKPT_HARD)
1320                 cortex_m3->fp_code_available--;
1321
1322         return cortex_m3_set_breakpoint(target, breakpoint);
1323 }
1324
1325 static int
1326 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1327 {
1328         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1329
1330         /* REVISIT why check? FBP can be updated with core running ... */
1331         if (target->state != TARGET_HALTED)
1332         {
1333                 LOG_WARNING("target not halted");
1334                 return ERROR_TARGET_NOT_HALTED;
1335         }
1336
1337         if (cortex_m3->auto_bp_type)
1338         {
1339                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1340         }
1341
1342         if (breakpoint->set)
1343         {
1344                 cortex_m3_unset_breakpoint(target, breakpoint);
1345         }
1346
1347         if (breakpoint->type == BKPT_HARD)
1348                 cortex_m3->fp_code_available++;
1349
1350         return ERROR_OK;
1351 }
1352
1353 static int
1354 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1355 {
1356         int dwt_num = 0;
1357         uint32_t mask, temp;
1358         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1359
1360         /* watchpoint params were validated earlier */
1361         mask = 0;
1362         temp = watchpoint->length;
1363         while (temp) {
1364                 temp >>= 1;
1365                 mask++;
1366         }
1367         mask--;
1368
1369         /* REVISIT Don't fully trust these "not used" records ... users
1370          * may set up breakpoints by hand, e.g. dual-address data value
1371          * watchpoint using comparator #1; comparator #0 matching cycle
1372          * count; send data trace info through ITM and TPIU; etc
1373          */
1374         struct cortex_m3_dwt_comparator *comparator;
1375
1376         for (comparator = cortex_m3->dwt_comparator_list;
1377                         comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1378                         comparator++, dwt_num++)
1379                 continue;
1380         if (dwt_num >= cortex_m3->dwt_num_comp)
1381         {
1382                 LOG_ERROR("Can not find free DWT Comparator");
1383                 return ERROR_FAIL;
1384         }
1385         comparator->used = 1;
1386         watchpoint->set = dwt_num + 1;
1387
1388         comparator->comp = watchpoint->address;
1389         target_write_u32(target, comparator->dwt_comparator_address + 0,
1390                         comparator->comp);
1391
1392         comparator->mask = mask;
1393         target_write_u32(target, comparator->dwt_comparator_address + 4,
1394                         comparator->mask);
1395
1396         switch (watchpoint->rw) {
1397         case WPT_READ:
1398                 comparator->function = 5;
1399                 break;
1400         case WPT_WRITE:
1401                 comparator->function = 6;
1402                 break;
1403         case WPT_ACCESS:
1404                 comparator->function = 7;
1405                 break;
1406         }
1407         target_write_u32(target, comparator->dwt_comparator_address + 8,
1408                         comparator->function);
1409
1410         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1411                         watchpoint->unique_id, dwt_num,
1412                         (unsigned) comparator->comp,
1413                         (unsigned) comparator->mask,
1414                         (unsigned) comparator->function);
1415         return ERROR_OK;
1416 }
1417
1418 static int
1419 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1420 {
1421         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1422         struct cortex_m3_dwt_comparator *comparator;
1423         int dwt_num;
1424
1425         if (!watchpoint->set)
1426         {
1427                 LOG_WARNING("watchpoint (wpid: %d) not set",
1428                                 watchpoint->unique_id);
1429                 return ERROR_OK;
1430         }
1431
1432         dwt_num = watchpoint->set - 1;
1433
1434         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1435                         watchpoint->unique_id, dwt_num,
1436                         (unsigned) watchpoint->address);
1437
1438         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
1439         {
1440                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1441                 return ERROR_OK;
1442         }
1443
1444         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1445         comparator->used = 0;
1446         comparator->function = 0;
1447         target_write_u32(target, comparator->dwt_comparator_address + 8,
1448                         comparator->function);
1449
1450         watchpoint->set = false;
1451
1452         return ERROR_OK;
1453 }
1454
1455 static int
1456 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1457 {
1458         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1459
1460         if (cortex_m3->dwt_comp_available < 1)
1461         {
1462                 LOG_DEBUG("no comparators?");
1463                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1464         }
1465
1466         /* hardware doesn't support data value masking */
1467         if (watchpoint->mask != ~(uint32_t)0) {
1468                 LOG_DEBUG("watchpoint value masks not supported");
1469                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1470         }
1471
1472         /* hardware allows address masks of up to 32K */
1473         unsigned mask;
1474
1475         for (mask = 0; mask < 16; mask++) {
1476                 if ((1u << mask) == watchpoint->length)
1477                         break;
1478         }
1479         if (mask == 16) {
1480                 LOG_DEBUG("unsupported watchpoint length");
1481                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1482         }
1483         if (watchpoint->address & ((1 << mask) - 1)) {
1484                 LOG_DEBUG("watchpoint address is unaligned");
1485                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1486         }
1487
1488         /* Caller doesn't seem to be able to describe watching for data
1489          * values of zero; that flags "no value".
1490          *
1491          * REVISIT This DWT may well be able to watch for specific data
1492          * values.  Requires comparator #1 to set DATAVMATCH and match
1493          * the data, and another comparator (DATAVADDR0) matching addr.
1494          */
1495         if (watchpoint->value) {
1496                 LOG_DEBUG("data value watchpoint not YET supported");
1497                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1498         }
1499
1500         cortex_m3->dwt_comp_available--;
1501         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1502
1503         return ERROR_OK;
1504 }
1505
1506 static int
1507 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1508 {
1509         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1510
1511         /* REVISIT why check? DWT can be updated with core running ... */
1512         if (target->state != TARGET_HALTED)
1513         {
1514                 LOG_WARNING("target not halted");
1515                 return ERROR_TARGET_NOT_HALTED;
1516         }
1517
1518         if (watchpoint->set)
1519         {
1520                 cortex_m3_unset_watchpoint(target, watchpoint);
1521         }
1522
1523         cortex_m3->dwt_comp_available++;
1524         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1525
1526         return ERROR_OK;
1527 }
1528
1529 static void cortex_m3_enable_watchpoints(struct target *target)
1530 {
1531         struct watchpoint *watchpoint = target->watchpoints;
1532
1533         /* set any pending watchpoints */
1534         while (watchpoint)
1535         {
1536                 if (!watchpoint->set)
1537                         cortex_m3_set_watchpoint(target, watchpoint);
1538                 watchpoint = watchpoint->next;
1539         }
1540 }
1541
1542 static int cortex_m3_load_core_reg_u32(struct target *target,
1543                 enum armv7m_regtype type, uint32_t num, uint32_t * value)
1544 {
1545         int retval;
1546         struct armv7m_common *armv7m = target_to_armv7m(target);
1547         struct adiv5_dap *swjdp = &armv7m->dap;
1548
1549         /* NOTE:  we "know" here that the register identifiers used
1550          * in the v7m header match the Cortex-M3 Debug Core Register
1551          * Selector values for R0..R15, xPSR, MSP, and PSP.
1552          */
1553         switch (num) {
1554         case 0 ... 18:
1555                 /* read a normal core register */
1556                 retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1557
1558                 if (retval != ERROR_OK)
1559                 {
1560                         LOG_ERROR("JTAG failure %i",retval);
1561                         return ERROR_JTAG_DEVICE_ERROR;
1562                 }
1563                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
1564                 break;
1565
1566         case ARMV7M_PRIMASK:
1567         case ARMV7M_BASEPRI:
1568         case ARMV7M_FAULTMASK:
1569         case ARMV7M_CONTROL:
1570                 /* Cortex-M3 packages these four registers as bitfields
1571                  * in one Debug Core register.  So say r0 and r2 docs;
1572                  * it was removed from r1 docs, but still works.
1573                  */
1574                 cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1575
1576                 switch (num)
1577                 {
1578                         case ARMV7M_PRIMASK:
1579                                 *value = buf_get_u32((uint8_t*)value, 0, 1);
1580                                 break;
1581
1582                         case ARMV7M_BASEPRI:
1583                                 *value = buf_get_u32((uint8_t*)value, 8, 8);
1584                                 break;
1585
1586                         case ARMV7M_FAULTMASK:
1587                                 *value = buf_get_u32((uint8_t*)value, 16, 1);
1588                                 break;
1589
1590                         case ARMV7M_CONTROL:
1591                                 *value = buf_get_u32((uint8_t*)value, 24, 2);
1592                                 break;
1593                 }
1594
1595                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1596                 break;
1597
1598         default:
1599                 return ERROR_INVALID_ARGUMENTS;
1600         }
1601
1602         return ERROR_OK;
1603 }
1604
1605 static int cortex_m3_store_core_reg_u32(struct target *target,
1606                 enum armv7m_regtype type, uint32_t num, uint32_t value)
1607 {
1608         int retval;
1609         uint32_t reg;
1610         struct armv7m_common *armv7m = target_to_armv7m(target);
1611         struct adiv5_dap *swjdp = &armv7m->dap;
1612
1613 #ifdef ARMV7_GDB_HACKS
1614         /* If the LR register is being modified, make sure it will put us
1615          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1616          * hack to deal with the fact that gdb will sometimes "forge"
1617          * return addresses, and doesn't set the LSB correctly (i.e., when
1618          * printing expressions containing function calls, it sets LR = 0.)
1619          * Valid exception return codes have bit 0 set too.
1620          */
1621         if (num == ARMV7M_R14)
1622                 value |= 0x01;
1623 #endif
1624
1625         /* NOTE:  we "know" here that the register identifiers used
1626          * in the v7m header match the Cortex-M3 Debug Core Register
1627          * Selector values for R0..R15, xPSR, MSP, and PSP.
1628          */
1629         switch (num) {
1630         case 0 ... 18:
1631                 retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1632                 if (retval != ERROR_OK)
1633                 {
1634                         struct reg *r;
1635
1636                         LOG_ERROR("JTAG failure");
1637                         r = armv7m->core_cache->reg_list + num;
1638                         r->dirty = r->valid;
1639                         return ERROR_JTAG_DEVICE_ERROR;
1640                 }
1641                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1642                 break;
1643
1644         case ARMV7M_PRIMASK:
1645         case ARMV7M_BASEPRI:
1646         case ARMV7M_FAULTMASK:
1647         case ARMV7M_CONTROL:
1648                 /* Cortex-M3 packages these four registers as bitfields
1649                  * in one Debug Core register.  So say r0 and r2 docs;
1650                  * it was removed from r1 docs, but still works.
1651                  */
1652                 cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1653
1654                 switch (num)
1655                 {
1656                         case ARMV7M_PRIMASK:
1657                                 buf_set_u32((uint8_t*)&reg, 0, 1, value);
1658                                 break;
1659
1660                         case ARMV7M_BASEPRI:
1661                                 buf_set_u32((uint8_t*)&reg, 8, 8, value);
1662                                 break;
1663
1664                         case ARMV7M_FAULTMASK:
1665                                 buf_set_u32((uint8_t*)&reg, 16, 1, value);
1666                                 break;
1667
1668                         case ARMV7M_CONTROL:
1669                                 buf_set_u32((uint8_t*)&reg, 24, 2, value);
1670                                 break;
1671                 }
1672
1673                 cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1674
1675                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1676                 break;
1677
1678         default:
1679                 return ERROR_INVALID_ARGUMENTS;
1680         }
1681
1682         return ERROR_OK;
1683 }
1684
1685 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1686                 uint32_t size, uint32_t count, uint8_t *buffer)
1687 {
1688         struct armv7m_common *armv7m = target_to_armv7m(target);
1689         struct adiv5_dap *swjdp = &armv7m->dap;
1690         int retval = ERROR_INVALID_ARGUMENTS;
1691
1692         /* cortex_m3 handles unaligned memory access */
1693         if (count && buffer) {
1694                 switch (size) {
1695                 case 4:
1696                         retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1697                         break;
1698                 case 2:
1699                         retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1700                         break;
1701                 case 1:
1702                         retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1703                         break;
1704                 }
1705         }
1706
1707         return retval;
1708 }
1709
1710 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1711                 uint32_t size, uint32_t count, const uint8_t *buffer)
1712 {
1713         struct armv7m_common *armv7m = target_to_armv7m(target);
1714         struct adiv5_dap *swjdp = &armv7m->dap;
1715         int retval = ERROR_INVALID_ARGUMENTS;
1716
1717         if (count && buffer) {
1718                 switch (size) {
1719                 case 4:
1720                         retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1721                         break;
1722                 case 2:
1723                         retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1724                         break;
1725                 case 1:
1726                         retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1727                         break;
1728                 }
1729         }
1730
1731         return retval;
1732 }
1733
1734 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1735                 uint32_t count, const uint8_t *buffer)
1736 {
1737         return cortex_m3_write_memory(target, address, 4, count, buffer);
1738 }
1739
1740 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1741                 struct target *target)
1742 {
1743         armv7m_build_reg_cache(target);
1744         return ERROR_OK;
1745 }
1746
1747 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1748  * on r/w if the core is not running, and clear on resume or reset ... or
1749  * at least, in a post_restore_context() method.
1750  */
1751
1752 struct dwt_reg_state {
1753         struct target   *target;
1754         uint32_t        addr;
1755         uint32_t        value;  /* scratch/cache */
1756 };
1757
1758 static int cortex_m3_dwt_get_reg(struct reg *reg)
1759 {
1760         struct dwt_reg_state *state = reg->arch_info;
1761
1762         return target_read_u32(state->target, state->addr, &state->value);
1763 }
1764
1765 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1766 {
1767         struct dwt_reg_state *state = reg->arch_info;
1768
1769         return target_write_u32(state->target, state->addr,
1770                         buf_get_u32(buf, 0, reg->size));
1771 }
1772
1773 struct dwt_reg {
1774         uint32_t        addr;
1775         char            *name;
1776         unsigned        size;
1777 };
1778
1779 static struct dwt_reg dwt_base_regs[] = {
1780         { DWT_CTRL, "dwt_ctrl", 32, },
1781         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1782          * increments while the core is asleep.
1783          */
1784         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1785         /* plus some 8 bit counters, useful for profiling with TPIU */
1786 };
1787
1788 static struct dwt_reg dwt_comp[] = {
1789 #define DWT_COMPARATOR(i) \
1790                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1791                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1792                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1793         DWT_COMPARATOR(0),
1794         DWT_COMPARATOR(1),
1795         DWT_COMPARATOR(2),
1796         DWT_COMPARATOR(3),
1797 #undef DWT_COMPARATOR
1798 };
1799
1800 static const struct reg_arch_type dwt_reg_type = {
1801         .get = cortex_m3_dwt_get_reg,
1802         .set = cortex_m3_dwt_set_reg,
1803 };
1804
1805 static void
1806 cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1807 {
1808         struct dwt_reg_state *state;
1809
1810         state = calloc(1, sizeof *state);
1811         if (!state)
1812                 return;
1813         state->addr = d->addr;
1814         state->target = t;
1815
1816         r->name = d->name;
1817         r->size = d->size;
1818         r->value = &state->value;
1819         r->arch_info = state;
1820         r->type = &dwt_reg_type;
1821 }
1822
1823 static void
1824 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1825 {
1826         uint32_t dwtcr;
1827         struct reg_cache *cache;
1828         struct cortex_m3_dwt_comparator *comparator;
1829         int reg, i;
1830
1831         target_read_u32(target, DWT_CTRL, &dwtcr);
1832         if (!dwtcr) {
1833                 LOG_DEBUG("no DWT");
1834                 return;
1835         }
1836
1837         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1838         cm3->dwt_comp_available = cm3->dwt_num_comp;
1839         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1840                         sizeof(struct cortex_m3_dwt_comparator));
1841         if (!cm3->dwt_comparator_list) {
1842 fail0:
1843                 cm3->dwt_num_comp = 0;
1844                 LOG_ERROR("out of mem");
1845                 return;
1846         }
1847
1848         cache = calloc(1, sizeof *cache);
1849         if (!cache) {
1850 fail1:
1851                 free(cm3->dwt_comparator_list);
1852                 goto fail0;
1853         }
1854         cache->name = "cortex-m3 dwt registers";
1855         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1856         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1857         if (!cache->reg_list) {
1858                 free(cache);
1859                 goto fail1;
1860         }
1861
1862         for (reg = 0; reg < 2; reg++)
1863                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1864                                 dwt_base_regs + reg);
1865
1866         comparator = cm3->dwt_comparator_list;
1867         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1868                 int j;
1869
1870                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1871                 for (j = 0; j < 3; j++, reg++)
1872                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1873                                         dwt_comp + 3 * i + j);
1874         }
1875
1876         *register_get_last_cache_p(&target->reg_cache) = cache;
1877         cm3->dwt_cache = cache;
1878
1879         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1880                         dwtcr, cm3->dwt_num_comp,
1881                         (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1882
1883         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1884          * implement single-address data value watchpoints ... so we
1885          * won't need to check it later, when asked to set one up.
1886          */
1887 }
1888
1889 static int cortex_m3_examine(struct target *target)
1890 {
1891         int retval;
1892         uint32_t cpuid, fpcr;
1893         int i;
1894         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1895         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1896
1897         if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
1898                 return retval;
1899
1900         if (!target_was_examined(target))
1901         {
1902                 target_set_examined(target);
1903
1904                 /* Read from Device Identification Registers */
1905                 retval = target_read_u32(target, CPUID, &cpuid);
1906                 if (retval != ERROR_OK)
1907                         return retval;
1908
1909                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1910                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1911                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1912                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1913
1914                 /* NOTE: FPB and DWT are both optional. */
1915
1916                 /* Setup FPB */
1917                 target_read_u32(target, FP_CTRL, &fpcr);
1918                 cortex_m3->auto_bp_type = 1;
1919                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
1920                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1921                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1922                 cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
1923                 cortex_m3->fpb_enabled = fpcr & 1;
1924                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
1925                 {
1926                         cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1927                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1928                 }
1929                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
1930
1931                 /* Setup DWT */
1932                 cortex_m3_dwt_setup(cortex_m3, target);
1933
1934                 /* These hardware breakpoints only work for code in flash! */
1935                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1936                                 target_name(target),
1937                                 cortex_m3->fp_num_code,
1938                                 cortex_m3->dwt_num_comp);
1939         }
1940
1941         return ERROR_OK;
1942 }
1943
1944 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1945 {
1946         uint16_t dcrdr;
1947         int retval;
1948
1949         mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1950         *ctrl = (uint8_t)dcrdr;
1951         *value = (uint8_t)(dcrdr >> 8);
1952
1953         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1954
1955         /* write ack back to software dcc register
1956          * signify we have read data */
1957         if (dcrdr & (1 << 0))
1958         {
1959                 dcrdr = 0;
1960                 retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
1961                 if (retval != ERROR_OK)
1962                         return retval;
1963         }
1964
1965         return ERROR_OK;
1966 }
1967
1968 static int cortex_m3_target_request_data(struct target *target,
1969                 uint32_t size, uint8_t *buffer)
1970 {
1971         struct armv7m_common *armv7m = target_to_armv7m(target);
1972         struct adiv5_dap *swjdp = &armv7m->dap;
1973         uint8_t data;
1974         uint8_t ctrl;
1975         uint32_t i;
1976
1977         for (i = 0; i < (size * 4); i++)
1978         {
1979                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1980                 buffer[i] = data;
1981         }
1982
1983         return ERROR_OK;
1984 }
1985
1986 static int cortex_m3_handle_target_request(void *priv)
1987 {
1988         struct target *target = priv;
1989         if (!target_was_examined(target))
1990                 return ERROR_OK;
1991         struct armv7m_common *armv7m = target_to_armv7m(target);
1992         struct adiv5_dap *swjdp = &armv7m->dap;
1993
1994         if (!target->dbg_msg_enabled)
1995                 return ERROR_OK;
1996
1997         if (target->state == TARGET_RUNNING)
1998         {
1999                 uint8_t data;
2000                 uint8_t ctrl;
2001
2002                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
2003
2004                 /* check if we have data */
2005                 if (ctrl & (1 << 0))
2006                 {
2007                         uint32_t request;
2008
2009                         /* we assume target is quick enough */
2010                         request = data;
2011                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
2012                         request |= (data << 8);
2013                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
2014                         request |= (data << 16);
2015                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
2016                         request |= (data << 24);
2017                         target_request(target, request);
2018                 }
2019         }
2020
2021         return ERROR_OK;
2022 }
2023
2024 static int cortex_m3_init_arch_info(struct target *target,
2025                 struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
2026 {
2027         int retval;
2028         struct armv7m_common *armv7m = &cortex_m3->armv7m;
2029
2030         armv7m_init_arch_info(target, armv7m);
2031
2032         /* prepare JTAG information for the new target */
2033         cortex_m3->jtag_info.tap = tap;
2034         cortex_m3->jtag_info.scann_size = 4;
2035
2036         /* default reset mode is to use srst if fitted
2037          * if not it will use CORTEX_M3_RESET_VECTRESET */
2038         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2039
2040         armv7m->arm.dap = &armv7m->dap;
2041
2042         /* Leave (only) generic DAP stuff for debugport_init(); */
2043         armv7m->dap.jtag_info = &cortex_m3->jtag_info;
2044         armv7m->dap.memaccess_tck = 8;
2045         /* Cortex-M3 has 4096 bytes autoincrement range */
2046         armv7m->dap.tar_autoincr_block = (1 << 12);
2047
2048         /* register arch-specific functions */
2049         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
2050
2051         armv7m->post_debug_entry = NULL;
2052
2053         armv7m->pre_restore_context = NULL;
2054
2055         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
2056         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
2057
2058         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
2059
2060         if ((retval = arm_jtag_setup_connection(&cortex_m3->jtag_info)) != ERROR_OK)
2061         {
2062                 return retval;
2063         }
2064
2065         return ERROR_OK;
2066 }
2067
2068 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
2069 {
2070         struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
2071
2072         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
2073         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
2074
2075         return ERROR_OK;
2076 }
2077
2078 /*--------------------------------------------------------------------------*/
2079
2080 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
2081                 struct cortex_m3_common *cm3)
2082 {
2083         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
2084                 command_print(cmd_ctx, "target is not a Cortex-M3");
2085                 return ERROR_TARGET_INVALID;
2086         }
2087         return ERROR_OK;
2088 }
2089
2090 /*
2091  * Only stuff below this line should need to verify that its target
2092  * is a Cortex-M3.  Everything else should have indirected through the
2093  * cortexm3_target structure, which is only used with CM3 targets.
2094  */
2095
2096 static const struct {
2097         char name[10];
2098         unsigned mask;
2099 } vec_ids[] = {
2100         { "hard_err",   VC_HARDERR, },
2101         { "int_err",    VC_INTERR, },
2102         { "bus_err",    VC_BUSERR, },
2103         { "state_err",  VC_STATERR, },
2104         { "chk_err",    VC_CHKERR, },
2105         { "nocp_err",   VC_NOCPERR, },
2106         { "mm_err",     VC_MMERR, },
2107         { "reset",      VC_CORERESET, },
2108 };
2109
2110 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
2111 {
2112         struct target *target = get_current_target(CMD_CTX);
2113         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2114         struct armv7m_common *armv7m = &cortex_m3->armv7m;
2115         struct adiv5_dap *swjdp = &armv7m->dap;
2116         uint32_t demcr = 0;
2117         int retval;
2118
2119         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2120         if (retval != ERROR_OK)
2121                 return retval;
2122
2123         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2124         if (retval != ERROR_OK)
2125                 return retval;
2126
2127         if (CMD_ARGC > 0) {
2128                 unsigned catch = 0;
2129
2130                 if (CMD_ARGC == 1) {
2131                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2132                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2133                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2134                                         | VC_MMERR | VC_CORERESET;
2135                                 goto write;
2136                         } else if (strcmp(CMD_ARGV[0], "none") == 0) {
2137                                 goto write;
2138                         }
2139                 }
2140                 while (CMD_ARGC-- > 0) {
2141                         unsigned i;
2142                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2143                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2144                                         continue;
2145                                 catch |= vec_ids[i].mask;
2146                                 break;
2147                         }
2148                         if (i == ARRAY_SIZE(vec_ids)) {
2149                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2150                                 return ERROR_INVALID_ARGUMENTS;
2151                         }
2152                 }
2153 write:
2154                 /* For now, armv7m->demcr only stores vector catch flags. */
2155                 armv7m->demcr = catch;
2156
2157                 demcr &= ~0xffff;
2158                 demcr |= catch;
2159
2160                 /* write, but don't assume it stuck (why not??) */
2161                 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2162                 if (retval != ERROR_OK)
2163                         return retval;
2164                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2165                 if (retval != ERROR_OK)
2166                         return retval;
2167
2168                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2169                  * Otherwise the vector catch hardware could fire when there's
2170                  * no debugger hooked up, causing much confusion...
2171                  */
2172         }
2173
2174         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)
2175         {
2176                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2177                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2178         }
2179
2180         return ERROR_OK;
2181 }
2182
2183 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2184 {
2185         struct target *target = get_current_target(CMD_CTX);
2186         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2187         int retval;
2188
2189         static const Jim_Nvp nvp_maskisr_modes[] = {
2190                 { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
2191                 { .name = "off" , .value = CORTEX_M3_ISRMASK_OFF },
2192                 { .name = "on"  , .value = CORTEX_M3_ISRMASK_ON },
2193                 { .name = NULL  , .value = -1 },
2194         };
2195         const Jim_Nvp *n;
2196
2197
2198         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2199         if (retval != ERROR_OK)
2200                 return retval;
2201
2202         if (target->state != TARGET_HALTED)
2203         {
2204                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2205                 return ERROR_OK;
2206         }
2207
2208         if (CMD_ARGC > 0)
2209         {
2210                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2211                 if (n->name == NULL)
2212                 {
2213                         return ERROR_COMMAND_SYNTAX_ERROR;
2214                 }
2215                 cortex_m3->isrmasking_mode = n->value;
2216
2217
2218                 if(cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
2219                 {
2220                         cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2221                 }
2222                 else
2223                 {
2224                         cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2225                 }
2226         }
2227
2228         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
2229         command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
2230
2231         return ERROR_OK;
2232 }
2233
2234 COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
2235 {
2236         struct target *target = get_current_target(CMD_CTX);
2237         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2238         int retval;
2239         char *reset_config;
2240
2241         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2242         if (retval != ERROR_OK)
2243                 return retval;
2244
2245         if (CMD_ARGC > 0)
2246         {
2247                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2248                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
2249                 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2250                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2251         }
2252
2253         switch (cortex_m3->soft_reset_config)
2254         {
2255                 case CORTEX_M3_RESET_SYSRESETREQ:
2256                         reset_config = "sysresetreq";
2257                         break;
2258
2259                 case CORTEX_M3_RESET_VECTRESET:
2260                         reset_config = "vectreset";
2261                         break;
2262
2263                 default:
2264                         reset_config = "unknown";
2265                         break;
2266         }
2267
2268         command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
2269
2270         return ERROR_OK;
2271 }
2272
2273 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2274         {
2275                 .name = "maskisr",
2276                 .handler = handle_cortex_m3_mask_interrupts_command,
2277                 .mode = COMMAND_EXEC,
2278                 .help = "mask cortex_m3 interrupts",
2279                 .usage = "['auto'|'on'|'off']",
2280         },
2281         {
2282                 .name = "vector_catch",
2283                 .handler = handle_cortex_m3_vector_catch_command,
2284                 .mode = COMMAND_EXEC,
2285                 .help = "configure hardware vectors to trigger debug entry",
2286                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2287         },
2288         {
2289                 .name = "reset_config",
2290                 .handler = handle_cortex_m3_reset_config_command,
2291                 .mode = COMMAND_ANY,
2292                 .help = "configure software reset handling",
2293                 .usage = "['srst'|'sysresetreq'|'vectreset']",
2294         },
2295         COMMAND_REGISTRATION_DONE
2296 };
2297 static const struct command_registration cortex_m3_command_handlers[] = {
2298         {
2299                 .chain = armv7m_command_handlers,
2300         },
2301         {
2302                 .name = "cortex_m3",
2303                 .mode = COMMAND_EXEC,
2304                 .help = "Cortex-M3 command group",
2305                 .chain = cortex_m3_exec_command_handlers,
2306         },
2307         COMMAND_REGISTRATION_DONE
2308 };
2309
2310 struct target_type cortexm3_target =
2311 {
2312         .name = "cortex_m3",
2313
2314         .poll = cortex_m3_poll,
2315         .arch_state = armv7m_arch_state,
2316
2317         .target_request_data = cortex_m3_target_request_data,
2318
2319         .halt = cortex_m3_halt,
2320         .resume = cortex_m3_resume,
2321         .step = cortex_m3_step,
2322
2323         .assert_reset = cortex_m3_assert_reset,
2324         .deassert_reset = cortex_m3_deassert_reset,
2325         .soft_reset_halt = cortex_m3_soft_reset_halt,
2326
2327         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2328
2329         .read_memory = cortex_m3_read_memory,
2330         .write_memory = cortex_m3_write_memory,
2331         .bulk_write_memory = cortex_m3_bulk_write_memory,
2332         .checksum_memory = armv7m_checksum_memory,
2333         .blank_check_memory = armv7m_blank_check_memory,
2334
2335         .run_algorithm = armv7m_run_algorithm,
2336         .start_algorithm = armv7m_start_algorithm,
2337         .wait_algorithm = armv7m_wait_algorithm,
2338
2339         .add_breakpoint = cortex_m3_add_breakpoint,
2340         .remove_breakpoint = cortex_m3_remove_breakpoint,
2341         .add_watchpoint = cortex_m3_add_watchpoint,
2342         .remove_watchpoint = cortex_m3_remove_watchpoint,
2343
2344         .commands = cortex_m3_command_handlers,
2345         .target_create = cortex_m3_target_create,
2346         .init_target = cortex_m3_init_target,
2347         .examine = cortex_m3_examine,
2348 };