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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2006 by Magnus Lundin                                   *
   6  *   lundin@mlu.mine.nu                                                    *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Spencer Oliver                                  *
   9  *   spen@spen-soft.co.uk                                                  *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  *                                                                         *
  26  *                                                                         *
  27  *   Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0)              *
  28  *                                                                         *
  29  ***************************************************************************/
  30 #ifdef HAVE_CONFIG_H
  31 #include "config.h"
  32 #endif
  33
  34 #include "breakpoints.h"
  35 #include "cortex_m.h"
  36 #include "target_request.h"
  37 #include "target_type.h"
  38 #include "arm_disassembler.h"
  39 #include "register.h"
  40 #include "arm_opcodes.h"
  41 #include "arm_semihosting.h"
  42 #include <helper/time_support.h>
  43
  44 /* NOTE:  most of this should work fine for the Cortex-M1 and
  45  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
  46  * Some differences:  M0/M1 doesn't have FBP remapping or the
  47  * DWT tracing/profiling support.  (So the cycle counter will
  48  * not be usable; the other stuff isn't currently used here.)
  49  *
  50  * Although there are some workarounds for errata seen only in r0p0
  51  * silicon, such old parts are hard to find and thus not much tested
  52  * any longer.
  53  */
  54
  55 /**
  56  * Returns the type of a break point required by address location
  57  */
  58 #define BKPT_TYPE_BY_ADDR(addr) ((addr) < 0x20000000 ? BKPT_HARD : BKPT_SOFT)
  59
  60
  61 /* forward declarations */
  62 static int cortex_m3_store_core_reg_u32(struct target *target,
  63         enum armv7m_regtype type, uint32_t num, uint32_t value);
  64
  65 static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
  66         uint32_t *value, int regnum)
  67 {
  68         int retval;
  69         uint32_t dcrdr;
  70
  71         /* because the DCB_DCRDR is used for the emulated dcc channel
  72          * we have to save/restore the DCB_DCRDR when used */
  73
  74         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
  75         if (retval != ERROR_OK)
  76                 return retval;
  77
  78         /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
  79         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
  80         if (retval != ERROR_OK)
  81                 return retval;
  82         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
  83         if (retval != ERROR_OK)
  84                 return retval;
  85
  86         /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
  87         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
  88         if (retval != ERROR_OK)
  89                 return retval;
  90         retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
  91         if (retval != ERROR_OK)
  92                 return retval;
  93
  94         retval = dap_run(swjdp);
  95         if (retval != ERROR_OK)
  96                 return retval;
  97
  98         /* restore DCB_DCRDR - this needs to be in a seperate
  99          * transaction otherwise the emulated DCC channel breaks */
 100         if (retval == ERROR_OK)
 101                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 102
 103         return retval;
 104 }
 105
 106 static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
 107         uint32_t value, int regnum)
 108 {
 109         int retval;
 110         uint32_t dcrdr;
 111
 112         /* because the DCB_DCRDR is used for the emulated dcc channel
 113          * we have to save/restore the DCB_DCRDR when used */
 114
 115         retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 116         if (retval != ERROR_OK)
 117                 return retval;
 118
 119         /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
 120         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 121         if (retval != ERROR_OK)
 122                 return retval;
 123         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 124         if (retval != ERROR_OK)
 125                 return retval;
 126
 127         /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
 128         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 129         if (retval != ERROR_OK)
 130                 return retval;
 131         retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 132         if (retval != ERROR_OK)
 133                 return retval;
 134
 135         retval = dap_run(swjdp);
 136         if (retval != ERROR_OK)
 137                 return retval;
 138
 139         /* restore DCB_DCRDR - this needs to be in a seperate
 140          * transaction otherwise the emulated DCC channel breaks */
 141         if (retval == ERROR_OK)
 142                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
 143
 144         return retval;
 145 }
 146
 147 static int cortex_m3_write_debug_halt_mask(struct target *target,
 148         uint32_t mask_on, uint32_t mask_off)
 149 {
 150         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 151         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 152
 153         /* mask off status bits */
 154         cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
 155         /* create new register mask */
 156         cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
 157
 158         return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
 159 }
 160
 161 static int cortex_m3_clear_halt(struct target *target)
 162 {
 163         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 164         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 165         int retval;
 166
 167         /* clear step if any */
 168         cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 169
 170         /* Read Debug Fault Status Register */
 171         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 172         if (retval != ERROR_OK)
 173                 return retval;
 174
 175         /* Clear Debug Fault Status */
 176         retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
 177         if (retval != ERROR_OK)
 178                 return retval;
 179         LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 180
 181         return ERROR_OK;
 182 }
 183
 184 static int cortex_m3_single_step_core(struct target *target)
 185 {
 186         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 187         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 188         uint32_t dhcsr_save;
 189         int retval;
 190
 191         /* backup dhcsr reg */
 192         dhcsr_save = cortex_m3->dcb_dhcsr;
 193
 194         /* Mask interrupts before clearing halt, if done already.  This avoids
 195          * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
 196          * HALT can put the core into an unknown state.
 197          */
 198         if (!(cortex_m3->dcb_dhcsr & C_MASKINTS)) {
 199                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 200                                 DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
 201                 if (retval != ERROR_OK)
 202                         return retval;
 203         }
 204         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 205                         DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
 206         if (retval != ERROR_OK)
 207                 return retval;
 208         LOG_DEBUG(" ");
 209
 210         /* restore dhcsr reg */
 211         cortex_m3->dcb_dhcsr = dhcsr_save;
 212         cortex_m3_clear_halt(target);
 213
 214         return ERROR_OK;
 215 }
 216
 217 static int cortex_m3_endreset_event(struct target *target)
 218 {
 219         int i;
 220         int retval;
 221         uint32_t dcb_demcr;
 222         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 223         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 224         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 225         struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 226         struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 227
 228         /* REVISIT The four debug monitor bits are currently ignored... */
 229         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 230         if (retval != ERROR_OK)
 231                 return retval;
 232         LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
 233
 234         /* this register is used for emulated dcc channel */
 235         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 236         if (retval != ERROR_OK)
 237                 return retval;
 238
 239         /* Enable debug requests */
 240         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 241         if (retval != ERROR_OK)
 242                 return retval;
 243         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) {
 244                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 245                 if (retval != ERROR_OK)
 246                         return retval;
 247         }
 248
 249         /* clear any interrupt masking */
 250         cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 251
 252         /* Enable features controlled by ITM and DWT blocks, and catch only
 253          * the vectors we were told to pay attention to.
 254          *
 255          * Target firmware is responsible for all fault handling policy
 256          * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
 257          * or manual updates to the NVIC SHCSR and CCR registers.
 258          */
 259         retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         /* Paranoia: evidently some (early?) chips don't preserve all the
 264          * debug state (including FBP, DWT, etc) across reset...
 265          */
 266
 267         /* Enable FPB */
 268         retval = target_write_u32(target, FP_CTRL, 3);
 269         if (retval != ERROR_OK)
 270                 return retval;
 271
 272         cortex_m3->fpb_enabled = 1;
 273
 274         /* Restore FPB registers */
 275         for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
 276                 retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
 277                 if (retval != ERROR_OK)
 278                         return retval;
 279         }
 280
 281         /* Restore DWT registers */
 282         for (i = 0; i < cortex_m3->dwt_num_comp; i++) {
 283                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
 284                                 dwt_list[i].comp);
 285                 if (retval != ERROR_OK)
 286                         return retval;
 287                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
 288                                 dwt_list[i].mask);
 289                 if (retval != ERROR_OK)
 290                         return retval;
 291                 retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 292                                 dwt_list[i].function);
 293                 if (retval != ERROR_OK)
 294                         return retval;
 295         }
 296         retval = dap_run(swjdp);
 297         if (retval != ERROR_OK)
 298                 return retval;
 299
 300         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 301
 302         /* make sure we have latest dhcsr flags */
 303         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 304
 305         return retval;
 306 }
 307
 308 static int cortex_m3_examine_debug_reason(struct target *target)
 309 {
 310         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 311
 312         /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
 313          * only check the debug reason if we don't know it already */
 314
 315         if ((target->debug_reason != DBG_REASON_DBGRQ)
 316                 && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 317                 if (cortex_m3->nvic_dfsr & DFSR_BKPT) {
 318                         target->debug_reason = DBG_REASON_BREAKPOINT;
 319                         if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 320                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 321                 } else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
 322                         target->debug_reason = DBG_REASON_WATCHPOINT;
 323                 else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
 324                         target->debug_reason = DBG_REASON_BREAKPOINT;
 325                 else    /* EXTERNAL, HALTED */
 326                         target->debug_reason = DBG_REASON_UNDEFINED;
 327         }
 328
 329         return ERROR_OK;
 330 }
 331
 332 static int cortex_m3_examine_exception_reason(struct target *target)
 333 {
 334         uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
 335         struct armv7m_common *armv7m = target_to_armv7m(target);
 336         struct adiv5_dap *swjdp = &armv7m->dap;
 337         int retval;
 338
 339         retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
 340         if (retval != ERROR_OK)
 341                 return retval;
 342         switch (armv7m->exception_number) {
 343                 case 2: /* NMI */
 344                         break;
 345                 case 3: /* Hard Fault */
 346                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
 347                         if (retval != ERROR_OK)
 348                                 return retval;
 349                         if (except_sr & 0x40000000) {
 350                                 retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
 351                                 if (retval != ERROR_OK)
 352                                         return retval;
 353                         }
 354                         break;
 355                 case 4: /* Memory Management */
 356                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 357                         if (retval != ERROR_OK)
 358                                 return retval;
 359                         retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
 360                         if (retval != ERROR_OK)
 361                                 return retval;
 362                         break;
 363                 case 5: /* Bus Fault */
 364                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 365                         if (retval != ERROR_OK)
 366                                 return retval;
 367                         retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
 368                         if (retval != ERROR_OK)
 369                                 return retval;
 370                         break;
 371                 case 6: /* Usage Fault */
 372                         retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
 373                         if (retval != ERROR_OK)
 374                                 return retval;
 375                         break;
 376                 case 11:        /* SVCall */
 377                         break;
 378                 case 12:        /* Debug Monitor */
 379                         retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
 380                         if (retval != ERROR_OK)
 381                                 return retval;
 382                         break;
 383                 case 14:        /* PendSV */
 384                         break;
 385                 case 15:        /* SysTick */
 386                         break;
 387                 default:
 388                         except_sr = 0;
 389                         break;
 390         }
 391         retval = dap_run(swjdp);
 392         if (retval == ERROR_OK)
 393                 LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
 394                         ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
 395                         armv7m_exception_string(armv7m->exception_number),
 396                         shcsr, except_sr, cfsr, except_ar);
 397         return retval;
 398 }
 399
 400 static int cortex_m3_debug_entry(struct target *target)
 401 {
 402         int i;
 403         uint32_t xPSR;
 404         int retval;
 405         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 406         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 407         struct arm *arm = &armv7m->arm;
 408         struct adiv5_dap *swjdp = &armv7m->dap;
 409         struct reg *r;
 410
 411         LOG_DEBUG(" ");
 412
 413         cortex_m3_clear_halt(target);
 414         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 415         if (retval != ERROR_OK)
 416                 return retval;
 417
 418         retval = armv7m->examine_debug_reason(target);
 419         if (retval != ERROR_OK)
 420                 return retval;
 421
 422         /* Examine target state and mode
 423          * First load register acessible through core debug port*/
 424         int num_regs = armv7m->core_cache->num_regs;
 425
 426         for (i = 0; i < num_regs; i++) {
 427                 if (!armv7m->core_cache->reg_list[i].valid)
 428                         armv7m->read_core_reg(target, i);
 429         }
 430
 431         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 432         xPSR = buf_get_u32(r->value, 0, 32);
 433
 434 #ifdef ARMV7_GDB_HACKS
 435         /* FIXME this breaks on scan chains with more than one Cortex-M3.
 436          * Instead, each CM3 should have its own dummy value...
 437          */
 438         /* copy real xpsr reg for gdb, setting thumb bit */
 439         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
 440         buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
 441         armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
 442         armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
 443 #endif
 444
 445         /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
 446         if (xPSR & 0xf00) {
 447                 r->dirty = r->valid;
 448                 cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR & ~0xff);
 449         }
 450
 451         /* Are we in an exception handler */
 452         if (xPSR & 0x1FF) {
 453                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 454                 armv7m->exception_number = (xPSR & 0x1FF);
 455
 456                 arm->core_mode = ARM_MODE_HANDLER;
 457                 arm->map = armv7m_msp_reg_map;
 458         } else {
 459                 unsigned control = buf_get_u32(armv7m->core_cache
 460                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 461
 462                 /* is this thread privileged? */
 463                 armv7m->core_mode = control & 1;
 464                 arm->core_mode = armv7m->core_mode
 465                         ? ARM_MODE_USER_THREAD
 466                         : ARM_MODE_THREAD;
 467
 468                 /* which stack is it using? */
 469                 if (control & 2)
 470                         arm->map = armv7m_psp_reg_map;
 471                 else
 472                         arm->map = armv7m_msp_reg_map;
 473
 474                 armv7m->exception_number = 0;
 475         }
 476
 477         if (armv7m->exception_number)
 478                 cortex_m3_examine_exception_reason(target);
 479
 480         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 481                 armv7m_mode_strings[armv7m->core_mode],
 482                 *(uint32_t *)(arm->pc->value),
 483                 target_state_name(target));
 484
 485         if (armv7m->post_debug_entry) {
 486                 retval = armv7m->post_debug_entry(target);
 487                 if (retval != ERROR_OK)
 488                         return retval;
 489         }
 490
 491         return ERROR_OK;
 492 }
 493
 494 static int cortex_m3_poll(struct target *target)
 495 {
 496         int detected_failure = ERROR_OK;
 497         int retval = ERROR_OK;
 498         enum target_state prev_target_state = target->state;
 499         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 500         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 501
 502         /* Read from Debug Halting Control and Status Register */
 503         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 504         if (retval != ERROR_OK) {
 505                 target->state = TARGET_UNKNOWN;
 506                 return retval;
 507         }
 508
 509         /* Recover from lockup.  See ARMv7-M architecture spec,
 510          * section B1.5.15 "Unrecoverable exception cases".
 511          */
 512         if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
 513                 LOG_ERROR("%s -- clearing lockup after double fault",
 514                         target_name(target));
 515                 cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 516                 target->debug_reason = DBG_REASON_DBGRQ;
 517
 518                 /* We have to execute the rest (the "finally" equivalent, but
 519                  * still throw this exception again).
 520                  */
 521                 detected_failure = ERROR_FAIL;
 522
 523                 /* refresh status bits */
 524                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 525                 if (retval != ERROR_OK)
 526                         return retval;
 527         }
 528
 529         if (cortex_m3->dcb_dhcsr & S_RESET_ST) {
 530                 /* check if still in reset */
 531                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 532                 if (retval != ERROR_OK)
 533                         return retval;
 534
 535                 if (cortex_m3->dcb_dhcsr & S_RESET_ST) {
 536                         target->state = TARGET_RESET;
 537                         return ERROR_OK;
 538                 }
 539         }
 540
 541         if (target->state == TARGET_RESET) {
 542                 /* Cannot switch context while running so endreset is
 543                  * called with target->state == TARGET_RESET
 544                  */
 545                 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
 546                         cortex_m3->dcb_dhcsr);
 547                 cortex_m3_endreset_event(target);
 548                 target->state = TARGET_RUNNING;
 549                 prev_target_state = TARGET_RUNNING;
 550         }
 551
 552         if (cortex_m3->dcb_dhcsr & S_HALT) {
 553                 target->state = TARGET_HALTED;
 554
 555                 if ((prev_target_state == TARGET_RUNNING) || (prev_target_state == TARGET_RESET)) {
 556                         retval = cortex_m3_debug_entry(target);
 557                         if (retval != ERROR_OK)
 558                                 return retval;
 559
 560                         if (arm_semihosting(target, &retval) != 0)
 561                                 return retval;
 562
 563                         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 564                 }
 565                 if (prev_target_state == TARGET_DEBUG_RUNNING) {
 566                         LOG_DEBUG(" ");
 567                         retval = cortex_m3_debug_entry(target);
 568                         if (retval != ERROR_OK)
 569                                 return retval;
 570
 571                         target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
 572                 }
 573         }
 574
 575         /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
 576          * How best to model low power modes?
 577          */
 578
 579         if (target->state == TARGET_UNKNOWN) {
 580                 /* check if processor is retiring instructions */
 581                 if (cortex_m3->dcb_dhcsr & S_RETIRE_ST) {
 582                         target->state = TARGET_RUNNING;
 583                         retval = ERROR_OK;
 584                 }
 585         }
 586
 587         /* Did we detect a failure condition that we cleared? */
 588         if (detected_failure != ERROR_OK)
 589                 retval = detected_failure;
 590         return retval;
 591 }
 592
 593 static int cortex_m3_halt(struct target *target)
 594 {
 595         LOG_DEBUG("target->state: %s",
 596                 target_state_name(target));
 597
 598         if (target->state == TARGET_HALTED) {
 599                 LOG_DEBUG("target was already halted");
 600                 return ERROR_OK;
 601         }
 602
 603         if (target->state == TARGET_UNKNOWN)
 604                 LOG_WARNING("target was in unknown state when halt was requested");
 605
 606         if (target->state == TARGET_RESET) {
 607                 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
 608                         LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
 609                         return ERROR_TARGET_FAILURE;
 610                 } else {
 611                         /* we came here in a reset_halt or reset_init sequence
 612                          * debug entry was already prepared in cortex_m3_assert_reset()
 613                          */
 614                         target->debug_reason = DBG_REASON_DBGRQ;
 615
 616                         return ERROR_OK;
 617                 }
 618         }
 619
 620         /* Write to Debug Halting Control and Status Register */
 621         cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
 622
 623         target->debug_reason = DBG_REASON_DBGRQ;
 624
 625         return ERROR_OK;
 626 }
 627
 628 static int cortex_m3_soft_reset_halt(struct target *target)
 629 {
 630         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 631         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 632         uint32_t dcb_dhcsr = 0;
 633         int retval, timeout = 0;
 634
 635         /* Enter debug state on reset; restore DEMCR in endreset_event() */
 636         retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
 637                         TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 638         if (retval != ERROR_OK)
 639                 return retval;
 640
 641         /* Request a core-only reset */
 642         retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
 643                         AIRCR_VECTKEY | AIRCR_VECTRESET);
 644         if (retval != ERROR_OK)
 645                 return retval;
 646         target->state = TARGET_RESET;
 647
 648         /* registers are now invalid */
 649         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 650
 651         while (timeout < 100) {
 652                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
 653                 if (retval == ERROR_OK) {
 654                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
 655                                         &cortex_m3->nvic_dfsr);
 656                         if (retval != ERROR_OK)
 657                                 return retval;
 658                         if ((dcb_dhcsr & S_HALT)
 659                                 && (cortex_m3->nvic_dfsr & DFSR_VCATCH)) {
 660                                 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
 661                                         "DFSR 0x%08x",
 662                                         (unsigned) dcb_dhcsr,
 663                                         (unsigned) cortex_m3->nvic_dfsr);
 664                                 cortex_m3_poll(target);
 665                                 /* FIXME restore user's vector catch config */
 666                                 return ERROR_OK;
 667                         } else
 668                                 LOG_DEBUG("waiting for system reset-halt, "
 669                                         "DHCSR 0x%08x, %d ms",
 670                                         (unsigned) dcb_dhcsr, timeout);
 671                 }
 672                 timeout++;
 673                 alive_sleep(1);
 674         }
 675
 676         return ERROR_OK;
 677 }
 678
 679 static void cortex_m3_enable_breakpoints(struct target *target)
 680 {
 681         struct breakpoint *breakpoint = target->breakpoints;
 682
 683         /* set any pending breakpoints */
 684         while (breakpoint) {
 685                 if (!breakpoint->set)
 686                         cortex_m3_set_breakpoint(target, breakpoint);
 687                 breakpoint = breakpoint->next;
 688         }
 689 }
 690
 691 static int cortex_m3_resume(struct target *target, int current,
 692         uint32_t address, int handle_breakpoints, int debug_execution)
 693 {
 694         struct armv7m_common *armv7m = target_to_armv7m(target);
 695         struct breakpoint *breakpoint = NULL;
 696         uint32_t resume_pc;
 697         struct reg *r;
 698
 699         if (target->state != TARGET_HALTED) {
 700                 LOG_WARNING("target not halted");
 701                 return ERROR_TARGET_NOT_HALTED;
 702         }
 703
 704         if (!debug_execution) {
 705                 target_free_all_working_areas(target);
 706                 cortex_m3_enable_breakpoints(target);
 707                 cortex_m3_enable_watchpoints(target);
 708         }
 709
 710         if (debug_execution) {
 711                 r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
 712
 713                 /* Disable interrupts */
 714                 /* We disable interrupts in the PRIMASK register instead of
 715                  * masking with C_MASKINTS.  This is probably the same issue
 716                  * as Cortex-M3 Erratum 377493 (fixed in r1p0):  C_MASKINTS
 717                  * in parallel with disabled interrupts can cause local faults
 718                  * to not be taken.
 719                  *
 720                  * REVISIT this clearly breaks non-debug execution, since the
 721                  * PRIMASK register state isn't saved/restored...  workaround
 722                  * by never resuming app code after debug execution.
 723                  */
 724                 buf_set_u32(r->value, 0, 1, 1);
 725                 r->dirty = true;
 726                 r->valid = true;
 727
 728                 /* Make sure we are in Thumb mode */
 729                 r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 730                 buf_set_u32(r->value, 24, 1, 1);
 731                 r->dirty = true;
 732                 r->valid = true;
 733         }
 734
 735         /* current = 1: continue on current pc, otherwise continue at <address> */
 736         r = armv7m->arm.pc;
 737         if (!current) {
 738                 buf_set_u32(r->value, 0, 32, address);
 739                 r->dirty = true;
 740                 r->valid = true;
 741         }
 742
 743         /* if we halted last time due to a bkpt instruction
 744          * then we have to manually step over it, otherwise
 745          * the core will break again */
 746
 747         if (!breakpoint_find(target, buf_get_u32(r->value, 0, 32))
 748                 && !debug_execution)
 749                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 750
 751         resume_pc = buf_get_u32(r->value, 0, 32);
 752
 753         armv7m_restore_context(target);
 754
 755         /* the front-end may request us not to handle breakpoints */
 756         if (handle_breakpoints) {
 757                 /* Single step past breakpoint at current address */
 758                 breakpoint = breakpoint_find(target, resume_pc);
 759                 if (breakpoint) {
 760                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 761                                 breakpoint->address,
 762                                 breakpoint->unique_id);
 763                         cortex_m3_unset_breakpoint(target, breakpoint);
 764                         cortex_m3_single_step_core(target);
 765                         cortex_m3_set_breakpoint(target, breakpoint);
 766                 }
 767         }
 768
 769         /* Restart core */
 770         cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 771
 772         target->debug_reason = DBG_REASON_NOTHALTED;
 773
 774         /* registers are now invalid */
 775         register_cache_invalidate(armv7m->core_cache);
 776
 777         if (!debug_execution) {
 778                 target->state = TARGET_RUNNING;
 779                 target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 780                 LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 781         } else {
 782                 target->state = TARGET_DEBUG_RUNNING;
 783                 target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
 784                 LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 785         }
 786
 787         return ERROR_OK;
 788 }
 789
 790 /* int irqstepcount = 0; */
 791 static int cortex_m3_step(struct target *target, int current,
 792         uint32_t address, int handle_breakpoints)
 793 {
 794         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 795         struct armv7m_common *armv7m = &cortex_m3->armv7m;
 796         struct adiv5_dap *swjdp = &armv7m->dap;
 797         struct breakpoint *breakpoint = NULL;
 798         struct reg *pc = armv7m->arm.pc;
 799         bool bkpt_inst_found = false;
 800         int retval;
 801         bool isr_timed_out = false;
 802
 803         if (target->state != TARGET_HALTED) {
 804                 LOG_WARNING("target not halted");
 805                 return ERROR_TARGET_NOT_HALTED;
 806         }
 807
 808         /* current = 1: continue on current pc, otherwise continue at <address> */
 809         if (!current)
 810                 buf_set_u32(pc->value, 0, 32, address);
 811
 812         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 813
 814         /* the front-end may request us not to handle breakpoints */
 815         if (handle_breakpoints) {
 816                 breakpoint = breakpoint_find(target, pc_value);
 817                 if (breakpoint)
 818                         cortex_m3_unset_breakpoint(target, breakpoint);
 819         }
 820
 821         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 822
 823         target->debug_reason = DBG_REASON_SINGLESTEP;
 824
 825         armv7m_restore_context(target);
 826
 827         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 828
 829         /* if no bkpt instruction is found at pc then we can perform
 830          * a normal step, otherwise we have to manually step over the bkpt
 831          * instruction - as such simulate a step */
 832         if (bkpt_inst_found == false) {
 833                 /* Automatic ISR masking mode off: Just step over the next instruction */
 834                 if ((cortex_m3->isrmasking_mode != CORTEX_M3_ISRMASK_AUTO))
 835                         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 836                 else {
 837                         /* Process interrupts during stepping in a way they don't interfere
 838                          * debugging.
 839                          *
 840                          * Principle:
 841                          *
 842                          * Set a temporary break point at the current pc and let the core run
 843                          * with interrupts enabled. Pending interrupts get served and we run
 844                          * into the breakpoint again afterwards. Then we step over the next
 845                          * instruction with interrupts disabled.
 846                          *
 847                          * If the pending interrupts don't complete within time, we leave the
 848                          * core running. This may happen if the interrupts trigger faster
 849                          * than the core can process them or the handler doesn't return.
 850                          *
 851                          * If no more breakpoints are available we simply do a step with
 852                          * interrupts enabled.
 853                          *
 854                          */
 855
 856                         /* Set a temporary break point */
 857                         retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
 858                         bool tmp_bp_set = (retval == ERROR_OK);
 859
 860                         /* No more breakpoints left, just do a step */
 861                         if (!tmp_bp_set)
 862                                 cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 863                         else {
 864                                 /* Start the core */
 865                                 LOG_DEBUG("Starting core to serve pending interrupts");
 866                                 int64_t t_start = timeval_ms();
 867                                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
 868
 869                                 /* Wait for pending handlers to complete or timeout */
 870                                 do {
 871                                         retval = mem_ap_read_atomic_u32(swjdp,
 872                                                         DCB_DHCSR,
 873                                                         &cortex_m3->dcb_dhcsr);
 874                                         if (retval != ERROR_OK) {
 875                                                 target->state = TARGET_UNKNOWN;
 876                                                 return retval;
 877                                         }
 878                                         isr_timed_out = ((timeval_ms() - t_start) > 500);
 879                                 } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
 880
 881                                 /* Remove the temporary breakpoint */
 882                                 breakpoint_remove(target, pc_value);
 883
 884                                 if (isr_timed_out) {
 885                                         LOG_DEBUG("Interrupt handlers didn't complete within time, "
 886                                                 "leaving target running");
 887                                 } else {
 888                                         /* Step over next instruction with interrupts disabled */
 889                                         cortex_m3_write_debug_halt_mask(target,
 890                                                 C_HALT | C_MASKINTS,
 891                                                 0);
 892                                         cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
 893                                         /* Re-enable interrupts */
 894                                         cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
 895                                 }
 896                         }
 897                 }
 898         }
 899
 900         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 901         if (retval != ERROR_OK)
 902                 return retval;
 903
 904         /* registers are now invalid */
 905         register_cache_invalidate(cortex_m3->armv7m.core_cache);
 906
 907         if (breakpoint)
 908                 cortex_m3_set_breakpoint(target, breakpoint);
 909
 910         if (isr_timed_out) {
 911                 /* Leave the core running. The user has to stop execution manually. */
 912                 target->debug_reason = DBG_REASON_NOTHALTED;
 913                 target->state = TARGET_RUNNING;
 914                 return ERROR_OK;
 915         }
 916
 917         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 918                 " nvic_icsr = 0x%" PRIx32,
 919                 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 920
 921         retval = cortex_m3_debug_entry(target);
 922         if (retval != ERROR_OK)
 923                 return retval;
 924         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 925
 926         LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
 927                 " nvic_icsr = 0x%" PRIx32,
 928                 cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 929
 930         return ERROR_OK;
 931 }
 932
 933 static int cortex_m3_assert_reset(struct target *target)
 934 {
 935         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 936         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 937         enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
 938
 939         LOG_DEBUG("target->state: %s",
 940                 target_state_name(target));
 941
 942         enum reset_types jtag_reset_config = jtag_get_reset_config();
 943
 944         if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
 945                 /* allow scripts to override the reset event */
 946
 947                 target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
 948                 register_cache_invalidate(cortex_m3->armv7m.core_cache);
 949                 target->state = TARGET_RESET;
 950
 951                 return ERROR_OK;
 952         }
 953
 954         /* Enable debug requests */
 955         int retval;
 956         retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 957         if (retval != ERROR_OK)
 958                 return retval;
 959         if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN)) {
 960                 retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 961                 if (retval != ERROR_OK)
 962                         return retval;
 963         }
 964
 965         retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 966         if (retval != ERROR_OK)
 967                 return retval;
 968
 969         if (!target->reset_halt) {
 970                 /* Set/Clear C_MASKINTS in a separate operation */
 971                 if (cortex_m3->dcb_dhcsr & C_MASKINTS) {
 972                         retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
 973                                         DBGKEY | C_DEBUGEN | C_HALT);
 974                         if (retval != ERROR_OK)
 975                                 return retval;
 976                 }
 977
 978                 /* clear any debug flags before resuming */
 979                 cortex_m3_clear_halt(target);
 980
 981                 /* clear C_HALT in dhcsr reg */
 982                 cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
 983         } else {
 984                 /* Halt in debug on reset; endreset_event() restores DEMCR.
 985                  *
 986                  * REVISIT catching BUSERR presumably helps to defend against
 987                  * bad vector table entries.  Should this include MMERR or
 988                  * other flags too?
 989                  */
 990                 retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 991                                 TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 992                 if (retval != ERROR_OK)
 993                         return retval;
 994         }
 995
 996         if (jtag_reset_config & RESET_HAS_SRST) {
 997                 /* default to asserting srst */
 998                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 999                         jtag_add_reset(1, 1);
1000                 else
1001                         jtag_add_reset(0, 1);
1002         } else {
1003                 /* Use a standard Cortex-M3 software reset mechanism.
1004                  * We default to using VECRESET as it is supported on all current cores.
1005                  * This has the disadvantage of not resetting the peripherals, so a
1006                  * reset-init event handler is needed to perform any peripheral resets.
1007                  */
1008                 retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
1009                                 AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1010                                 ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
1011                 if (retval != ERROR_OK)
1012                         return retval;
1013
1014                 LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
1015                         ? "SYSRESETREQ" : "VECTRESET");
1016
1017                 if (reset_config == CORTEX_M3_RESET_VECTRESET) {
1018                         LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
1019                                 "handler to reset any peripherals");
1020                 }
1021
1022                 {
1023                         /* I do not know why this is necessary, but it
1024                          * fixes strange effects (step/resume cause NMI
1025                          * after reset) on LM3S6918 -- Michael Schwingen
1026                          */
1027                         uint32_t tmp;
1028                         retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
1029                         if (retval != ERROR_OK)
1030                                 return retval;
1031                 }
1032         }
1033
1034         target->state = TARGET_RESET;
1035         jtag_add_sleep(50000);
1036
1037         register_cache_invalidate(cortex_m3->armv7m.core_cache);
1038
1039         if (target->reset_halt) {
1040                 retval = target_halt(target);
1041                 if (retval != ERROR_OK)
1042                         return retval;
1043         }
1044
1045         return ERROR_OK;
1046 }
1047
1048 static int cortex_m3_deassert_reset(struct target *target)
1049 {
1050         LOG_DEBUG("target->state: %s",
1051                 target_state_name(target));
1052
1053         /* deassert reset lines */
1054         jtag_add_reset(0, 0);
1055
1056         return ERROR_OK;
1057 }
1058
1059 int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
1060 {
1061         int retval;
1062         int fp_num = 0;
1063         uint32_t hilo;
1064         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1065         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1066
1067         if (breakpoint->set) {
1068                 LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
1069                 return ERROR_OK;
1070         }
1071
1072         if (cortex_m3->auto_bp_type)
1073                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1074
1075         if (breakpoint->type == BKPT_HARD) {
1076                 while (comparator_list[fp_num].used && (fp_num < cortex_m3->fp_num_code))
1077                         fp_num++;
1078                 if (fp_num >= cortex_m3->fp_num_code) {
1079                         LOG_ERROR("Can not find free FPB Comparator!");
1080                         return ERROR_FAIL;
1081                 }
1082                 breakpoint->set = fp_num + 1;
1083                 hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
1084                 comparator_list[fp_num].used = 1;
1085                 comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
1086                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1087                         comparator_list[fp_num].fpcr_value);
1088                 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
1089                         fp_num,
1090                         comparator_list[fp_num].fpcr_value);
1091                 if (!cortex_m3->fpb_enabled) {
1092                         LOG_DEBUG("FPB wasn't enabled, do it now");
1093                         target_write_u32(target, FP_CTRL, 3);
1094                 }
1095         } else if (breakpoint->type == BKPT_SOFT) {
1096                 uint8_t code[4];
1097
1098                 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1099                  * semihosting; don't use that.  Otherwise the BKPT
1100                  * parameter is arbitrary.
1101                  */
1102                 buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
1103                 retval = target_read_memory(target,
1104                                 breakpoint->address & 0xFFFFFFFE,
1105                                 breakpoint->length, 1,
1106                                 breakpoint->orig_instr);
1107                 if (retval != ERROR_OK)
1108                         return retval;
1109                 retval = target_write_memory(target,
1110                                 breakpoint->address & 0xFFFFFFFE,
1111                                 breakpoint->length, 1,
1112                                 code);
1113                 if (retval != ERROR_OK)
1114                         return retval;
1115                 breakpoint->set = true;
1116         }
1117
1118         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1119                 breakpoint->unique_id,
1120                 (int)(breakpoint->type),
1121                 breakpoint->address,
1122                 breakpoint->length,
1123                 breakpoint->set);
1124
1125         return ERROR_OK;
1126 }
1127
1128 int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
1129 {
1130         int retval;
1131         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1132         struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
1133
1134         if (!breakpoint->set) {
1135                 LOG_WARNING("breakpoint not set");
1136                 return ERROR_OK;
1137         }
1138
1139         LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
1140                 breakpoint->unique_id,
1141                 (int)(breakpoint->type),
1142                 breakpoint->address,
1143                 breakpoint->length,
1144                 breakpoint->set);
1145
1146         if (breakpoint->type == BKPT_HARD) {
1147                 int fp_num = breakpoint->set - 1;
1148                 if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code)) {
1149                         LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1150                         return ERROR_OK;
1151                 }
1152                 comparator_list[fp_num].used = 0;
1153                 comparator_list[fp_num].fpcr_value = 0;
1154                 target_write_u32(target, comparator_list[fp_num].fpcr_address,
1155                         comparator_list[fp_num].fpcr_value);
1156         } else {
1157                 /* restore original instruction (kept in target endianness) */
1158                 if (breakpoint->length == 4) {
1159                         retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 4, 1,
1160                                         breakpoint->orig_instr);
1161                         if (retval != ERROR_OK)
1162                                 return retval;
1163                 } else {
1164                         retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, 2, 1,
1165                                         breakpoint->orig_instr);
1166                         if (retval != ERROR_OK)
1167                                 return retval;
1168                 }
1169         }
1170         breakpoint->set = false;
1171
1172         return ERROR_OK;
1173 }
1174
1175 int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
1176 {
1177         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1178
1179         if (cortex_m3->auto_bp_type) {
1180                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1181 #ifdef ARMV7_GDB_HACKS
1182                 if (breakpoint->length != 2) {
1183                         /* XXX Hack: Replace all breakpoints with length != 2 with
1184                          * a hardware breakpoint. */
1185                         breakpoint->type = BKPT_HARD;
1186                         breakpoint->length = 2;
1187                 }
1188 #endif
1189         }
1190
1191         if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
1192                 if (breakpoint->type == BKPT_HARD) {
1193                         LOG_INFO("flash patch comparator requested outside code memory region");
1194                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1195                 }
1196
1197                 if (breakpoint->type == BKPT_SOFT) {
1198                         LOG_INFO("soft breakpoint requested in code (flash) memory region");
1199                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1200                 }
1201         }
1202
1203         if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1)) {
1204                 LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
1205                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1206         }
1207
1208         if ((breakpoint->length != 2)) {
1209                 LOG_INFO("only breakpoints of two bytes length supported");
1210                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1211         }
1212
1213         if (breakpoint->type == BKPT_HARD)
1214                 cortex_m3->fp_code_available--;
1215
1216         return cortex_m3_set_breakpoint(target, breakpoint);
1217 }
1218
1219 int cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
1220 {
1221         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1222
1223         /* REVISIT why check? FBP can be updated with core running ... */
1224         if (target->state != TARGET_HALTED) {
1225                 LOG_WARNING("target not halted");
1226                 return ERROR_TARGET_NOT_HALTED;
1227         }
1228
1229         if (cortex_m3->auto_bp_type)
1230                 breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
1231
1232         if (breakpoint->set)
1233                 cortex_m3_unset_breakpoint(target, breakpoint);
1234
1235         if (breakpoint->type == BKPT_HARD)
1236                 cortex_m3->fp_code_available++;
1237
1238         return ERROR_OK;
1239 }
1240
1241 int cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
1242 {
1243         int dwt_num = 0;
1244         uint32_t mask, temp;
1245         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1246
1247         /* watchpoint params were validated earlier */
1248         mask = 0;
1249         temp = watchpoint->length;
1250         while (temp) {
1251                 temp >>= 1;
1252                 mask++;
1253         }
1254         mask--;
1255
1256         /* REVISIT Don't fully trust these "not used" records ... users
1257          * may set up breakpoints by hand, e.g. dual-address data value
1258          * watchpoint using comparator #1; comparator #0 matching cycle
1259          * count; send data trace info through ITM and TPIU; etc
1260          */
1261         struct cortex_m3_dwt_comparator *comparator;
1262
1263         for (comparator = cortex_m3->dwt_comparator_list;
1264                 comparator->used && dwt_num < cortex_m3->dwt_num_comp;
1265                 comparator++, dwt_num++)
1266                 continue;
1267         if (dwt_num >= cortex_m3->dwt_num_comp) {
1268                 LOG_ERROR("Can not find free DWT Comparator");
1269                 return ERROR_FAIL;
1270         }
1271         comparator->used = 1;
1272         watchpoint->set = dwt_num + 1;
1273
1274         comparator->comp = watchpoint->address;
1275         target_write_u32(target, comparator->dwt_comparator_address + 0,
1276                 comparator->comp);
1277
1278         comparator->mask = mask;
1279         target_write_u32(target, comparator->dwt_comparator_address + 4,
1280                 comparator->mask);
1281
1282         switch (watchpoint->rw) {
1283                 case WPT_READ:
1284                         comparator->function = 5;
1285                         break;
1286                 case WPT_WRITE:
1287                         comparator->function = 6;
1288                         break;
1289                 case WPT_ACCESS:
1290                         comparator->function = 7;
1291                         break;
1292         }
1293         target_write_u32(target, comparator->dwt_comparator_address + 8,
1294                 comparator->function);
1295
1296         LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1297                 watchpoint->unique_id, dwt_num,
1298                 (unsigned) comparator->comp,
1299                 (unsigned) comparator->mask,
1300                 (unsigned) comparator->function);
1301         return ERROR_OK;
1302 }
1303
1304 int cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
1305 {
1306         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1307         struct cortex_m3_dwt_comparator *comparator;
1308         int dwt_num;
1309
1310         if (!watchpoint->set) {
1311                 LOG_WARNING("watchpoint (wpid: %d) not set",
1312                         watchpoint->unique_id);
1313                 return ERROR_OK;
1314         }
1315
1316         dwt_num = watchpoint->set - 1;
1317
1318         LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1319                 watchpoint->unique_id, dwt_num,
1320                 (unsigned) watchpoint->address);
1321
1322         if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp)) {
1323                 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1324                 return ERROR_OK;
1325         }
1326
1327         comparator = cortex_m3->dwt_comparator_list + dwt_num;
1328         comparator->used = 0;
1329         comparator->function = 0;
1330         target_write_u32(target, comparator->dwt_comparator_address + 8,
1331                 comparator->function);
1332
1333         watchpoint->set = false;
1334
1335         return ERROR_OK;
1336 }
1337
1338 int cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
1339 {
1340         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1341
1342         if (cortex_m3->dwt_comp_available < 1) {
1343                 LOG_DEBUG("no comparators?");
1344                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1345         }
1346
1347         /* hardware doesn't support data value masking */
1348         if (watchpoint->mask != ~(uint32_t)0) {
1349                 LOG_DEBUG("watchpoint value masks not supported");
1350                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1351         }
1352
1353         /* hardware allows address masks of up to 32K */
1354         unsigned mask;
1355
1356         for (mask = 0; mask < 16; mask++) {
1357                 if ((1u << mask) == watchpoint->length)
1358                         break;
1359         }
1360         if (mask == 16) {
1361                 LOG_DEBUG("unsupported watchpoint length");
1362                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1363         }
1364         if (watchpoint->address & ((1 << mask) - 1)) {
1365                 LOG_DEBUG("watchpoint address is unaligned");
1366                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1367         }
1368
1369         /* Caller doesn't seem to be able to describe watching for data
1370          * values of zero; that flags "no value".
1371          *
1372          * REVISIT This DWT may well be able to watch for specific data
1373          * values.  Requires comparator #1 to set DATAVMATCH and match
1374          * the data, and another comparator (DATAVADDR0) matching addr.
1375          */
1376         if (watchpoint->value) {
1377                 LOG_DEBUG("data value watchpoint not YET supported");
1378                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1379         }
1380
1381         cortex_m3->dwt_comp_available--;
1382         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1383
1384         return ERROR_OK;
1385 }
1386
1387 int cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
1388 {
1389         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1390
1391         /* REVISIT why check? DWT can be updated with core running ... */
1392         if (target->state != TARGET_HALTED) {
1393                 LOG_WARNING("target not halted");
1394                 return ERROR_TARGET_NOT_HALTED;
1395         }
1396
1397         if (watchpoint->set)
1398                 cortex_m3_unset_watchpoint(target, watchpoint);
1399
1400         cortex_m3->dwt_comp_available++;
1401         LOG_DEBUG("dwt_comp_available: %d", cortex_m3->dwt_comp_available);
1402
1403         return ERROR_OK;
1404 }
1405
1406 void cortex_m3_enable_watchpoints(struct target *target)
1407 {
1408         struct watchpoint *watchpoint = target->watchpoints;
1409
1410         /* set any pending watchpoints */
1411         while (watchpoint) {
1412                 if (!watchpoint->set)
1413                         cortex_m3_set_watchpoint(target, watchpoint);
1414                 watchpoint = watchpoint->next;
1415         }
1416 }
1417
1418 static int cortex_m3_load_core_reg_u32(struct target *target,
1419         enum armv7m_regtype type, uint32_t num, uint32_t *value)
1420 {
1421         int retval;
1422         struct armv7m_common *armv7m = target_to_armv7m(target);
1423         struct adiv5_dap *swjdp = &armv7m->dap;
1424
1425         /* NOTE:  we "know" here that the register identifiers used
1426          * in the v7m header match the Cortex-M3 Debug Core Register
1427          * Selector values for R0..R15, xPSR, MSP, and PSP.
1428          */
1429         switch (num) {
1430                 case 0 ... 18:
1431                         /* read a normal core register */
1432                         retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
1433
1434                         if (retval != ERROR_OK) {
1435                                 LOG_ERROR("JTAG failure %i", retval);
1436                                 return ERROR_JTAG_DEVICE_ERROR;
1437                         }
1438                         LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
1439                         break;
1440
1441                 case ARMV7M_PRIMASK:
1442                 case ARMV7M_BASEPRI:
1443                 case ARMV7M_FAULTMASK:
1444                 case ARMV7M_CONTROL:
1445                         /* Cortex-M3 packages these four registers as bitfields
1446                          * in one Debug Core register.  So say r0 and r2 docs;
1447                          * it was removed from r1 docs, but still works.
1448                          */
1449                         cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
1450
1451                         switch (num) {
1452                                 case ARMV7M_PRIMASK:
1453                                         *value = buf_get_u32((uint8_t *)value, 0, 1);
1454                                         break;
1455
1456                                 case ARMV7M_BASEPRI:
1457                                         *value = buf_get_u32((uint8_t *)value, 8, 8);
1458                                         break;
1459
1460                                 case ARMV7M_FAULTMASK:
1461                                         *value = buf_get_u32((uint8_t *)value, 16, 1);
1462                                         break;
1463
1464                                 case ARMV7M_CONTROL:
1465                                         *value = buf_get_u32((uint8_t *)value, 24, 2);
1466                                         break;
1467                         }
1468
1469                         LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
1470                         break;
1471
1472                 default:
1473                         return ERROR_COMMAND_SYNTAX_ERROR;
1474         }
1475
1476         return ERROR_OK;
1477 }
1478
1479 static int cortex_m3_store_core_reg_u32(struct target *target,
1480         enum armv7m_regtype type, uint32_t num, uint32_t value)
1481 {
1482         int retval;
1483         uint32_t reg;
1484         struct armv7m_common *armv7m = target_to_armv7m(target);
1485         struct adiv5_dap *swjdp = &armv7m->dap;
1486
1487 #ifdef ARMV7_GDB_HACKS
1488         /* If the LR register is being modified, make sure it will put us
1489          * in "thumb" mode, or an INVSTATE exception will occur. This is a
1490          * hack to deal with the fact that gdb will sometimes "forge"
1491          * return addresses, and doesn't set the LSB correctly (i.e., when
1492          * printing expressions containing function calls, it sets LR = 0.)
1493          * Valid exception return codes have bit 0 set too.
1494          */
1495         if (num == ARMV7M_R14)
1496                 value |= 0x01;
1497 #endif
1498
1499         /* NOTE:  we "know" here that the register identifiers used
1500          * in the v7m header match the Cortex-M3 Debug Core Register
1501          * Selector values for R0..R15, xPSR, MSP, and PSP.
1502          */
1503         switch (num) {
1504                 case 0 ... 18:
1505                         retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
1506                         if (retval != ERROR_OK) {
1507                                 struct reg *r;
1508
1509                                 LOG_ERROR("JTAG failure");
1510                                 r = armv7m->core_cache->reg_list + num;
1511                                 r->dirty = r->valid;
1512                                 return ERROR_JTAG_DEVICE_ERROR;
1513                         }
1514                         LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
1515                         break;
1516
1517                 case ARMV7M_PRIMASK:
1518                 case ARMV7M_BASEPRI:
1519                 case ARMV7M_FAULTMASK:
1520                 case ARMV7M_CONTROL:
1521                         /* Cortex-M3 packages these four registers as bitfields
1522                          * in one Debug Core register.  So say r0 and r2 docs;
1523                          * it was removed from r1 docs, but still works.
1524                          */
1525                         cortexm3_dap_read_coreregister_u32(swjdp, &reg, 20);
1526
1527                         switch (num) {
1528                                 case ARMV7M_PRIMASK:
1529                                         buf_set_u32((uint8_t *)&reg, 0, 1, value);
1530                                         break;
1531
1532                                 case ARMV7M_BASEPRI:
1533                                         buf_set_u32((uint8_t *)&reg, 8, 8, value);
1534                                         break;
1535
1536                                 case ARMV7M_FAULTMASK:
1537                                         buf_set_u32((uint8_t *)&reg, 16, 1, value);
1538                                         break;
1539
1540                                 case ARMV7M_CONTROL:
1541                                         buf_set_u32((uint8_t *)&reg, 24, 2, value);
1542                                         break;
1543                         }
1544
1545                         cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
1546
1547                         LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
1548                         break;
1549
1550                 default:
1551                         return ERROR_COMMAND_SYNTAX_ERROR;
1552         }
1553
1554         return ERROR_OK;
1555 }
1556
1557 static int cortex_m3_read_memory(struct target *target, uint32_t address,
1558         uint32_t size, uint32_t count, uint8_t *buffer)
1559 {
1560         struct armv7m_common *armv7m = target_to_armv7m(target);
1561         struct adiv5_dap *swjdp = &armv7m->dap;
1562         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1563
1564         /* cortex_m3 handles unaligned memory access */
1565         if (count && buffer) {
1566                 switch (size) {
1567                         case 4:
1568                                 retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
1569                                 break;
1570                         case 2:
1571                                 retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
1572                                 break;
1573                         case 1:
1574                                 retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
1575                                 break;
1576                 }
1577         }
1578
1579         return retval;
1580 }
1581
1582 static int cortex_m3_write_memory(struct target *target, uint32_t address,
1583         uint32_t size, uint32_t count, const uint8_t *buffer)
1584 {
1585         struct armv7m_common *armv7m = target_to_armv7m(target);
1586         struct adiv5_dap *swjdp = &armv7m->dap;
1587         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1588
1589         if (count && buffer) {
1590                 switch (size) {
1591                         case 4:
1592                                 retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
1593                                 break;
1594                         case 2:
1595                                 retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
1596                                 break;
1597                         case 1:
1598                                 retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
1599                                 break;
1600                 }
1601         }
1602
1603         return retval;
1604 }
1605
1606 static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
1607         uint32_t count, const uint8_t *buffer)
1608 {
1609         return cortex_m3_write_memory(target, address, 4, count, buffer);
1610 }
1611
1612 static int cortex_m3_init_target(struct command_context *cmd_ctx,
1613         struct target *target)
1614 {
1615         armv7m_build_reg_cache(target);
1616         return ERROR_OK;
1617 }
1618
1619 /* REVISIT cache valid/dirty bits are unmaintained.  We could set "valid"
1620  * on r/w if the core is not running, and clear on resume or reset ... or
1621  * at least, in a post_restore_context() method.
1622  */
1623
1624 struct dwt_reg_state {
1625         struct target *target;
1626         uint32_t addr;
1627         uint32_t value;         /* scratch/cache */
1628 };
1629
1630 static int cortex_m3_dwt_get_reg(struct reg *reg)
1631 {
1632         struct dwt_reg_state *state = reg->arch_info;
1633
1634         return target_read_u32(state->target, state->addr, &state->value);
1635 }
1636
1637 static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
1638 {
1639         struct dwt_reg_state *state = reg->arch_info;
1640
1641         return target_write_u32(state->target, state->addr,
1642                         buf_get_u32(buf, 0, reg->size));
1643 }
1644
1645 struct dwt_reg {
1646         uint32_t addr;
1647         char *name;
1648         unsigned size;
1649 };
1650
1651 static struct dwt_reg dwt_base_regs[] = {
1652         { DWT_CTRL, "dwt_ctrl", 32, },
1653         /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT:  it wrongly
1654          * increments while the core is asleep.
1655          */
1656         { DWT_CYCCNT, "dwt_cyccnt", 32, },
1657         /* plus some 8 bit counters, useful for profiling with TPIU */
1658 };
1659
1660 static struct dwt_reg dwt_comp[] = {
1661 #define DWT_COMPARATOR(i) \
1662                 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1663                 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1664                 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1665         DWT_COMPARATOR(0),
1666         DWT_COMPARATOR(1),
1667         DWT_COMPARATOR(2),
1668         DWT_COMPARATOR(3),
1669 #undef DWT_COMPARATOR
1670 };
1671
1672 static const struct reg_arch_type dwt_reg_type = {
1673         .get = cortex_m3_dwt_get_reg,
1674         .set = cortex_m3_dwt_set_reg,
1675 };
1676
1677 static void cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
1678 {
1679         struct dwt_reg_state *state;
1680
1681         state = calloc(1, sizeof *state);
1682         if (!state)
1683                 return;
1684         state->addr = d->addr;
1685         state->target = t;
1686
1687         r->name = d->name;
1688         r->size = d->size;
1689         r->value = &state->value;
1690         r->arch_info = state;
1691         r->type = &dwt_reg_type;
1692 }
1693
1694 void cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
1695 {
1696         uint32_t dwtcr;
1697         struct reg_cache *cache;
1698         struct cortex_m3_dwt_comparator *comparator;
1699         int reg, i;
1700
1701         target_read_u32(target, DWT_CTRL, &dwtcr);
1702         if (!dwtcr) {
1703                 LOG_DEBUG("no DWT");
1704                 return;
1705         }
1706
1707         cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
1708         cm3->dwt_comp_available = cm3->dwt_num_comp;
1709         cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
1710                         sizeof(struct cortex_m3_dwt_comparator));
1711         if (!cm3->dwt_comparator_list) {
1712 fail0:
1713                 cm3->dwt_num_comp = 0;
1714                 LOG_ERROR("out of mem");
1715                 return;
1716         }
1717
1718         cache = calloc(1, sizeof *cache);
1719         if (!cache) {
1720 fail1:
1721                 free(cm3->dwt_comparator_list);
1722                 goto fail0;
1723         }
1724         cache->name = "cortex-m3 dwt registers";
1725         cache->num_regs = 2 + cm3->dwt_num_comp * 3;
1726         cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
1727         if (!cache->reg_list) {
1728                 free(cache);
1729                 goto fail1;
1730         }
1731
1732         for (reg = 0; reg < 2; reg++)
1733                 cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1734                         dwt_base_regs + reg);
1735
1736         comparator = cm3->dwt_comparator_list;
1737         for (i = 0; i < cm3->dwt_num_comp; i++, comparator++) {
1738                 int j;
1739
1740                 comparator->dwt_comparator_address = DWT_COMP0 + 0x10 * i;
1741                 for (j = 0; j < 3; j++, reg++)
1742                         cortex_m3_dwt_addreg(target, cache->reg_list + reg,
1743                                 dwt_comp + 3 * i + j);
1744         }
1745
1746         *register_get_last_cache_p(&target->reg_cache) = cache;
1747         cm3->dwt_cache = cache;
1748
1749         LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
1750                 dwtcr, cm3->dwt_num_comp,
1751                 (dwtcr & (0xf << 24)) ? " only" : "/trigger");
1752
1753         /* REVISIT:  if num_comp > 1, check whether comparator #1 can
1754          * implement single-address data value watchpoints ... so we
1755          * won't need to check it later, when asked to set one up.
1756          */
1757 }
1758
1759 static int cortex_m3_examine(struct target *target)
1760 {
1761         int retval;
1762         uint32_t cpuid, fpcr;
1763         int i;
1764         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1765         struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
1766
1767         retval = ahbap_debugport_init(swjdp);
1768         if (retval != ERROR_OK)
1769                 return retval;
1770
1771         if (!target_was_examined(target)) {
1772                 target_set_examined(target);
1773
1774                 /* Read from Device Identification Registers */
1775                 retval = target_read_u32(target, CPUID, &cpuid);
1776                 if (retval != ERROR_OK)
1777                         return retval;
1778
1779                 if (((cpuid >> 4) & 0xc3f) == 0xc23)
1780                         LOG_DEBUG("Cortex-M3 r%" PRId8 "p%" PRId8 " processor detected",
1781                                 (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
1782                 LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
1783
1784                 /* NOTE: FPB and DWT are both optional. */
1785
1786                 /* Setup FPB */
1787                 target_read_u32(target, FP_CTRL, &fpcr);
1788                 cortex_m3->auto_bp_type = 1;
1789                 cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);    /* bits
1790                                                                                          *[14:12]
1791                                                                                          *and [7:4]
1792                                                                                          **/
1793                 cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
1794                 cortex_m3->fp_code_available = cortex_m3->fp_num_code;
1795                 cortex_m3->fp_comparator_list = calloc(
1796                                 cortex_m3->fp_num_code + cortex_m3->fp_num_lit,
1797                                 sizeof(struct cortex_m3_fp_comparator));
1798                 cortex_m3->fpb_enabled = fpcr & 1;
1799                 for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++) {
1800                         cortex_m3->fp_comparator_list[i].type =
1801                                 (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
1802                         cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
1803                 }
1804                 LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
1805                         fpcr,
1806                         cortex_m3->fp_num_code,
1807                         cortex_m3->fp_num_lit);
1808
1809                 /* Setup DWT */
1810                 cortex_m3_dwt_setup(cortex_m3, target);
1811
1812                 /* These hardware breakpoints only work for code in flash! */
1813                 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1814                         target_name(target),
1815                         cortex_m3->fp_num_code,
1816                         cortex_m3->dwt_num_comp);
1817         }
1818
1819         return ERROR_OK;
1820 }
1821
1822 static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
1823 {
1824         uint16_t dcrdr;
1825         int retval;
1826
1827         mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
1828         *ctrl = (uint8_t)dcrdr;
1829         *value = (uint8_t)(dcrdr >> 8);
1830
1831         LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
1832
1833         /* write ack back to software dcc register
1834          * signify we have read data */
1835         if (dcrdr & (1 << 0)) {
1836                 dcrdr = 0;
1837                 retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
1838                 if (retval != ERROR_OK)
1839                         return retval;
1840         }
1841
1842         return ERROR_OK;
1843 }
1844
1845 static int cortex_m3_target_request_data(struct target *target,
1846         uint32_t size, uint8_t *buffer)
1847 {
1848         struct armv7m_common *armv7m = target_to_armv7m(target);
1849         struct adiv5_dap *swjdp = &armv7m->dap;
1850         uint8_t data;
1851         uint8_t ctrl;
1852         uint32_t i;
1853
1854         for (i = 0; i < (size * 4); i++) {
1855                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1856                 buffer[i] = data;
1857         }
1858
1859         return ERROR_OK;
1860 }
1861
1862 static int cortex_m3_handle_target_request(void *priv)
1863 {
1864         struct target *target = priv;
1865         if (!target_was_examined(target))
1866                 return ERROR_OK;
1867         struct armv7m_common *armv7m = target_to_armv7m(target);
1868         struct adiv5_dap *swjdp = &armv7m->dap;
1869
1870         if (!target->dbg_msg_enabled)
1871                 return ERROR_OK;
1872
1873         if (target->state == TARGET_RUNNING) {
1874                 uint8_t data;
1875                 uint8_t ctrl;
1876
1877                 cortex_m3_dcc_read(swjdp, &data, &ctrl);
1878
1879                 /* check if we have data */
1880                 if (ctrl & (1 << 0)) {
1881                         uint32_t request;
1882
1883                         /* we assume target is quick enough */
1884                         request = data;
1885                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1886                         request |= (data << 8);
1887                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1888                         request |= (data << 16);
1889                         cortex_m3_dcc_read(swjdp, &data, &ctrl);
1890                         request |= (data << 24);
1891                         target_request(target, request);
1892                 }
1893         }
1894
1895         return ERROR_OK;
1896 }
1897
1898 static int cortex_m3_init_arch_info(struct target *target,
1899         struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
1900 {
1901         int retval;
1902         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1903
1904         armv7m_init_arch_info(target, armv7m);
1905
1906         /* prepare JTAG information for the new target */
1907         cortex_m3->jtag_info.tap = tap;
1908         cortex_m3->jtag_info.scann_size = 4;
1909
1910         /* default reset mode is to use srst if fitted
1911          * if not it will use CORTEX_M3_RESET_VECTRESET */
1912         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
1913
1914         armv7m->arm.dap = &armv7m->dap;
1915
1916         /* Leave (only) generic DAP stuff for debugport_init(); */
1917         armv7m->dap.jtag_info = &cortex_m3->jtag_info;
1918         armv7m->dap.memaccess_tck = 8;
1919         /* Cortex-M3 has 4096 bytes autoincrement range */
1920         armv7m->dap.tar_autoincr_block = (1 << 12);
1921
1922         /* register arch-specific functions */
1923         armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
1924
1925         armv7m->post_debug_entry = NULL;
1926
1927         armv7m->pre_restore_context = NULL;
1928
1929         armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
1930         armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
1931
1932         target_register_timer_callback(cortex_m3_handle_target_request, 1, 1, target);
1933
1934         retval = arm_jtag_setup_connection(&cortex_m3->jtag_info);
1935         if (retval != ERROR_OK)
1936                 return retval;
1937
1938         return ERROR_OK;
1939 }
1940
1941 static int cortex_m3_target_create(struct target *target, Jim_Interp *interp)
1942 {
1943         struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common));
1944
1945         cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
1946         cortex_m3_init_arch_info(target, cortex_m3, target->tap);
1947
1948         return ERROR_OK;
1949 }
1950
1951 /*--------------------------------------------------------------------------*/
1952
1953 static int cortex_m3_verify_pointer(struct command_context *cmd_ctx,
1954         struct cortex_m3_common *cm3)
1955 {
1956         if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
1957                 command_print(cmd_ctx, "target is not a Cortex-M3");
1958                 return ERROR_TARGET_INVALID;
1959         }
1960         return ERROR_OK;
1961 }
1962
1963 /*
1964  * Only stuff below this line should need to verify that its target
1965  * is a Cortex-M3.  Everything else should have indirected through the
1966  * cortexm3_target structure, which is only used with CM3 targets.
1967  */
1968
1969 static const struct {
1970         char name[10];
1971         unsigned mask;
1972 } vec_ids[] = {
1973         { "hard_err",   VC_HARDERR, },
1974         { "int_err",    VC_INTERR, },
1975         { "bus_err",    VC_BUSERR, },
1976         { "state_err",  VC_STATERR, },
1977         { "chk_err",    VC_CHKERR, },
1978         { "nocp_err",   VC_NOCPERR, },
1979         { "mm_err",     VC_MMERR, },
1980         { "reset",      VC_CORERESET, },
1981 };
1982
1983 COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
1984 {
1985         struct target *target = get_current_target(CMD_CTX);
1986         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
1987         struct armv7m_common *armv7m = &cortex_m3->armv7m;
1988         struct adiv5_dap *swjdp = &armv7m->dap;
1989         uint32_t demcr = 0;
1990         int retval;
1991
1992         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
1993         if (retval != ERROR_OK)
1994                 return retval;
1995
1996         retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
1997         if (retval != ERROR_OK)
1998                 return retval;
1999
2000         if (CMD_ARGC > 0) {
2001                 unsigned catch = 0;
2002
2003                 if (CMD_ARGC == 1) {
2004                         if (strcmp(CMD_ARGV[0], "all") == 0) {
2005                                 catch = VC_HARDERR | VC_INTERR | VC_BUSERR
2006                                         | VC_STATERR | VC_CHKERR | VC_NOCPERR
2007                                         | VC_MMERR | VC_CORERESET;
2008                                 goto write;
2009                         } else if (strcmp(CMD_ARGV[0], "none") == 0)
2010                                 goto write;
2011                 }
2012                 while (CMD_ARGC-- > 0) {
2013                         unsigned i;
2014                         for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2015                                 if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
2016                                         continue;
2017                                 catch |= vec_ids[i].mask;
2018                                 break;
2019                         }
2020                         if (i == ARRAY_SIZE(vec_ids)) {
2021                                 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
2022                                 return ERROR_COMMAND_SYNTAX_ERROR;
2023                         }
2024                 }
2025 write:
2026                 /* For now, armv7m->demcr only stores vector catch flags. */
2027                 armv7m->demcr = catch;
2028
2029                 demcr &= ~0xffff;
2030                 demcr |= catch;
2031
2032                 /* write, but don't assume it stuck (why not??) */
2033                 retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
2034                 if (retval != ERROR_OK)
2035                         return retval;
2036                 retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
2037                 if (retval != ERROR_OK)
2038                         return retval;
2039
2040                 /* FIXME be sure to clear DEMCR on clean server shutdown.
2041                  * Otherwise the vector catch hardware could fire when there's
2042                  * no debugger hooked up, causing much confusion...
2043                  */
2044         }
2045
2046         for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
2047                 command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
2048                         (demcr & vec_ids[i].mask) ? "catch" : "ignore");
2049         }
2050
2051         return ERROR_OK;
2052 }
2053
2054 COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
2055 {
2056         struct target *target = get_current_target(CMD_CTX);
2057         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2058         int retval;
2059
2060         static const Jim_Nvp nvp_maskisr_modes[] = {
2061                 { .name = "auto", .value = CORTEX_M3_ISRMASK_AUTO },
2062                 { .name = "off", .value = CORTEX_M3_ISRMASK_OFF },
2063                 { .name = "on", .value = CORTEX_M3_ISRMASK_ON },
2064                 { .name = NULL, .value = -1 },
2065         };
2066         const Jim_Nvp *n;
2067
2068
2069         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2070         if (retval != ERROR_OK)
2071                 return retval;
2072
2073         if (target->state != TARGET_HALTED) {
2074                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
2075                 return ERROR_OK;
2076         }
2077
2078         if (CMD_ARGC > 0) {
2079                 n = Jim_Nvp_name2value_simple(nvp_maskisr_modes, CMD_ARGV[0]);
2080                 if (n->name == NULL)
2081                         return ERROR_COMMAND_SYNTAX_ERROR;
2082                 cortex_m3->isrmasking_mode = n->value;
2083
2084
2085                 if (cortex_m3->isrmasking_mode == CORTEX_M3_ISRMASK_ON)
2086                         cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
2087                 else
2088                         cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
2089         }
2090
2091         n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m3->isrmasking_mode);
2092         command_print(CMD_CTX, "cortex_m3 interrupt mask %s", n->name);
2093
2094         return ERROR_OK;
2095 }
2096
2097 COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
2098 {
2099         struct target *target = get_current_target(CMD_CTX);
2100         struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
2101         int retval;
2102         char *reset_config;
2103
2104         retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
2105         if (retval != ERROR_OK)
2106                 return retval;
2107
2108         if (CMD_ARGC > 0) {
2109                 if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
2110                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
2111                 else if (strcmp(*CMD_ARGV, "vectreset") == 0)
2112                         cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
2113         }
2114
2115         switch (cortex_m3->soft_reset_config) {
2116                 case CORTEX_M3_RESET_SYSRESETREQ:
2117                         reset_config = "sysresetreq";
2118                         break;
2119
2120                 case CORTEX_M3_RESET_VECTRESET:
2121                         reset_config = "vectreset";
2122                         break;
2123
2124                 default:
2125                         reset_config = "unknown";
2126                         break;
2127         }
2128
2129         command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
2130
2131         return ERROR_OK;
2132 }
2133
2134 static const struct command_registration cortex_m3_exec_command_handlers[] = {
2135         {
2136                 .name = "maskisr",
2137                 .handler = handle_cortex_m3_mask_interrupts_command,
2138                 .mode = COMMAND_EXEC,
2139                 .help = "mask cortex_m3 interrupts",
2140                 .usage = "['auto'|'on'|'off']",
2141         },
2142         {
2143                 .name = "vector_catch",
2144                 .handler = handle_cortex_m3_vector_catch_command,
2145                 .mode = COMMAND_EXEC,
2146                 .help = "configure hardware vectors to trigger debug entry",
2147                 .usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2148         },
2149         {
2150                 .name = "reset_config",
2151                 .handler = handle_cortex_m3_reset_config_command,
2152                 .mode = COMMAND_ANY,
2153                 .help = "configure software reset handling",
2154                 .usage = "['srst'|'sysresetreq'|'vectreset']",
2155         },
2156         COMMAND_REGISTRATION_DONE
2157 };
2158 static const struct command_registration cortex_m3_command_handlers[] = {
2159         {
2160                 .chain = armv7m_command_handlers,
2161         },
2162         {
2163                 .name = "cortex_m3",
2164                 .mode = COMMAND_EXEC,
2165                 .help = "Cortex-M3 command group",
2166                 .usage = "",
2167                 .chain = cortex_m3_exec_command_handlers,
2168         },
2169         COMMAND_REGISTRATION_DONE
2170 };
2171
2172 struct target_type cortexm3_target = {
2173         .name = "cortex_m3",
2174
2175         .poll = cortex_m3_poll,
2176         .arch_state = armv7m_arch_state,
2177
2178         .target_request_data = cortex_m3_target_request_data,
2179
2180         .halt = cortex_m3_halt,
2181         .resume = cortex_m3_resume,
2182         .step = cortex_m3_step,
2183
2184         .assert_reset = cortex_m3_assert_reset,
2185         .deassert_reset = cortex_m3_deassert_reset,
2186         .soft_reset_halt = cortex_m3_soft_reset_halt,
2187
2188         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
2189
2190         .read_memory = cortex_m3_read_memory,
2191         .write_memory = cortex_m3_write_memory,
2192         .bulk_write_memory = cortex_m3_bulk_write_memory,
2193         .checksum_memory = armv7m_checksum_memory,
2194         .blank_check_memory = armv7m_blank_check_memory,
2195
2196         .run_algorithm = armv7m_run_algorithm,
2197         .start_algorithm = armv7m_start_algorithm,
2198         .wait_algorithm = armv7m_wait_algorithm,
2199
2200         .add_breakpoint = cortex_m3_add_breakpoint,
2201         .remove_breakpoint = cortex_m3_remove_breakpoint,
2202         .add_watchpoint = cortex_m3_add_watchpoint,
2203         .remove_watchpoint = cortex_m3_remove_watchpoint,
2204
2205         .commands = cortex_m3_command_handlers,
2206         .target_create = cortex_m3_target_create,
2207         .init_target = cortex_m3_init_target,
2208         .examine = cortex_m3_examine,
2209 };