1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
13 * Copyright (C) 2009 by Dirk Behme *
14 * dirk.behme@gmail.com - copy from cortex_m3 *
15 ***************************************************************************/
17 #ifndef OPENOCD_TARGET_CORTEX_A_H
18 #define OPENOCD_TARGET_CORTEX_A_H
22 #define CORTEX_A_COMMON_MAGIC 0x411fc082
23 #define CORTEX_A15_COMMON_MAGIC 0x413fc0f1
25 #define CORTEX_A5_PARTNUM 0xc05
26 #define CORTEX_A7_PARTNUM 0xc07
27 #define CORTEX_A8_PARTNUM 0xc08
28 #define CORTEX_A9_PARTNUM 0xc09
29 #define CORTEX_A15_PARTNUM 0xc0f
30 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
31 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
33 #define CPUDBG_CPUID 0xD00
34 #define CPUDBG_CTYPR 0xD04
35 #define CPUDBG_TTYPR 0xD0C
36 #define CPUDBG_LOCKACCESS 0xFB0
37 #define CPUDBG_LOCKSTATUS 0xFB4
38 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
43 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
45 enum cortex_a_isrmasking_mode {
50 enum cortex_a_dacrfixup_mode {
51 CORTEX_A_DACRFIXUP_OFF,
70 struct cortex_a_common {
73 /* Context information */
76 /* Saved cp15 registers */
77 uint32_t cp15_control_reg;
78 /* latest cp15 register value written and cpsr processor mode */
79 uint32_t cp15_control_reg_curr;
80 /* auxiliary control reg */
81 uint32_t cp15_aux_control_reg;
83 uint32_t cp15_dacr_reg;
84 enum arm_mode curr_mode;
86 /* Breakpoint register pairs */
89 int brp_num_available;
90 struct cortex_a_brp *brp_list;
92 int wrp_num_available;
93 struct cortex_a_wrp *wrp_list;
98 enum cortex_a_isrmasking_mode isrmasking_mode;
99 enum cortex_a_dacrfixup_mode dacrfixup_mode;
101 struct armv7a_common armv7a_common;
105 static inline struct cortex_a_common *
106 target_to_cortex_a(struct target *target)
108 return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
111 #endif /* OPENOCD_TARGET_CORTEX_A_H */