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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  *                                                                         *
   7  *   Copyright (C) 2006 by Magnus Lundin                                   *
   8  *   lundin@mlu.mine.nu                                                    *
   9  *                                                                         *
  10  *   Copyright (C) 2008 by Spencer Oliver                                  *
  11  *   spen@spen-soft.co.uk                                                  *
  12  *                                                                         *
  13  *   Copyright (C) 2009 by Dirk Behme                                      *
  14  *   dirk.behme@gmail.com - copy from cortex_m3                            *
  15  ***************************************************************************/
  16
  17 #ifndef OPENOCD_TARGET_CORTEX_A_H
  18 #define OPENOCD_TARGET_CORTEX_A_H
  19
  20 #include "armv7a.h"
  21
  22 #define CORTEX_A_COMMON_MAGIC 0x411fc082
  23
  24 #define CORTEX_A5_PARTNUM 0xc05
  25 #define CORTEX_A7_PARTNUM 0xc07
  26 #define CORTEX_A8_PARTNUM 0xc08
  27 #define CORTEX_A9_PARTNUM 0xc09
  28 #define CORTEX_A15_PARTNUM 0xc0f
  29 #define CORTEX_A_MIDR_PARTNUM_MASK 0x0000fff0
  30 #define CORTEX_A_MIDR_PARTNUM_SHIFT 4
  31
  32 #define CPUDBG_CPUID    0xD00
  33 #define CPUDBG_CTYPR    0xD04
  34 #define CPUDBG_TTYPR    0xD0C
  35 #define CPUDBG_LOCKACCESS 0xFB0
  36 #define CPUDBG_LOCKSTATUS 0xFB4
  37 #define CPUDBG_OSLAR_LK_MASK (1 << 1)
  38
  39 #define BRP_NORMAL 0
  40 #define BRP_CONTEXT 1
  41
  42 #define CORTEX_A_PADDRDBG_CPU_SHIFT 13
  43
  44 enum cortex_a_isrmasking_mode {
  45         CORTEX_A_ISRMASK_OFF,
  46         CORTEX_A_ISRMASK_ON,
  47 };
  48
  49 enum cortex_a_dacrfixup_mode {
  50         CORTEX_A_DACRFIXUP_OFF,
  51         CORTEX_A_DACRFIXUP_ON
  52 };
  53
  54 struct cortex_a_brp {
  55         bool used;
  56         int type;
  57         uint32_t value;
  58         uint32_t control;
  59         uint8_t brpn;
  60 };
  61
  62 struct cortex_a_wrp {
  63         bool used;
  64         uint32_t value;
  65         uint32_t control;
  66         uint8_t wrpn;
  67 };
  68
  69 struct cortex_a_common {
  70         int common_magic;
  71
  72         /* Context information */
  73         uint32_t cpudbg_dscr;
  74
  75         /* Saved cp15 registers */
  76         uint32_t cp15_control_reg;
  77         /* latest cp15 register value written and cpsr processor mode */
  78         uint32_t cp15_control_reg_curr;
  79         /* auxiliary control reg */
  80         uint32_t cp15_aux_control_reg;
  81         /* DACR */
  82         uint32_t cp15_dacr_reg;
  83         enum arm_mode curr_mode;
  84
  85         /* Breakpoint register pairs */
  86         int brp_num_context;
  87         int brp_num;
  88         int brp_num_available;
  89         struct cortex_a_brp *brp_list;
  90         int wrp_num;
  91         int wrp_num_available;
  92         struct cortex_a_wrp *wrp_list;
  93
  94         uint32_t cpuid;
  95         uint32_t didr;
  96
  97         enum cortex_a_isrmasking_mode isrmasking_mode;
  98         enum cortex_a_dacrfixup_mode dacrfixup_mode;
  99
 100         struct armv7a_common armv7a_common;
 101
 102 };
 103
 104 static inline struct cortex_a_common *
 105 target_to_cortex_a(struct target *target)
 106 {
 107         return container_of(target->arch_info, struct cortex_a_common, armv7a_common.arm);
 108 }
 109
 110 #endif /* OPENOCD_TARGET_CORTEX_A_H */