1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 ***************************************************************************/
12 #include <helper/log.h>
14 #include "armv4_5_mmu.h"
16 int armv4_5_mmu_translate_va(struct target *target,
17 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t va, uint32_t *cb, uint32_t *val)
19 uint32_t first_lvl_descriptor = 0x0;
20 uint32_t second_lvl_descriptor = 0x0;
23 retval = armv4_5_mmu->get_ttb(target, &ttb);
24 if (retval != ERROR_OK)
27 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
28 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
29 4, 1, (uint8_t *)&first_lvl_descriptor);
30 if (retval != ERROR_OK)
32 first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
34 LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
36 if ((first_lvl_descriptor & 0x3) == 0) {
37 LOG_ERROR("Address translation failure");
38 return ERROR_TARGET_TRANSLATION_FAULT;
41 if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3)) {
42 LOG_ERROR("Address translation failure");
43 return ERROR_TARGET_TRANSLATION_FAULT;
46 if ((first_lvl_descriptor & 0x3) == 2) {
47 /* section descriptor */
48 *cb = (first_lvl_descriptor & 0xc) >> 2;
49 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
53 if ((first_lvl_descriptor & 0x3) == 1) {
54 /* coarse page table */
55 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
56 (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
57 4, 1, (uint8_t *)&second_lvl_descriptor);
58 if (retval != ERROR_OK)
60 } else if ((first_lvl_descriptor & 0x3) == 3) {
62 retval = armv4_5_mmu_read_physical(target, armv4_5_mmu,
63 (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
64 4, 1, (uint8_t *)&second_lvl_descriptor);
65 if (retval != ERROR_OK)
69 second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
71 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
73 if ((second_lvl_descriptor & 0x3) == 0) {
74 LOG_ERROR("Address translation failure");
75 return ERROR_TARGET_TRANSLATION_FAULT;
78 /* cacheable/bufferable is always specified in bits 3-2 */
79 *cb = (second_lvl_descriptor & 0xc) >> 2;
81 if ((second_lvl_descriptor & 0x3) == 1) {
82 /* large page descriptor */
83 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
87 if ((second_lvl_descriptor & 0x3) == 2) {
88 /* small page descriptor */
89 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
93 if ((second_lvl_descriptor & 0x3) == 3) {
94 /* tiny page descriptor */
95 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
99 /* should not happen */
100 LOG_ERROR("Address translation failure");
101 return ERROR_TARGET_TRANSLATION_FAULT;
104 int armv4_5_mmu_read_physical(struct target *target,
105 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
106 uint32_t size, uint32_t count, uint8_t *buffer)
110 if (target->state != TARGET_HALTED)
111 return ERROR_TARGET_NOT_HALTED;
113 /* disable MMU and data (or unified) cache */
114 retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
115 if (retval != ERROR_OK)
118 retval = armv4_5_mmu->read_memory(target, address, size, count, buffer);
119 if (retval != ERROR_OK)
122 /* reenable MMU / cache */
123 retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
124 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
125 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
126 if (retval != ERROR_OK)
132 int armv4_5_mmu_write_physical(struct target *target,
133 struct armv4_5_mmu_common *armv4_5_mmu, uint32_t address,
134 uint32_t size, uint32_t count, const uint8_t *buffer)
138 if (target->state != TARGET_HALTED)
139 return ERROR_TARGET_NOT_HALTED;
141 /* disable MMU and data (or unified) cache */
142 retval = armv4_5_mmu->disable_mmu_caches(target, 1, 1, 0);
143 if (retval != ERROR_OK)
146 retval = armv4_5_mmu->write_memory(target, address, size, count, buffer);
147 if (retval != ERROR_OK)
150 /* reenable MMU / cache */
151 retval = armv4_5_mmu->enable_mmu_caches(target, armv4_5_mmu->mmu_enabled,
152 armv4_5_mmu->armv4_5_cache.d_u_cache_enabled,
153 armv4_5_mmu->armv4_5_cache.i_cache_enabled);
154 if (retval != ERROR_OK)