git.gag.com Git - fw/openocd/blob - src/target/arm_adi_v5.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 /**
  28  * @file
  29  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  30  * debugging architecture.  Compared with previous versions, this includes
  31  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  32  * transport, and focusses on memory mapped resources as defined by the
  33  * CoreSight architecture.
  34  *
  35  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  36  * basic components:  a Debug Port (DP) transporting messages to and from a
  37  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  38  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  39  * One uses only SWD for communication, and is called SW-DP.  The third can
  40  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  41  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  42  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  43  */
  44
  45 /*
  46  * Relevant specifications from ARM include:
  47  *
  48  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  49  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  50  *
  51  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  52  * Cortex-M3(tm) TRM, ARM DDI 0337G
  53  */
  54
  55 #ifdef HAVE_CONFIG_H
  56 #include "config.h"
  57 #endif
  58
  59 #include "arm_adi_v5.h"
  60 #include <helper/time_support.h>
  61
  62 /*
  63  * Transaction Mode:
  64  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  66  * result checking until swjdp_end_transaction()
  67  * This must be done before using or deallocating any return variables.
  68  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  69  * All reads and writes to the AHB bus are checked for valid completion, and return values
  70  * are immediatley available.
  71 */
  72
  73
  74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  75
  76 /*
  77         uint32_t tar_block_size(uint32_t address)
  78         Return the largest block starting at address that does not cross a tar block size alignment boundary
  79 */
  80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  81 {
  82         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  83 }
  84
  85 /***************************************************************************
  86  *                                                                         *
  87  * DPACC and APACC scanchain access through JTAG-DP                        *
  88  *                                                                         *
  89 ***************************************************************************/
  90
  91 /* Scan out and in from target ordered uint8_t buffers */
  92 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
  93                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  94                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
  95 {
  96         struct arm_jtag *jtag_info = swjdp->jtag_info;
  97         struct scan_field fields[2];
  98         uint8_t out_addr_buf;
  99
 100         jtag_set_end_state(TAP_IDLE);
 101         arm_jtag_set_instr(jtag_info, instr, NULL);
 102
 103         /* Add specified number of tck clocks before accessing memory bus */
 104         if ((instr == JTAG_DP_APACC)
 105                         && ((reg_addr == AP_REG_DRW)
 106                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 107                         && (swjdp->memaccess_tck != 0))
 108                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 109
 110         fields[0].tap = jtag_info->tap;
 111         fields[0].num_bits = 3;
 112         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 113         fields[0].out_value = &out_addr_buf;
 114         fields[0].in_value = ack;
 115
 116         fields[1].tap = jtag_info->tap;
 117         fields[1].num_bits = 32;
 118         fields[1].out_value = outvalue;
 119         fields[1].in_value = invalue;
 120
 121         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 122
 123         return ERROR_OK;
 124 }
 125
 126 /* Scan out and in from host ordered uint32_t variables */
 127 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 128                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 129                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 130 {
 131         struct arm_jtag *jtag_info = swjdp->jtag_info;
 132         struct scan_field fields[2];
 133         uint8_t out_value_buf[4];
 134         uint8_t out_addr_buf;
 135
 136         jtag_set_end_state(TAP_IDLE);
 137         arm_jtag_set_instr(jtag_info, instr, NULL);
 138
 139         /* Add specified number of tck clocks before accessing memory bus */
 140         if ((instr == JTAG_DP_APACC)
 141                         && ((reg_addr == AP_REG_DRW)
 142                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 143                         && (swjdp->memaccess_tck != 0))
 144                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 145
 146         fields[0].tap = jtag_info->tap;
 147         fields[0].num_bits = 3;
 148         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 149         fields[0].out_value = &out_addr_buf;
 150         fields[0].in_value = ack;
 151
 152         fields[1].tap = jtag_info->tap;
 153         fields[1].num_bits = 32;
 154         buf_set_u32(out_value_buf, 0, 32, outvalue);
 155         fields[1].out_value = out_value_buf;
 156         fields[1].in_value = NULL;
 157
 158         if (invalue)
 159         {
 160                 fields[1].in_value = (uint8_t *)invalue;
 161                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 162
 163                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 164         } else
 165         {
 166
 167                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 168         }
 169
 170         return ERROR_OK;
 171 }
 172
 173 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 174 static int scan_inout_check(struct swjdp_common *swjdp,
 175                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 176                 uint8_t *outvalue, uint8_t *invalue)
 177 {
 178         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 179
 180         if ((RnW == DPAP_READ) && (invalue != NULL))
 181                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 182                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 183
 184         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 185          * ack = OK/FAULT and the check CTRL_STAT
 186          */
 187         if ((instr == JTAG_DP_APACC)
 188                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 189                 return swjdp_transaction_endcheck(swjdp);
 190
 191         return ERROR_OK;
 192 }
 193
 194 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 195                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 196                 uint32_t outvalue, uint32_t *invalue)
 197 {
 198         /* Issue the read or write */
 199         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 200
 201         /* For reads,  collect posted value; RDBUFF has no other effect.
 202          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 203          */
 204         if ((RnW == DPAP_READ) && (invalue != NULL))
 205                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 206                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 207
 208         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 209          * ack = OK/FAULT and then check CTRL_STAT
 210          */
 211         if ((instr == JTAG_DP_APACC)
 212                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 213                 return swjdp_transaction_endcheck(swjdp);
 214
 215         return ERROR_OK;
 216 }
 217
 218 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 219 {
 220         int retval;
 221         uint32_t ctrlstat;
 222
 223         /* too expensive to call keep_alive() here */
 224
 225 #if 0
 226         /* Danger!!!! BROKEN!!!! */
 227         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 228                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 229         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 230         R956 introduced the check on return value here and now Michael Schwingen reports
 231         that this code no longer works....
 232
 233         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 234         */
 235         if ((retval = jtag_execute_queue()) != ERROR_OK)
 236         {
 237                 LOG_ERROR("BUG: Why does this fail the first time????");
 238         }
 239         /* Why??? second time it works??? */
 240 #endif
 241
 242         /* Post CTRL/STAT read; discard any previous posted read value
 243          * but collect its ACK status.
 244          */
 245         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 246                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 247         if ((retval = jtag_execute_queue()) != ERROR_OK)
 248                 return retval;
 249
 250         swjdp->ack = swjdp->ack & 0x7;
 251
 252         /* common code path avoids calling timeval_ms() */
 253         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 254         {
 255                 long long then = timeval_ms();
 256
 257                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 258                 {
 259                         if (swjdp->ack == JTAG_ACK_WAIT)
 260                         {
 261                                 if ((timeval_ms()-then) > 1000)
 262                                 {
 263                                         /* NOTE:  this would be a good spot
 264                                          * to use JTAG_DP_ABORT.
 265                                          */
 266                                         LOG_WARNING("Timeout (1000ms) waiting "
 267                                                 "for ACK=OK/FAULT "
 268                                                 "in JTAG-DP transaction");
 269                                         return ERROR_JTAG_DEVICE_ERROR;
 270                                 }
 271                         }
 272                         else
 273                         {
 274                                 LOG_WARNING("Invalid ACK "
 275                                                 "in JTAG-DP transaction");
 276                                 return ERROR_JTAG_DEVICE_ERROR;
 277                         }
 278
 279                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 280                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 281                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 282                                 return retval;
 283                         swjdp->ack = swjdp->ack & 0x7;
 284                 }
 285         }
 286
 287         /* Check for STICKYERR and STICKYORUN */
 288         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 289         {
 290                 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
 291                 /* Check power to debug regions */
 292                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 293                 {
 294                          ahbap_debugport_init(swjdp);
 295                 }
 296                 else
 297                 {
 298                         uint32_t mem_ap_csw, mem_ap_tar;
 299
 300                         /* Print information about last AHBAP access */
 301                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
 302                         if (ctrlstat & SSTICKYORUN)
 303                                 LOG_ERROR("JTAG-DP OVERRUN - "
 304                                         "check clock or reduce jtag speed");
 305
 306                         if (ctrlstat & SSTICKYERR)
 307                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 308
 309                         /* Clear Sticky Error Bits */
 310                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 311                                         DP_CTRL_STAT, DPAP_WRITE,
 312                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 313                                                 | SSTICKYERR, NULL);
 314                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 315                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 316                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 317                                 return retval;
 318
 319                         LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
 320
 321                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 322                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 323                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 324                                 return retval;
 325                         LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
 326
 327                 }
 328                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 329                         return retval;
 330                 return ERROR_JTAG_DEVICE_ERROR;
 331         }
 332
 333         return ERROR_OK;
 334 }
 335
 336 /***************************************************************************
 337  *                                                                         *
 338  * DP and MEM-AP  register access  through APACC and DPACC                 *
 339  *                                                                         *
 340 ***************************************************************************/
 341
 342 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 343                 uint32_t value, uint8_t reg_addr)
 344 {
 345         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 346                         reg_addr, DPAP_WRITE, value, NULL);
 347 }
 348
 349 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 350                 uint32_t *value, uint8_t reg_addr)
 351 {
 352         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 353                         reg_addr, DPAP_READ, 0, value);
 354 }
 355
 356 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 357 {
 358         uint32_t select;
 359         select = (apsel << 24) & 0xFF000000;
 360
 361         if (select != swjdp->apsel)
 362         {
 363                 swjdp->apsel = select;
 364                 /* Switching AP invalidates cached values */
 365                 swjdp->dp_select_value = -1;
 366                 swjdp->ap_csw_value = -1;
 367                 swjdp->ap_tar_value = -1;
 368         }
 369
 370         return ERROR_OK;
 371 }
 372
 373 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 374 {
 375         uint32_t select;
 376         select = (ap_reg & 0x000000F0);
 377
 378         if (select != swjdp->dp_select_value)
 379         {
 380                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 381                 swjdp->dp_select_value = select;
 382         }
 383
 384         return ERROR_OK;
 385 }
 386
 387 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 388                 uint32_t reg_addr, uint8_t *out_value_buf)
 389 {
 390         dap_dp_bankselect(swjdp, reg_addr);
 391         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 392                         DPAP_WRITE, out_value_buf, NULL);
 393
 394         return ERROR_OK;
 395 }
 396
 397 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 398 {
 399         uint8_t out_value_buf[4];
 400
 401         buf_set_u32(out_value_buf, 0, 32, value);
 402         dap_dp_bankselect(swjdp, reg_addr);
 403         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 404                         DPAP_WRITE, out_value_buf, NULL);
 405
 406         return ERROR_OK;
 407 }
 408
 409 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 410 {
 411         dap_dp_bankselect(swjdp, reg_addr);
 412         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 413                         DPAP_READ, 0, value);
 414
 415         return ERROR_OK;
 416 }
 417
 418 /***************************************************************************
 419  *                                                                         *
 420  * AHB-AP access to memory and system registers on AHB bus                 *
 421  *                                                                         *
 422 ***************************************************************************/
 423
 424 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 425 {
 426         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 427         if (csw != swjdp->ap_csw_value)
 428         {
 429                 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
 430                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 431                 swjdp->ap_csw_value = csw;
 432         }
 433         if (tar != swjdp->ap_tar_value)
 434         {
 435                 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
 436                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 437                 swjdp->ap_tar_value = tar;
 438         }
 439         if (csw & CSW_ADDRINC_MASK)
 440         {
 441                 /* Do not cache TAR value when autoincrementing */
 442                 swjdp->ap_tar_value = -1;
 443         }
 444         return ERROR_OK;
 445 }
 446
 447 /*****************************************************************************
 448 *                                                                            *
 449 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 450 *                                                                            *
 451 * Read a uint32_t value from memory or system register                            *
 452 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 453 * but with less overhead                                                     *
 454 *****************************************************************************/
 455 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 456 {
 457         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 458
 459         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 460         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 461
 462         return ERROR_OK;
 463 }
 464
 465 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 466 {
 467         mem_ap_read_u32(swjdp, address, value);
 468
 469         return swjdp_transaction_endcheck(swjdp);
 470 }
 471
 472 /*****************************************************************************
 473 *                                                                            *
 474 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 475 *                                                                            *
 476 * Write a uint32_t value to memory or memory mapped register                              *
 477 *                                                                            *
 478 *****************************************************************************/
 479 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 480 {
 481         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 482
 483         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 484         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 485
 486         return ERROR_OK;
 487 }
 488
 489 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 490 {
 491         mem_ap_write_u32(swjdp, address, value);
 492
 493         return swjdp_transaction_endcheck(swjdp);
 494 }
 495
 496 /*****************************************************************************
 497 *                                                                            *
 498 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 499 *                                                                            *
 500 * Write a buffer in target order (little endian)                             *
 501 *                                                                            *
 502 *****************************************************************************/
 503 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 504 {
 505         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 506         uint32_t adr = address;
 507         uint8_t* pBuffer = buffer;
 508
 509         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 510
 511         count >>= 2;
 512         wcount = count;
 513
 514         /* if we have an unaligned access - reorder data */
 515         if (adr & 0x3u)
 516         {
 517                 for (writecount = 0; writecount < count; writecount++)
 518                 {
 519                         int i;
 520                         uint32_t outvalue;
 521                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 522
 523                         for (i = 0; i < 4; i++)
 524                         {
 525                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 526                                 outvalue >>= 8;
 527                                 adr++;
 528                         }
 529                         pBuffer += sizeof(uint32_t);
 530                 }
 531         }
 532
 533         while (wcount > 0)
 534         {
 535                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 536                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 537                 if (wcount < blocksize)
 538                         blocksize = wcount;
 539
 540                 /* handle unaligned data at 4k boundary */
 541                 if (blocksize == 0)
 542                         blocksize = 1;
 543
 544                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 545
 546                 for (writecount = 0; writecount < blocksize; writecount++)
 547                 {
 548                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 549                 }
 550
 551                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 552                 {
 553                         wcount = wcount - blocksize;
 554                         address = address + 4 * blocksize;
 555                         buffer = buffer + 4 * blocksize;
 556                 }
 557                 else
 558                 {
 559                         errorcount++;
 560                 }
 561
 562                 if (errorcount > 1)
 563                 {
 564                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 565                         return ERROR_JTAG_DEVICE_ERROR;
 566                 }
 567         }
 568
 569         return retval;
 570 }
 571
 572 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 573                 uint8_t *buffer, int count, uint32_t address)
 574 {
 575         int retval = ERROR_OK;
 576         int wcount, blocksize, writecount, i;
 577
 578         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 579
 580         wcount = count >> 1;
 581
 582         while (wcount > 0)
 583         {
 584                 int nbytes;
 585
 586                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 587                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 588
 589                 if (wcount < blocksize)
 590                         blocksize = wcount;
 591
 592                 /* handle unaligned data at 4k boundary */
 593                 if (blocksize == 0)
 594                         blocksize = 1;
 595
 596                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 597                 writecount = blocksize;
 598
 599                 do
 600                 {
 601                         nbytes = MIN((writecount << 1), 4);
 602
 603                         if (nbytes < 4)
 604                         {
 605                                 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
 606                                 {
 607                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 608                                         return ERROR_JTAG_DEVICE_ERROR;
 609                                 }
 610
 611                                 address += nbytes >> 1;
 612                         }
 613                         else
 614                         {
 615                                 uint32_t outvalue;
 616                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 617
 618                                 for (i = 0; i < nbytes; i++)
 619                                 {
 620                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 621                                         outvalue >>= 8;
 622                                         address++;
 623                                 }
 624
 625                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 626                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 627                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 628                                 {
 629                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 630                                         return ERROR_JTAG_DEVICE_ERROR;
 631                                 }
 632                         }
 633
 634                         buffer += nbytes >> 1;
 635                         writecount -= nbytes >> 1;
 636
 637                 } while (writecount);
 638                 wcount -= blocksize;
 639         }
 640
 641         return retval;
 642 }
 643
 644 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 645 {
 646         int retval = ERROR_OK;
 647
 648         if (count >= 4)
 649                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 650
 651         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 652
 653         while (count > 0)
 654         {
 655                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 656                 uint16_t svalue;
 657                 memcpy(&svalue, buffer, sizeof(uint16_t));
 658                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 659                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 660                 retval = swjdp_transaction_endcheck(swjdp);
 661                 count -= 2;
 662                 address += 2;
 663                 buffer += 2;
 664         }
 665
 666         return retval;
 667 }
 668
 669 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 670                 uint8_t *buffer, int count, uint32_t address)
 671 {
 672         int retval = ERROR_OK;
 673         int wcount, blocksize, writecount, i;
 674
 675         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 676
 677         wcount = count;
 678
 679         while (wcount > 0)
 680         {
 681                 int nbytes;
 682
 683                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 684                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 685
 686                 if (wcount < blocksize)
 687                         blocksize = wcount;
 688
 689                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 690                 writecount = blocksize;
 691
 692                 do
 693                 {
 694                         nbytes = MIN(writecount, 4);
 695
 696                         if (nbytes < 4)
 697                         {
 698                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 699                                 {
 700                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 701                                         return ERROR_JTAG_DEVICE_ERROR;
 702                                 }
 703
 704                                 address += nbytes;
 705                         }
 706                         else
 707                         {
 708                                 uint32_t outvalue;
 709                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 710
 711                                 for (i = 0; i < nbytes; i++)
 712                                 {
 713                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 714                                         outvalue >>= 8;
 715                                         address++;
 716                                 }
 717
 718                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 719                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 720                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 721                                 {
 722                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 723                                         return ERROR_JTAG_DEVICE_ERROR;
 724                                 }
 725                         }
 726
 727                         buffer += nbytes;
 728                         writecount -= nbytes;
 729
 730                 } while (writecount);
 731                 wcount -= blocksize;
 732         }
 733
 734         return retval;
 735 }
 736
 737 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 738 {
 739         int retval = ERROR_OK;
 740
 741         if (count >= 4)
 742                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 743
 744         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 745
 746         while (count > 0)
 747         {
 748                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 749                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 750                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 751                 retval = swjdp_transaction_endcheck(swjdp);
 752                 count--;
 753                 address++;
 754                 buffer++;
 755         }
 756
 757         return retval;
 758 }
 759
 760 /*********************************************************************************
 761 *                                                                                *
 762 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 763 *                                                                                *
 764 * Read block fast in target order (little endian) into a buffer                  *
 765 *                                                                                *
 766 **********************************************************************************/
 767 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 768 {
 769         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 770         uint32_t adr = address;
 771         uint8_t* pBuffer = buffer;
 772
 773         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 774
 775         count >>= 2;
 776         wcount = count;
 777
 778         while (wcount > 0)
 779         {
 780                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 781                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 782                 if (wcount < blocksize)
 783                         blocksize = wcount;
 784
 785                 /* handle unaligned data at 4k boundary */
 786                 if (blocksize == 0)
 787                         blocksize = 1;
 788
 789                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 790
 791                 /* Scan out first read */
 792                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 793                                 DPAP_READ, 0, NULL, NULL);
 794                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 795                 {
 796                         /* Scan out next read; scan in posted value for the
 797                          * previous one.  Assumes read is acked "OK/FAULT",
 798                          * and CTRL_STAT says that meant "OK".
 799                          */
 800                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 801                                         DPAP_READ, 0, buffer + 4 * readcount,
 802                                         &swjdp->ack);
 803                 }
 804
 805                 /* Scan in last posted value; RDBUFF has no other effect,
 806                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 807                  */
 808                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 809                                 DPAP_READ, 0, buffer + 4 * readcount,
 810                                 &swjdp->ack);
 811                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 812                 {
 813                         wcount = wcount - blocksize;
 814                         address += 4 * blocksize;
 815                         buffer += 4 * blocksize;
 816                 }
 817                 else
 818                 {
 819                         errorcount++;
 820                 }
 821
 822                 if (errorcount > 1)
 823                 {
 824                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 825                         return ERROR_JTAG_DEVICE_ERROR;
 826                 }
 827         }
 828
 829         /* if we have an unaligned access - reorder data */
 830         if (adr & 0x3u)
 831         {
 832                 for (readcount = 0; readcount < count; readcount++)
 833                 {
 834                         int i;
 835                         uint32_t data;
 836                         memcpy(&data, pBuffer, sizeof(uint32_t));
 837
 838                         for (i = 0; i < 4; i++)
 839                         {
 840                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 841                                 pBuffer++;
 842                                 adr++;
 843                         }
 844                 }
 845         }
 846
 847         return retval;
 848 }
 849
 850 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 851                 uint8_t *buffer, int count, uint32_t address)
 852 {
 853         uint32_t invalue;
 854         int retval = ERROR_OK;
 855         int wcount, blocksize, readcount, i;
 856
 857         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 858
 859         wcount = count >> 1;
 860
 861         while (wcount > 0)
 862         {
 863                 int nbytes;
 864
 865                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 866                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 867                 if (wcount < blocksize)
 868                         blocksize = wcount;
 869
 870                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 871
 872                 /* handle unaligned data at 4k boundary */
 873                 if (blocksize == 0)
 874                         blocksize = 1;
 875                 readcount = blocksize;
 876
 877                 do
 878                 {
 879                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 880                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 881                         {
 882                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 883                                 return ERROR_JTAG_DEVICE_ERROR;
 884                         }
 885
 886                         nbytes = MIN((readcount << 1), 4);
 887
 888                         for (i = 0; i < nbytes; i++)
 889                         {
 890                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 891                                 buffer++;
 892                                 address++;
 893                         }
 894
 895                         readcount -= (nbytes >> 1);
 896                 } while (readcount);
 897                 wcount -= blocksize;
 898         }
 899
 900         return retval;
 901 }
 902
 903 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 904 {
 905         uint32_t invalue, i;
 906         int retval = ERROR_OK;
 907
 908         if (count >= 4)
 909                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 910
 911         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 912
 913         while (count > 0)
 914         {
 915                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 916                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 917                 retval = swjdp_transaction_endcheck(swjdp);
 918                 if (address & 0x1)
 919                 {
 920                         for (i = 0; i < 2; i++)
 921                         {
 922                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 923                                 buffer++;
 924                                 address++;
 925                         }
 926                 }
 927                 else
 928                 {
 929                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 930                         memcpy(buffer, &svalue, sizeof(uint16_t));
 931                         address += 2;
 932                         buffer += 2;
 933                 }
 934                 count -= 2;
 935         }
 936
 937         return retval;
 938 }
 939
 940 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 941  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 942  *
 943  * The solution is to arrange for a large out/in scan in this loop and
 944  * and convert data afterwards.
 945  */
 946 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 947                 uint8_t *buffer, int count, uint32_t address)
 948 {
 949         uint32_t invalue;
 950         int retval = ERROR_OK;
 951         int wcount, blocksize, readcount, i;
 952
 953         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 954
 955         wcount = count;
 956
 957         while (wcount > 0)
 958         {
 959                 int nbytes;
 960
 961                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 962                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 963
 964                 if (wcount < blocksize)
 965                         blocksize = wcount;
 966
 967                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 968                 readcount = blocksize;
 969
 970                 do
 971                 {
 972                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 973                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 974                         {
 975                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 976                                 return ERROR_JTAG_DEVICE_ERROR;
 977                         }
 978
 979                         nbytes = MIN(readcount, 4);
 980
 981                         for (i = 0; i < nbytes; i++)
 982                         {
 983                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 984                                 buffer++;
 985                                 address++;
 986                         }
 987
 988                         readcount -= nbytes;
 989                 } while (readcount);
 990                 wcount -= blocksize;
 991         }
 992
 993         return retval;
 994 }
 995
 996 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 997 {
 998         uint32_t invalue;
 999         int retval = ERROR_OK;
1000
1001         if (count >= 4)
1002                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1003
1004         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1005
1006         while (count > 0)
1007         {
1008                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1009                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1010                 retval = swjdp_transaction_endcheck(swjdp);
1011                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1012                 count--;
1013                 address++;
1014                 buffer++;
1015         }
1016
1017         return retval;
1018 }
1019
1020 /**
1021  * Initialize a DAP.
1022  *
1023  * @todo Rename this.  We also need an initialization scheme which account
1024  * for SWD transports not just JTAG; that will need to address differences
1025  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1026  */
1027 int ahbap_debugport_init(struct swjdp_common *swjdp)
1028 {
1029         uint32_t idreg, romaddr, dummy;
1030         uint32_t ctrlstat;
1031         int cnt = 0;
1032         int retval;
1033
1034         LOG_DEBUG(" ");
1035
1036         /* Default MEM-AP setup.
1037          *
1038          * REVISIT AP #0 may be an inappropriate default for this.
1039          * Should we probe, or receve a hint from the caller?
1040          * Presumably we can ignore the possibility of multiple APs.
1041          */
1042         swjdp->apsel = 0;
1043         swjdp->ap_csw_value = -1;
1044         swjdp->ap_tar_value = -1;
1045
1046         /* DP initialization */
1047         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1048         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1049         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1050         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1051
1052         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1053
1054         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1055         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1056         if ((retval = jtag_execute_queue()) != ERROR_OK)
1057                 return retval;
1058
1059         /* Check that we have debug power domains activated */
1060         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1061         {
1062                 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1063                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1064                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1065                         return retval;
1066                 alive_sleep(10);
1067         }
1068
1069         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1070         {
1071                 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1072                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1073                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1074                         return retval;
1075                 alive_sleep(10);
1076         }
1077
1078         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1079         /* With debug power on we can activate OVERRUN checking */
1080         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1081         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1082         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1083
1084         /*
1085          * REVISIT this isn't actually *initializing* anything in an AP,
1086          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1087          * Should it?  If the ROM address is valid, is this the right
1088          * place to scan the table and do any topology detection?
1089          */
1090         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1091         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1092
1093         LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1094
1095         return ERROR_OK;
1096 }
1097
1098 /* CID interpretation -- see ARM IHI 0029B section 3
1099  * and ARM IHI 0031A table 13-3.
1100  */
1101 static const char *class_description[16] ={
1102         "Reserved", "ROM table", "Reserved", "Reserved",
1103         "Reserved", "Reserved", "Reserved", "Reserved",
1104         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1105         "Reserved", "OptimoDE DESS",
1106                 "Generic IP component", "PrimeCell or System component"
1107 };
1108
1109 static bool
1110 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1111 {
1112         return cid3 == 0xb1 && cid2 == 0x05
1113                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1114 }
1115
1116 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1117 {
1118
1119         uint32_t dbgbase, apid;
1120         int romtable_present = 0;
1121         uint8_t mem_ap;
1122         uint32_t apselold;
1123
1124         apselold = swjdp->apsel;
1125         dap_ap_select(swjdp, apsel);
1126         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1127         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1128         swjdp_transaction_endcheck(swjdp);
1129         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1130         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1131         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1132         if (apid)
1133         {
1134                 switch (apid&0x0F)
1135                 {
1136                         case 0:
1137                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1138                                 break;
1139                         case 1:
1140                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1141                                 break;
1142                         case 2:
1143                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1144                                 break;
1145                         default:
1146                                 command_print(cmd_ctx, "\tUnknown AP type");
1147                                 break;
1148                 }
1149
1150                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1151                  * not a ROM table ... or have no such components at all.
1152                  */
1153                 if (mem_ap)
1154                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1155                                         dbgbase);
1156         }
1157         else
1158         {
1159                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1160         }
1161
1162         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1163         if (romtable_present)
1164         {
1165                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1166                 uint16_t entry_offset;
1167
1168                 /* bit 16 of apid indicates a memory access port */
1169                 if (dbgbase & 0x02)
1170                         command_print(cmd_ctx, "\tValid ROM table present");
1171                 else
1172                         command_print(cmd_ctx, "\tROM table in legacy format");
1173
1174                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1175                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1176                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1177                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1178                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1179                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1180                 swjdp_transaction_endcheck(swjdp);
1181                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1182                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1183                                         ", CID2 0x%2.2" PRIx32
1184                                         ", CID1 0x%2.2" PRIx32
1185                                         ", CID0 0x%2.2" PRIx32,
1186                                         cid3, cid2, cid1, cid0);
1187                 if (memtype & 0x01)
1188                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1189                 else
1190                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1191                                         "Dedicated debug bus.");
1192
1193                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1194                 entry_offset = 0;
1195                 do
1196                 {
1197                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1198                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1199                         if (romentry&0x01)
1200                         {
1201                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1202                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1203                                 uint32_t component_start, component_base;
1204                                 unsigned part_num;
1205                                 char *type, *full;
1206
1207                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1208                                                 + (int)(romentry & 0xFFFFF000));
1209                                 mem_ap_read_atomic_u32(swjdp,
1210                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1211                                 mem_ap_read_atomic_u32(swjdp,
1212                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1213                                 mem_ap_read_atomic_u32(swjdp,
1214                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1215                                 mem_ap_read_atomic_u32(swjdp,
1216                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1217                                 mem_ap_read_atomic_u32(swjdp,
1218                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1219                                 mem_ap_read_atomic_u32(swjdp,
1220                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1221                                 mem_ap_read_atomic_u32(swjdp,
1222                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1223                                 mem_ap_read_atomic_u32(swjdp,
1224                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1225                                 mem_ap_read_atomic_u32(swjdp,
1226                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1227                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1228
1229                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1230                                                 ", start address 0x%" PRIx32,
1231                                                 component_base, component_start);
1232                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1233                                                 (int) (c_cid1 >> 4) & 0xf,
1234                                                 /* See ARM IHI 0029B Table 3-3 */
1235                                                 class_description[(c_cid1 >> 4) & 0xf]);
1236
1237                                 /* CoreSight component? */
1238                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1239                                         uint32_t devtype;
1240                                         unsigned minor;
1241                                         char *major = "Reserved", *subtype = "Reserved";
1242
1243                                         mem_ap_read_atomic_u32(swjdp,
1244                                                         (component_base & 0xfffff000) | 0xfcc,
1245                                                         &devtype);
1246                                         minor = (devtype >> 4) & 0x0f;
1247                                         switch (devtype & 0x0f) {
1248                                         case 0:
1249                                                 major = "Miscellaneous";
1250                                                 switch (minor) {
1251                                                 case 0:
1252                                                         subtype = "other";
1253                                                         break;
1254                                                 case 4:
1255                                                         subtype = "Validation component";
1256                                                         break;
1257                                                 }
1258                                                 break;
1259                                         case 1:
1260                                                 major = "Trace Sink";
1261                                                 switch (minor) {
1262                                                 case 0:
1263                                                         subtype = "other";
1264                                                         break;
1265                                                 case 1:
1266                                                         subtype = "Port";
1267                                                         break;
1268                                                 case 2:
1269                                                         subtype = "Buffer";
1270                                                         break;
1271                                                 }
1272                                                 break;
1273                                         case 2:
1274                                                 major = "Trace Link";
1275                                                 switch (minor) {
1276                                                 case 0:
1277                                                         subtype = "other";
1278                                                         break;
1279                                                 case 1:
1280                                                         subtype = "Funnel, router";
1281                                                         break;
1282                                                 case 2:
1283                                                         subtype = "Filter";
1284                                                         break;
1285                                                 case 3:
1286                                                         subtype = "FIFO, buffer";
1287                                                         break;
1288                                                 }
1289                                                 break;
1290                                         case 3:
1291                                                 major = "Trace Source";
1292                                                 switch (minor) {
1293                                                 case 0:
1294                                                         subtype = "other";
1295                                                         break;
1296                                                 case 1:
1297                                                         subtype = "Processor";
1298                                                         break;
1299                                                 case 2:
1300                                                         subtype = "DSP";
1301                                                         break;
1302                                                 case 3:
1303                                                         subtype = "Engine/Coprocessor";
1304                                                         break;
1305                                                 case 4:
1306                                                         subtype = "Bus";
1307                                                         break;
1308                                                 }
1309                                                 break;
1310                                         case 4:
1311                                                 major = "Debug Control";
1312                                                 switch (minor) {
1313                                                 case 0:
1314                                                         subtype = "other";
1315                                                         break;
1316                                                 case 1:
1317                                                         subtype = "Trigger Matrix";
1318                                                         break;
1319                                                 case 2:
1320                                                         subtype = "Debug Auth";
1321                                                         break;
1322                                                 }
1323                                                 break;
1324                                         case 5:
1325                                                 major = "Debug Logic";
1326                                                 switch (minor) {
1327                                                 case 0:
1328                                                         subtype = "other";
1329                                                         break;
1330                                                 case 1:
1331                                                         subtype = "Processor";
1332                                                         break;
1333                                                 case 2:
1334                                                         subtype = "DSP";
1335                                                         break;
1336                                                 case 3:
1337                                                         subtype = "Engine/Coprocessor";
1338                                                         break;
1339                                                 }
1340                                                 break;
1341                                         }
1342                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1343                                                         (unsigned) (devtype & 0xff),
1344                                                         major, subtype);
1345                                         /* REVISIT also show 0xfc8 DevId */
1346                                 }
1347
1348                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1349                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1350                                                         ", CID2 0x%2.2" PRIx32
1351                                                         ", CID1 0x%2.2" PRIx32
1352                                                         ", CID0 0x%2.2" PRIx32,
1353                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1354                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1355                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1356                                                 (int) c_pid4,
1357                                                 (int) c_pid3, (int) c_pid2,
1358                                                 (int) c_pid1, (int) c_pid0);
1359
1360                                 /* Part number interpretations are from Cortex
1361                                  * core specs, the CoreSight components TRM
1362                                  * (ARM DDI 0314H), and ETM specs; also from
1363                                  * chip observation (e.g. TI SDTI).
1364                                  */
1365                                 part_num = c_pid0 & 0xff;
1366                                 part_num |= (c_pid1 & 0x0f) << 8;
1367                                 switch (part_num) {
1368                                 case 0x000:
1369                                         type = "Cortex-M3 NVIC";
1370                                         full = "(Interrupt Controller)";
1371                                         break;
1372                                 case 0x001:
1373                                         type = "Cortex-M3 ITM";
1374                                         full = "(Instrumentation Trace Module)";
1375                                         break;
1376                                 case 0x002:
1377                                         type = "Cortex-M3 DWT";
1378                                         full = "(Data Watchpoint and Trace)";
1379                                         break;
1380                                 case 0x003:
1381                                         type = "Cortex-M3 FBP";
1382                                         full = "(Flash Patch and Breakpoint)";
1383                                         break;
1384                                 case 0x00d:
1385                                         type = "CoreSight ETM11";
1386                                         full = "(Embedded Trace)";
1387                                         break;
1388                                 // case 0x113: what?
1389                                 case 0x120:             /* from OMAP3 memmap */
1390                                         type = "TI SDTI";
1391                                         full = "(System Debug Trace Interface)";
1392                                         break;
1393                                 case 0x343:             /* from OMAP3 memmap */
1394                                         type = "TI DAPCTL";
1395                                         full = "";
1396                                         break;
1397                                 case 0x4e0:
1398                                         type = "Cortex-M3 ETM";
1399                                         full = "(Embedded Trace)";
1400                                         break;
1401                                 case 0x906:
1402                                         type = "Coresight CTI";
1403                                         full = "(Cross Trigger)";
1404                                         break;
1405                                 case 0x907:
1406                                         type = "Coresight ETB";
1407                                         full = "(Trace Buffer)";
1408                                         break;
1409                                 case 0x908:
1410                                         type = "Coresight CSTF";
1411                                         full = "(Trace Funnel)";
1412                                         break;
1413                                 case 0x910:
1414                                         type = "CoreSight ETM9";
1415                                         full = "(Embedded Trace)";
1416                                         break;
1417                                 case 0x912:
1418                                         type = "Coresight TPIU";
1419                                         full = "(Trace Port Interface Unit)";
1420                                         break;
1421                                 case 0x921:
1422                                         type = "Cortex-A8 ETM";
1423                                         full = "(Embedded Trace)";
1424                                         break;
1425                                 case 0x922:
1426                                         type = "Cortex-A8 CTI";
1427                                         full = "(Cross Trigger)";
1428                                         break;
1429                                 case 0x923:
1430                                         type = "Cortex-M3 TPIU";
1431                                         full = "(Trace Port Interface Unit)";
1432                                         break;
1433                                 case 0xc08:
1434                                         type = "Cortex-A8 Debug";
1435                                         full = "(Debug Unit)";
1436                                         break;
1437                                 default:
1438                                         type = "-*- unrecognized -*-";
1439                                         full = "";
1440                                         break;
1441                                 }
1442                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1443                                                 type, full);
1444                         }
1445                         else
1446                         {
1447                                 if (romentry)
1448                                         command_print(cmd_ctx, "\t\tComponent not present");
1449                                 else
1450                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1451                         }
1452                         entry_offset += 4;
1453                 } while (romentry > 0);
1454         }
1455         else
1456         {
1457                 command_print(cmd_ctx, "\tNo ROM table present");
1458         }
1459         dap_ap_select(swjdp, apselold);
1460
1461         return ERROR_OK;
1462 }
1463
1464 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1465 {
1466         uint32_t apsel, apselsave, baseaddr;
1467         int retval;
1468
1469         apselsave = swjdp->apsel;
1470         switch (CMD_ARGC) {
1471         case 0:
1472                 apsel = swjdp->apsel;
1473                 break;
1474         case 1:
1475                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1476                 break;
1477         default:
1478                 return ERROR_COMMAND_SYNTAX_ERROR;
1479         }
1480
1481         if (apselsave != apsel)
1482                 dap_ap_select(swjdp, apsel);
1483
1484         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1485         retval = swjdp_transaction_endcheck(swjdp);
1486         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1487
1488         if (apselsave != apsel)
1489                 dap_ap_select(swjdp, apselsave);
1490
1491         return retval;
1492 }
1493
1494 DAP_COMMAND_HANDLER(dap_memaccess_command)
1495 {
1496         uint32_t memaccess_tck;
1497
1498         switch (CMD_ARGC) {
1499         case 0:
1500                 memaccess_tck = swjdp->memaccess_tck;
1501                 break;
1502         case 1:
1503                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1504                 break;
1505         default:
1506                 return ERROR_COMMAND_SYNTAX_ERROR;
1507         }
1508         swjdp->memaccess_tck = memaccess_tck;
1509
1510         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1511                         swjdp->memaccess_tck);
1512
1513         return ERROR_OK;
1514 }
1515
1516 DAP_COMMAND_HANDLER(dap_apsel_command)
1517 {
1518         uint32_t apsel, apid;
1519         int retval;
1520
1521         switch (CMD_ARGC) {
1522         case 0:
1523                 apsel = 0;
1524                 break;
1525         case 1:
1526                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1527                 break;
1528         default:
1529                 return ERROR_COMMAND_SYNTAX_ERROR;
1530         }
1531
1532         dap_ap_select(swjdp, apsel);
1533         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1534         retval = swjdp_transaction_endcheck(swjdp);
1535         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1536                         apsel, apid);
1537
1538         return retval;
1539 }
1540
1541 DAP_COMMAND_HANDLER(dap_apid_command)
1542 {
1543         uint32_t apsel, apselsave, apid;
1544         int retval;
1545
1546         apselsave = swjdp->apsel;
1547         switch (CMD_ARGC) {
1548         case 0:
1549                 apsel = swjdp->apsel;
1550                 break;
1551         case 1:
1552                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1553                 break;
1554         default:
1555                 return ERROR_COMMAND_SYNTAX_ERROR;
1556         }
1557
1558         if (apselsave != apsel)
1559                 dap_ap_select(swjdp, apsel);
1560
1561         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1562         retval = swjdp_transaction_endcheck(swjdp);
1563         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1564         if (apselsave != apsel)
1565                 dap_ap_select(swjdp, apselsave);
1566
1567         return retval;
1568 }