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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76
  77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  78
  79 /*
  80         uint32_t tar_block_size(uint32_t address)
  81         Return the largest block starting at address that does not cross a tar block size alignment boundary
  82 */
  83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  84 {
  85         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  86 }
  87
  88 /***************************************************************************
  89  *                                                                         *
  90  * DP and MEM-AP  register access  through APACC and DPACC                 *
  91  *                                                                         *
  92 ***************************************************************************/
  93
  94 /**
  95  * Select one of the APs connected to the specified DAP.  The
  96  * selection is implicitly used with future AP transactions.
  97  * This is a NOP if the specified AP is already selected.
  98  *
  99  * @param dap The DAP
 100  * @param apsel Number of the AP to (implicitly) use with further
 101  *      transactions.  This normally identifies a MEM-AP.
 102  */
 103 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
 104 {
 105         uint32_t new_ap = (ap << 24) & 0xFF000000;
 106
 107         if (new_ap != dap->ap_current)
 108         {
 109                 dap->ap_current = new_ap;
 110                 /* Switching AP invalidates cached values.
 111                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 112                  */
 113                 dap->ap_bank_value = -1;
 114                 dap->ap_csw_value = -1;
 115                 dap->ap_tar_value = -1;
 116         }
 117 }
 118
 119 /**
 120  * Queue transactions setting up transfer parameters for the
 121  * currently selected MEM-AP.
 122  *
 123  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 124  * initiate data reads or writes using memory or peripheral addresses.
 125  * If the CSW is configured for it, the TAR may be automatically
 126  * incremented after each transfer.
 127  *
 128  * @todo Rename to reflect it being specifically a MEM-AP function.
 129  *
 130  * @param dap The DAP connected to the MEM-AP.
 131  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 132  *      matches the cached value, the register is not changed.
 133  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 134  *      matches the cached address, the register is not changed.
 135  *
 136  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 137  */
 138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 139 {
 140         int retval;
 141
 142         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 143         if (csw != dap->ap_csw_value)
 144         {
 145                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 146                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 147                 if (retval != ERROR_OK)
 148                         return retval;
 149                 dap->ap_csw_value = csw;
 150         }
 151         if (tar != dap->ap_tar_value)
 152         {
 153                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 154                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 155                 if (retval != ERROR_OK)
 156                         return retval;
 157                 dap->ap_tar_value = tar;
 158         }
 159         /* Disable TAR cache when autoincrementing */
 160         if (csw & CSW_ADDRINC_MASK)
 161                 dap->ap_tar_value = -1;
 162         return ERROR_OK;
 163 }
 164
 165 /**
 166  * Asynchronous (queued) read of a word from memory or a system register.
 167  *
 168  * @param dap The DAP connected to the MEM-AP performing the read.
 169  * @param address Address of the 32-bit word to read; it must be
 170  *      readable by the currently selected MEM-AP.
 171  * @param value points to where the word will be stored when the
 172  *      transaction queue is flushed (assuming no errors).
 173  *
 174  * @return ERROR_OK for success.  Otherwise a fault code.
 175  */
 176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 177                 uint32_t *value)
 178 {
 179         int retval;
 180
 181         /* Use banked addressing (REG_BDx) to avoid some link traffic
 182          * (updating TAR) when reading several consecutive addresses.
 183          */
 184         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 185                         address & 0xFFFFFFF0);
 186         if (retval != ERROR_OK)
 187                 return retval;
 188
 189         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 190 }
 191
 192 /**
 193  * Synchronous read of a word from memory or a system register.
 194  * As a side effect, this flushes any queued transactions.
 195  *
 196  * @param dap The DAP connected to the MEM-AP performing the read.
 197  * @param address Address of the 32-bit word to read; it must be
 198  *      readable by the currently selected MEM-AP.
 199  * @param value points to where the result will be stored.
 200  *
 201  * @return ERROR_OK for success; *value holds the result.
 202  * Otherwise a fault code.
 203  */
 204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 205                 uint32_t *value)
 206 {
 207         int retval;
 208
 209         retval = mem_ap_read_u32(dap, address, value);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         return dap_run(dap);
 214 }
 215
 216 /**
 217  * Asynchronous (queued) write of a word to memory or a system register.
 218  *
 219  * @param dap The DAP connected to the MEM-AP.
 220  * @param address Address to be written; it must be writable by
 221  *      the currently selected MEM-AP.
 222  * @param value Word that will be written to the address when transaction
 223  *      queue is flushed (assuming no errors).
 224  *
 225  * @return ERROR_OK for success.  Otherwise a fault code.
 226  */
 227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 228                 uint32_t value)
 229 {
 230         int retval;
 231
 232         /* Use banked addressing (REG_BDx) to avoid some link traffic
 233          * (updating TAR) when writing several consecutive addresses.
 234          */
 235         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 236                         address & 0xFFFFFFF0);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 241                         value);
 242 }
 243
 244 /**
 245  * Synchronous write of a word to memory or a system register.
 246  * As a side effect, this flushes any queued transactions.
 247  *
 248  * @param dap The DAP connected to the MEM-AP.
 249  * @param address Address to be written; it must be writable by
 250  *      the currently selected MEM-AP.
 251  * @param value Word that will be written.
 252  *
 253  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 254  */
 255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 256                 uint32_t value)
 257 {
 258         int retval = mem_ap_write_u32(dap, address, value);
 259
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         return dap_run(dap);
 264 }
 265
 266 /*****************************************************************************
 267 *                                                                            *
 268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 269 *                                                                            *
 270 * Write a buffer in target order (little endian)                             *
 271 *                                                                            *
 272 *****************************************************************************/
 273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 274 {
 275         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 276         uint32_t adr = address;
 277         uint8_t* pBuffer = buffer;
 278
 279         count >>= 2;
 280         wcount = count;
 281
 282         /* if we have an unaligned access - reorder data */
 283         if (adr & 0x3u)
 284         {
 285                 for (writecount = 0; writecount < count; writecount++)
 286                 {
 287                         int i;
 288                         uint32_t outvalue;
 289                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 290
 291                         for (i = 0; i < 4; i++)
 292                         {
 293                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 294                                 outvalue >>= 8;
 295                                 adr++;
 296                         }
 297                         pBuffer += sizeof(uint32_t);
 298                 }
 299         }
 300
 301         while (wcount > 0)
 302         {
 303                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 304                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 305                 if (wcount < blocksize)
 306                         blocksize = wcount;
 307
 308                 /* handle unaligned data at 4k boundary */
 309                 if (blocksize == 0)
 310                         blocksize = 1;
 311
 312                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315
 316                 for (writecount = 0; writecount < blocksize; writecount++)
 317                 {
 318                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 319                                 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
 320                         if (retval != ERROR_OK)
 321                                 break;
 322                 }
 323
 324                 if ((retval = dap_run(dap)) == ERROR_OK)
 325                 {
 326                         wcount = wcount - blocksize;
 327                         address = address + 4 * blocksize;
 328                         buffer = buffer + 4 * blocksize;
 329                 }
 330                 else
 331                 {
 332                         errorcount++;
 333                 }
 334
 335                 if (errorcount > 1)
 336                 {
 337                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 338                         return retval;
 339                 }
 340         }
 341
 342         return retval;
 343 }
 344
 345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 346                 uint8_t *buffer, int count, uint32_t address)
 347 {
 348         int retval = ERROR_OK;
 349         int wcount, blocksize, writecount, i;
 350
 351         wcount = count >> 1;
 352
 353         while (wcount > 0)
 354         {
 355                 int nbytes;
 356
 357                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 358                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 359
 360                 if (wcount < blocksize)
 361                         blocksize = wcount;
 362
 363                 /* handle unaligned data at 4k boundary */
 364                 if (blocksize == 0)
 365                         blocksize = 1;
 366
 367                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 368                 if (retval != ERROR_OK)
 369                         return retval;
 370                 writecount = blocksize;
 371
 372                 do
 373                 {
 374                         nbytes = MIN((writecount << 1), 4);
 375
 376                         if (nbytes < 4)
 377                         {
 378                                 retval = mem_ap_write_buf_u16(dap, buffer,
 379                                                 nbytes, address);
 380                                 if (retval != ERROR_OK)
 381                                 {
 382                                         LOG_WARNING("Block write error address "
 383                                                 "0x%" PRIx32 ", count 0x%x",
 384                                                 address, count);
 385                                         return retval;
 386                                 }
 387
 388                                 address += nbytes >> 1;
 389                         }
 390                         else
 391                         {
 392                                 uint32_t outvalue;
 393                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 394
 395                                 for (i = 0; i < nbytes; i++)
 396                                 {
 397                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 398                                         outvalue >>= 8;
 399                                         address++;
 400                                 }
 401
 402                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 403                                 retval = dap_queue_ap_write(dap,
 404                                                 AP_REG_DRW, outvalue);
 405                                 if (retval != ERROR_OK)
 406                                         break;
 407
 408                                 if ((retval = dap_run(dap)) != ERROR_OK)
 409                                 {
 410                                         LOG_WARNING("Block write error address "
 411                                                 "0x%" PRIx32 ", count 0x%x",
 412                                                 address, count);
 413                                         return retval;
 414                                 }
 415                         }
 416
 417                         buffer += nbytes >> 1;
 418                         writecount -= nbytes >> 1;
 419
 420                 } while (writecount);
 421                 wcount -= blocksize;
 422         }
 423
 424         return retval;
 425 }
 426
 427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 428 {
 429         int retval = ERROR_OK;
 430
 431         if (count >= 4)
 432                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 433
 434         while (count > 0)
 435         {
 436                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 437                 if (retval != ERROR_OK)
 438                         return retval;
 439                 uint16_t svalue;
 440                 memcpy(&svalue, buffer, sizeof(uint16_t));
 441                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 442                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 443                 if (retval != ERROR_OK)
 444                         break;
 445
 446                 retval = dap_run(dap);
 447                 if (retval != ERROR_OK)
 448                         break;
 449
 450                 count -= 2;
 451                 address += 2;
 452                 buffer += 2;
 453         }
 454
 455         return retval;
 456 }
 457
 458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 459                 uint8_t *buffer, int count, uint32_t address)
 460 {
 461         int retval = ERROR_OK;
 462         int wcount, blocksize, writecount, i;
 463
 464         wcount = count;
 465
 466         while (wcount > 0)
 467         {
 468                 int nbytes;
 469
 470                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 471                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 472
 473                 if (wcount < blocksize)
 474                         blocksize = wcount;
 475
 476                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 477                 if (retval != ERROR_OK)
 478                         return retval;
 479                 writecount = blocksize;
 480
 481                 do
 482                 {
 483                         nbytes = MIN(writecount, 4);
 484
 485                         if (nbytes < 4)
 486                         {
 487                                 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
 488                                 if (retval != ERROR_OK)
 489                                 {
 490                                         LOG_WARNING("Block write error address "
 491                                                 "0x%" PRIx32 ", count 0x%x",
 492                                                 address, count);
 493                                         return retval;
 494                                 }
 495
 496                                 address += nbytes;
 497                         }
 498                         else
 499                         {
 500                                 uint32_t outvalue;
 501                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 502
 503                                 for (i = 0; i < nbytes; i++)
 504                                 {
 505                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 506                                         outvalue >>= 8;
 507                                         address++;
 508                                 }
 509
 510                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 511                                 retval = dap_queue_ap_write(dap,
 512                                                 AP_REG_DRW, outvalue);
 513                                 if (retval != ERROR_OK)
 514                                         break;
 515
 516                                 if ((retval = dap_run(dap)) != ERROR_OK)
 517                                 {
 518                                         LOG_WARNING("Block write error address "
 519                                                 "0x%" PRIx32 ", count 0x%x",
 520                                                 address, count);
 521                                         return retval;
 522                                 }
 523                         }
 524
 525                         buffer += nbytes;
 526                         writecount -= nbytes;
 527
 528                 } while (writecount);
 529                 wcount -= blocksize;
 530         }
 531
 532         return retval;
 533 }
 534
 535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 536 {
 537         int retval = ERROR_OK;
 538
 539         if (count >= 4)
 540                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 541
 542         while (count > 0)
 543         {
 544                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 545                 if (retval != ERROR_OK)
 546                         return retval;
 547                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 548                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 549                 if (retval != ERROR_OK)
 550                         break;
 551
 552                 retval = dap_run(dap);
 553                 if (retval != ERROR_OK)
 554                         break;
 555
 556                 count--;
 557                 address++;
 558                 buffer++;
 559         }
 560
 561         return retval;
 562 }
 563
 564 /* FIXME don't import ... this is a temporary workaround for the
 565  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 566  */
 567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 568                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 569                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 570
 571 /**
 572  * Synchronously read a block of 32-bit words into a buffer
 573  * @param dap The DAP connected to the MEM-AP.
 574  * @param buffer where the words will be stored (in host byte order).
 575  * @param count How many words to read.
 576  * @param address Memory address from which to read words; all the
 577  *      words must be readable by the currently selected MEM-AP.
 578  */
 579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 580                 int count, uint32_t address)
 581 {
 582         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 583         uint32_t adr = address;
 584         uint8_t* pBuffer = buffer;
 585
 586         count >>= 2;
 587         wcount = count;
 588
 589         while (wcount > 0)
 590         {
 591                 /* Adjust to read blocks within boundaries aligned to the
 592                  * TAR autoincrement size (at least 2^10).  Autoincrement
 593                  * mode avoids an extra per-word roundtrip to update TAR.
 594                  */
 595                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 596                                 address);
 597                 if (wcount < blocksize)
 598                         blocksize = wcount;
 599
 600                 /* handle unaligned data at 4k boundary */
 601                 if (blocksize == 0)
 602                         blocksize = 1;
 603
 604                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 605                                 address);
 606                 if (retval != ERROR_OK)
 607                         return retval;
 608
 609                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 610                  * so this routine becomes transport-neutral.  Be careful
 611                  * not to cause performance problems with JTAG; would it
 612                  * suffice to loop over dap_queue_ap_read(), or would that
 613                  * be slower when JTAG is the chosen transport?
 614                  */
 615
 616                 /* Scan out first read */
 617                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 618                                 DPAP_READ, 0, NULL, NULL);
 619                 if (retval != ERROR_OK)
 620                         return retval;
 621                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 622                 {
 623                         /* Scan out next read; scan in posted value for the
 624                          * previous one.  Assumes read is acked "OK/FAULT",
 625                          * and CTRL_STAT says that meant "OK".
 626                          */
 627                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 628                                         DPAP_READ, 0, buffer + 4 * readcount,
 629                                         &dap->ack);
 630                         if (retval != ERROR_OK)
 631                                 return retval;
 632                 }
 633
 634                 /* Scan in last posted value; RDBUFF has no other effect,
 635                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 636                  */
 637                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 638                                 DPAP_READ, 0, buffer + 4 * readcount,
 639                                 &dap->ack);
 640                 if (retval != ERROR_OK)
 641                         return retval;
 642
 643                 retval = dap_run(dap);
 644                 if (retval != ERROR_OK)
 645                 {
 646                         errorcount++;
 647                         if (errorcount <= 1)
 648                         {
 649                                 /* try again */
 650                                 continue;
 651                         }
 652                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 653                         return retval;
 654                 }
 655                 wcount = wcount - blocksize;
 656                 address += 4 * blocksize;
 657                 buffer += 4 * blocksize;
 658         }
 659
 660         /* if we have an unaligned access - reorder data */
 661         if (adr & 0x3u)
 662         {
 663                 for (readcount = 0; readcount < count; readcount++)
 664                 {
 665                         int i;
 666                         uint32_t data;
 667                         memcpy(&data, pBuffer, sizeof(uint32_t));
 668
 669                         for (i = 0; i < 4; i++)
 670                         {
 671                                 *((uint8_t*)pBuffer) =
 672                                                 (data >> 8 * (adr & 0x3));
 673                                 pBuffer++;
 674                                 adr++;
 675                         }
 676                 }
 677         }
 678
 679         return retval;
 680 }
 681
 682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 683                 uint8_t *buffer, int count, uint32_t address)
 684 {
 685         uint32_t invalue;
 686         int retval = ERROR_OK;
 687         int wcount, blocksize, readcount, i;
 688
 689         wcount = count >> 1;
 690
 691         while (wcount > 0)
 692         {
 693                 int nbytes;
 694
 695                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 696                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 697                 if (wcount < blocksize)
 698                         blocksize = wcount;
 699
 700                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 701                 if (retval != ERROR_OK)
 702                         return retval;
 703
 704                 /* handle unaligned data at 4k boundary */
 705                 if (blocksize == 0)
 706                         blocksize = 1;
 707                 readcount = blocksize;
 708
 709                 do
 710                 {
 711                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 712                         if (retval != ERROR_OK)
 713                                 return retval;
 714                         if ((retval = dap_run(dap)) != ERROR_OK)
 715                         {
 716                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 717                                 return retval;
 718                         }
 719
 720                         nbytes = MIN((readcount << 1), 4);
 721
 722                         for (i = 0; i < nbytes; i++)
 723                         {
 724                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 725                                 buffer++;
 726                                 address++;
 727                         }
 728
 729                         readcount -= (nbytes >> 1);
 730                 } while (readcount);
 731                 wcount -= blocksize;
 732         }
 733
 734         return retval;
 735 }
 736
 737 /**
 738  * Synchronously read a block of 16-bit halfwords into a buffer
 739  * @param dap The DAP connected to the MEM-AP.
 740  * @param buffer where the halfwords will be stored (in host byte order).
 741  * @param count How many halfwords to read.
 742  * @param address Memory address from which to read words; all the
 743  *      words must be readable by the currently selected MEM-AP.
 744  */
 745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 746                 int count, uint32_t address)
 747 {
 748         uint32_t invalue, i;
 749         int retval = ERROR_OK;
 750
 751         if (count >= 4)
 752                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 753
 754         while (count > 0)
 755         {
 756                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 757                 if (retval != ERROR_OK)
 758                         return retval;
 759                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 760                 if (retval != ERROR_OK)
 761                         break;
 762
 763                 retval = dap_run(dap);
 764                 if (retval != ERROR_OK)
 765                         break;
 766
 767                 if (address & 0x1)
 768                 {
 769                         for (i = 0; i < 2; i++)
 770                         {
 771                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 772                                 buffer++;
 773                                 address++;
 774                         }
 775                 }
 776                 else
 777                 {
 778                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 779                         memcpy(buffer, &svalue, sizeof(uint16_t));
 780                         address += 2;
 781                         buffer += 2;
 782                 }
 783                 count -= 2;
 784         }
 785
 786         return retval;
 787 }
 788
 789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 790  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 791  *
 792  * The solution is to arrange for a large out/in scan in this loop and
 793  * and convert data afterwards.
 794  */
 795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 796                 uint8_t *buffer, int count, uint32_t address)
 797 {
 798         uint32_t invalue;
 799         int retval = ERROR_OK;
 800         int wcount, blocksize, readcount, i;
 801
 802         wcount = count;
 803
 804         while (wcount > 0)
 805         {
 806                 int nbytes;
 807
 808                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 809                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 810
 811                 if (wcount < blocksize)
 812                         blocksize = wcount;
 813
 814                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 815                 if (retval != ERROR_OK)
 816                         return retval;
 817                 readcount = blocksize;
 818
 819                 do
 820                 {
 821                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 822                         if (retval != ERROR_OK)
 823                                 return retval;
 824                         if ((retval = dap_run(dap)) != ERROR_OK)
 825                         {
 826                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 827                                 return retval;
 828                         }
 829
 830                         nbytes = MIN(readcount, 4);
 831
 832                         for (i = 0; i < nbytes; i++)
 833                         {
 834                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 835                                 buffer++;
 836                                 address++;
 837                         }
 838
 839                         readcount -= nbytes;
 840                 } while (readcount);
 841                 wcount -= blocksize;
 842         }
 843
 844         return retval;
 845 }
 846
 847 /**
 848  * Synchronously read a block of bytes into a buffer
 849  * @param dap The DAP connected to the MEM-AP.
 850  * @param buffer where the bytes will be stored.
 851  * @param count How many bytes to read.
 852  * @param address Memory address from which to read data; all the
 853  *      data must be readable by the currently selected MEM-AP.
 854  */
 855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 856                 int count, uint32_t address)
 857 {
 858         uint32_t invalue;
 859         int retval = ERROR_OK;
 860
 861         if (count >= 4)
 862                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 863
 864         while (count > 0)
 865         {
 866                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 867                 if (retval != ERROR_OK)
 868                         return retval;
 869                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 870                 if (retval != ERROR_OK)
 871                         return retval;
 872                 retval = dap_run(dap);
 873                 if (retval != ERROR_OK)
 874                         break;
 875
 876                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 877                 count--;
 878                 address++;
 879                 buffer++;
 880         }
 881
 882         return retval;
 883 }
 884
 885 /*--------------------------------------------------------------------*/
 886 /*          Wrapping function with selection of AP                    */
 887 /*--------------------------------------------------------------------*/
 888 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 889                 uint32_t address, uint32_t *value)
 890 {
 891         dap_ap_select(swjdp, ap);
 892         return mem_ap_read_u32(swjdp, address, value);
 893 }
 894
 895 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 896                 uint32_t address, uint32_t value)
 897 {
 898         dap_ap_select(swjdp, ap);
 899         return mem_ap_write_u32(swjdp, address, value);
 900 }
 901
 902 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 903                 uint32_t address, uint32_t *value)
 904 {
 905         dap_ap_select(swjdp, ap);
 906         return mem_ap_read_atomic_u32(swjdp, address, value);
 907 }
 908
 909 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 910                 uint32_t address, uint32_t value)
 911 {
 912         dap_ap_select(swjdp, ap);
 913         return mem_ap_write_atomic_u32(swjdp, address, value);
 914 }
 915
 916 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 917                 uint8_t *buffer, int count, uint32_t address)
 918 {
 919         dap_ap_select(swjdp, ap);
 920         return mem_ap_read_buf_u8(swjdp, buffer, count, address);
 921 }
 922
 923 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 924                 uint8_t *buffer, int count, uint32_t address)
 925 {
 926         dap_ap_select(swjdp, ap);
 927         return mem_ap_read_buf_u16(swjdp, buffer, count, address);
 928 }
 929
 930 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 931                 uint8_t *buffer, int count, uint32_t address)
 932 {
 933         dap_ap_select(swjdp, ap);
 934         return mem_ap_read_buf_u32(swjdp, buffer, count, address);
 935 }
 936
 937 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 938                 uint8_t *buffer, int count, uint32_t address)
 939 {
 940         dap_ap_select(swjdp, ap);
 941         return mem_ap_write_buf_u8(swjdp, buffer, count, address);
 942 }
 943
 944 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 945                 uint8_t *buffer, int count, uint32_t address)
 946 {
 947         dap_ap_select(swjdp, ap);
 948         return mem_ap_write_buf_u16(swjdp, buffer, count, address);
 949 }
 950
 951 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 952                 uint8_t *buffer, int count, uint32_t address)
 953 {
 954         dap_ap_select(swjdp, ap);
 955         return mem_ap_write_buf_u32(swjdp, buffer, count, address);
 956 }
 957
 958
 959 /*--------------------------------------------------------------------------*/
 960
 961
 962 /* FIXME don't import ... just initialize as
 963  * part of DAP transport setup
 964 */
 965 extern const struct dap_ops jtag_dp_ops;
 966
 967 /*--------------------------------------------------------------------------*/
 968
 969 /**
 970  * Initialize a DAP.  This sets up the power domains, prepares the DP
 971  * for further use, and arranges to use AP #0 for all AP operations
 972  * until dap_ap-select() changes that policy.
 973  *
 974  * @param dap The DAP being initialized.
 975  *
 976  * @todo Rename this.  We also need an initialization scheme which account
 977  * for SWD transports not just JTAG; that will need to address differences
 978  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 979  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 980  */
 981 int ahbap_debugport_init(struct adiv5_dap *dap)
 982 {
 983         uint32_t ctrlstat;
 984         int cnt = 0;
 985         int retval;
 986
 987         LOG_DEBUG(" ");
 988
 989         /* JTAG-DP or SWJ-DP, in JTAG mode
 990          * ... for SWD mode this is patched as part
 991          * of link switchover
 992          */
 993         if (!dap->ops)
 994                 dap->ops = &jtag_dp_ops;
 995
 996         /* Default MEM-AP setup.
 997          *
 998          * REVISIT AP #0 may be an inappropriate default for this.
 999          * Should we probe, or take a hint from the caller?
1000          * Presumably we can ignore the possibility of multiple APs.
1001          */
1002         dap->ap_current = !0;
1003         dap_ap_select(dap, 0);
1004
1005         /* DP initialization */
1006
1007         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1008         if (retval != ERROR_OK)
1009                 return retval;
1010
1011         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1012         if (retval != ERROR_OK)
1013                 return retval;
1014
1015         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1016         if (retval != ERROR_OK)
1017                 return retval;
1018
1019         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1020         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1021         if (retval != ERROR_OK)
1022                 return retval;
1023
1024         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1025         if (retval != ERROR_OK)
1026                 return retval;
1027         if ((retval = dap_run(dap)) != ERROR_OK)
1028                 return retval;
1029
1030         /* Check that we have debug power domains activated */
1031         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1032         {
1033                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1034                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1035                 if (retval != ERROR_OK)
1036                         return retval;
1037                 if ((retval = dap_run(dap)) != ERROR_OK)
1038                         return retval;
1039                 alive_sleep(10);
1040         }
1041
1042         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1043         {
1044                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1045                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1046                 if (retval != ERROR_OK)
1047                         return retval;
1048                 if ((retval = dap_run(dap)) != ERROR_OK)
1049                         return retval;
1050                 alive_sleep(10);
1051         }
1052
1053         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1054         if (retval != ERROR_OK)
1055                 return retval;
1056         /* With debug power on we can activate OVERRUN checking */
1057         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1058         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1059         if (retval != ERROR_OK)
1060                 return retval;
1061         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1062         if (retval != ERROR_OK)
1063                 return retval;
1064
1065         return ERROR_OK;
1066 }
1067
1068 /* CID interpretation -- see ARM IHI 0029B section 3
1069  * and ARM IHI 0031A table 13-3.
1070  */
1071 static const char *class_description[16] ={
1072         "Reserved", "ROM table", "Reserved", "Reserved",
1073         "Reserved", "Reserved", "Reserved", "Reserved",
1074         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1075         "Reserved", "OptimoDE DESS",
1076                 "Generic IP component", "PrimeCell or System component"
1077 };
1078
1079 static bool
1080 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1081 {
1082         return cid3 == 0xb1 && cid2 == 0x05
1083                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1084 }
1085
1086 struct broken_cpu {
1087         uint32_t        dbgbase;
1088         uint32_t        apid;
1089         uint32_t        idcode;
1090         uint32_t        correct_dbgbase;
1091         char            *model;
1092 } broken_cpus[] = {
1093         { 0x80000000, 0x04770002, 0x1ba00477, 0x60000000, "imx51" },
1094 };
1095
1096 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1097                         uint32_t *out_dbgbase, uint32_t *out_apid)
1098 {
1099         uint32_t ap_old;
1100         int retval;
1101         unsigned int i;
1102         uint32_t dbgbase, apid, idcode;
1103
1104         /* AP address is in bits 31:24 of DP_SELECT */
1105         if (ap >= 256)
1106                 return ERROR_INVALID_ARGUMENTS;
1107
1108         ap_old = dap->ap_current;
1109         dap_ap_select(dap, ap);
1110
1111         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1112         if (retval != ERROR_OK)
1113                 return retval;
1114         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1115         if (retval != ERROR_OK)
1116                 return retval;
1117         retval = dap_run(dap);
1118         if (retval != ERROR_OK)
1119                 return retval;
1120
1121         /* Excavate the device ID code */
1122         struct jtag_tap *tap = dap->jtag_info->tap;
1123         while (tap != NULL) {
1124                 if (tap->hasidcode) {
1125                         idcode = tap->idcode;
1126                         break;
1127                 }
1128                 tap = tap->next_tap;
1129         }
1130         if (tap == NULL || !tap->hasidcode)
1131                 return ERROR_OK;
1132
1133         /* Some CPUs are messed up, so fixup if needed. */
1134         for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
1135                 if (broken_cpus[i].dbgbase == dbgbase &&
1136                         broken_cpus[i].apid == apid &&
1137                         broken_cpus[i].idcode == idcode) {
1138                         LOG_WARNING("Found broken CPU (%s), trying to fixup "
1139                                 "ROM Table location from 0x%08x to 0x%08x",
1140                                 broken_cpus[i].model, dbgbase,
1141                                 broken_cpus[i].correct_dbgbase);
1142                         dbgbase = broken_cpus[i].correct_dbgbase;
1143                         break;
1144                 }
1145
1146         dap_ap_select(dap, ap_old);
1147
1148         /* The asignment happens only here to prevent modification of these
1149          * values before they are certain. */
1150         *out_dbgbase = dbgbase;
1151         *out_apid = apid;
1152
1153         return ERROR_OK;
1154 }
1155
1156 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1157                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
1158 {
1159         uint32_t ap_old;
1160         uint32_t romentry, entry_offset = 0, component_base, devtype;
1161         int retval = ERROR_FAIL;
1162
1163         if (ap >= 256)
1164                 return ERROR_INVALID_ARGUMENTS;
1165
1166         ap_old = dap->ap_current;
1167         dap_ap_select(dap, ap);
1168
1169         do
1170         {
1171                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1172                                                 entry_offset, &romentry);
1173                 if (retval != ERROR_OK)
1174                         return retval;
1175
1176                 component_base = (dbgbase & 0xFFFFF000)
1177                         + (romentry & 0xFFFFF000);
1178
1179                 if (romentry & 0x1) {
1180                         retval = mem_ap_read_atomic_u32(dap,
1181                                         (component_base & 0xfffff000) | 0xfcc,
1182                                         &devtype);
1183                         if ((devtype & 0xff) == type) {
1184                                 *addr = component_base;
1185                                 retval = ERROR_OK;
1186                                 break;
1187                         }
1188                 }
1189                 entry_offset += 4;
1190         } while (romentry > 0);
1191
1192         dap_ap_select(dap, ap_old);
1193
1194         return retval;
1195 }
1196
1197 static int dap_info_command(struct command_context *cmd_ctx,
1198                 struct adiv5_dap *dap, int ap)
1199 {
1200         int retval;
1201         uint32_t dbgbase, apid;
1202         int romtable_present = 0;
1203         uint8_t mem_ap;
1204         uint32_t ap_old;
1205
1206         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1207         if (retval != ERROR_OK)
1208                 return retval;
1209
1210         ap_old = dap->ap_current;
1211         dap_ap_select(dap, ap);
1212
1213         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1214         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1215         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1216         if (apid)
1217         {
1218                 switch (apid&0x0F)
1219                 {
1220                         case 0:
1221                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1222                                 break;
1223                         case 1:
1224                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1225                                 break;
1226                         case 2:
1227                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1228                                 break;
1229                         default:
1230                                 command_print(cmd_ctx, "\tUnknown AP type");
1231                                 break;
1232                 }
1233
1234                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1235                  * not a ROM table ... or have no such components at all.
1236                  */
1237                 if (mem_ap)
1238                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1239                                         dbgbase);
1240         }
1241         else
1242         {
1243                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1244         }
1245
1246         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1247         if (romtable_present)
1248         {
1249                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1250                 uint16_t entry_offset;
1251
1252                 /* bit 16 of apid indicates a memory access port */
1253                 if (dbgbase & 0x02)
1254                         command_print(cmd_ctx, "\tValid ROM table present");
1255                 else
1256                         command_print(cmd_ctx, "\tROM table in legacy format");
1257
1258                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1259                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1260                 if (retval != ERROR_OK)
1261                         return retval;
1262                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1263                 if (retval != ERROR_OK)
1264                         return retval;
1265                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1266                 if (retval != ERROR_OK)
1267                         return retval;
1268                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1269                 if (retval != ERROR_OK)
1270                         return retval;
1271                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1272                 if (retval != ERROR_OK)
1273                         return retval;
1274                 retval = dap_run(dap);
1275                 if (retval != ERROR_OK)
1276                         return retval;
1277
1278                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1279                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1280                                         ", CID2 0x%2.2x"
1281                                         ", CID1 0x%2.2x"
1282                                         ", CID0 0x%2.2x",
1283                                         (unsigned) cid3, (unsigned)cid2,
1284                                         (unsigned) cid1, (unsigned) cid0);
1285                 if (memtype & 0x01)
1286                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1287                 else
1288                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1289                                         "Dedicated debug bus.");
1290
1291                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1292                 entry_offset = 0;
1293                 do
1294                 {
1295                         retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1296                         if (retval != ERROR_OK)
1297                                 return retval;
1298                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1299                         if (romentry&0x01)
1300                         {
1301                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1302                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1303                                 uint32_t component_base;
1304                                 unsigned part_num;
1305                                 char *type, *full;
1306
1307                                 component_base = (dbgbase & 0xFFFFF000)
1308                                                 + (romentry & 0xFFFFF000);
1309
1310                                 /* IDs are in last 4K section */
1311
1312
1313                                 retval = mem_ap_read_atomic_u32(dap,
1314                                         component_base + 0xFE0, &c_pid0);
1315                                 if (retval != ERROR_OK)
1316                                         return retval;
1317                                 c_pid0 &= 0xff;
1318                                 retval = mem_ap_read_atomic_u32(dap,
1319                                         component_base + 0xFE4, &c_pid1);
1320                                 if (retval != ERROR_OK)
1321                                         return retval;
1322                                 c_pid1 &= 0xff;
1323                                 retval = mem_ap_read_atomic_u32(dap,
1324                                         component_base + 0xFE8, &c_pid2);
1325                                 if (retval != ERROR_OK)
1326                                         return retval;
1327                                 c_pid2 &= 0xff;
1328                                 retval = mem_ap_read_atomic_u32(dap,
1329                                         component_base + 0xFEC, &c_pid3);
1330                                 if (retval != ERROR_OK)
1331                                         return retval;
1332                                 c_pid3 &= 0xff;
1333                                 retval = mem_ap_read_atomic_u32(dap,
1334                                         component_base + 0xFD0, &c_pid4);
1335                                 if (retval != ERROR_OK)
1336                                         return retval;
1337                                 c_pid4 &= 0xff;
1338
1339                                 retval = mem_ap_read_atomic_u32(dap,
1340                                         component_base + 0xFF0, &c_cid0);
1341                                 if (retval != ERROR_OK)
1342                                         return retval;
1343                                 c_cid0 &= 0xff;
1344                                 retval = mem_ap_read_atomic_u32(dap,
1345                                         component_base + 0xFF4, &c_cid1);
1346                                 if (retval != ERROR_OK)
1347                                         return retval;
1348                                 c_cid1 &= 0xff;
1349                                 retval = mem_ap_read_atomic_u32(dap,
1350                                         component_base + 0xFF8, &c_cid2);
1351                                 if (retval != ERROR_OK)
1352                                         return retval;
1353                                 c_cid2 &= 0xff;
1354                                 retval = mem_ap_read_atomic_u32(dap,
1355                                         component_base + 0xFFC, &c_cid3);
1356                                 if (retval != ERROR_OK)
1357                                         return retval;
1358                                 c_cid3 &= 0xff;
1359
1360
1361                                 command_print(cmd_ctx,
1362                                 "\t\tComponent base address 0x%" PRIx32
1363                                         ", start address 0x%" PRIx32,
1364                                                 component_base,
1365                                 /* component may take multiple 4K pages */
1366                                 component_base - 0x1000*(c_pid4 >> 4));
1367                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1368                                                 (int) (c_cid1 >> 4) & 0xf,
1369                                                 /* See ARM IHI 0029B Table 3-3 */
1370                                                 class_description[(c_cid1 >> 4) & 0xf]);
1371
1372                                 /* CoreSight component? */
1373                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1374                                         uint32_t devtype;
1375                                         unsigned minor;
1376                                         char *major = "Reserved", *subtype = "Reserved";
1377
1378                                         retval = mem_ap_read_atomic_u32(dap,
1379                                                         (component_base & 0xfffff000) | 0xfcc,
1380                                                         &devtype);
1381                                         if (retval != ERROR_OK)
1382                                                 return retval;
1383                                         minor = (devtype >> 4) & 0x0f;
1384                                         switch (devtype & 0x0f) {
1385                                         case 0:
1386                                                 major = "Miscellaneous";
1387                                                 switch (minor) {
1388                                                 case 0:
1389                                                         subtype = "other";
1390                                                         break;
1391                                                 case 4:
1392                                                         subtype = "Validation component";
1393                                                         break;
1394                                                 }
1395                                                 break;
1396                                         case 1:
1397                                                 major = "Trace Sink";
1398                                                 switch (minor) {
1399                                                 case 0:
1400                                                         subtype = "other";
1401                                                         break;
1402                                                 case 1:
1403                                                         subtype = "Port";
1404                                                         break;
1405                                                 case 2:
1406                                                         subtype = "Buffer";
1407                                                         break;
1408                                                 }
1409                                                 break;
1410                                         case 2:
1411                                                 major = "Trace Link";
1412                                                 switch (minor) {
1413                                                 case 0:
1414                                                         subtype = "other";
1415                                                         break;
1416                                                 case 1:
1417                                                         subtype = "Funnel, router";
1418                                                         break;
1419                                                 case 2:
1420                                                         subtype = "Filter";
1421                                                         break;
1422                                                 case 3:
1423                                                         subtype = "FIFO, buffer";
1424                                                         break;
1425                                                 }
1426                                                 break;
1427                                         case 3:
1428                                                 major = "Trace Source";
1429                                                 switch (minor) {
1430                                                 case 0:
1431                                                         subtype = "other";
1432                                                         break;
1433                                                 case 1:
1434                                                         subtype = "Processor";
1435                                                         break;
1436                                                 case 2:
1437                                                         subtype = "DSP";
1438                                                         break;
1439                                                 case 3:
1440                                                         subtype = "Engine/Coprocessor";
1441                                                         break;
1442                                                 case 4:
1443                                                         subtype = "Bus";
1444                                                         break;
1445                                                 }
1446                                                 break;
1447                                         case 4:
1448                                                 major = "Debug Control";
1449                                                 switch (minor) {
1450                                                 case 0:
1451                                                         subtype = "other";
1452                                                         break;
1453                                                 case 1:
1454                                                         subtype = "Trigger Matrix";
1455                                                         break;
1456                                                 case 2:
1457                                                         subtype = "Debug Auth";
1458                                                         break;
1459                                                 }
1460                                                 break;
1461                                         case 5:
1462                                                 major = "Debug Logic";
1463                                                 switch (minor) {
1464                                                 case 0:
1465                                                         subtype = "other";
1466                                                         break;
1467                                                 case 1:
1468                                                         subtype = "Processor";
1469                                                         break;
1470                                                 case 2:
1471                                                         subtype = "DSP";
1472                                                         break;
1473                                                 case 3:
1474                                                         subtype = "Engine/Coprocessor";
1475                                                         break;
1476                                                 }
1477                                                 break;
1478                                         }
1479                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1480                                                         (unsigned) (devtype & 0xff),
1481                                                         major, subtype);
1482                                         /* REVISIT also show 0xfc8 DevId */
1483                                 }
1484
1485                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1486                                         command_print(cmd_ctx,
1487                                                       "\t\tCID3 0%2.2x"
1488                                                         ", CID2 0%2.2x"
1489                                                         ", CID1 0%2.2x"
1490                                                         ", CID0 0%2.2x",
1491                                                         (int) c_cid3,
1492                                                         (int) c_cid2,
1493                                                         (int)c_cid1,
1494                                                         (int)c_cid0);
1495                                 command_print(cmd_ctx,
1496                                 "\t\tPeripheral ID[4..0] = hex "
1497                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1498                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1499                                 (int) c_pid1, (int) c_pid0);
1500
1501                                 /* Part number interpretations are from Cortex
1502                                  * core specs, the CoreSight components TRM
1503                                  * (ARM DDI 0314H), CoreSight System Design
1504                                  * Guide (ARM DGI 0012D) and ETM specs; also
1505                                  * from chip observation (e.g. TI SDTI).
1506                                  */
1507                                 part_num = (c_pid0 & 0xff);
1508                                 part_num |= (c_pid1 & 0x0f) << 8;
1509                                 switch (part_num) {
1510                                 case 0x000:
1511                                         type = "Cortex-M3 NVIC";
1512                                         full = "(Interrupt Controller)";
1513                                         break;
1514                                 case 0x001:
1515                                         type = "Cortex-M3 ITM";
1516                                         full = "(Instrumentation Trace Module)";
1517                                         break;
1518                                 case 0x002:
1519                                         type = "Cortex-M3 DWT";
1520                                         full = "(Data Watchpoint and Trace)";
1521                                         break;
1522                                 case 0x003:
1523                                         type = "Cortex-M3 FBP";
1524                                         full = "(Flash Patch and Breakpoint)";
1525                                         break;
1526                                 case 0x00d:
1527                                         type = "CoreSight ETM11";
1528                                         full = "(Embedded Trace)";
1529                                         break;
1530                                 // case 0x113: what?
1531                                 case 0x120:             /* from OMAP3 memmap */
1532                                         type = "TI SDTI";
1533                                         full = "(System Debug Trace Interface)";
1534                                         break;
1535                                 case 0x343:             /* from OMAP3 memmap */
1536                                         type = "TI DAPCTL";
1537                                         full = "";
1538                                         break;
1539                                 case 0x906:
1540                                         type = "Coresight CTI";
1541                                         full = "(Cross Trigger)";
1542                                         break;
1543                                 case 0x907:
1544                                         type = "Coresight ETB";
1545                                         full = "(Trace Buffer)";
1546                                         break;
1547                                 case 0x908:
1548                                         type = "Coresight CSTF";
1549                                         full = "(Trace Funnel)";
1550                                         break;
1551                                 case 0x910:
1552                                         type = "CoreSight ETM9";
1553                                         full = "(Embedded Trace)";
1554                                         break;
1555                                 case 0x912:
1556                                         type = "Coresight TPIU";
1557                                         full = "(Trace Port Interface Unit)";
1558                                         break;
1559                                 case 0x921:
1560                                         type = "Cortex-A8 ETM";
1561                                         full = "(Embedded Trace)";
1562                                         break;
1563                                 case 0x922:
1564                                         type = "Cortex-A8 CTI";
1565                                         full = "(Cross Trigger)";
1566                                         break;
1567                                 case 0x923:
1568                                         type = "Cortex-M3 TPIU";
1569                                         full = "(Trace Port Interface Unit)";
1570                                         break;
1571                                 case 0x924:
1572                                         type = "Cortex-M3 ETM";
1573                                         full = "(Embedded Trace)";
1574                                         break;
1575                                 case 0x930:
1576                                         type = "Cortex-R4 ETM";
1577                                         full = "(Embedded Trace)";
1578                                         break;
1579                                 case 0xc08:
1580                                         type = "Cortex-A8 Debug";
1581                                         full = "(Debug Unit)";
1582                                         break;
1583                                 default:
1584                                         type = "-*- unrecognized -*-";
1585                                         full = "";
1586                                         break;
1587                                 }
1588                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1589                                                 type, full);
1590                         }
1591                         else
1592                         {
1593                                 if (romentry)
1594                                         command_print(cmd_ctx, "\t\tComponent not present");
1595                                 else
1596                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1597                         }
1598                         entry_offset += 4;
1599                 } while (romentry > 0);
1600         }
1601         else
1602         {
1603                 command_print(cmd_ctx, "\tNo ROM table present");
1604         }
1605         dap_ap_select(dap, ap_old);
1606
1607         return ERROR_OK;
1608 }
1609
1610 COMMAND_HANDLER(handle_dap_info_command)
1611 {
1612         struct target *target = get_current_target(CMD_CTX);
1613         struct arm *arm = target_to_arm(target);
1614         struct adiv5_dap *dap = arm->dap;
1615         uint32_t apsel;
1616
1617         switch (CMD_ARGC) {
1618         case 0:
1619                 apsel = dap->apsel;
1620                 break;
1621         case 1:
1622                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1623                 break;
1624         default:
1625                 return ERROR_COMMAND_SYNTAX_ERROR;
1626         }
1627
1628         return dap_info_command(CMD_CTX, dap, apsel);
1629 }
1630
1631 COMMAND_HANDLER(dap_baseaddr_command)
1632 {
1633         struct target *target = get_current_target(CMD_CTX);
1634         struct arm *arm = target_to_arm(target);
1635         struct adiv5_dap *dap = arm->dap;
1636
1637         uint32_t apsel, baseaddr;
1638         int retval;
1639
1640         switch (CMD_ARGC) {
1641         case 0:
1642                 apsel = dap->apsel;
1643                 break;
1644         case 1:
1645                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1646                 /* AP address is in bits 31:24 of DP_SELECT */
1647                 if (apsel >= 256)
1648                         return ERROR_INVALID_ARGUMENTS;
1649                 break;
1650         default:
1651                 return ERROR_COMMAND_SYNTAX_ERROR;
1652         }
1653
1654         dap_ap_select(dap, apsel);
1655
1656         /* NOTE:  assumes we're talking to a MEM-AP, which
1657          * has a base address.  There are other kinds of AP,
1658          * though they're not common for now.  This should
1659          * use the ID register to verify it's a MEM-AP.
1660          */
1661         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1662         if (retval != ERROR_OK)
1663                 return retval;
1664         retval = dap_run(dap);
1665         if (retval != ERROR_OK)
1666                 return retval;
1667
1668         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1669
1670         return retval;
1671 }
1672
1673 COMMAND_HANDLER(dap_memaccess_command)
1674 {
1675         struct target *target = get_current_target(CMD_CTX);
1676         struct arm *arm = target_to_arm(target);
1677         struct adiv5_dap *dap = arm->dap;
1678
1679         uint32_t memaccess_tck;
1680
1681         switch (CMD_ARGC) {
1682         case 0:
1683                 memaccess_tck = dap->memaccess_tck;
1684                 break;
1685         case 1:
1686                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1687                 break;
1688         default:
1689                 return ERROR_COMMAND_SYNTAX_ERROR;
1690         }
1691         dap->memaccess_tck = memaccess_tck;
1692
1693         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1694                         dap->memaccess_tck);
1695
1696         return ERROR_OK;
1697 }
1698
1699 COMMAND_HANDLER(dap_apsel_command)
1700 {
1701         struct target *target = get_current_target(CMD_CTX);
1702         struct arm *arm = target_to_arm(target);
1703         struct adiv5_dap *dap = arm->dap;
1704
1705         uint32_t apsel, apid;
1706         int retval;
1707
1708         switch (CMD_ARGC) {
1709         case 0:
1710                 apsel = 0;
1711                 break;
1712         case 1:
1713                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1714                 /* AP address is in bits 31:24 of DP_SELECT */
1715                 if (apsel >= 256)
1716                         return ERROR_INVALID_ARGUMENTS;
1717                 break;
1718         default:
1719                 return ERROR_COMMAND_SYNTAX_ERROR;
1720         }
1721
1722         dap->apsel = apsel;
1723         dap_ap_select(dap, apsel);
1724
1725         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1726         if (retval != ERROR_OK)
1727                 return retval;
1728         retval = dap_run(dap);
1729         if (retval != ERROR_OK)
1730                 return retval;
1731
1732         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1733                         apsel, apid);
1734
1735         return retval;
1736 }
1737
1738 COMMAND_HANDLER(dap_apid_command)
1739 {
1740         struct target *target = get_current_target(CMD_CTX);
1741         struct arm *arm = target_to_arm(target);
1742         struct adiv5_dap *dap = arm->dap;
1743
1744         uint32_t apsel, apid;
1745         int retval;
1746
1747         switch (CMD_ARGC) {
1748         case 0:
1749                 apsel = dap->apsel;
1750                 break;
1751         case 1:
1752                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1753                 /* AP address is in bits 31:24 of DP_SELECT */
1754                 if (apsel >= 256)
1755                         return ERROR_INVALID_ARGUMENTS;
1756                 break;
1757         default:
1758                 return ERROR_COMMAND_SYNTAX_ERROR;
1759         }
1760
1761         dap_ap_select(dap, apsel);
1762
1763         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1764         if (retval != ERROR_OK)
1765                 return retval;
1766         retval = dap_run(dap);
1767         if (retval != ERROR_OK)
1768                 return retval;
1769
1770         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1771
1772         return retval;
1773 }
1774
1775 static const struct command_registration dap_commands[] = {
1776         {
1777                 .name = "info",
1778                 .handler = handle_dap_info_command,
1779                 .mode = COMMAND_EXEC,
1780                 .help = "display ROM table for MEM-AP "
1781                         "(default currently selected AP)",
1782                 .usage = "[ap_num]",
1783         },
1784         {
1785                 .name = "apsel",
1786                 .handler = dap_apsel_command,
1787                 .mode = COMMAND_EXEC,
1788                 .help = "Set the currently selected AP (default 0) "
1789                         "and display the result",
1790                 .usage = "[ap_num]",
1791         },
1792         {
1793                 .name = "apid",
1794                 .handler = dap_apid_command,
1795                 .mode = COMMAND_EXEC,
1796                 .help = "return ID register from AP "
1797                         "(default currently selected AP)",
1798                 .usage = "[ap_num]",
1799         },
1800         {
1801                 .name = "baseaddr",
1802                 .handler = dap_baseaddr_command,
1803                 .mode = COMMAND_EXEC,
1804                 .help = "return debug base address from MEM-AP "
1805                         "(default currently selected AP)",
1806                 .usage = "[ap_num]",
1807         },
1808         {
1809                 .name = "memaccess",
1810                 .handler = dap_memaccess_command,
1811                 .mode = COMMAND_EXEC,
1812                 .help = "set/get number of extra tck for MEM-AP memory "
1813                         "bus access [0-255]",
1814                 .usage = "[cycles]",
1815         },
1816         COMMAND_REGISTRATION_DONE
1817 };
1818
1819 const struct command_registration dap_command_handlers[] = {
1820         {
1821                 .name = "dap",
1822                 .mode = COMMAND_EXEC,
1823                 .help = "DAP command group",
1824                 .chain = dap_commands,
1825         },
1826         COMMAND_REGISTRATION_DONE
1827 };
1828
1829