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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76
  77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  78
  79 /*
  80         uint32_t tar_block_size(uint32_t address)
  81         Return the largest block starting at address that does not cross a tar block size alignment boundary
  82 */
  83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  84 {
  85         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  86 }
  87
  88 /***************************************************************************
  89  *                                                                         *
  90  * DP and MEM-AP  register access  through APACC and DPACC                 *
  91  *                                                                         *
  92 ***************************************************************************/
  93
  94 /**
  95  * Select one of the APs connected to the specified DAP.  The
  96  * selection is implicitly used with future AP transactions.
  97  * This is a NOP if the specified AP is already selected.
  98  *
  99  * @param dap The DAP
 100  * @param apsel Number of the AP to (implicitly) use with further
 101  *      transactions.  This normally identifies a MEM-AP.
 102  */
 103 void dap_ap_select(struct adiv5_dap *dap,uint8_t ap)
 104 {
 105         uint32_t new_ap = (ap << 24) & 0xFF000000;
 106
 107         if (new_ap != dap->ap_current)
 108         {
 109                 dap->ap_current = new_ap;
 110                 /* Switching AP invalidates cached values.
 111                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 112                  */
 113                 dap->ap_bank_value = -1;
 114                 dap->ap_csw_value = -1;
 115                 dap->ap_tar_value = -1;
 116         }
 117 }
 118
 119 /**
 120  * Queue transactions setting up transfer parameters for the
 121  * currently selected MEM-AP.
 122  *
 123  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 124  * initiate data reads or writes using memory or peripheral addresses.
 125  * If the CSW is configured for it, the TAR may be automatically
 126  * incremented after each transfer.
 127  *
 128  * @todo Rename to reflect it being specifically a MEM-AP function.
 129  *
 130  * @param dap The DAP connected to the MEM-AP.
 131  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 132  *      matches the cached value, the register is not changed.
 133  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 134  *      matches the cached address, the register is not changed.
 135  *
 136  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 137  */
 138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 139 {
 140         int retval;
 141
 142         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 143         if (csw != dap->ap_csw_value)
 144         {
 145                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 146                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 147                 if (retval != ERROR_OK)
 148                         return retval;
 149                 dap->ap_csw_value = csw;
 150         }
 151         if (tar != dap->ap_tar_value)
 152         {
 153                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 154                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 155                 if (retval != ERROR_OK)
 156                         return retval;
 157                 dap->ap_tar_value = tar;
 158         }
 159         /* Disable TAR cache when autoincrementing */
 160         if (csw & CSW_ADDRINC_MASK)
 161                 dap->ap_tar_value = -1;
 162         return ERROR_OK;
 163 }
 164
 165 /**
 166  * Asynchronous (queued) read of a word from memory or a system register.
 167  *
 168  * @param dap The DAP connected to the MEM-AP performing the read.
 169  * @param address Address of the 32-bit word to read; it must be
 170  *      readable by the currently selected MEM-AP.
 171  * @param value points to where the word will be stored when the
 172  *      transaction queue is flushed (assuming no errors).
 173  *
 174  * @return ERROR_OK for success.  Otherwise a fault code.
 175  */
 176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 177                 uint32_t *value)
 178 {
 179         int retval;
 180
 181         /* Use banked addressing (REG_BDx) to avoid some link traffic
 182          * (updating TAR) when reading several consecutive addresses.
 183          */
 184         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 185                         address & 0xFFFFFFF0);
 186         if (retval != ERROR_OK)
 187                 return retval;
 188
 189         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 190 }
 191
 192 /**
 193  * Synchronous read of a word from memory or a system register.
 194  * As a side effect, this flushes any queued transactions.
 195  *
 196  * @param dap The DAP connected to the MEM-AP performing the read.
 197  * @param address Address of the 32-bit word to read; it must be
 198  *      readable by the currently selected MEM-AP.
 199  * @param value points to where the result will be stored.
 200  *
 201  * @return ERROR_OK for success; *value holds the result.
 202  * Otherwise a fault code.
 203  */
 204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 205                 uint32_t *value)
 206 {
 207         int retval;
 208
 209         retval = mem_ap_read_u32(dap, address, value);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         return dap_run(dap);
 214 }
 215
 216 /**
 217  * Asynchronous (queued) write of a word to memory or a system register.
 218  *
 219  * @param dap The DAP connected to the MEM-AP.
 220  * @param address Address to be written; it must be writable by
 221  *      the currently selected MEM-AP.
 222  * @param value Word that will be written to the address when transaction
 223  *      queue is flushed (assuming no errors).
 224  *
 225  * @return ERROR_OK for success.  Otherwise a fault code.
 226  */
 227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 228                 uint32_t value)
 229 {
 230         int retval;
 231
 232         /* Use banked addressing (REG_BDx) to avoid some link traffic
 233          * (updating TAR) when writing several consecutive addresses.
 234          */
 235         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 236                         address & 0xFFFFFFF0);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 241                         value);
 242 }
 243
 244 /**
 245  * Synchronous write of a word to memory or a system register.
 246  * As a side effect, this flushes any queued transactions.
 247  *
 248  * @param dap The DAP connected to the MEM-AP.
 249  * @param address Address to be written; it must be writable by
 250  *      the currently selected MEM-AP.
 251  * @param value Word that will be written.
 252  *
 253  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 254  */
 255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 256                 uint32_t value)
 257 {
 258         int retval = mem_ap_write_u32(dap, address, value);
 259
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         return dap_run(dap);
 264 }
 265
 266 /*****************************************************************************
 267 *                                                                            *
 268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 269 *                                                                            *
 270 * Write a buffer in target order (little endian)                             *
 271 *                                                                            *
 272 *****************************************************************************/
 273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 274 {
 275         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 276         uint32_t adr = address;
 277         const uint8_t* pBuffer = buffer;
 278
 279         count >>= 2;
 280         wcount = count;
 281
 282         /* if we have an unaligned access - reorder data */
 283         if (adr & 0x3u)
 284         {
 285                 for (writecount = 0; writecount < count; writecount++)
 286                 {
 287                         int i;
 288                         uint32_t outvalue;
 289                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 290
 291                         for (i = 0; i < 4; i++)
 292                         {
 293                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 294                                 outvalue >>= 8;
 295                                 adr++;
 296                         }
 297                         pBuffer += sizeof(uint32_t);
 298                 }
 299         }
 300
 301         while (wcount > 0)
 302         {
 303                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 304                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 305                 if (wcount < blocksize)
 306                         blocksize = wcount;
 307
 308                 /* handle unaligned data at 4k boundary */
 309                 if (blocksize == 0)
 310                         blocksize = 1;
 311
 312                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315
 316                 for (writecount = 0; writecount < blocksize; writecount++)
 317                 {
 318                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 319                                 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
 320                         if (retval != ERROR_OK)
 321                                 break;
 322                 }
 323
 324                 if ((retval = dap_run(dap)) == ERROR_OK)
 325                 {
 326                         wcount = wcount - blocksize;
 327                         address = address + 4 * blocksize;
 328                         buffer = buffer + 4 * blocksize;
 329                 }
 330                 else
 331                 {
 332                         errorcount++;
 333                 }
 334
 335                 if (errorcount > 1)
 336                 {
 337                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 338                         return retval;
 339                 }
 340         }
 341
 342         return retval;
 343 }
 344
 345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 346                 const uint8_t *buffer, int count, uint32_t address)
 347 {
 348         int retval = ERROR_OK;
 349         int wcount, blocksize, writecount, i;
 350
 351         wcount = count >> 1;
 352
 353         while (wcount > 0)
 354         {
 355                 int nbytes;
 356
 357                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 358                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 359
 360                 if (wcount < blocksize)
 361                         blocksize = wcount;
 362
 363                 /* handle unaligned data at 4k boundary */
 364                 if (blocksize == 0)
 365                         blocksize = 1;
 366
 367                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 368                 if (retval != ERROR_OK)
 369                         return retval;
 370                 writecount = blocksize;
 371
 372                 do
 373                 {
 374                         nbytes = MIN((writecount << 1), 4);
 375
 376                         if (nbytes < 4)
 377                         {
 378                                 retval = mem_ap_write_buf_u16(dap, buffer,
 379                                                 nbytes, address);
 380                                 if (retval != ERROR_OK)
 381                                 {
 382                                         LOG_WARNING("Block write error address "
 383                                                 "0x%" PRIx32 ", count 0x%x",
 384                                                 address, count);
 385                                         return retval;
 386                                 }
 387
 388                                 address += nbytes >> 1;
 389                         }
 390                         else
 391                         {
 392                                 uint32_t outvalue;
 393                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 394
 395                                 for (i = 0; i < nbytes; i++)
 396                                 {
 397                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 398                                         outvalue >>= 8;
 399                                         address++;
 400                                 }
 401
 402                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 403                                 retval = dap_queue_ap_write(dap,
 404                                                 AP_REG_DRW, outvalue);
 405                                 if (retval != ERROR_OK)
 406                                         break;
 407
 408                                 if ((retval = dap_run(dap)) != ERROR_OK)
 409                                 {
 410                                         LOG_WARNING("Block write error address "
 411                                                 "0x%" PRIx32 ", count 0x%x",
 412                                                 address, count);
 413                                         return retval;
 414                                 }
 415                         }
 416
 417                         buffer += nbytes >> 1;
 418                         writecount -= nbytes >> 1;
 419
 420                 } while (writecount);
 421                 wcount -= blocksize;
 422         }
 423
 424         return retval;
 425 }
 426
 427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 428 {
 429         int retval = ERROR_OK;
 430
 431         if (count >= 4)
 432                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 433
 434         while (count > 0)
 435         {
 436                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 437                 if (retval != ERROR_OK)
 438                         return retval;
 439                 uint16_t svalue;
 440                 memcpy(&svalue, buffer, sizeof(uint16_t));
 441                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 442                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 443                 if (retval != ERROR_OK)
 444                         break;
 445
 446                 retval = dap_run(dap);
 447                 if (retval != ERROR_OK)
 448                         break;
 449
 450                 count -= 2;
 451                 address += 2;
 452                 buffer += 2;
 453         }
 454
 455         return retval;
 456 }
 457
 458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 459                 const uint8_t *buffer, int count, uint32_t address)
 460 {
 461         int retval = ERROR_OK;
 462         int wcount, blocksize, writecount, i;
 463
 464         wcount = count;
 465
 466         while (wcount > 0)
 467         {
 468                 int nbytes;
 469
 470                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 471                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 472
 473                 if (wcount < blocksize)
 474                         blocksize = wcount;
 475
 476                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 477                 if (retval != ERROR_OK)
 478                         return retval;
 479                 writecount = blocksize;
 480
 481                 do
 482                 {
 483                         nbytes = MIN(writecount, 4);
 484
 485                         if (nbytes < 4)
 486                         {
 487                                 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
 488                                 if (retval != ERROR_OK)
 489                                 {
 490                                         LOG_WARNING("Block write error address "
 491                                                 "0x%" PRIx32 ", count 0x%x",
 492                                                 address, count);
 493                                         return retval;
 494                                 }
 495
 496                                 address += nbytes;
 497                         }
 498                         else
 499                         {
 500                                 uint32_t outvalue;
 501                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 502
 503                                 for (i = 0; i < nbytes; i++)
 504                                 {
 505                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 506                                         outvalue >>= 8;
 507                                         address++;
 508                                 }
 509
 510                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 511                                 retval = dap_queue_ap_write(dap,
 512                                                 AP_REG_DRW, outvalue);
 513                                 if (retval != ERROR_OK)
 514                                         break;
 515
 516                                 if ((retval = dap_run(dap)) != ERROR_OK)
 517                                 {
 518                                         LOG_WARNING("Block write error address "
 519                                                 "0x%" PRIx32 ", count 0x%x",
 520                                                 address, count);
 521                                         return retval;
 522                                 }
 523                         }
 524
 525                         buffer += nbytes;
 526                         writecount -= nbytes;
 527
 528                 } while (writecount);
 529                 wcount -= blocksize;
 530         }
 531
 532         return retval;
 533 }
 534
 535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 536 {
 537         int retval = ERROR_OK;
 538
 539         if (count >= 4)
 540                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 541
 542         while (count > 0)
 543         {
 544                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 545                 if (retval != ERROR_OK)
 546                         return retval;
 547                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 548                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 549                 if (retval != ERROR_OK)
 550                         break;
 551
 552                 retval = dap_run(dap);
 553                 if (retval != ERROR_OK)
 554                         break;
 555
 556                 count--;
 557                 address++;
 558                 buffer++;
 559         }
 560
 561         return retval;
 562 }
 563
 564 /* FIXME don't import ... this is a temporary workaround for the
 565  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 566  */
 567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 568                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 569                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 570
 571 /**
 572  * Synchronously read a block of 32-bit words into a buffer
 573  * @param dap The DAP connected to the MEM-AP.
 574  * @param buffer where the words will be stored (in host byte order).
 575  * @param count How many words to read.
 576  * @param address Memory address from which to read words; all the
 577  *      words must be readable by the currently selected MEM-AP.
 578  */
 579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 580                 int count, uint32_t address)
 581 {
 582         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 583         uint32_t adr = address;
 584         uint8_t* pBuffer = buffer;
 585
 586         count >>= 2;
 587         wcount = count;
 588
 589         while (wcount > 0)
 590         {
 591                 /* Adjust to read blocks within boundaries aligned to the
 592                  * TAR autoincrement size (at least 2^10).  Autoincrement
 593                  * mode avoids an extra per-word roundtrip to update TAR.
 594                  */
 595                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 596                                 address);
 597                 if (wcount < blocksize)
 598                         blocksize = wcount;
 599
 600                 /* handle unaligned data at 4k boundary */
 601                 if (blocksize == 0)
 602                         blocksize = 1;
 603
 604                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 605                                 address);
 606                 if (retval != ERROR_OK)
 607                         return retval;
 608
 609                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 610                  * so this routine becomes transport-neutral.  Be careful
 611                  * not to cause performance problems with JTAG; would it
 612                  * suffice to loop over dap_queue_ap_read(), or would that
 613                  * be slower when JTAG is the chosen transport?
 614                  */
 615
 616                 /* Scan out first read */
 617                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 618                                 DPAP_READ, 0, NULL, NULL);
 619                 if (retval != ERROR_OK)
 620                         return retval;
 621                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 622                 {
 623                         /* Scan out next read; scan in posted value for the
 624                          * previous one.  Assumes read is acked "OK/FAULT",
 625                          * and CTRL_STAT says that meant "OK".
 626                          */
 627                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 628                                         DPAP_READ, 0, buffer + 4 * readcount,
 629                                         &dap->ack);
 630                         if (retval != ERROR_OK)
 631                                 return retval;
 632                 }
 633
 634                 /* Scan in last posted value; RDBUFF has no other effect,
 635                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 636                  */
 637                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 638                                 DPAP_READ, 0, buffer + 4 * readcount,
 639                                 &dap->ack);
 640                 if (retval != ERROR_OK)
 641                         return retval;
 642
 643                 retval = dap_run(dap);
 644                 if (retval != ERROR_OK)
 645                 {
 646                         errorcount++;
 647                         if (errorcount <= 1)
 648                         {
 649                                 /* try again */
 650                                 continue;
 651                         }
 652                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 653                         return retval;
 654                 }
 655                 wcount = wcount - blocksize;
 656                 address += 4 * blocksize;
 657                 buffer += 4 * blocksize;
 658         }
 659
 660         /* if we have an unaligned access - reorder data */
 661         if (adr & 0x3u)
 662         {
 663                 for (readcount = 0; readcount < count; readcount++)
 664                 {
 665                         int i;
 666                         uint32_t data;
 667                         memcpy(&data, pBuffer, sizeof(uint32_t));
 668
 669                         for (i = 0; i < 4; i++)
 670                         {
 671                                 *((uint8_t*)pBuffer) =
 672                                                 (data >> 8 * (adr & 0x3));
 673                                 pBuffer++;
 674                                 adr++;
 675                         }
 676                 }
 677         }
 678
 679         return retval;
 680 }
 681
 682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 683                 uint8_t *buffer, int count, uint32_t address)
 684 {
 685         uint32_t invalue;
 686         int retval = ERROR_OK;
 687         int wcount, blocksize, readcount, i;
 688
 689         wcount = count >> 1;
 690
 691         while (wcount > 0)
 692         {
 693                 int nbytes;
 694
 695                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 696                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 697                 if (wcount < blocksize)
 698                         blocksize = wcount;
 699
 700                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 701                 if (retval != ERROR_OK)
 702                         return retval;
 703
 704                 /* handle unaligned data at 4k boundary */
 705                 if (blocksize == 0)
 706                         blocksize = 1;
 707                 readcount = blocksize;
 708
 709                 do
 710                 {
 711                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 712                         if (retval != ERROR_OK)
 713                                 return retval;
 714                         if ((retval = dap_run(dap)) != ERROR_OK)
 715                         {
 716                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 717                                 return retval;
 718                         }
 719
 720                         nbytes = MIN((readcount << 1), 4);
 721
 722                         for (i = 0; i < nbytes; i++)
 723                         {
 724                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 725                                 buffer++;
 726                                 address++;
 727                         }
 728
 729                         readcount -= (nbytes >> 1);
 730                 } while (readcount);
 731                 wcount -= blocksize;
 732         }
 733
 734         return retval;
 735 }
 736
 737 /**
 738  * Synchronously read a block of 16-bit halfwords into a buffer
 739  * @param dap The DAP connected to the MEM-AP.
 740  * @param buffer where the halfwords will be stored (in host byte order).
 741  * @param count How many halfwords to read.
 742  * @param address Memory address from which to read words; all the
 743  *      words must be readable by the currently selected MEM-AP.
 744  */
 745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 746                 int count, uint32_t address)
 747 {
 748         uint32_t invalue, i;
 749         int retval = ERROR_OK;
 750
 751         if (count >= 4)
 752                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 753
 754         while (count > 0)
 755         {
 756                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 757                 if (retval != ERROR_OK)
 758                         return retval;
 759                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 760                 if (retval != ERROR_OK)
 761                         break;
 762
 763                 retval = dap_run(dap);
 764                 if (retval != ERROR_OK)
 765                         break;
 766
 767                 if (address & 0x1)
 768                 {
 769                         for (i = 0; i < 2; i++)
 770                         {
 771                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 772                                 buffer++;
 773                                 address++;
 774                         }
 775                 }
 776                 else
 777                 {
 778                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 779                         memcpy(buffer, &svalue, sizeof(uint16_t));
 780                         address += 2;
 781                         buffer += 2;
 782                 }
 783                 count -= 2;
 784         }
 785
 786         return retval;
 787 }
 788
 789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 790  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 791  *
 792  * The solution is to arrange for a large out/in scan in this loop and
 793  * and convert data afterwards.
 794  */
 795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 796                 uint8_t *buffer, int count, uint32_t address)
 797 {
 798         uint32_t invalue;
 799         int retval = ERROR_OK;
 800         int wcount, blocksize, readcount, i;
 801
 802         wcount = count;
 803
 804         while (wcount > 0)
 805         {
 806                 int nbytes;
 807
 808                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 809                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 810
 811                 if (wcount < blocksize)
 812                         blocksize = wcount;
 813
 814                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 815                 if (retval != ERROR_OK)
 816                         return retval;
 817                 readcount = blocksize;
 818
 819                 do
 820                 {
 821                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 822                         if (retval != ERROR_OK)
 823                                 return retval;
 824                         if ((retval = dap_run(dap)) != ERROR_OK)
 825                         {
 826                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 827                                 return retval;
 828                         }
 829
 830                         nbytes = MIN(readcount, 4);
 831
 832                         for (i = 0; i < nbytes; i++)
 833                         {
 834                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 835                                 buffer++;
 836                                 address++;
 837                         }
 838
 839                         readcount -= nbytes;
 840                 } while (readcount);
 841                 wcount -= blocksize;
 842         }
 843
 844         return retval;
 845 }
 846
 847 /**
 848  * Synchronously read a block of bytes into a buffer
 849  * @param dap The DAP connected to the MEM-AP.
 850  * @param buffer where the bytes will be stored.
 851  * @param count How many bytes to read.
 852  * @param address Memory address from which to read data; all the
 853  *      data must be readable by the currently selected MEM-AP.
 854  */
 855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 856                 int count, uint32_t address)
 857 {
 858         uint32_t invalue;
 859         int retval = ERROR_OK;
 860
 861         if (count >= 4)
 862                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 863
 864         while (count > 0)
 865         {
 866                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 867                 if (retval != ERROR_OK)
 868                         return retval;
 869                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 870                 if (retval != ERROR_OK)
 871                         return retval;
 872                 retval = dap_run(dap);
 873                 if (retval != ERROR_OK)
 874                         break;
 875
 876                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 877                 count--;
 878                 address++;
 879                 buffer++;
 880         }
 881
 882         return retval;
 883 }
 884
 885 /*--------------------------------------------------------------------*/
 886 /*          Wrapping function with selection of AP                    */
 887 /*--------------------------------------------------------------------*/
 888 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 889                 uint32_t address, uint32_t *value)
 890 {
 891         dap_ap_select(swjdp, ap);
 892         return mem_ap_read_u32(swjdp, address, value);
 893 }
 894
 895 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 896                 uint32_t address, uint32_t value)
 897 {
 898         dap_ap_select(swjdp, ap);
 899         return mem_ap_write_u32(swjdp, address, value);
 900 }
 901
 902 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 903                 uint32_t address, uint32_t *value)
 904 {
 905         dap_ap_select(swjdp, ap);
 906         return mem_ap_read_atomic_u32(swjdp, address, value);
 907 }
 908
 909 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 910                 uint32_t address, uint32_t value)
 911 {
 912         dap_ap_select(swjdp, ap);
 913         return mem_ap_write_atomic_u32(swjdp, address, value);
 914 }
 915
 916 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 917                 uint8_t *buffer, int count, uint32_t address)
 918 {
 919         dap_ap_select(swjdp, ap);
 920         return mem_ap_read_buf_u8(swjdp, buffer, count, address);
 921 }
 922
 923 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 924                 uint8_t *buffer, int count, uint32_t address)
 925 {
 926         dap_ap_select(swjdp, ap);
 927         return mem_ap_read_buf_u16(swjdp, buffer, count, address);
 928 }
 929
 930 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 931                 uint8_t *buffer, int count, uint32_t address)
 932 {
 933         dap_ap_select(swjdp, ap);
 934         return mem_ap_read_buf_u32(swjdp, buffer, count, address);
 935 }
 936
 937 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 938                 const uint8_t *buffer, int count, uint32_t address)
 939 {
 940         dap_ap_select(swjdp, ap);
 941         return mem_ap_write_buf_u8(swjdp, buffer, count, address);
 942 }
 943
 944 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 945                 const uint8_t *buffer, int count, uint32_t address)
 946 {
 947         dap_ap_select(swjdp, ap);
 948         return mem_ap_write_buf_u16(swjdp, buffer, count, address);
 949 }
 950
 951 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 952                 const uint8_t *buffer, int count, uint32_t address)
 953 {
 954         dap_ap_select(swjdp, ap);
 955         return mem_ap_write_buf_u32(swjdp, buffer, count, address);
 956 }
 957
 958 #define MDM_REG_STAT            0x00
 959 #define MDM_REG_CTRL            0x04
 960 #define MDM_REG_ID              0xfc
 961
 962 #define MDM_STAT_FMEACK         (1<<0)
 963 #define MDM_STAT_FREADY         (1<<1)
 964 #define MDM_STAT_SYSSEC         (1<<2)
 965 #define MDM_STAT_SYSRES         (1<<3)
 966 #define MDM_STAT_FMEEN          (1<<5)
 967 #define MDM_STAT_BACKDOOREN     (1<<6)
 968 #define MDM_STAT_LPEN           (1<<7)
 969 #define MDM_STAT_VLPEN          (1<<8)
 970 #define MDM_STAT_LLSMODEXIT     (1<<9)
 971 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 972 #define MDM_STAT_CORE_HALTED    (1<<16)
 973 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 974 #define MDM_STAT_CORESLEEPING   (1<<18)
 975
 976 #define MEM_CTRL_FMEIP          (1<<0)
 977 #define MEM_CTRL_DBG_DIS        (1<<1)
 978 #define MEM_CTRL_DBG_REQ        (1<<2)
 979 #define MEM_CTRL_SYS_RES_REQ    (1<<3)
 980 #define MEM_CTRL_CORE_HOLD_RES  (1<<4)
 981 #define MEM_CTRL_VLLSX_DBG_REQ  (1<<5)
 982 #define MEM_CTRL_VLLSX_DBG_ACK  (1<<6)
 983 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
 984
 985 /**
 986  *
 987  */
 988 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
 989 {
 990         uint32_t val;
 991         int retval;
 992         enum reset_types jtag_reset_config = jtag_get_reset_config();
 993
 994         dap_ap_select(dap, 1);
 995
 996         /* first check mdm-ap id register */
 997         retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
 998         if (retval != ERROR_OK)
 999                 return retval;
1000         dap_run(dap);
1001
1002         if ( val != 0x001C0000 )
1003         {
1004                 LOG_DEBUG("id doesn't match %08X != 0x001C0000",val);
1005                 dap_ap_select(dap, 0);
1006                 return ERROR_FAIL;
1007         }
1008
1009         /* read and parse status register
1010          * it's important that the device is out of
1011          * reset here
1012          */
1013         retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1014         if (retval != ERROR_OK)
1015                 return retval;
1016         dap_run(dap);
1017
1018         LOG_DEBUG("MDM_REG_STAT %08X",val);
1019
1020         if ( (val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY) )
1021         {
1022                 LOG_DEBUG("MDMAP: system is secured, masserase needed");
1023
1024                 if ( !(val & MDM_STAT_FMEEN) )
1025                 {
1026                         LOG_DEBUG("MDMAP: masserase is disabled");
1027                 }
1028                 else
1029                 {
1030                         /* we need to assert reset */
1031                         if ( jtag_reset_config & RESET_HAS_SRST )
1032                         {
1033                                 /* default to asserting srst */
1034                                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
1035                                 {
1036                                         jtag_add_reset(1, 1);
1037                                 }
1038                                 else
1039                                 {
1040                                         jtag_add_reset(0, 1);
1041                                 }
1042                         }
1043                         else
1044                         {
1045                                 LOG_DEBUG("SRST not configured");
1046                                 dap_ap_select(dap, 0);
1047                                 return ERROR_FAIL;
1048                         }
1049
1050                         while(1)
1051                         {
1052                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
1053                                 if (retval != ERROR_OK)
1054                                         return retval;
1055                                 dap_run(dap);
1056                                 /* read status register and wait for ready */
1057                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1058                                 if (retval != ERROR_OK)
1059                                         return retval;
1060                                 dap_run(dap);
1061                                 LOG_DEBUG("MDM_REG_STAT %08X",val);
1062
1063                                 if ( (val&1))
1064                                         break;
1065                         }
1066
1067                         while(1)
1068                         {
1069                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1070                                 if (retval != ERROR_OK)
1071                                         return retval;
1072                                 dap_run(dap);
1073                                 /* read status register */
1074                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1075                                 if (retval != ERROR_OK)
1076                                         return retval;
1077                                 dap_run(dap);
1078                                 LOG_DEBUG("MDM_REG_STAT %08X",val);
1079                                 /* read control register and wait for ready */
1080                                 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1081                                 if (retval != ERROR_OK)
1082                                         return retval;
1083                                 dap_run(dap);
1084                                 LOG_DEBUG("MDM_REG_CTRL %08X",val);
1085
1086                                 if ( val == 0x00 )
1087                                         break;
1088                         }
1089                 }
1090         }
1091
1092         dap_ap_select(dap, 0);
1093
1094         return ERROR_OK;
1095 }
1096
1097 /** */
1098 struct dap_syssec_filter {
1099         /** */
1100         uint32_t idcode;
1101         /** */
1102         int (*dap_init)(struct adiv5_dap *dap);
1103 };
1104
1105 /** */
1106 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1107         { 0x4BA00477, dap_syssec_kinetis_mdmap }
1108 };
1109
1110
1111 /**
1112  *
1113  */
1114 int dap_syssec(struct adiv5_dap *dap)
1115 {
1116         unsigned int i;
1117         struct jtag_tap *tap;
1118
1119         for(i=0;i<sizeof(dap_syssec_filter_data);i++)
1120         {
1121                 tap = dap->jtag_info->tap;
1122
1123                 while (tap != NULL)
1124                 {
1125                         if ( tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode) )
1126                         {
1127                                 LOG_DEBUG("DAP: mdmap_init for idcode: %08x",tap->idcode);
1128                                 dap_syssec_filter_data[i].dap_init(dap);
1129                         }
1130                         tap = tap->next_tap;
1131                 }
1132         }
1133
1134         return ERROR_OK;
1135 }
1136
1137 /*--------------------------------------------------------------------------*/
1138
1139
1140 /* FIXME don't import ... just initialize as
1141  * part of DAP transport setup
1142 */
1143 extern const struct dap_ops jtag_dp_ops;
1144
1145 /*--------------------------------------------------------------------------*/
1146
1147 /**
1148  * Initialize a DAP.  This sets up the power domains, prepares the DP
1149  * for further use, and arranges to use AP #0 for all AP operations
1150  * until dap_ap-select() changes that policy.
1151  *
1152  * @param dap The DAP being initialized.
1153  *
1154  * @todo Rename this.  We also need an initialization scheme which account
1155  * for SWD transports not just JTAG; that will need to address differences
1156  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1157  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1158  */
1159 int ahbap_debugport_init(struct adiv5_dap *dap)
1160 {
1161         uint32_t ctrlstat;
1162         int cnt = 0;
1163         int retval;
1164
1165         LOG_DEBUG(" ");
1166
1167         /* JTAG-DP or SWJ-DP, in JTAG mode
1168          * ... for SWD mode this is patched as part
1169          * of link switchover
1170          */
1171         if (!dap->ops)
1172                 dap->ops = &jtag_dp_ops;
1173
1174         /* Default MEM-AP setup.
1175          *
1176          * REVISIT AP #0 may be an inappropriate default for this.
1177          * Should we probe, or take a hint from the caller?
1178          * Presumably we can ignore the possibility of multiple APs.
1179          */
1180         dap->ap_current = !0;
1181         dap_ap_select(dap, 0);
1182
1183         /* DP initialization */
1184
1185         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1186         if (retval != ERROR_OK)
1187                 return retval;
1188
1189         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1190         if (retval != ERROR_OK)
1191                 return retval;
1192
1193         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1194         if (retval != ERROR_OK)
1195                 return retval;
1196
1197         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1198         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1199         if (retval != ERROR_OK)
1200                 return retval;
1201
1202         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1203         if (retval != ERROR_OK)
1204                 return retval;
1205         if ((retval = dap_run(dap)) != ERROR_OK)
1206                 return retval;
1207
1208         /* Check that we have debug power domains activated */
1209         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1210         {
1211                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1212                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1213                 if (retval != ERROR_OK)
1214                         return retval;
1215                 if ((retval = dap_run(dap)) != ERROR_OK)
1216                         return retval;
1217                 alive_sleep(10);
1218         }
1219
1220         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1221         {
1222                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1223                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1224                 if (retval != ERROR_OK)
1225                         return retval;
1226                 if ((retval = dap_run(dap)) != ERROR_OK)
1227                         return retval;
1228                 alive_sleep(10);
1229         }
1230
1231         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1232         if (retval != ERROR_OK)
1233                 return retval;
1234         /* With debug power on we can activate OVERRUN checking */
1235         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1236         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1237         if (retval != ERROR_OK)
1238                 return retval;
1239         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1240         if (retval != ERROR_OK)
1241                 return retval;
1242
1243         dap_syssec(dap);
1244
1245         return ERROR_OK;
1246 }
1247
1248 /* CID interpretation -- see ARM IHI 0029B section 3
1249  * and ARM IHI 0031A table 13-3.
1250  */
1251 static const char *class_description[16] ={
1252         "Reserved", "ROM table", "Reserved", "Reserved",
1253         "Reserved", "Reserved", "Reserved", "Reserved",
1254         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1255         "Reserved", "OptimoDE DESS",
1256                 "Generic IP component", "PrimeCell or System component"
1257 };
1258
1259 static bool
1260 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1261 {
1262         return cid3 == 0xb1 && cid2 == 0x05
1263                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1264 }
1265
1266 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1267                         uint32_t *out_dbgbase, uint32_t *out_apid)
1268 {
1269         uint32_t ap_old;
1270         int retval;
1271         uint32_t dbgbase, apid;
1272
1273         /* AP address is in bits 31:24 of DP_SELECT */
1274         if (ap >= 256)
1275                 return ERROR_INVALID_ARGUMENTS;
1276
1277         ap_old = dap->ap_current;
1278         dap_ap_select(dap, ap);
1279
1280         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1281         if (retval != ERROR_OK)
1282                 return retval;
1283         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1284         if (retval != ERROR_OK)
1285                 return retval;
1286         retval = dap_run(dap);
1287         if (retval != ERROR_OK)
1288                 return retval;
1289
1290         /* Excavate the device ID code */
1291         struct jtag_tap *tap = dap->jtag_info->tap;
1292         while (tap != NULL) {
1293                 if (tap->hasidcode)
1294                         break;
1295                 tap = tap->next_tap;
1296         }
1297         if (tap == NULL || !tap->hasidcode)
1298                 return ERROR_OK;
1299
1300         dap_ap_select(dap, ap_old);
1301
1302         /* The asignment happens only here to prevent modification of these
1303          * values before they are certain. */
1304         *out_dbgbase = dbgbase;
1305         *out_apid = apid;
1306
1307         return ERROR_OK;
1308 }
1309
1310 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1311                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
1312 {
1313         uint32_t ap_old;
1314         uint32_t romentry, entry_offset = 0, component_base, devtype;
1315         int retval = ERROR_FAIL;
1316
1317         if (ap >= 256)
1318                 return ERROR_INVALID_ARGUMENTS;
1319
1320         ap_old = dap->ap_current;
1321         dap_ap_select(dap, ap);
1322
1323         do
1324         {
1325                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1326                                                 entry_offset, &romentry);
1327                 if (retval != ERROR_OK)
1328                         return retval;
1329
1330                 component_base = (dbgbase & 0xFFFFF000)
1331                         + (romentry & 0xFFFFF000);
1332
1333                 if (romentry & 0x1) {
1334                         retval = mem_ap_read_atomic_u32(dap,
1335                                         (component_base & 0xfffff000) | 0xfcc,
1336                                         &devtype);
1337                         if ((devtype & 0xff) == type) {
1338                                 *addr = component_base;
1339                                 retval = ERROR_OK;
1340                                 break;
1341                         }
1342                 }
1343                 entry_offset += 4;
1344         } while (romentry > 0);
1345
1346         dap_ap_select(dap, ap_old);
1347
1348         return retval;
1349 }
1350
1351 static int dap_info_command(struct command_context *cmd_ctx,
1352                 struct adiv5_dap *dap, int ap)
1353 {
1354         int retval;
1355         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1356         int romtable_present = 0;
1357         uint8_t mem_ap;
1358         uint32_t ap_old;
1359
1360         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1361         if (retval != ERROR_OK)
1362                 return retval;
1363
1364         ap_old = dap->ap_current;
1365         dap_ap_select(dap, ap);
1366
1367         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1368         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1369         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1370         if (apid)
1371         {
1372                 switch (apid&0x0F)
1373                 {
1374                         case 0:
1375                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1376                                 break;
1377                         case 1:
1378                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1379                                 break;
1380                         case 2:
1381                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1382                                 break;
1383                         default:
1384                                 command_print(cmd_ctx, "\tUnknown AP type");
1385                                 break;
1386                 }
1387
1388                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1389                  * not a ROM table ... or have no such components at all.
1390                  */
1391                 if (mem_ap)
1392                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1393                                         dbgbase);
1394         }
1395         else
1396         {
1397                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1398         }
1399
1400         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1401         if (romtable_present)
1402         {
1403                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1404                 uint16_t entry_offset;
1405
1406                 /* bit 16 of apid indicates a memory access port */
1407                 if (dbgbase & 0x02)
1408                         command_print(cmd_ctx, "\tValid ROM table present");
1409                 else
1410                         command_print(cmd_ctx, "\tROM table in legacy format");
1411
1412                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1413                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1414                 if (retval != ERROR_OK)
1415                         return retval;
1416                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1417                 if (retval != ERROR_OK)
1418                         return retval;
1419                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1420                 if (retval != ERROR_OK)
1421                         return retval;
1422                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1423                 if (retval != ERROR_OK)
1424                         return retval;
1425                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1426                 if (retval != ERROR_OK)
1427                         return retval;
1428                 retval = dap_run(dap);
1429                 if (retval != ERROR_OK)
1430                         return retval;
1431
1432                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1433                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1434                                         ", CID2 0x%2.2x"
1435                                         ", CID1 0x%2.2x"
1436                                         ", CID0 0x%2.2x",
1437                                         (unsigned) cid3, (unsigned)cid2,
1438                                         (unsigned) cid1, (unsigned) cid0);
1439                 if (memtype & 0x01)
1440                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1441                 else
1442                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1443                                         "Dedicated debug bus.");
1444
1445                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1446                 entry_offset = 0;
1447                 do
1448                 {
1449                         retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1450                         if (retval != ERROR_OK)
1451                                 return retval;
1452                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1453                         if (romentry&0x01)
1454                         {
1455                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1456                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1457                                 uint32_t component_base;
1458                                 unsigned part_num;
1459                                 char *type, *full;
1460
1461                                 component_base = (dbgbase & 0xFFFFF000)
1462                                                 + (romentry & 0xFFFFF000);
1463
1464                                 /* IDs are in last 4K section */
1465
1466
1467                                 retval = mem_ap_read_atomic_u32(dap,
1468                                         component_base + 0xFE0, &c_pid0);
1469                                 if (retval != ERROR_OK)
1470                                         return retval;
1471                                 c_pid0 &= 0xff;
1472                                 retval = mem_ap_read_atomic_u32(dap,
1473                                         component_base + 0xFE4, &c_pid1);
1474                                 if (retval != ERROR_OK)
1475                                         return retval;
1476                                 c_pid1 &= 0xff;
1477                                 retval = mem_ap_read_atomic_u32(dap,
1478                                         component_base + 0xFE8, &c_pid2);
1479                                 if (retval != ERROR_OK)
1480                                         return retval;
1481                                 c_pid2 &= 0xff;
1482                                 retval = mem_ap_read_atomic_u32(dap,
1483                                         component_base + 0xFEC, &c_pid3);
1484                                 if (retval != ERROR_OK)
1485                                         return retval;
1486                                 c_pid3 &= 0xff;
1487                                 retval = mem_ap_read_atomic_u32(dap,
1488                                         component_base + 0xFD0, &c_pid4);
1489                                 if (retval != ERROR_OK)
1490                                         return retval;
1491                                 c_pid4 &= 0xff;
1492
1493                                 retval = mem_ap_read_atomic_u32(dap,
1494                                         component_base + 0xFF0, &c_cid0);
1495                                 if (retval != ERROR_OK)
1496                                         return retval;
1497                                 c_cid0 &= 0xff;
1498                                 retval = mem_ap_read_atomic_u32(dap,
1499                                         component_base + 0xFF4, &c_cid1);
1500                                 if (retval != ERROR_OK)
1501                                         return retval;
1502                                 c_cid1 &= 0xff;
1503                                 retval = mem_ap_read_atomic_u32(dap,
1504                                         component_base + 0xFF8, &c_cid2);
1505                                 if (retval != ERROR_OK)
1506                                         return retval;
1507                                 c_cid2 &= 0xff;
1508                                 retval = mem_ap_read_atomic_u32(dap,
1509                                         component_base + 0xFFC, &c_cid3);
1510                                 if (retval != ERROR_OK)
1511                                         return retval;
1512                                 c_cid3 &= 0xff;
1513
1514
1515                                 command_print(cmd_ctx,
1516                                 "\t\tComponent base address 0x%" PRIx32
1517                                         ", start address 0x%" PRIx32,
1518                                                 component_base,
1519                                 /* component may take multiple 4K pages */
1520                                 component_base - 0x1000*(c_pid4 >> 4));
1521                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1522                                                 (int) (c_cid1 >> 4) & 0xf,
1523                                                 /* See ARM IHI 0029B Table 3-3 */
1524                                                 class_description[(c_cid1 >> 4) & 0xf]);
1525
1526                                 /* CoreSight component? */
1527                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1528                                         uint32_t devtype;
1529                                         unsigned minor;
1530                                         char *major = "Reserved", *subtype = "Reserved";
1531
1532                                         retval = mem_ap_read_atomic_u32(dap,
1533                                                         (component_base & 0xfffff000) | 0xfcc,
1534                                                         &devtype);
1535                                         if (retval != ERROR_OK)
1536                                                 return retval;
1537                                         minor = (devtype >> 4) & 0x0f;
1538                                         switch (devtype & 0x0f) {
1539                                         case 0:
1540                                                 major = "Miscellaneous";
1541                                                 switch (minor) {
1542                                                 case 0:
1543                                                         subtype = "other";
1544                                                         break;
1545                                                 case 4:
1546                                                         subtype = "Validation component";
1547                                                         break;
1548                                                 }
1549                                                 break;
1550                                         case 1:
1551                                                 major = "Trace Sink";
1552                                                 switch (minor) {
1553                                                 case 0:
1554                                                         subtype = "other";
1555                                                         break;
1556                                                 case 1:
1557                                                         subtype = "Port";
1558                                                         break;
1559                                                 case 2:
1560                                                         subtype = "Buffer";
1561                                                         break;
1562                                                 }
1563                                                 break;
1564                                         case 2:
1565                                                 major = "Trace Link";
1566                                                 switch (minor) {
1567                                                 case 0:
1568                                                         subtype = "other";
1569                                                         break;
1570                                                 case 1:
1571                                                         subtype = "Funnel, router";
1572                                                         break;
1573                                                 case 2:
1574                                                         subtype = "Filter";
1575                                                         break;
1576                                                 case 3:
1577                                                         subtype = "FIFO, buffer";
1578                                                         break;
1579                                                 }
1580                                                 break;
1581                                         case 3:
1582                                                 major = "Trace Source";
1583                                                 switch (minor) {
1584                                                 case 0:
1585                                                         subtype = "other";
1586                                                         break;
1587                                                 case 1:
1588                                                         subtype = "Processor";
1589                                                         break;
1590                                                 case 2:
1591                                                         subtype = "DSP";
1592                                                         break;
1593                                                 case 3:
1594                                                         subtype = "Engine/Coprocessor";
1595                                                         break;
1596                                                 case 4:
1597                                                         subtype = "Bus";
1598                                                         break;
1599                                                 }
1600                                                 break;
1601                                         case 4:
1602                                                 major = "Debug Control";
1603                                                 switch (minor) {
1604                                                 case 0:
1605                                                         subtype = "other";
1606                                                         break;
1607                                                 case 1:
1608                                                         subtype = "Trigger Matrix";
1609                                                         break;
1610                                                 case 2:
1611                                                         subtype = "Debug Auth";
1612                                                         break;
1613                                                 }
1614                                                 break;
1615                                         case 5:
1616                                                 major = "Debug Logic";
1617                                                 switch (minor) {
1618                                                 case 0:
1619                                                         subtype = "other";
1620                                                         break;
1621                                                 case 1:
1622                                                         subtype = "Processor";
1623                                                         break;
1624                                                 case 2:
1625                                                         subtype = "DSP";
1626                                                         break;
1627                                                 case 3:
1628                                                         subtype = "Engine/Coprocessor";
1629                                                         break;
1630                                                 }
1631                                                 break;
1632                                         }
1633                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1634                                                         (unsigned) (devtype & 0xff),
1635                                                         major, subtype);
1636                                         /* REVISIT also show 0xfc8 DevId */
1637                                 }
1638
1639                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1640                                         command_print(cmd_ctx,
1641                                                       "\t\tCID3 0%2.2x"
1642                                                         ", CID2 0%2.2x"
1643                                                         ", CID1 0%2.2x"
1644                                                         ", CID0 0%2.2x",
1645                                                         (int) c_cid3,
1646                                                         (int) c_cid2,
1647                                                         (int)c_cid1,
1648                                                         (int)c_cid0);
1649                                 command_print(cmd_ctx,
1650                                 "\t\tPeripheral ID[4..0] = hex "
1651                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1652                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1653                                 (int) c_pid1, (int) c_pid0);
1654
1655                                 /* Part number interpretations are from Cortex
1656                                  * core specs, the CoreSight components TRM
1657                                  * (ARM DDI 0314H), CoreSight System Design
1658                                  * Guide (ARM DGI 0012D) and ETM specs; also
1659                                  * from chip observation (e.g. TI SDTI).
1660                                  */
1661                                 part_num = (c_pid0 & 0xff);
1662                                 part_num |= (c_pid1 & 0x0f) << 8;
1663                                 switch (part_num) {
1664                                 case 0x000:
1665                                         type = "Cortex-M3 NVIC";
1666                                         full = "(Interrupt Controller)";
1667                                         break;
1668                                 case 0x001:
1669                                         type = "Cortex-M3 ITM";
1670                                         full = "(Instrumentation Trace Module)";
1671                                         break;
1672                                 case 0x002:
1673                                         type = "Cortex-M3 DWT";
1674                                         full = "(Data Watchpoint and Trace)";
1675                                         break;
1676                                 case 0x003:
1677                                         type = "Cortex-M3 FBP";
1678                                         full = "(Flash Patch and Breakpoint)";
1679                                         break;
1680                                 case 0x00d:
1681                                         type = "CoreSight ETM11";
1682                                         full = "(Embedded Trace)";
1683                                         break;
1684                                 // case 0x113: what?
1685                                 case 0x120:             /* from OMAP3 memmap */
1686                                         type = "TI SDTI";
1687                                         full = "(System Debug Trace Interface)";
1688                                         break;
1689                                 case 0x343:             /* from OMAP3 memmap */
1690                                         type = "TI DAPCTL";
1691                                         full = "";
1692                                         break;
1693                                 case 0x906:
1694                                         type = "Coresight CTI";
1695                                         full = "(Cross Trigger)";
1696                                         break;
1697                                 case 0x907:
1698                                         type = "Coresight ETB";
1699                                         full = "(Trace Buffer)";
1700                                         break;
1701                                 case 0x908:
1702                                         type = "Coresight CSTF";
1703                                         full = "(Trace Funnel)";
1704                                         break;
1705                                 case 0x910:
1706                                         type = "CoreSight ETM9";
1707                                         full = "(Embedded Trace)";
1708                                         break;
1709                                 case 0x912:
1710                                         type = "Coresight TPIU";
1711                                         full = "(Trace Port Interface Unit)";
1712                                         break;
1713                                 case 0x921:
1714                                         type = "Cortex-A8 ETM";
1715                                         full = "(Embedded Trace)";
1716                                         break;
1717                                 case 0x922:
1718                                         type = "Cortex-A8 CTI";
1719                                         full = "(Cross Trigger)";
1720                                         break;
1721                                 case 0x923:
1722                                         type = "Cortex-M3 TPIU";
1723                                         full = "(Trace Port Interface Unit)";
1724                                         break;
1725                                 case 0x924:
1726                                         type = "Cortex-M3 ETM";
1727                                         full = "(Embedded Trace)";
1728                                         break;
1729                                 case 0x930:
1730                                         type = "Cortex-R4 ETM";
1731                                         full = "(Embedded Trace)";
1732                                         break;
1733                                 case 0xc08:
1734                                         type = "Cortex-A8 Debug";
1735                                         full = "(Debug Unit)";
1736                                         break;
1737                                 default:
1738                                         type = "-*- unrecognized -*-";
1739                                         full = "";
1740                                         break;
1741                                 }
1742                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1743                                                 type, full);
1744                         }
1745                         else
1746                         {
1747                                 if (romentry)
1748                                         command_print(cmd_ctx, "\t\tComponent not present");
1749                                 else
1750                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1751                         }
1752                         entry_offset += 4;
1753                 } while (romentry > 0);
1754         }
1755         else
1756         {
1757                 command_print(cmd_ctx, "\tNo ROM table present");
1758         }
1759         dap_ap_select(dap, ap_old);
1760
1761         return ERROR_OK;
1762 }
1763
1764 COMMAND_HANDLER(handle_dap_info_command)
1765 {
1766         struct target *target = get_current_target(CMD_CTX);
1767         struct arm *arm = target_to_arm(target);
1768         struct adiv5_dap *dap = arm->dap;
1769         uint32_t apsel;
1770
1771         switch (CMD_ARGC) {
1772         case 0:
1773                 apsel = dap->apsel;
1774                 break;
1775         case 1:
1776                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1777                 break;
1778         default:
1779                 return ERROR_COMMAND_SYNTAX_ERROR;
1780         }
1781
1782         return dap_info_command(CMD_CTX, dap, apsel);
1783 }
1784
1785 COMMAND_HANDLER(dap_baseaddr_command)
1786 {
1787         struct target *target = get_current_target(CMD_CTX);
1788         struct arm *arm = target_to_arm(target);
1789         struct adiv5_dap *dap = arm->dap;
1790
1791         uint32_t apsel, baseaddr;
1792         int retval;
1793
1794         switch (CMD_ARGC) {
1795         case 0:
1796                 apsel = dap->apsel;
1797                 break;
1798         case 1:
1799                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1800                 /* AP address is in bits 31:24 of DP_SELECT */
1801                 if (apsel >= 256)
1802                         return ERROR_INVALID_ARGUMENTS;
1803                 break;
1804         default:
1805                 return ERROR_COMMAND_SYNTAX_ERROR;
1806         }
1807
1808         dap_ap_select(dap, apsel);
1809
1810         /* NOTE:  assumes we're talking to a MEM-AP, which
1811          * has a base address.  There are other kinds of AP,
1812          * though they're not common for now.  This should
1813          * use the ID register to verify it's a MEM-AP.
1814          */
1815         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1816         if (retval != ERROR_OK)
1817                 return retval;
1818         retval = dap_run(dap);
1819         if (retval != ERROR_OK)
1820                 return retval;
1821
1822         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1823
1824         return retval;
1825 }
1826
1827 COMMAND_HANDLER(dap_memaccess_command)
1828 {
1829         struct target *target = get_current_target(CMD_CTX);
1830         struct arm *arm = target_to_arm(target);
1831         struct adiv5_dap *dap = arm->dap;
1832
1833         uint32_t memaccess_tck;
1834
1835         switch (CMD_ARGC) {
1836         case 0:
1837                 memaccess_tck = dap->memaccess_tck;
1838                 break;
1839         case 1:
1840                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1841                 break;
1842         default:
1843                 return ERROR_COMMAND_SYNTAX_ERROR;
1844         }
1845         dap->memaccess_tck = memaccess_tck;
1846
1847         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1848                         dap->memaccess_tck);
1849
1850         return ERROR_OK;
1851 }
1852
1853 COMMAND_HANDLER(dap_apsel_command)
1854 {
1855         struct target *target = get_current_target(CMD_CTX);
1856         struct arm *arm = target_to_arm(target);
1857         struct adiv5_dap *dap = arm->dap;
1858
1859         uint32_t apsel, apid;
1860         int retval;
1861
1862         switch (CMD_ARGC) {
1863         case 0:
1864                 apsel = 0;
1865                 break;
1866         case 1:
1867                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1868                 /* AP address is in bits 31:24 of DP_SELECT */
1869                 if (apsel >= 256)
1870                         return ERROR_INVALID_ARGUMENTS;
1871                 break;
1872         default:
1873                 return ERROR_COMMAND_SYNTAX_ERROR;
1874         }
1875
1876         dap->apsel = apsel;
1877         dap_ap_select(dap, apsel);
1878
1879         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1880         if (retval != ERROR_OK)
1881                 return retval;
1882         retval = dap_run(dap);
1883         if (retval != ERROR_OK)
1884                 return retval;
1885
1886         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1887                         apsel, apid);
1888
1889         return retval;
1890 }
1891
1892 COMMAND_HANDLER(dap_apid_command)
1893 {
1894         struct target *target = get_current_target(CMD_CTX);
1895         struct arm *arm = target_to_arm(target);
1896         struct adiv5_dap *dap = arm->dap;
1897
1898         uint32_t apsel, apid;
1899         int retval;
1900
1901         switch (CMD_ARGC) {
1902         case 0:
1903                 apsel = dap->apsel;
1904                 break;
1905         case 1:
1906                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1907                 /* AP address is in bits 31:24 of DP_SELECT */
1908                 if (apsel >= 256)
1909                         return ERROR_INVALID_ARGUMENTS;
1910                 break;
1911         default:
1912                 return ERROR_COMMAND_SYNTAX_ERROR;
1913         }
1914
1915         dap_ap_select(dap, apsel);
1916
1917         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1918         if (retval != ERROR_OK)
1919                 return retval;
1920         retval = dap_run(dap);
1921         if (retval != ERROR_OK)
1922                 return retval;
1923
1924         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1925
1926         return retval;
1927 }
1928
1929 static const struct command_registration dap_commands[] = {
1930         {
1931                 .name = "info",
1932                 .handler = handle_dap_info_command,
1933                 .mode = COMMAND_EXEC,
1934                 .help = "display ROM table for MEM-AP "
1935                         "(default currently selected AP)",
1936                 .usage = "[ap_num]",
1937         },
1938         {
1939                 .name = "apsel",
1940                 .handler = dap_apsel_command,
1941                 .mode = COMMAND_EXEC,
1942                 .help = "Set the currently selected AP (default 0) "
1943                         "and display the result",
1944                 .usage = "[ap_num]",
1945         },
1946         {
1947                 .name = "apid",
1948                 .handler = dap_apid_command,
1949                 .mode = COMMAND_EXEC,
1950                 .help = "return ID register from AP "
1951                         "(default currently selected AP)",
1952                 .usage = "[ap_num]",
1953         },
1954         {
1955                 .name = "baseaddr",
1956                 .handler = dap_baseaddr_command,
1957                 .mode = COMMAND_EXEC,
1958                 .help = "return debug base address from MEM-AP "
1959                         "(default currently selected AP)",
1960                 .usage = "[ap_num]",
1961         },
1962         {
1963                 .name = "memaccess",
1964                 .handler = dap_memaccess_command,
1965                 .mode = COMMAND_EXEC,
1966                 .help = "set/get number of extra tck for MEM-AP memory "
1967                         "bus access [0-255]",
1968                 .usage = "[cycles]",
1969         },
1970         COMMAND_REGISTRATION_DONE
1971 };
1972
1973 const struct command_registration dap_command_handlers[] = {
1974         {
1975                 .name = "dap",
1976                 .mode = COMMAND_EXEC,
1977                 .help = "DAP command group",
1978                 .chain = dap_commands,
1979         },
1980         COMMAND_REGISTRATION_DONE
1981 };
1982
1983