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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  77
  78 /*
  79         uint32_t tar_block_size(uint32_t address)
  80         Return the largest block starting at address that does not cross a tar block size alignment boundary
  81 */
  82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  83 {
  84         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  85 }
  86
  87 /***************************************************************************
  88  *                                                                         *
  89  * DP and MEM-AP  register access  through APACC and DPACC                 *
  90  *                                                                         *
  91 ***************************************************************************/
  92
  93 /**
  94  * Select one of the APs connected to the specified DAP.  The
  95  * selection is implicitly used with future AP transactions.
  96  * This is a NOP if the specified AP is already selected.
  97  *
  98  * @param dap The DAP
  99  * @param apsel Number of the AP to (implicitly) use with further
 100  *      transactions.  This normally identifies a MEM-AP.
 101  */
 102 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 103 {
 104         uint32_t new_ap = (ap << 24) & 0xFF000000;
 105
 106         if (new_ap != dap->ap_current) {
 107                 dap->ap_current = new_ap;
 108                 /* Switching AP invalidates cached values.
 109                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 110                  */
 111                 dap->ap_bank_value = -1;
 112                 dap->ap_csw_value = -1;
 113                 dap->ap_tar_value = -1;
 114         }
 115 }
 116
 117 /**
 118  * Queue transactions setting up transfer parameters for the
 119  * currently selected MEM-AP.
 120  *
 121  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 122  * initiate data reads or writes using memory or peripheral addresses.
 123  * If the CSW is configured for it, the TAR may be automatically
 124  * incremented after each transfer.
 125  *
 126  * @todo Rename to reflect it being specifically a MEM-AP function.
 127  *
 128  * @param dap The DAP connected to the MEM-AP.
 129  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 130  *      matches the cached value, the register is not changed.
 131  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 132  *      matches the cached address, the register is not changed.
 133  *
 134  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 135  */
 136 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 137 {
 138         int retval;
 139
 140         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 141         if (csw != dap->ap_csw_value) {
 142                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 143                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 144                 if (retval != ERROR_OK)
 145                         return retval;
 146                 dap->ap_csw_value = csw;
 147         }
 148         if (tar != dap->ap_tar_value) {
 149                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 150                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 151                 if (retval != ERROR_OK)
 152                         return retval;
 153                 dap->ap_tar_value = tar;
 154         }
 155         /* Disable TAR cache when autoincrementing */
 156         if (csw & CSW_ADDRINC_MASK)
 157                 dap->ap_tar_value = -1;
 158         return ERROR_OK;
 159 }
 160
 161 /**
 162  * Asynchronous (queued) read of a word from memory or a system register.
 163  *
 164  * @param dap The DAP connected to the MEM-AP performing the read.
 165  * @param address Address of the 32-bit word to read; it must be
 166  *      readable by the currently selected MEM-AP.
 167  * @param value points to where the word will be stored when the
 168  *      transaction queue is flushed (assuming no errors).
 169  *
 170  * @return ERROR_OK for success.  Otherwise a fault code.
 171  */
 172 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 173                 uint32_t *value)
 174 {
 175         int retval;
 176
 177         /* Use banked addressing (REG_BDx) to avoid some link traffic
 178          * (updating TAR) when reading several consecutive addresses.
 179          */
 180         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 181                         address & 0xFFFFFFF0);
 182         if (retval != ERROR_OK)
 183                 return retval;
 184
 185         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 186 }
 187
 188 /**
 189  * Synchronous read of a word from memory or a system register.
 190  * As a side effect, this flushes any queued transactions.
 191  *
 192  * @param dap The DAP connected to the MEM-AP performing the read.
 193  * @param address Address of the 32-bit word to read; it must be
 194  *      readable by the currently selected MEM-AP.
 195  * @param value points to where the result will be stored.
 196  *
 197  * @return ERROR_OK for success; *value holds the result.
 198  * Otherwise a fault code.
 199  */
 200 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 201                 uint32_t *value)
 202 {
 203         int retval;
 204
 205         retval = mem_ap_read_u32(dap, address, value);
 206         if (retval != ERROR_OK)
 207                 return retval;
 208
 209         return dap_run(dap);
 210 }
 211
 212 /**
 213  * Asynchronous (queued) write of a word to memory or a system register.
 214  *
 215  * @param dap The DAP connected to the MEM-AP.
 216  * @param address Address to be written; it must be writable by
 217  *      the currently selected MEM-AP.
 218  * @param value Word that will be written to the address when transaction
 219  *      queue is flushed (assuming no errors).
 220  *
 221  * @return ERROR_OK for success.  Otherwise a fault code.
 222  */
 223 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 224                 uint32_t value)
 225 {
 226         int retval;
 227
 228         /* Use banked addressing (REG_BDx) to avoid some link traffic
 229          * (updating TAR) when writing several consecutive addresses.
 230          */
 231         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 232                         address & 0xFFFFFFF0);
 233         if (retval != ERROR_OK)
 234                 return retval;
 235
 236         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 237                         value);
 238 }
 239
 240 /**
 241  * Synchronous write of a word to memory or a system register.
 242  * As a side effect, this flushes any queued transactions.
 243  *
 244  * @param dap The DAP connected to the MEM-AP.
 245  * @param address Address to be written; it must be writable by
 246  *      the currently selected MEM-AP.
 247  * @param value Word that will be written.
 248  *
 249  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 250  */
 251 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 252                 uint32_t value)
 253 {
 254         int retval = mem_ap_write_u32(dap, address, value);
 255
 256         if (retval != ERROR_OK)
 257                 return retval;
 258
 259         return dap_run(dap);
 260 }
 261
 262 /*****************************************************************************
 263 *                                                                            *
 264 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 265 *                                                                            *
 266 * Write a buffer in target order (little endian)                             *
 267 *                                                                            *
 268 *****************************************************************************/
 269 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 270 {
 271         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 272         uint32_t adr = address;
 273         const uint8_t *pBuffer = buffer;
 274
 275         count >>= 2;
 276         wcount = count;
 277
 278         /* if we have an unaligned access - reorder data */
 279         if (adr & 0x3u) {
 280                 for (writecount = 0; writecount < count; writecount++) {
 281                         int i;
 282                         uint32_t outvalue;
 283                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 284
 285                         for (i = 0; i < 4; i++) {
 286                                 *((uint8_t *)pBuffer + (adr & 0x3)) = outvalue;
 287                                 outvalue >>= 8;
 288                                 adr++;
 289                         }
 290                         pBuffer += sizeof(uint32_t);
 291                 }
 292         }
 293
 294         while (wcount > 0) {
 295                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 296                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 297                 if (wcount < blocksize)
 298                         blocksize = wcount;
 299
 300                 /* handle unaligned data at 4k boundary */
 301                 if (blocksize == 0)
 302                         blocksize = 1;
 303
 304                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 305                 if (retval != ERROR_OK)
 306                         return retval;
 307
 308                 for (writecount = 0; writecount < blocksize; writecount++) {
 309                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 310                                 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
 311                         if (retval != ERROR_OK)
 312                                 break;
 313                 }
 314
 315                 retval = dap_run(dap);
 316                 if (retval == ERROR_OK) {
 317                         wcount = wcount - blocksize;
 318                         address = address + 4 * blocksize;
 319                         buffer = buffer + 4 * blocksize;
 320                 } else
 321                         errorcount++;
 322
 323                 if (errorcount > 1) {
 324                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 325                         return retval;
 326                 }
 327         }
 328
 329         return retval;
 330 }
 331
 332 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 333                 const uint8_t *buffer, int count, uint32_t address)
 334 {
 335         int retval = ERROR_OK;
 336         int wcount, blocksize, writecount, i;
 337
 338         wcount = count >> 1;
 339
 340         while (wcount > 0) {
 341                 int nbytes;
 342
 343                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 344                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 345
 346                 if (wcount < blocksize)
 347                         blocksize = wcount;
 348
 349                 /* handle unaligned data at 4k boundary */
 350                 if (blocksize == 0)
 351                         blocksize = 1;
 352
 353                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 354                 if (retval != ERROR_OK)
 355                         return retval;
 356                 writecount = blocksize;
 357
 358                 do {
 359                         nbytes = MIN((writecount << 1), 4);
 360
 361                         if (nbytes < 4) {
 362                                 retval = mem_ap_write_buf_u16(dap, buffer,
 363                                                 nbytes, address);
 364                                 if (retval != ERROR_OK) {
 365                                         LOG_WARNING("Block write error address "
 366                                                 "0x%" PRIx32 ", count 0x%x",
 367                                                 address, count);
 368                                         return retval;
 369                                 }
 370
 371                                 address += nbytes >> 1;
 372                         } else {
 373                                 uint32_t outvalue;
 374                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 375
 376                                 for (i = 0; i < nbytes; i++) {
 377                                         *((uint8_t *)buffer + (address & 0x3)) = outvalue;
 378                                         outvalue >>= 8;
 379                                         address++;
 380                                 }
 381
 382                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 383                                 retval = dap_queue_ap_write(dap,
 384                                                 AP_REG_DRW, outvalue);
 385                                 if (retval != ERROR_OK)
 386                                         break;
 387
 388                                 retval = dap_run(dap);
 389                                 if (retval != ERROR_OK) {
 390                                         LOG_WARNING("Block write error address "
 391                                                 "0x%" PRIx32 ", count 0x%x",
 392                                                 address, count);
 393                                         return retval;
 394                                 }
 395                         }
 396
 397                         buffer += nbytes >> 1;
 398                         writecount -= nbytes >> 1;
 399
 400                 } while (writecount);
 401                 wcount -= blocksize;
 402         }
 403
 404         return retval;
 405 }
 406
 407 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 408 {
 409         int retval = ERROR_OK;
 410
 411         if (count >= 4)
 412                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 413
 414         while (count > 0) {
 415                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 416                 if (retval != ERROR_OK)
 417                         return retval;
 418                 uint16_t svalue;
 419                 memcpy(&svalue, buffer, sizeof(uint16_t));
 420                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 421                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 422                 if (retval != ERROR_OK)
 423                         break;
 424
 425                 retval = dap_run(dap);
 426                 if (retval != ERROR_OK)
 427                         break;
 428
 429                 count -= 2;
 430                 address += 2;
 431                 buffer += 2;
 432         }
 433
 434         return retval;
 435 }
 436
 437 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 438                 const uint8_t *buffer, int count, uint32_t address)
 439 {
 440         int retval = ERROR_OK;
 441         int wcount, blocksize, writecount, i;
 442
 443         wcount = count;
 444
 445         while (wcount > 0) {
 446                 int nbytes;
 447
 448                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 449                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 450
 451                 if (wcount < blocksize)
 452                         blocksize = wcount;
 453
 454                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 455                 if (retval != ERROR_OK)
 456                         return retval;
 457                 writecount = blocksize;
 458
 459                 do {
 460                         nbytes = MIN(writecount, 4);
 461
 462                         if (nbytes < 4) {
 463                                 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
 464                                 if (retval != ERROR_OK) {
 465                                         LOG_WARNING("Block write error address "
 466                                                 "0x%" PRIx32 ", count 0x%x",
 467                                                 address, count);
 468                                         return retval;
 469                                 }
 470
 471                                 address += nbytes;
 472                         } else {
 473                                 uint32_t outvalue;
 474                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 475
 476                                 for (i = 0; i < nbytes; i++) {
 477                                         *((uint8_t *)buffer + (address & 0x3)) = outvalue;
 478                                         outvalue >>= 8;
 479                                         address++;
 480                                 }
 481
 482                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 483                                 retval = dap_queue_ap_write(dap,
 484                                                 AP_REG_DRW, outvalue);
 485                                 if (retval != ERROR_OK)
 486                                         break;
 487
 488                                 retval = dap_run(dap);
 489                                 if (retval != ERROR_OK) {
 490                                         LOG_WARNING("Block write error address "
 491                                                 "0x%" PRIx32 ", count 0x%x",
 492                                                 address, count);
 493                                         return retval;
 494                                 }
 495                         }
 496
 497                         buffer += nbytes;
 498                         writecount -= nbytes;
 499
 500                 } while (writecount);
 501                 wcount -= blocksize;
 502         }
 503
 504         return retval;
 505 }
 506
 507 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 508 {
 509         int retval = ERROR_OK;
 510
 511         if (count >= 4)
 512                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 513
 514         while (count > 0) {
 515                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 516                 if (retval != ERROR_OK)
 517                         return retval;
 518                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 519                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 520                 if (retval != ERROR_OK)
 521                         break;
 522
 523                 retval = dap_run(dap);
 524                 if (retval != ERROR_OK)
 525                         break;
 526
 527                 count--;
 528                 address++;
 529                 buffer++;
 530         }
 531
 532         return retval;
 533 }
 534
 535 /* FIXME don't import ... this is a temporary workaround for the
 536  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 537  */
 538 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 539                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 540                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 541
 542 /**
 543  * Synchronously read a block of 32-bit words into a buffer
 544  * @param dap The DAP connected to the MEM-AP.
 545  * @param buffer where the words will be stored (in host byte order).
 546  * @param count How many words to read.
 547  * @param address Memory address from which to read words; all the
 548  *      words must be readable by the currently selected MEM-AP.
 549  */
 550 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 551                 int count, uint32_t address)
 552 {
 553         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 554         uint32_t adr = address;
 555         uint8_t *pBuffer = buffer;
 556
 557         count >>= 2;
 558         wcount = count;
 559
 560         while (wcount > 0) {
 561                 /* Adjust to read blocks within boundaries aligned to the
 562                  * TAR autoincrement size (at least 2^10).  Autoincrement
 563                  * mode avoids an extra per-word roundtrip to update TAR.
 564                  */
 565                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 566                                 address);
 567                 if (wcount < blocksize)
 568                         blocksize = wcount;
 569
 570                 /* handle unaligned data at 4k boundary */
 571                 if (blocksize == 0)
 572                         blocksize = 1;
 573
 574                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 575                                 address);
 576                 if (retval != ERROR_OK)
 577                         return retval;
 578
 579                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 580                  * so this routine becomes transport-neutral.  Be careful
 581                  * not to cause performance problems with JTAG; would it
 582                  * suffice to loop over dap_queue_ap_read(), or would that
 583                  * be slower when JTAG is the chosen transport?
 584                  */
 585
 586                 /* Scan out first read */
 587                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 588                                 DPAP_READ, 0, NULL, NULL);
 589                 if (retval != ERROR_OK)
 590                         return retval;
 591                 for (readcount = 0; readcount < blocksize - 1; readcount++) {
 592                         /* Scan out next read; scan in posted value for the
 593                          * previous one.  Assumes read is acked "OK/FAULT",
 594                          * and CTRL_STAT says that meant "OK".
 595                          */
 596                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 597                                         DPAP_READ, 0, buffer + 4 * readcount,
 598                                         &dap->ack);
 599                         if (retval != ERROR_OK)
 600                                 return retval;
 601                 }
 602
 603                 /* Scan in last posted value; RDBUFF has no other effect,
 604                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 605                  */
 606                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 607                                 DPAP_READ, 0, buffer + 4 * readcount,
 608                                 &dap->ack);
 609                 if (retval != ERROR_OK)
 610                         return retval;
 611
 612                 retval = dap_run(dap);
 613                 if (retval != ERROR_OK) {
 614                         errorcount++;
 615                         if (errorcount <= 1) {
 616                                 /* try again */
 617                                 continue;
 618                         }
 619                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 620                         return retval;
 621                 }
 622                 wcount = wcount - blocksize;
 623                 address += 4 * blocksize;
 624                 buffer += 4 * blocksize;
 625         }
 626
 627         /* if we have an unaligned access - reorder data */
 628         if (adr & 0x3u) {
 629                 for (readcount = 0; readcount < count; readcount++) {
 630                         int i;
 631                         uint32_t data;
 632                         memcpy(&data, pBuffer, sizeof(uint32_t));
 633
 634                         for (i = 0; i < 4; i++) {
 635                                 *((uint8_t *)pBuffer) =
 636                                                 (data >> 8 * (adr & 0x3));
 637                                 pBuffer++;
 638                                 adr++;
 639                         }
 640                 }
 641         }
 642
 643         return retval;
 644 }
 645
 646 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 647                 uint8_t *buffer, int count, uint32_t address)
 648 {
 649         uint32_t invalue;
 650         int retval = ERROR_OK;
 651         int wcount, blocksize, readcount, i;
 652
 653         wcount = count >> 1;
 654
 655         while (wcount > 0) {
 656                 int nbytes;
 657
 658                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 659                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 660                 if (wcount < blocksize)
 661                         blocksize = wcount;
 662
 663                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 664                 if (retval != ERROR_OK)
 665                         return retval;
 666
 667                 /* handle unaligned data at 4k boundary */
 668                 if (blocksize == 0)
 669                         blocksize = 1;
 670                 readcount = blocksize;
 671
 672                 do {
 673                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 674                         if (retval != ERROR_OK)
 675                                 return retval;
 676                         retval = dap_run(dap);
 677                         if (retval != ERROR_OK) {
 678                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 679                                 return retval;
 680                         }
 681
 682                         nbytes = MIN((readcount << 1), 4);
 683
 684                         for (i = 0; i < nbytes; i++) {
 685                                 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
 686                                 buffer++;
 687                                 address++;
 688                         }
 689
 690                         readcount -= (nbytes >> 1);
 691                 } while (readcount);
 692                 wcount -= blocksize;
 693         }
 694
 695         return retval;
 696 }
 697
 698 /**
 699  * Synchronously read a block of 16-bit halfwords into a buffer
 700  * @param dap The DAP connected to the MEM-AP.
 701  * @param buffer where the halfwords will be stored (in host byte order).
 702  * @param count How many halfwords to read.
 703  * @param address Memory address from which to read words; all the
 704  *      words must be readable by the currently selected MEM-AP.
 705  */
 706 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 707                 int count, uint32_t address)
 708 {
 709         uint32_t invalue, i;
 710         int retval = ERROR_OK;
 711
 712         if (count >= 4)
 713                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 714
 715         while (count > 0) {
 716                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 717                 if (retval != ERROR_OK)
 718                         return retval;
 719                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 720                 if (retval != ERROR_OK)
 721                         break;
 722
 723                 retval = dap_run(dap);
 724                 if (retval != ERROR_OK)
 725                         break;
 726
 727                 if (address & 0x1) {
 728                         for (i = 0; i < 2; i++) {
 729                                 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
 730                                 buffer++;
 731                                 address++;
 732                         }
 733                 } else {
 734                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 735                         memcpy(buffer, &svalue, sizeof(uint16_t));
 736                         address += 2;
 737                         buffer += 2;
 738                 }
 739                 count -= 2;
 740         }
 741
 742         return retval;
 743 }
 744
 745 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 746  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 747  *
 748  * The solution is to arrange for a large out/in scan in this loop and
 749  * and convert data afterwards.
 750  */
 751 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 752                 uint8_t *buffer, int count, uint32_t address)
 753 {
 754         uint32_t invalue;
 755         int retval = ERROR_OK;
 756         int wcount, blocksize, readcount, i;
 757
 758         wcount = count;
 759
 760         while (wcount > 0) {
 761                 int nbytes;
 762
 763                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 764                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 765
 766                 if (wcount < blocksize)
 767                         blocksize = wcount;
 768
 769                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 770                 if (retval != ERROR_OK)
 771                         return retval;
 772                 readcount = blocksize;
 773
 774                 do {
 775                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 776                         if (retval != ERROR_OK)
 777                                 return retval;
 778                         retval = dap_run(dap);
 779                         if (retval != ERROR_OK) {
 780                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 781                                 return retval;
 782                         }
 783
 784                         nbytes = MIN(readcount, 4);
 785
 786                         for (i = 0; i < nbytes; i++) {
 787                                 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
 788                                 buffer++;
 789                                 address++;
 790                         }
 791
 792                         readcount -= nbytes;
 793                 } while (readcount);
 794                 wcount -= blocksize;
 795         }
 796
 797         return retval;
 798 }
 799
 800 /**
 801  * Synchronously read a block of bytes into a buffer
 802  * @param dap The DAP connected to the MEM-AP.
 803  * @param buffer where the bytes will be stored.
 804  * @param count How many bytes to read.
 805  * @param address Memory address from which to read data; all the
 806  *      data must be readable by the currently selected MEM-AP.
 807  */
 808 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 809                 int count, uint32_t address)
 810 {
 811         uint32_t invalue;
 812         int retval = ERROR_OK;
 813
 814         if (count >= 4)
 815                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 816
 817         while (count > 0) {
 818                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 819                 if (retval != ERROR_OK)
 820                         return retval;
 821                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 822                 if (retval != ERROR_OK)
 823                         return retval;
 824                 retval = dap_run(dap);
 825                 if (retval != ERROR_OK)
 826                         break;
 827
 828                 *((uint8_t *)buffer) = (invalue >> 8 * (address & 0x3));
 829                 count--;
 830                 address++;
 831                 buffer++;
 832         }
 833
 834         return retval;
 835 }
 836
 837 /*--------------------------------------------------------------------*/
 838 /*          Wrapping function with selection of AP                    */
 839 /*--------------------------------------------------------------------*/
 840 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 841                 uint32_t address, uint32_t *value)
 842 {
 843         dap_ap_select(swjdp, ap);
 844         return mem_ap_read_u32(swjdp, address, value);
 845 }
 846
 847 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 848                 uint32_t address, uint32_t value)
 849 {
 850         dap_ap_select(swjdp, ap);
 851         return mem_ap_write_u32(swjdp, address, value);
 852 }
 853
 854 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 855                 uint32_t address, uint32_t *value)
 856 {
 857         dap_ap_select(swjdp, ap);
 858         return mem_ap_read_atomic_u32(swjdp, address, value);
 859 }
 860
 861 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 862                 uint32_t address, uint32_t value)
 863 {
 864         dap_ap_select(swjdp, ap);
 865         return mem_ap_write_atomic_u32(swjdp, address, value);
 866 }
 867
 868 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 869                 uint8_t *buffer, int count, uint32_t address)
 870 {
 871         dap_ap_select(swjdp, ap);
 872         return mem_ap_read_buf_u8(swjdp, buffer, count, address);
 873 }
 874
 875 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 876                 uint8_t *buffer, int count, uint32_t address)
 877 {
 878         dap_ap_select(swjdp, ap);
 879         return mem_ap_read_buf_u16(swjdp, buffer, count, address);
 880 }
 881
 882 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 883                 uint8_t *buffer, int count, uint32_t address)
 884 {
 885         dap_ap_select(swjdp, ap);
 886         return mem_ap_read_buf_u32(swjdp, buffer, count, address);
 887 }
 888
 889 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 890                 const uint8_t *buffer, int count, uint32_t address)
 891 {
 892         dap_ap_select(swjdp, ap);
 893         return mem_ap_write_buf_u8(swjdp, buffer, count, address);
 894 }
 895
 896 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 897                 const uint8_t *buffer, int count, uint32_t address)
 898 {
 899         dap_ap_select(swjdp, ap);
 900         return mem_ap_write_buf_u16(swjdp, buffer, count, address);
 901 }
 902
 903 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 904                 const uint8_t *buffer, int count, uint32_t address)
 905 {
 906         dap_ap_select(swjdp, ap);
 907         return mem_ap_write_buf_u32(swjdp, buffer, count, address);
 908 }
 909
 910 #define MDM_REG_STAT            0x00
 911 #define MDM_REG_CTRL            0x04
 912 #define MDM_REG_ID              0xfc
 913
 914 #define MDM_STAT_FMEACK         (1<<0)
 915 #define MDM_STAT_FREADY         (1<<1)
 916 #define MDM_STAT_SYSSEC         (1<<2)
 917 #define MDM_STAT_SYSRES         (1<<3)
 918 #define MDM_STAT_FMEEN          (1<<5)
 919 #define MDM_STAT_BACKDOOREN     (1<<6)
 920 #define MDM_STAT_LPEN           (1<<7)
 921 #define MDM_STAT_VLPEN          (1<<8)
 922 #define MDM_STAT_LLSMODEXIT     (1<<9)
 923 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 924 #define MDM_STAT_CORE_HALTED    (1<<16)
 925 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 926 #define MDM_STAT_CORESLEEPING   (1<<18)
 927
 928 #define MEM_CTRL_FMEIP          (1<<0)
 929 #define MEM_CTRL_DBG_DIS        (1<<1)
 930 #define MEM_CTRL_DBG_REQ        (1<<2)
 931 #define MEM_CTRL_SYS_RES_REQ    (1<<3)
 932 #define MEM_CTRL_CORE_HOLD_RES  (1<<4)
 933 #define MEM_CTRL_VLLSX_DBG_REQ  (1<<5)
 934 #define MEM_CTRL_VLLSX_DBG_ACK  (1<<6)
 935 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
 936
 937 /**
 938  *
 939  */
 940 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
 941 {
 942         uint32_t val;
 943         int retval;
 944         enum reset_types jtag_reset_config = jtag_get_reset_config();
 945
 946         dap_ap_select(dap, 1);
 947
 948         /* first check mdm-ap id register */
 949         retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
 950         if (retval != ERROR_OK)
 951                 return retval;
 952         dap_run(dap);
 953
 954         if (val != 0x001C0000) {
 955                 LOG_DEBUG("id doesn't match %08X != 0x001C0000", val);
 956                 dap_ap_select(dap, 0);
 957                 return ERROR_FAIL;
 958         }
 959
 960         /* read and parse status register
 961          * it's important that the device is out of
 962          * reset here
 963          */
 964         retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 965         if (retval != ERROR_OK)
 966                 return retval;
 967         dap_run(dap);
 968
 969         LOG_DEBUG("MDM_REG_STAT %08X", val);
 970
 971         if ((val & (MDM_STAT_SYSSEC|MDM_STAT_FREADY)) != (MDM_STAT_FREADY)) {
 972                 LOG_DEBUG("MDMAP: system is secured, masserase needed");
 973
 974                 if (!(val & MDM_STAT_FMEEN))
 975                         LOG_DEBUG("MDMAP: masserase is disabled");
 976                 else {
 977                         /* we need to assert reset */
 978                         if (jtag_reset_config & RESET_HAS_SRST) {
 979                                 /* default to asserting srst */
 980                                 if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 981                                         jtag_add_reset(1, 1);
 982                                 else
 983                                         jtag_add_reset(0, 1);
 984                         } else {
 985                                 LOG_DEBUG("SRST not configured");
 986                                 dap_ap_select(dap, 0);
 987                                 return ERROR_FAIL;
 988                         }
 989
 990                         while (1) {
 991                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
 992                                 if (retval != ERROR_OK)
 993                                         return retval;
 994                                 dap_run(dap);
 995                                 /* read status register and wait for ready */
 996                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 997                                 if (retval != ERROR_OK)
 998                                         return retval;
 999                                 dap_run(dap);
1000                                 LOG_DEBUG("MDM_REG_STAT %08X", val);
1001
1002                                 if ((val & 1))
1003                                         break;
1004                         }
1005
1006                         while (1) {
1007                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
1008                                 if (retval != ERROR_OK)
1009                                         return retval;
1010                                 dap_run(dap);
1011                                 /* read status register */
1012                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
1013                                 if (retval != ERROR_OK)
1014                                         return retval;
1015                                 dap_run(dap);
1016                                 LOG_DEBUG("MDM_REG_STAT %08X", val);
1017                                 /* read control register and wait for ready */
1018                                 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
1019                                 if (retval != ERROR_OK)
1020                                         return retval;
1021                                 dap_run(dap);
1022                                 LOG_DEBUG("MDM_REG_CTRL %08X", val);
1023
1024                                 if (val == 0x00)
1025                                         break;
1026                         }
1027                 }
1028         }
1029
1030         dap_ap_select(dap, 0);
1031
1032         return ERROR_OK;
1033 }
1034
1035 /** */
1036 struct dap_syssec_filter {
1037         /** */
1038         uint32_t idcode;
1039         /** */
1040         int (*dap_init)(struct adiv5_dap *dap);
1041 };
1042
1043 /** */
1044 static struct dap_syssec_filter dap_syssec_filter_data[] = {
1045         { 0x4BA00477, dap_syssec_kinetis_mdmap }
1046 };
1047
1048 /**
1049  *
1050  */
1051 int dap_syssec(struct adiv5_dap *dap)
1052 {
1053         unsigned int i;
1054         struct jtag_tap *tap;
1055
1056         for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
1057                 tap = dap->jtag_info->tap;
1058
1059                 while (tap != NULL) {
1060                         if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
1061                                 LOG_DEBUG("DAP: mdmap_init for idcode: %08x", tap->idcode);
1062                                 dap_syssec_filter_data[i].dap_init(dap);
1063                         }
1064                         tap = tap->next_tap;
1065                 }
1066         }
1067
1068         return ERROR_OK;
1069 }
1070
1071 /*--------------------------------------------------------------------------*/
1072
1073
1074 /* FIXME don't import ... just initialize as
1075  * part of DAP transport setup
1076 */
1077 extern const struct dap_ops jtag_dp_ops;
1078
1079 /*--------------------------------------------------------------------------*/
1080
1081 /**
1082  * Initialize a DAP.  This sets up the power domains, prepares the DP
1083  * for further use, and arranges to use AP #0 for all AP operations
1084  * until dap_ap-select() changes that policy.
1085  *
1086  * @param dap The DAP being initialized.
1087  *
1088  * @todo Rename this.  We also need an initialization scheme which account
1089  * for SWD transports not just JTAG; that will need to address differences
1090  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1091  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1092  */
1093 int ahbap_debugport_init(struct adiv5_dap *dap)
1094 {
1095         uint32_t ctrlstat;
1096         int cnt = 0;
1097         int retval;
1098
1099         LOG_DEBUG(" ");
1100
1101         /* test for initialized low level jtag hardware
1102          * this always fails for stlink hardware
1103          */
1104         if (!dap->jtag_info) {
1105                 LOG_DEBUG("No low level jtag hardware found");
1106                 return ERROR_OK;
1107         }
1108
1109         /* JTAG-DP or SWJ-DP, in JTAG mode
1110          * ... for SWD mode this is patched as part
1111          * of link switchover
1112          */
1113         if (!dap->ops)
1114                 dap->ops = &jtag_dp_ops;
1115
1116         /* Default MEM-AP setup.
1117          *
1118          * REVISIT AP #0 may be an inappropriate default for this.
1119          * Should we probe, or take a hint from the caller?
1120          * Presumably we can ignore the possibility of multiple APs.
1121          */
1122         dap->ap_current = !0;
1123         dap_ap_select(dap, 0);
1124
1125         /* DP initialization */
1126
1127         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1128         if (retval != ERROR_OK)
1129                 return retval;
1130
1131         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
1132         if (retval != ERROR_OK)
1133                 return retval;
1134
1135         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1136         if (retval != ERROR_OK)
1137                 return retval;
1138
1139         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1140         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1141         if (retval != ERROR_OK)
1142                 return retval;
1143
1144         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1145         if (retval != ERROR_OK)
1146                 return retval;
1147         retval = dap_run(dap);
1148         if (retval != ERROR_OK)
1149                 return retval;
1150
1151         /* Check that we have debug power domains activated */
1152         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
1153                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1154                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1155                 if (retval != ERROR_OK)
1156                         return retval;
1157                 retval = dap_run(dap);
1158                 if (retval != ERROR_OK)
1159                         return retval;
1160                 alive_sleep(10);
1161         }
1162
1163         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
1164                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1165                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
1166                 if (retval != ERROR_OK)
1167                         return retval;
1168                 retval = dap_run(dap);
1169                 if (retval != ERROR_OK)
1170                         return retval;
1171                 alive_sleep(10);
1172         }
1173
1174         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1175         if (retval != ERROR_OK)
1176                 return retval;
1177         /* With debug power on we can activate OVERRUN checking */
1178         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1179         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
1180         if (retval != ERROR_OK)
1181                 return retval;
1182         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
1183         if (retval != ERROR_OK)
1184                 return retval;
1185
1186         dap_syssec(dap);
1187
1188         return ERROR_OK;
1189 }
1190
1191 /* CID interpretation -- see ARM IHI 0029B section 3
1192  * and ARM IHI 0031A table 13-3.
1193  */
1194 static const char *class_description[16] = {
1195         "Reserved", "ROM table", "Reserved", "Reserved",
1196         "Reserved", "Reserved", "Reserved", "Reserved",
1197         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1198         "Reserved", "OptimoDE DESS",
1199         "Generic IP component", "PrimeCell or System component"
1200 };
1201
1202 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1203 {
1204         return cid3 == 0xb1 && cid2 == 0x05
1205                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1206 }
1207
1208 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1209                         uint32_t *out_dbgbase, uint32_t *out_apid)
1210 {
1211         uint32_t ap_old;
1212         int retval;
1213         uint32_t dbgbase, apid;
1214
1215         /* AP address is in bits 31:24 of DP_SELECT */
1216         if (ap >= 256)
1217                 return ERROR_COMMAND_SYNTAX_ERROR;
1218
1219         ap_old = dap->ap_current;
1220         dap_ap_select(dap, ap);
1221
1222         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1223         if (retval != ERROR_OK)
1224                 return retval;
1225         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1226         if (retval != ERROR_OK)
1227                 return retval;
1228         retval = dap_run(dap);
1229         if (retval != ERROR_OK)
1230                 return retval;
1231
1232         /* Excavate the device ID code */
1233         struct jtag_tap *tap = dap->jtag_info->tap;
1234         while (tap != NULL) {
1235                 if (tap->hasidcode)
1236                         break;
1237                 tap = tap->next_tap;
1238         }
1239         if (tap == NULL || !tap->hasidcode)
1240                 return ERROR_OK;
1241
1242         dap_ap_select(dap, ap_old);
1243
1244         /* The asignment happens only here to prevent modification of these
1245          * values before they are certain. */
1246         *out_dbgbase = dbgbase;
1247         *out_apid = apid;
1248
1249         return ERROR_OK;
1250 }
1251
1252 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1253                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
1254 {
1255         uint32_t ap_old;
1256         uint32_t romentry, entry_offset = 0, component_base, devtype;
1257         int retval = ERROR_FAIL;
1258
1259         if (ap >= 256)
1260                 return ERROR_COMMAND_SYNTAX_ERROR;
1261
1262         ap_old = dap->ap_current;
1263         dap_ap_select(dap, ap);
1264
1265         do {
1266                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1267                                                 entry_offset, &romentry);
1268                 if (retval != ERROR_OK)
1269                         return retval;
1270
1271                 component_base = (dbgbase & 0xFFFFF000)
1272                         + (romentry & 0xFFFFF000);
1273
1274                 if (romentry & 0x1) {
1275                         retval = mem_ap_read_atomic_u32(dap,
1276                                         (component_base & 0xfffff000) | 0xfcc,
1277                                         &devtype);
1278                         if ((devtype & 0xff) == type) {
1279                                 *addr = component_base;
1280                                 retval = ERROR_OK;
1281                                 break;
1282                         }
1283                 }
1284                 entry_offset += 4;
1285         } while (romentry > 0);
1286
1287         dap_ap_select(dap, ap_old);
1288
1289         return retval;
1290 }
1291
1292 static int dap_info_command(struct command_context *cmd_ctx,
1293                 struct adiv5_dap *dap, int ap)
1294 {
1295         int retval;
1296         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1297         int romtable_present = 0;
1298         uint8_t mem_ap;
1299         uint32_t ap_old;
1300
1301         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1302         if (retval != ERROR_OK)
1303                 return retval;
1304
1305         ap_old = dap->ap_current;
1306         dap_ap_select(dap, ap);
1307
1308         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1309         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1310         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1311         if (apid) {
1312                 switch (apid&0x0F) {
1313                         case 0:
1314                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1315                                 break;
1316                         case 1:
1317                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1318                                 break;
1319                         case 2:
1320                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1321                                 break;
1322                         default:
1323                                 command_print(cmd_ctx, "\tUnknown AP type");
1324                                 break;
1325                 }
1326
1327                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1328                  * not a ROM table ... or have no such components at all.
1329                  */
1330                 if (mem_ap)
1331                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1332         } else
1333                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1334
1335         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1336         if (romtable_present) {
1337                 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1338                 uint16_t entry_offset;
1339
1340                 /* bit 16 of apid indicates a memory access port */
1341                 if (dbgbase & 0x02)
1342                         command_print(cmd_ctx, "\tValid ROM table present");
1343                 else
1344                         command_print(cmd_ctx, "\tROM table in legacy format");
1345
1346                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1347                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1348                 if (retval != ERROR_OK)
1349                         return retval;
1350                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1351                 if (retval != ERROR_OK)
1352                         return retval;
1353                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1354                 if (retval != ERROR_OK)
1355                         return retval;
1356                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1357                 if (retval != ERROR_OK)
1358                         return retval;
1359                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1360                 if (retval != ERROR_OK)
1361                         return retval;
1362                 retval = dap_run(dap);
1363                 if (retval != ERROR_OK)
1364                         return retval;
1365
1366                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1367                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1368                                         ", CID2 0x%2.2x"
1369                                         ", CID1 0x%2.2x"
1370                                         ", CID0 0x%2.2x",
1371                                         (unsigned) cid3, (unsigned)cid2,
1372                                         (unsigned) cid1, (unsigned) cid0);
1373                 if (memtype & 0x01)
1374                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1375                 else
1376                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1377                                         "Dedicated debug bus.");
1378
1379                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1380                 entry_offset = 0;
1381                 do {
1382                         retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1383                         if (retval != ERROR_OK)
1384                                 return retval;
1385                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1386                         if (romentry & 0x01) {
1387                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1388                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1389                                 uint32_t component_base;
1390                                 unsigned part_num;
1391                                 char *type, *full;
1392
1393                                 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1394
1395                                 /* IDs are in last 4K section */
1396                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1397                                 if (retval != ERROR_OK)
1398                                         return retval;
1399                                 c_pid0 &= 0xff;
1400                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1401                                 if (retval != ERROR_OK)
1402                                         return retval;
1403                                 c_pid1 &= 0xff;
1404                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1405                                 if (retval != ERROR_OK)
1406                                         return retval;
1407                                 c_pid2 &= 0xff;
1408                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1409                                 if (retval != ERROR_OK)
1410                                         return retval;
1411                                 c_pid3 &= 0xff;
1412                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1413                                 if (retval != ERROR_OK)
1414                                         return retval;
1415                                 c_pid4 &= 0xff;
1416
1417                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1418                                 if (retval != ERROR_OK)
1419                                         return retval;
1420                                 c_cid0 &= 0xff;
1421                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1422                                 if (retval != ERROR_OK)
1423                                         return retval;
1424                                 c_cid1 &= 0xff;
1425                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1426                                 if (retval != ERROR_OK)
1427                                         return retval;
1428                                 c_cid2 &= 0xff;
1429                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1430                                 if (retval != ERROR_OK)
1431                                         return retval;
1432                                 c_cid3 &= 0xff;
1433
1434                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1435                                                 "start address 0x%" PRIx32, component_base,
1436                                 /* component may take multiple 4K pages */
1437                                 component_base - 0x1000*(c_pid4 >> 4));
1438                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1439                                                 (int) (c_cid1 >> 4) & 0xf,
1440                                                 /* See ARM IHI 0029B Table 3-3 */
1441                                                 class_description[(c_cid1 >> 4) & 0xf]);
1442
1443                                 /* CoreSight component? */
1444                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1445                                         uint32_t devtype;
1446                                         unsigned minor;
1447                                         char *major = "Reserved", *subtype = "Reserved";
1448
1449                                         retval = mem_ap_read_atomic_u32(dap,
1450                                                         (component_base & 0xfffff000) | 0xfcc,
1451                                                         &devtype);
1452                                         if (retval != ERROR_OK)
1453                                                 return retval;
1454                                         minor = (devtype >> 4) & 0x0f;
1455                                         switch (devtype & 0x0f) {
1456                                         case 0:
1457                                                 major = "Miscellaneous";
1458                                                 switch (minor) {
1459                                                 case 0:
1460                                                         subtype = "other";
1461                                                         break;
1462                                                 case 4:
1463                                                         subtype = "Validation component";
1464                                                         break;
1465                                                 }
1466                                                 break;
1467                                         case 1:
1468                                                 major = "Trace Sink";
1469                                                 switch (minor) {
1470                                                 case 0:
1471                                                         subtype = "other";
1472                                                         break;
1473                                                 case 1:
1474                                                         subtype = "Port";
1475                                                         break;
1476                                                 case 2:
1477                                                         subtype = "Buffer";
1478                                                         break;
1479                                                 }
1480                                                 break;
1481                                         case 2:
1482                                                 major = "Trace Link";
1483                                                 switch (minor) {
1484                                                 case 0:
1485                                                         subtype = "other";
1486                                                         break;
1487                                                 case 1:
1488                                                         subtype = "Funnel, router";
1489                                                         break;
1490                                                 case 2:
1491                                                         subtype = "Filter";
1492                                                         break;
1493                                                 case 3:
1494                                                         subtype = "FIFO, buffer";
1495                                                         break;
1496                                                 }
1497                                                 break;
1498                                         case 3:
1499                                                 major = "Trace Source";
1500                                                 switch (minor) {
1501                                                 case 0:
1502                                                         subtype = "other";
1503                                                         break;
1504                                                 case 1:
1505                                                         subtype = "Processor";
1506                                                         break;
1507                                                 case 2:
1508                                                         subtype = "DSP";
1509                                                         break;
1510                                                 case 3:
1511                                                         subtype = "Engine/Coprocessor";
1512                                                         break;
1513                                                 case 4:
1514                                                         subtype = "Bus";
1515                                                         break;
1516                                                 }
1517                                                 break;
1518                                         case 4:
1519                                                 major = "Debug Control";
1520                                                 switch (minor) {
1521                                                 case 0:
1522                                                         subtype = "other";
1523                                                         break;
1524                                                 case 1:
1525                                                         subtype = "Trigger Matrix";
1526                                                         break;
1527                                                 case 2:
1528                                                         subtype = "Debug Auth";
1529                                                         break;
1530                                                 }
1531                                                 break;
1532                                         case 5:
1533                                                 major = "Debug Logic";
1534                                                 switch (minor) {
1535                                                 case 0:
1536                                                         subtype = "other";
1537                                                         break;
1538                                                 case 1:
1539                                                         subtype = "Processor";
1540                                                         break;
1541                                                 case 2:
1542                                                         subtype = "DSP";
1543                                                         break;
1544                                                 case 3:
1545                                                         subtype = "Engine/Coprocessor";
1546                                                         break;
1547                                                 }
1548                                                 break;
1549                                         }
1550                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1551                                                         (unsigned) (devtype & 0xff),
1552                                                         major, subtype);
1553                                         /* REVISIT also show 0xfc8 DevId */
1554                                 }
1555
1556                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1557                                         command_print(cmd_ctx,
1558                                                         "\t\tCID3 0%2.2x"
1559                                                         ", CID2 0%2.2x"
1560                                                         ", CID1 0%2.2x"
1561                                                         ", CID0 0%2.2x",
1562                                                         (int) c_cid3,
1563                                                         (int) c_cid2,
1564                                                         (int)c_cid1,
1565                                                         (int)c_cid0);
1566                                 command_print(cmd_ctx,
1567                                 "\t\tPeripheral ID[4..0] = hex "
1568                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1569                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1570                                 (int) c_pid1, (int) c_pid0);
1571
1572                                 /* Part number interpretations are from Cortex
1573                                  * core specs, the CoreSight components TRM
1574                                  * (ARM DDI 0314H), CoreSight System Design
1575                                  * Guide (ARM DGI 0012D) and ETM specs; also
1576                                  * from chip observation (e.g. TI SDTI).
1577                                  */
1578                                 part_num = (c_pid0 & 0xff);
1579                                 part_num |= (c_pid1 & 0x0f) << 8;
1580                                 switch (part_num) {
1581                                 case 0x000:
1582                                         type = "Cortex-M3 NVIC";
1583                                         full = "(Interrupt Controller)";
1584                                         break;
1585                                 case 0x001:
1586                                         type = "Cortex-M3 ITM";
1587                                         full = "(Instrumentation Trace Module)";
1588                                         break;
1589                                 case 0x002:
1590                                         type = "Cortex-M3 DWT";
1591                                         full = "(Data Watchpoint and Trace)";
1592                                         break;
1593                                 case 0x003:
1594                                         type = "Cortex-M3 FBP";
1595                                         full = "(Flash Patch and Breakpoint)";
1596                                         break;
1597                                 case 0x00d:
1598                                         type = "CoreSight ETM11";
1599                                         full = "(Embedded Trace)";
1600                                         break;
1601                                 /* case 0x113: what? */
1602                                 case 0x120:             /* from OMAP3 memmap */
1603                                         type = "TI SDTI";
1604                                         full = "(System Debug Trace Interface)";
1605                                         break;
1606                                 case 0x343:             /* from OMAP3 memmap */
1607                                         type = "TI DAPCTL";
1608                                         full = "";
1609                                         break;
1610                                 case 0x906:
1611                                         type = "Coresight CTI";
1612                                         full = "(Cross Trigger)";
1613                                         break;
1614                                 case 0x907:
1615                                         type = "Coresight ETB";
1616                                         full = "(Trace Buffer)";
1617                                         break;
1618                                 case 0x908:
1619                                         type = "Coresight CSTF";
1620                                         full = "(Trace Funnel)";
1621                                         break;
1622                                 case 0x910:
1623                                         type = "CoreSight ETM9";
1624                                         full = "(Embedded Trace)";
1625                                         break;
1626                                 case 0x912:
1627                                         type = "Coresight TPIU";
1628                                         full = "(Trace Port Interface Unit)";
1629                                         break;
1630                                 case 0x921:
1631                                         type = "Cortex-A8 ETM";
1632                                         full = "(Embedded Trace)";
1633                                         break;
1634                                 case 0x922:
1635                                         type = "Cortex-A8 CTI";
1636                                         full = "(Cross Trigger)";
1637                                         break;
1638                                 case 0x923:
1639                                         type = "Cortex-M3 TPIU";
1640                                         full = "(Trace Port Interface Unit)";
1641                                         break;
1642                                 case 0x924:
1643                                         type = "Cortex-M3 ETM";
1644                                         full = "(Embedded Trace)";
1645                                         break;
1646                                 case 0x930:
1647                                         type = "Cortex-R4 ETM";
1648                                         full = "(Embedded Trace)";
1649                                         break;
1650                                 case 0xc08:
1651                                         type = "Cortex-A8 Debug";
1652                                         full = "(Debug Unit)";
1653                                         break;
1654                                 default:
1655                                         type = "-*- unrecognized -*-";
1656                                         full = "";
1657                                         break;
1658                                 }
1659                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1660                                                 type, full);
1661                         } else {
1662                                 if (romentry)
1663                                         command_print(cmd_ctx, "\t\tComponent not present");
1664                                 else
1665                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1666                         }
1667                         entry_offset += 4;
1668                 } while (romentry > 0);
1669         } else
1670                 command_print(cmd_ctx, "\tNo ROM table present");
1671         dap_ap_select(dap, ap_old);
1672
1673         return ERROR_OK;
1674 }
1675
1676 COMMAND_HANDLER(handle_dap_info_command)
1677 {
1678         struct target *target = get_current_target(CMD_CTX);
1679         struct arm *arm = target_to_arm(target);
1680         struct adiv5_dap *dap = arm->dap;
1681         uint32_t apsel;
1682
1683         switch (CMD_ARGC) {
1684         case 0:
1685                 apsel = dap->apsel;
1686                 break;
1687         case 1:
1688                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1689                 break;
1690         default:
1691                 return ERROR_COMMAND_SYNTAX_ERROR;
1692         }
1693
1694         return dap_info_command(CMD_CTX, dap, apsel);
1695 }
1696
1697 COMMAND_HANDLER(dap_baseaddr_command)
1698 {
1699         struct target *target = get_current_target(CMD_CTX);
1700         struct arm *arm = target_to_arm(target);
1701         struct adiv5_dap *dap = arm->dap;
1702
1703         uint32_t apsel, baseaddr;
1704         int retval;
1705
1706         switch (CMD_ARGC) {
1707         case 0:
1708                 apsel = dap->apsel;
1709                 break;
1710         case 1:
1711                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1712                 /* AP address is in bits 31:24 of DP_SELECT */
1713                 if (apsel >= 256)
1714                         return ERROR_COMMAND_SYNTAX_ERROR;
1715                 break;
1716         default:
1717                 return ERROR_COMMAND_SYNTAX_ERROR;
1718         }
1719
1720         dap_ap_select(dap, apsel);
1721
1722         /* NOTE:  assumes we're talking to a MEM-AP, which
1723          * has a base address.  There are other kinds of AP,
1724          * though they're not common for now.  This should
1725          * use the ID register to verify it's a MEM-AP.
1726          */
1727         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1728         if (retval != ERROR_OK)
1729                 return retval;
1730         retval = dap_run(dap);
1731         if (retval != ERROR_OK)
1732                 return retval;
1733
1734         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1735
1736         return retval;
1737 }
1738
1739 COMMAND_HANDLER(dap_memaccess_command)
1740 {
1741         struct target *target = get_current_target(CMD_CTX);
1742         struct arm *arm = target_to_arm(target);
1743         struct adiv5_dap *dap = arm->dap;
1744
1745         uint32_t memaccess_tck;
1746
1747         switch (CMD_ARGC) {
1748         case 0:
1749                 memaccess_tck = dap->memaccess_tck;
1750                 break;
1751         case 1:
1752                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1753                 break;
1754         default:
1755                 return ERROR_COMMAND_SYNTAX_ERROR;
1756         }
1757         dap->memaccess_tck = memaccess_tck;
1758
1759         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1760                         dap->memaccess_tck);
1761
1762         return ERROR_OK;
1763 }
1764
1765 COMMAND_HANDLER(dap_apsel_command)
1766 {
1767         struct target *target = get_current_target(CMD_CTX);
1768         struct arm *arm = target_to_arm(target);
1769         struct adiv5_dap *dap = arm->dap;
1770
1771         uint32_t apsel, apid;
1772         int retval;
1773
1774         switch (CMD_ARGC) {
1775         case 0:
1776                 apsel = 0;
1777                 break;
1778         case 1:
1779                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1780                 /* AP address is in bits 31:24 of DP_SELECT */
1781                 if (apsel >= 256)
1782                         return ERROR_COMMAND_SYNTAX_ERROR;
1783                 break;
1784         default:
1785                 return ERROR_COMMAND_SYNTAX_ERROR;
1786         }
1787
1788         dap->apsel = apsel;
1789         dap_ap_select(dap, apsel);
1790
1791         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1792         if (retval != ERROR_OK)
1793                 return retval;
1794         retval = dap_run(dap);
1795         if (retval != ERROR_OK)
1796                 return retval;
1797
1798         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1799                         apsel, apid);
1800
1801         return retval;
1802 }
1803
1804 COMMAND_HANDLER(dap_apid_command)
1805 {
1806         struct target *target = get_current_target(CMD_CTX);
1807         struct arm *arm = target_to_arm(target);
1808         struct adiv5_dap *dap = arm->dap;
1809
1810         uint32_t apsel, apid;
1811         int retval;
1812
1813         switch (CMD_ARGC) {
1814         case 0:
1815                 apsel = dap->apsel;
1816                 break;
1817         case 1:
1818                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1819                 /* AP address is in bits 31:24 of DP_SELECT */
1820                 if (apsel >= 256)
1821                         return ERROR_COMMAND_SYNTAX_ERROR;
1822                 break;
1823         default:
1824                 return ERROR_COMMAND_SYNTAX_ERROR;
1825         }
1826
1827         dap_ap_select(dap, apsel);
1828
1829         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1830         if (retval != ERROR_OK)
1831                 return retval;
1832         retval = dap_run(dap);
1833         if (retval != ERROR_OK)
1834                 return retval;
1835
1836         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1837
1838         return retval;
1839 }
1840
1841 static const struct command_registration dap_commands[] = {
1842         {
1843                 .name = "info",
1844                 .handler = handle_dap_info_command,
1845                 .mode = COMMAND_EXEC,
1846                 .help = "display ROM table for MEM-AP "
1847                         "(default currently selected AP)",
1848                 .usage = "[ap_num]",
1849         },
1850         {
1851                 .name = "apsel",
1852                 .handler = dap_apsel_command,
1853                 .mode = COMMAND_EXEC,
1854                 .help = "Set the currently selected AP (default 0) "
1855                         "and display the result",
1856                 .usage = "[ap_num]",
1857         },
1858         {
1859                 .name = "apid",
1860                 .handler = dap_apid_command,
1861                 .mode = COMMAND_EXEC,
1862                 .help = "return ID register from AP "
1863                         "(default currently selected AP)",
1864                 .usage = "[ap_num]",
1865         },
1866         {
1867                 .name = "baseaddr",
1868                 .handler = dap_baseaddr_command,
1869                 .mode = COMMAND_EXEC,
1870                 .help = "return debug base address from MEM-AP "
1871                         "(default currently selected AP)",
1872                 .usage = "[ap_num]",
1873         },
1874         {
1875                 .name = "memaccess",
1876                 .handler = dap_memaccess_command,
1877                 .mode = COMMAND_EXEC,
1878                 .help = "set/get number of extra tck for MEM-AP memory "
1879                         "bus access [0-255]",
1880                 .usage = "[cycles]",
1881         },
1882         COMMAND_REGISTRATION_DONE
1883 };
1884
1885 const struct command_registration dap_command_handlers[] = {
1886         {
1887                 .name = "dap",
1888                 .mode = COMMAND_EXEC,
1889                 .help = "DAP command group",
1890                 .usage = "",
1891                 .chain = dap_commands,
1892         },
1893         COMMAND_REGISTRATION_DONE
1894 };