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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm_adi_v5.h"
  73 #include <helper/time_support.h>
  74
  75
  76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  77
  78 /*
  79         uint32_t tar_block_size(uint32_t address)
  80         Return the largest block starting at address that does not cross a tar block size alignment boundary
  81 */
  82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  83 {
  84         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  85 }
  86
  87 /***************************************************************************
  88  *                                                                         *
  89  * DPACC and APACC scanchain access through JTAG-DP                        *
  90  *                                                                         *
  91 ***************************************************************************/
  92
  93 /**
  94  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  95  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  96  * discusses operations which access these registers.
  97  *
  98  * Note that only one scan is performed.  If RnW is set, a separate scan
  99  * will be needed to collect the data which was read; the "invalue" collects
 100  * the posted result of a preceding operation, not the current one.
 101  *
 102  * @param swjdp the DAP
 103  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 104  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 105  *      SELECT register has more addressing bits.
 106  * @param RnW false iff outvalue will be written to the DP or AP
 107  * @param outvalue points to a 32-bit (little-endian) integer
 108  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 109  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 110  */
 111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 112                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 113                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 114 {
 115         struct arm_jtag *jtag_info = swjdp->jtag_info;
 116         struct scan_field fields[2];
 117         uint8_t out_addr_buf;
 118
 119         jtag_set_end_state(TAP_IDLE);
 120         arm_jtag_set_instr(jtag_info, instr, NULL);
 121
 122         /* Scan out a read or write operation using some DP or AP register.
 123          * For APACC access with any sticky error flag set, this is discarded.
 124          */
 125         fields[0].tap = jtag_info->tap;
 126         fields[0].num_bits = 3;
 127         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 128         fields[0].out_value = &out_addr_buf;
 129         fields[0].in_value = ack;
 130
 131         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 132          * complete; data we write is discarded, data we read is unpredictable.
 133          * When overrun detect is active, STICKYORUN is set.
 134          */
 135
 136         fields[1].tap = jtag_info->tap;
 137         fields[1].num_bits = 32;
 138         fields[1].out_value = outvalue;
 139         fields[1].in_value = invalue;
 140
 141         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 142
 143         /* Add specified number of tck clocks after starting memory bus
 144          * access, giving the hardware time to complete the access.
 145          * They provide more time for the (MEM) AP to complete the read ...
 146          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 147          */
 148         if ((instr == JTAG_DP_APACC)
 149                         && ((reg_addr == AP_REG_DRW)
 150                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 151                         && (swjdp->memaccess_tck != 0))
 152                 jtag_add_runtest(swjdp->memaccess_tck,
 153                                 jtag_set_end_state(TAP_IDLE));
 154
 155         return jtag_get_error();
 156 }
 157
 158 /**
 159  * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
 160  * This is exactly like adi_jtag_dp_scan(), except that endianness
 161  * conversions are performed (so the types of invalue and outvalue
 162  * must be different).
 163  */
 164 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 165                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 166                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 167 {
 168         uint8_t out_value_buf[4];
 169         int retval;
 170
 171         buf_set_u32(out_value_buf, 0, 32, outvalue);
 172
 173         retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
 174                         out_value_buf, (uint8_t *)invalue, ack);
 175         if (retval != ERROR_OK)
 176                 return retval;
 177
 178         if (invalue)
 179                 jtag_add_callback(arm_le_to_h_u32,
 180                                 (jtag_callback_data_t) invalue);
 181
 182         return retval;
 183 }
 184
 185 /**
 186  * Utility to write AP registers.
 187  */
 188 static inline int adi_jtag_ap_write_check(struct swjdp_common *dap,
 189                 uint8_t reg_addr, uint8_t *outvalue)
 190 {
 191         return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
 192                         outvalue, NULL, NULL);
 193 }
 194
 195 static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
 196                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 197                 uint32_t outvalue, uint32_t *invalue)
 198 {
 199         int retval;
 200
 201         /* Issue the read or write */
 202         retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
 203                         RnW, outvalue, NULL, NULL);
 204         if (retval != ERROR_OK)
 205                 return retval;
 206
 207         /* For reads,  collect posted value; RDBUFF has no other effect.
 208          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 209          */
 210         if ((RnW == DPAP_READ) && (invalue != NULL))
 211                 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 212                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 213         return retval;
 214 }
 215
 216 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 217 {
 218         int retval;
 219         uint32_t ctrlstat;
 220
 221         /* too expensive to call keep_alive() here */
 222
 223 #if 0
 224         /* Danger!!!! BROKEN!!!! */
 225         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 226                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 227         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 228         R956 introduced the check on return value here and now Michael Schwingen reports
 229         that this code no longer works....
 230
 231         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 232         */
 233         if ((retval = jtag_execute_queue()) != ERROR_OK)
 234         {
 235                 LOG_ERROR("BUG: Why does this fail the first time????");
 236         }
 237         /* Why??? second time it works??? */
 238 #endif
 239
 240         /* Post CTRL/STAT read; discard any previous posted read value
 241          * but collect its ACK status.
 242          */
 243         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 244                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 245         if ((retval = jtag_execute_queue()) != ERROR_OK)
 246                 return retval;
 247
 248         swjdp->ack = swjdp->ack & 0x7;
 249
 250         /* common code path avoids calling timeval_ms() */
 251         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 252         {
 253                 long long then = timeval_ms();
 254
 255                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 256                 {
 257                         if (swjdp->ack == JTAG_ACK_WAIT)
 258                         {
 259                                 if ((timeval_ms()-then) > 1000)
 260                                 {
 261                                         /* NOTE:  this would be a good spot
 262                                          * to use JTAG_DP_ABORT.
 263                                          */
 264                                         LOG_WARNING("Timeout (1000ms) waiting "
 265                                                 "for ACK=OK/FAULT "
 266                                                 "in JTAG-DP transaction");
 267                                         return ERROR_JTAG_DEVICE_ERROR;
 268                                 }
 269                         }
 270                         else
 271                         {
 272                                 LOG_WARNING("Invalid ACK %#x "
 273                                                 "in JTAG-DP transaction",
 274                                                 swjdp->ack);
 275                                 return ERROR_JTAG_DEVICE_ERROR;
 276                         }
 277
 278                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 279                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 280                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 281                                 return retval;
 282                         swjdp->ack = swjdp->ack & 0x7;
 283                 }
 284         }
 285
 286         /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 287
 288         /* Check for STICKYERR and STICKYORUN */
 289         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 290         {
 291                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 292                 /* Check power to debug regions */
 293                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 294                          ahbap_debugport_init(swjdp);
 295                 else
 296                 {
 297                         uint32_t mem_ap_csw, mem_ap_tar;
 298
 299                         /* Maybe print information about last intended
 300                          * MEM-AP access; but not if autoincrementing.
 301                          * *Real* CSW and TAR values are always shown.
 302                          */
 303                         if (swjdp->ap_tar_value != (uint32_t) -1)
 304                                 LOG_DEBUG("MEM-AP Cached values: "
 305                                         "ap_bank 0x%" PRIx32
 306                                         ", ap_csw 0x%" PRIx32
 307                                         ", ap_tar 0x%" PRIx32,
 308                                         swjdp->ap_bank_value,
 309                                         swjdp->ap_csw_value,
 310                                         swjdp->ap_tar_value);
 311
 312                         if (ctrlstat & SSTICKYORUN)
 313                                 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 314                                         "memaccess, or reduce jtag speed");
 315
 316                         if (ctrlstat & SSTICKYERR)
 317                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 318
 319                         /* Clear Sticky Error Bits */
 320                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 321                                         DP_CTRL_STAT, DPAP_WRITE,
 322                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 323                                                 | SSTICKYERR, NULL);
 324                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 325                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 326                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 327                                 return retval;
 328
 329                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 330
 331                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 332                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 333                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 334                                 return retval;
 335                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 336                                         PRIx32, mem_ap_csw, mem_ap_tar);
 337
 338                 }
 339                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 340                         return retval;
 341                 return ERROR_JTAG_DEVICE_ERROR;
 342         }
 343
 344         return ERROR_OK;
 345 }
 346
 347 /***************************************************************************
 348  *                                                                         *
 349  * DP and MEM-AP  register access  through APACC and DPACC                 *
 350  *                                                                         *
 351 ***************************************************************************/
 352
 353 /* FIXME remove dap_dp_{read,write}_reg() ... these should become the
 354  * bodies of the JTAG implementations of dap_queue_dp_{read,write}() and
 355  * callers should switch over to the transport-neutral calls.
 356  */
 357
 358 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 359                 uint32_t value, uint8_t reg_addr)
 360 {
 361         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 362                         reg_addr, DPAP_WRITE, value, NULL);
 363 }
 364
 365 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 366                 uint32_t *value, uint8_t reg_addr)
 367 {
 368         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 369                         reg_addr, DPAP_READ, 0, value);
 370 }
 371
 372 /**
 373  * Select one of the APs connected to the specified DAP.  The
 374  * selection is implicitly used with future AP transactions.
 375  * This is a NOP if the specified AP is already selected.
 376  *
 377  * @param swjdp The DAP
 378  * @param apsel Number of the AP to (implicitly) use with further
 379  *      transactions.  This normally identifies a MEM-AP.
 380  */
 381 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 382 {
 383         uint32_t select = (apsel << 24) & 0xFF000000;
 384
 385         if (select != swjdp->apsel)
 386         {
 387                 swjdp->apsel = select;
 388                 /* Switching AP invalidates cached values.
 389                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 390                  */
 391                 swjdp->ap_bank_value = -1;
 392                 swjdp->ap_csw_value = -1;
 393                 swjdp->ap_tar_value = -1;
 394         }
 395 }
 396
 397 /** Select the AP register bank matching bits 7:4 of ap_reg. */
 398 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 399 {
 400         uint32_t select = (ap_reg & 0x000000F0);
 401
 402         if (select != swjdp->ap_bank_value)
 403         {
 404                 swjdp->ap_bank_value = select;
 405                 select |= swjdp->apsel;
 406                 return dap_dp_write_reg(swjdp, select, DP_SELECT);
 407         } else
 408                 return ERROR_OK;
 409 }
 410
 411 /* FIXME remove dap_ap_{read,write}_reg() and dap_ap_write_reg_u32()
 412  * ... these should become the bodies of the JTAG implementations of
 413  * dap_queue_ap_{read,write}(), then all their current callers should
 414  * switch over to the transport-neutral calls.
 415  */
 416
 417 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 418                 uint32_t reg_addr, uint8_t *out_value_buf)
 419 {
 420         int retval;
 421
 422         retval = dap_ap_bankselect(swjdp, reg_addr);
 423         if (retval != ERROR_OK)
 424                 return retval;
 425
 426         return adi_jtag_ap_write_check(swjdp, reg_addr, out_value_buf);
 427 }
 428
 429 /**
 430  * Asynchronous (queued) AP register write.
 431  *
 432  * @param swjdp The DAP whose currently selected AP will be written.
 433  * @param reg_addr Eight bit AP register address.
 434  * @param value Word to be written at reg_addr
 435  *
 436  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 437  */
 438 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 439                 uint32_t reg_addr, uint32_t value)
 440 {
 441         uint8_t out_value_buf[4];
 442
 443         buf_set_u32(out_value_buf, 0, 32, value);
 444         return dap_ap_write_reg(swjdp,
 445                         reg_addr, out_value_buf);
 446 }
 447
 448 /**
 449  * Asynchronous (queued) AP register eread.
 450  *
 451  * @param swjdp The DAP whose currently selected AP will be read.
 452  * @param reg_addr Eight bit AP register address.
 453  * @param value Points to where the 32-bit (little-endian) word will be stored.
 454  *
 455  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 456  */
 457 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 458                 uint32_t reg_addr, uint32_t *value)
 459 {
 460         int retval;
 461
 462         retval = dap_ap_bankselect(swjdp, reg_addr);
 463         if (retval != ERROR_OK)
 464                 return retval;
 465
 466         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 467                         DPAP_READ, 0, value);
 468 }
 469
 470 /**
 471  * Queue transactions setting up transfer parameters for the
 472  * currently selected MEM-AP.
 473  *
 474  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 475  * initiate data reads or writes using memory or peripheral addresses.
 476  * If the CSW is configured for it, the TAR may be automatically
 477  * incremented after each transfer.
 478  *
 479  * @todo Rename to reflect it being specifically a MEM-AP function.
 480  *
 481  * @param swjdp The DAP connected to the MEM-AP.
 482  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 483  *      matches the cached value, the register is not changed.
 484  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 485  *      matches the cached address, the register is not changed.
 486  *
 487  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 488  */
 489 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 490 {
 491         int retval;
 492
 493         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 494         if (csw != swjdp->ap_csw_value)
 495         {
 496                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 497                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 498                 if (retval != ERROR_OK)
 499                         return retval;
 500                 swjdp->ap_csw_value = csw;
 501         }
 502         if (tar != swjdp->ap_tar_value)
 503         {
 504                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 505                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 506                 if (retval != ERROR_OK)
 507                         return retval;
 508                 swjdp->ap_tar_value = tar;
 509         }
 510         /* Disable TAR cache when autoincrementing */
 511         if (csw & CSW_ADDRINC_MASK)
 512                 swjdp->ap_tar_value = -1;
 513         return ERROR_OK;
 514 }
 515
 516 /**
 517  * Asynchronous (queued) read of a word from memory or a system register.
 518  *
 519  * @param swjdp The DAP connected to the MEM-AP performing the read.
 520  * @param address Address of the 32-bit word to read; it must be
 521  *      readable by the currently selected MEM-AP.
 522  * @param value points to where the word will be stored when the
 523  *      transaction queue is flushed (assuming no errors).
 524  *
 525  * @return ERROR_OK for success.  Otherwise a fault code.
 526  */
 527 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
 528                 uint32_t *value)
 529 {
 530         int retval;
 531
 532         /* Use banked addressing (REG_BDx) to avoid some link traffic
 533          * (updating TAR) when reading several consecutive addresses.
 534          */
 535         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 536                         address & 0xFFFFFFF0);
 537         if (retval != ERROR_OK)
 538                 return retval;
 539
 540         return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 541 }
 542
 543 /**
 544  * Synchronous read of a word from memory or a system register.
 545  * As a side effect, this flushes any queued transactions.
 546  *
 547  * @param swjdp The DAP connected to the MEM-AP performing the read.
 548  * @param address Address of the 32-bit word to read; it must be
 549  *      readable by the currently selected MEM-AP.
 550  * @param value points to where the result will be stored.
 551  *
 552  * @return ERROR_OK for success; *value holds the result.
 553  * Otherwise a fault code.
 554  */
 555 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 556                 uint32_t *value)
 557 {
 558         int retval;
 559
 560         retval = mem_ap_read_u32(swjdp, address, value);
 561         if (retval != ERROR_OK)
 562                 return retval;
 563
 564         return jtagdp_transaction_endcheck(swjdp);
 565 }
 566
 567 /**
 568  * Asynchronous (queued) write of a word to memory or a system register.
 569  *
 570  * @param swjdp The DAP connected to the MEM-AP.
 571  * @param address Address to be written; it must be writable by
 572  *      the currently selected MEM-AP.
 573  * @param value Word that will be written to the address when transaction
 574  *      queue is flushed (assuming no errors).
 575  *
 576  * @return ERROR_OK for success.  Otherwise a fault code.
 577  */
 578 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
 579                 uint32_t value)
 580 {
 581         int retval;
 582
 583         /* Use banked addressing (REG_BDx) to avoid some link traffic
 584          * (updating TAR) when writing several consecutive addresses.
 585          */
 586         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 587                         address & 0xFFFFFFF0);
 588         if (retval != ERROR_OK)
 589                 return retval;
 590
 591         return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
 592                         value);
 593 }
 594
 595 /**
 596  * Synchronous write of a word to memory or a system register.
 597  * As a side effect, this flushes any queued transactions.
 598  *
 599  * @param swjdp The DAP connected to the MEM-AP.
 600  * @param address Address to be written; it must be writable by
 601  *      the currently selected MEM-AP.
 602  * @param value Word that will be written.
 603  *
 604  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 605  */
 606 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 607                 uint32_t value)
 608 {
 609         int retval = mem_ap_write_u32(swjdp, address, value);
 610
 611         if (retval != ERROR_OK)
 612                 return retval;
 613
 614         return jtagdp_transaction_endcheck(swjdp);
 615 }
 616
 617 /*****************************************************************************
 618 *                                                                            *
 619 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 620 *                                                                            *
 621 * Write a buffer in target order (little endian)                             *
 622 *                                                                            *
 623 *****************************************************************************/
 624 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 625 {
 626         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 627         uint32_t adr = address;
 628         uint8_t* pBuffer = buffer;
 629
 630         count >>= 2;
 631         wcount = count;
 632
 633         /* if we have an unaligned access - reorder data */
 634         if (adr & 0x3u)
 635         {
 636                 for (writecount = 0; writecount < count; writecount++)
 637                 {
 638                         int i;
 639                         uint32_t outvalue;
 640                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 641
 642                         for (i = 0; i < 4; i++)
 643                         {
 644                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 645                                 outvalue >>= 8;
 646                                 adr++;
 647                         }
 648                         pBuffer += sizeof(uint32_t);
 649                 }
 650         }
 651
 652         while (wcount > 0)
 653         {
 654                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 655                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 656                 if (wcount < blocksize)
 657                         blocksize = wcount;
 658
 659                 /* handle unaligned data at 4k boundary */
 660                 if (blocksize == 0)
 661                         blocksize = 1;
 662
 663                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 664
 665                 for (writecount = 0; writecount < blocksize; writecount++)
 666                 {
 667                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 668                 }
 669
 670                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 671                 {
 672                         wcount = wcount - blocksize;
 673                         address = address + 4 * blocksize;
 674                         buffer = buffer + 4 * blocksize;
 675                 }
 676                 else
 677                 {
 678                         errorcount++;
 679                 }
 680
 681                 if (errorcount > 1)
 682                 {
 683                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 684                         return ERROR_JTAG_DEVICE_ERROR;
 685                 }
 686         }
 687
 688         return retval;
 689 }
 690
 691 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 692                 uint8_t *buffer, int count, uint32_t address)
 693 {
 694         int retval = ERROR_OK;
 695         int wcount, blocksize, writecount, i;
 696
 697         wcount = count >> 1;
 698
 699         while (wcount > 0)
 700         {
 701                 int nbytes;
 702
 703                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 704                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 705
 706                 if (wcount < blocksize)
 707                         blocksize = wcount;
 708
 709                 /* handle unaligned data at 4k boundary */
 710                 if (blocksize == 0)
 711                         blocksize = 1;
 712
 713                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 714                 writecount = blocksize;
 715
 716                 do
 717                 {
 718                         nbytes = MIN((writecount << 1), 4);
 719
 720                         if (nbytes < 4)
 721                         {
 722                                 if (mem_ap_write_buf_u16(swjdp, buffer,
 723                                                 nbytes, address) != ERROR_OK)
 724                                 {
 725                                         LOG_WARNING("Block write error address "
 726                                                 "0x%" PRIx32 ", count 0x%x",
 727                                                 address, count);
 728                                         return ERROR_JTAG_DEVICE_ERROR;
 729                                 }
 730
 731                                 address += nbytes >> 1;
 732                         }
 733                         else
 734                         {
 735                                 uint32_t outvalue;
 736                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 737
 738                                 for (i = 0; i < nbytes; i++)
 739                                 {
 740                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 741                                         outvalue >>= 8;
 742                                         address++;
 743                                 }
 744
 745                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 746                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 747                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 748                                 {
 749                                         LOG_WARNING("Block write error address "
 750                                                 "0x%" PRIx32 ", count 0x%x",
 751                                                 address, count);
 752                                         return ERROR_JTAG_DEVICE_ERROR;
 753                                 }
 754                         }
 755
 756                         buffer += nbytes >> 1;
 757                         writecount -= nbytes >> 1;
 758
 759                 } while (writecount);
 760                 wcount -= blocksize;
 761         }
 762
 763         return retval;
 764 }
 765
 766 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 767 {
 768         int retval = ERROR_OK;
 769
 770         if (count >= 4)
 771                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 772
 773         while (count > 0)
 774         {
 775                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 776                 uint16_t svalue;
 777                 memcpy(&svalue, buffer, sizeof(uint16_t));
 778                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 779                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 780                 retval = jtagdp_transaction_endcheck(swjdp);
 781                 count -= 2;
 782                 address += 2;
 783                 buffer += 2;
 784         }
 785
 786         return retval;
 787 }
 788
 789 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 790                 uint8_t *buffer, int count, uint32_t address)
 791 {
 792         int retval = ERROR_OK;
 793         int wcount, blocksize, writecount, i;
 794
 795         wcount = count;
 796
 797         while (wcount > 0)
 798         {
 799                 int nbytes;
 800
 801                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 802                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 803
 804                 if (wcount < blocksize)
 805                         blocksize = wcount;
 806
 807                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 808                 writecount = blocksize;
 809
 810                 do
 811                 {
 812                         nbytes = MIN(writecount, 4);
 813
 814                         if (nbytes < 4)
 815                         {
 816                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 817                                 {
 818                                         LOG_WARNING("Block write error address "
 819                                                 "0x%" PRIx32 ", count 0x%x",
 820                                                 address, count);
 821                                         return ERROR_JTAG_DEVICE_ERROR;
 822                                 }
 823
 824                                 address += nbytes;
 825                         }
 826                         else
 827                         {
 828                                 uint32_t outvalue;
 829                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 830
 831                                 for (i = 0; i < nbytes; i++)
 832                                 {
 833                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 834                                         outvalue >>= 8;
 835                                         address++;
 836                                 }
 837
 838                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 839                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 840                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 841                                 {
 842                                         LOG_WARNING("Block write error address "
 843                                                 "0x%" PRIx32 ", count 0x%x",
 844                                                 address, count);
 845                                         return ERROR_JTAG_DEVICE_ERROR;
 846                                 }
 847                         }
 848
 849                         buffer += nbytes;
 850                         writecount -= nbytes;
 851
 852                 } while (writecount);
 853                 wcount -= blocksize;
 854         }
 855
 856         return retval;
 857 }
 858
 859 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 860 {
 861         int retval = ERROR_OK;
 862
 863         if (count >= 4)
 864                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 865
 866         while (count > 0)
 867         {
 868                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 869                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 870                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 871                 retval = jtagdp_transaction_endcheck(swjdp);
 872                 count--;
 873                 address++;
 874                 buffer++;
 875         }
 876
 877         return retval;
 878 }
 879
 880 /**
 881  * Synchronously read a block of 32-bit words into a buffer
 882  * @param swjdp The DAP connected to the MEM-AP.
 883  * @param buffer where the words will be stored (in host byte order).
 884  * @param count How many words to read.
 885  * @param address Memory address from which to read words; all the
 886  *      words must be readable by the currently selected MEM-AP.
 887  */
 888 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
 889                 int count, uint32_t address)
 890 {
 891         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 892         uint32_t adr = address;
 893         uint8_t* pBuffer = buffer;
 894
 895         count >>= 2;
 896         wcount = count;
 897
 898         while (wcount > 0)
 899         {
 900                 /* Adjust to read blocks within boundaries aligned to the
 901                  * TAR autoincrement size (at least 2^10).  Autoincrement
 902                  * mode avoids an extra per-word roundtrip to update TAR.
 903                  */
 904                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
 905                                 address);
 906                 if (wcount < blocksize)
 907                         blocksize = wcount;
 908
 909                 /* handle unaligned data at 4k boundary */
 910                 if (blocksize == 0)
 911                         blocksize = 1;
 912
 913                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
 914                                 address);
 915
 916                 /* Scan out first read */
 917                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 918                                 DPAP_READ, 0, NULL, NULL);
 919                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 920                 {
 921                         /* Scan out next read; scan in posted value for the
 922                          * previous one.  Assumes read is acked "OK/FAULT",
 923                          * and CTRL_STAT says that meant "OK".
 924                          */
 925                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 926                                         DPAP_READ, 0, buffer + 4 * readcount,
 927                                         &swjdp->ack);
 928                 }
 929
 930                 /* Scan in last posted value; RDBUFF has no other effect,
 931                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 932                  */
 933                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 934                                 DPAP_READ, 0, buffer + 4 * readcount,
 935                                 &swjdp->ack);
 936                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 937                 {
 938                         wcount = wcount - blocksize;
 939                         address += 4 * blocksize;
 940                         buffer += 4 * blocksize;
 941                 }
 942                 else
 943                 {
 944                         errorcount++;
 945                 }
 946
 947                 if (errorcount > 1)
 948                 {
 949                         LOG_WARNING("Block read error address 0x%" PRIx32
 950                                 ", count 0x%x", address, count);
 951                         return ERROR_JTAG_DEVICE_ERROR;
 952                 }
 953         }
 954
 955         /* if we have an unaligned access - reorder data */
 956         if (adr & 0x3u)
 957         {
 958                 for (readcount = 0; readcount < count; readcount++)
 959                 {
 960                         int i;
 961                         uint32_t data;
 962                         memcpy(&data, pBuffer, sizeof(uint32_t));
 963
 964                         for (i = 0; i < 4; i++)
 965                         {
 966                                 *((uint8_t*)pBuffer) =
 967                                                 (data >> 8 * (adr & 0x3));
 968                                 pBuffer++;
 969                                 adr++;
 970                         }
 971                 }
 972         }
 973
 974         return retval;
 975 }
 976
 977 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 978                 uint8_t *buffer, int count, uint32_t address)
 979 {
 980         uint32_t invalue;
 981         int retval = ERROR_OK;
 982         int wcount, blocksize, readcount, i;
 983
 984         wcount = count >> 1;
 985
 986         while (wcount > 0)
 987         {
 988                 int nbytes;
 989
 990                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 991                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 992                 if (wcount < blocksize)
 993                         blocksize = wcount;
 994
 995                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 996
 997                 /* handle unaligned data at 4k boundary */
 998                 if (blocksize == 0)
 999                         blocksize = 1;
1000                 readcount = blocksize;
1001
1002                 do
1003                 {
1004                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1005                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1006                         {
1007                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1008                                 return ERROR_JTAG_DEVICE_ERROR;
1009                         }
1010
1011                         nbytes = MIN((readcount << 1), 4);
1012
1013                         for (i = 0; i < nbytes; i++)
1014                         {
1015                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1016                                 buffer++;
1017                                 address++;
1018                         }
1019
1020                         readcount -= (nbytes >> 1);
1021                 } while (readcount);
1022                 wcount -= blocksize;
1023         }
1024
1025         return retval;
1026 }
1027
1028 /**
1029  * Synchronously read a block of 16-bit halfwords into a buffer
1030  * @param swjdp The DAP connected to the MEM-AP.
1031  * @param buffer where the halfwords will be stored (in host byte order).
1032  * @param count How many halfwords to read.
1033  * @param address Memory address from which to read words; all the
1034  *      words must be readable by the currently selected MEM-AP.
1035  */
1036 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
1037                 int count, uint32_t address)
1038 {
1039         uint32_t invalue, i;
1040         int retval = ERROR_OK;
1041
1042         if (count >= 4)
1043                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1044
1045         while (count > 0)
1046         {
1047                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1048                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1049                 retval = jtagdp_transaction_endcheck(swjdp);
1050                 if (address & 0x1)
1051                 {
1052                         for (i = 0; i < 2; i++)
1053                         {
1054                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1055                                 buffer++;
1056                                 address++;
1057                         }
1058                 }
1059                 else
1060                 {
1061                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
1062                         memcpy(buffer, &svalue, sizeof(uint16_t));
1063                         address += 2;
1064                         buffer += 2;
1065                 }
1066                 count -= 2;
1067         }
1068
1069         return retval;
1070 }
1071
1072 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1073  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1074  *
1075  * The solution is to arrange for a large out/in scan in this loop and
1076  * and convert data afterwards.
1077  */
1078 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1079                 uint8_t *buffer, int count, uint32_t address)
1080 {
1081         uint32_t invalue;
1082         int retval = ERROR_OK;
1083         int wcount, blocksize, readcount, i;
1084
1085         wcount = count;
1086
1087         while (wcount > 0)
1088         {
1089                 int nbytes;
1090
1091                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1092                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1093
1094                 if (wcount < blocksize)
1095                         blocksize = wcount;
1096
1097                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1098                 readcount = blocksize;
1099
1100                 do
1101                 {
1102                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1103                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1104                         {
1105                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1106                                 return ERROR_JTAG_DEVICE_ERROR;
1107                         }
1108
1109                         nbytes = MIN(readcount, 4);
1110
1111                         for (i = 0; i < nbytes; i++)
1112                         {
1113                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1114                                 buffer++;
1115                                 address++;
1116                         }
1117
1118                         readcount -= nbytes;
1119                 } while (readcount);
1120                 wcount -= blocksize;
1121         }
1122
1123         return retval;
1124 }
1125
1126 /**
1127  * Synchronously read a block of bytes into a buffer
1128  * @param swjdp The DAP connected to the MEM-AP.
1129  * @param buffer where the bytes will be stored.
1130  * @param count How many bytes to read.
1131  * @param address Memory address from which to read data; all the
1132  *      data must be readable by the currently selected MEM-AP.
1133  */
1134 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
1135                 int count, uint32_t address)
1136 {
1137         uint32_t invalue;
1138         int retval = ERROR_OK;
1139
1140         if (count >= 4)
1141                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1142
1143         while (count > 0)
1144         {
1145                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1146                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1147                 retval = jtagdp_transaction_endcheck(swjdp);
1148                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1149                 count--;
1150                 address++;
1151                 buffer++;
1152         }
1153
1154         return retval;
1155 }
1156
1157 /*--------------------------------------------------------------------------*/
1158
1159 static int jtag_idcode_q_read(struct swjdp_common *dap,
1160                 uint8_t *ack, uint32_t *data)
1161 {
1162         struct arm_jtag *jtag_info = dap->jtag_info;
1163         int retval;
1164         struct scan_field fields[1];
1165
1166         jtag_set_end_state(TAP_IDLE);
1167
1168         /* This is a standard JTAG operation -- no DAP tweakage */
1169         retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
1170         if (retval != ERROR_OK)
1171                 return retval;
1172
1173         fields[0].tap = jtag_info->tap;
1174         fields[0].num_bits = 32;
1175         fields[0].out_value = NULL;
1176         fields[0].in_value = (void *) data;
1177
1178         jtag_add_dr_scan(1, fields, jtag_get_end_state());
1179         retval = jtag_get_error();
1180         if (retval != ERROR_OK)
1181                 return retval;
1182
1183         jtag_add_callback(arm_le_to_h_u32,
1184                         (jtag_callback_data_t) data);
1185
1186         return retval;
1187 }
1188
1189 static int jtag_dp_q_read(struct swjdp_common *dap, unsigned reg,
1190                 uint32_t *data)
1191 {
1192         return dap_dp_read_reg(dap, data, reg);
1193 }
1194
1195 static int jtag_dp_q_write(struct swjdp_common *dap, unsigned reg,
1196                 uint32_t data)
1197 {
1198         return dap_dp_write_reg(dap, data, reg);
1199 }
1200
1201 static int jtag_ap_q_bankselect(struct swjdp_common *dap, unsigned reg)
1202 {
1203         uint32_t select = reg & 0x000000F0;
1204
1205         if (select == dap->ap_bank_value)
1206                 return ERROR_OK;
1207         dap->ap_bank_value = select;
1208
1209         select |= dap->apsel;
1210
1211         return jtag_dp_q_write(dap, DP_SELECT, select);
1212 }
1213
1214 static int jtag_ap_q_read(struct swjdp_common *dap, unsigned reg,
1215                 uint32_t *data)
1216 {
1217         int retval = jtag_ap_q_bankselect(dap, reg);
1218
1219         if (retval != ERROR_OK)
1220                 return retval;
1221         return dap_ap_read_reg_u32(dap, reg, data);
1222 }
1223
1224 static int jtag_ap_q_write(struct swjdp_common *dap, unsigned reg,
1225                 uint32_t data)
1226 {
1227         int retval = jtag_ap_q_bankselect(dap, reg);
1228
1229         if (retval != ERROR_OK)
1230                 return retval;
1231         return dap_ap_write_reg_u32(dap, reg, data);
1232 }
1233
1234 static int jtag_ap_q_abort(struct swjdp_common *dap, uint8_t *ack)
1235 {
1236         /* for JTAG, this is the only valid ABORT register operation */
1237         return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
1238                         0, DPAP_WRITE, 1, NULL, ack);
1239 }
1240
1241 static int jtag_dp_run(struct swjdp_common *dap)
1242 {
1243         return jtagdp_transaction_endcheck(dap);
1244 }
1245
1246 static const struct dap_ops jtag_dp_ops = {
1247         .queue_idcode_read =    jtag_idcode_q_read,
1248         .queue_dp_read =        jtag_dp_q_read,
1249         .queue_dp_write =       jtag_dp_q_write,
1250         .queue_ap_read =        jtag_ap_q_read,
1251         .queue_ap_write =       jtag_ap_q_write,
1252         .queue_ap_abort =       jtag_ap_q_abort,
1253         .run =                  jtag_dp_run,
1254 };
1255
1256 /*--------------------------------------------------------------------------*/
1257
1258 /**
1259  * Initialize a DAP.  This sets up the power domains, prepares the DP
1260  * for further use, and arranges to use AP #0 for all AP operations
1261  * until dap_ap-select() changes that policy.
1262  *
1263  * @param swjdp The DAP being initialized.
1264  *
1265  * @todo Rename this.  We also need an initialization scheme which account
1266  * for SWD transports not just JTAG; that will need to address differences
1267  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1268  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1269  */
1270 int ahbap_debugport_init(struct swjdp_common *swjdp)
1271 {
1272         uint32_t idreg, romaddr, dummy;
1273         uint32_t ctrlstat;
1274         int cnt = 0;
1275         int retval;
1276
1277         LOG_DEBUG(" ");
1278
1279         /* JTAG-DP or SWJ-DP, in JTAG mode */
1280         swjdp->ops = &jtag_dp_ops;
1281
1282         /* Default MEM-AP setup.
1283          *
1284          * REVISIT AP #0 may be an inappropriate default for this.
1285          * Should we probe, or take a hint from the caller?
1286          * Presumably we can ignore the possibility of multiple APs.
1287          */
1288         swjdp->apsel = !0;
1289         dap_ap_select(swjdp, 0);
1290
1291         /* DP initialization */
1292         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1293         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1294         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1295
1296         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1297
1298         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1299         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1300         if ((retval = jtag_execute_queue()) != ERROR_OK)
1301                 return retval;
1302
1303         /* Check that we have debug power domains activated */
1304         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1305         {
1306                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1307                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1308                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1309                         return retval;
1310                 alive_sleep(10);
1311         }
1312
1313         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1314         {
1315                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1316                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1317                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1318                         return retval;
1319                 alive_sleep(10);
1320         }
1321
1322         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1323         /* With debug power on we can activate OVERRUN checking */
1324         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1325         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1326         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1327
1328         /*
1329          * REVISIT this isn't actually *initializing* anything in an AP,
1330          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1331          * Should it?  If the ROM address is valid, is this the right
1332          * place to scan the table and do any topology detection?
1333          */
1334         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1335         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1336
1337         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1338                 ", Debug ROM Address 0x%" PRIx32,
1339                 swjdp->apsel, idreg, romaddr);
1340
1341         return ERROR_OK;
1342 }
1343
1344 /* CID interpretation -- see ARM IHI 0029B section 3
1345  * and ARM IHI 0031A table 13-3.
1346  */
1347 static const char *class_description[16] ={
1348         "Reserved", "ROM table", "Reserved", "Reserved",
1349         "Reserved", "Reserved", "Reserved", "Reserved",
1350         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1351         "Reserved", "OptimoDE DESS",
1352                 "Generic IP component", "PrimeCell or System component"
1353 };
1354
1355 static bool
1356 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1357 {
1358         return cid3 == 0xb1 && cid2 == 0x05
1359                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1360 }
1361
1362 int dap_info_command(struct command_context *cmd_ctx,
1363                 struct swjdp_common *swjdp, int apsel)
1364 {
1365
1366         uint32_t dbgbase, apid;
1367         int romtable_present = 0;
1368         uint8_t mem_ap;
1369         uint32_t apselold;
1370
1371         /* AP address is in bits 31:24 of DP_SELECT */
1372         if (apsel >= 256)
1373                 return ERROR_INVALID_ARGUMENTS;
1374
1375         apselold = swjdp->apsel;
1376         dap_ap_select(swjdp, apsel);
1377         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1378         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1379         jtagdp_transaction_endcheck(swjdp);
1380         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1381         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1382         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1383         if (apid)
1384         {
1385                 switch (apid&0x0F)
1386                 {
1387                         case 0:
1388                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1389                                 break;
1390                         case 1:
1391                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1392                                 break;
1393                         case 2:
1394                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1395                                 break;
1396                         default:
1397                                 command_print(cmd_ctx, "\tUnknown AP type");
1398                                 break;
1399                 }
1400
1401                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1402                  * not a ROM table ... or have no such components at all.
1403                  */
1404                 if (mem_ap)
1405                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1406                                         dbgbase);
1407         }
1408         else
1409         {
1410                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1411         }
1412
1413         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1414         if (romtable_present)
1415         {
1416                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1417                 uint16_t entry_offset;
1418
1419                 /* bit 16 of apid indicates a memory access port */
1420                 if (dbgbase & 0x02)
1421                         command_print(cmd_ctx, "\tValid ROM table present");
1422                 else
1423                         command_print(cmd_ctx, "\tROM table in legacy format");
1424
1425                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1426                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1427                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1428                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1429                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1430                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1431                 jtagdp_transaction_endcheck(swjdp);
1432                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1433                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1434                                         ", CID2 0x%2.2" PRIx32
1435                                         ", CID1 0x%2.2" PRIx32
1436                                         ", CID0 0x%2.2" PRIx32,
1437                                         cid3, cid2, cid1, cid0);
1438                 if (memtype & 0x01)
1439                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1440                 else
1441                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1442                                         "Dedicated debug bus.");
1443
1444                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1445                 entry_offset = 0;
1446                 do
1447                 {
1448                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1449                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1450                         if (romentry&0x01)
1451                         {
1452                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1453                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1454                                 uint32_t component_start, component_base;
1455                                 unsigned part_num;
1456                                 char *type, *full;
1457
1458                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1459                                                 + (int)(romentry & 0xFFFFF000));
1460                                 mem_ap_read_atomic_u32(swjdp,
1461                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1462                                 mem_ap_read_atomic_u32(swjdp,
1463                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1464                                 mem_ap_read_atomic_u32(swjdp,
1465                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1466                                 mem_ap_read_atomic_u32(swjdp,
1467                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1468                                 mem_ap_read_atomic_u32(swjdp,
1469                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1470                                 mem_ap_read_atomic_u32(swjdp,
1471                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1472                                 mem_ap_read_atomic_u32(swjdp,
1473                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1474                                 mem_ap_read_atomic_u32(swjdp,
1475                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1476                                 mem_ap_read_atomic_u32(swjdp,
1477                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1478                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1479
1480                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1481                                                 ", start address 0x%" PRIx32,
1482                                                 component_base, component_start);
1483                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1484                                                 (int) (c_cid1 >> 4) & 0xf,
1485                                                 /* See ARM IHI 0029B Table 3-3 */
1486                                                 class_description[(c_cid1 >> 4) & 0xf]);
1487
1488                                 /* CoreSight component? */
1489                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1490                                         uint32_t devtype;
1491                                         unsigned minor;
1492                                         char *major = "Reserved", *subtype = "Reserved";
1493
1494                                         mem_ap_read_atomic_u32(swjdp,
1495                                                         (component_base & 0xfffff000) | 0xfcc,
1496                                                         &devtype);
1497                                         minor = (devtype >> 4) & 0x0f;
1498                                         switch (devtype & 0x0f) {
1499                                         case 0:
1500                                                 major = "Miscellaneous";
1501                                                 switch (minor) {
1502                                                 case 0:
1503                                                         subtype = "other";
1504                                                         break;
1505                                                 case 4:
1506                                                         subtype = "Validation component";
1507                                                         break;
1508                                                 }
1509                                                 break;
1510                                         case 1:
1511                                                 major = "Trace Sink";
1512                                                 switch (minor) {
1513                                                 case 0:
1514                                                         subtype = "other";
1515                                                         break;
1516                                                 case 1:
1517                                                         subtype = "Port";
1518                                                         break;
1519                                                 case 2:
1520                                                         subtype = "Buffer";
1521                                                         break;
1522                                                 }
1523                                                 break;
1524                                         case 2:
1525                                                 major = "Trace Link";
1526                                                 switch (minor) {
1527                                                 case 0:
1528                                                         subtype = "other";
1529                                                         break;
1530                                                 case 1:
1531                                                         subtype = "Funnel, router";
1532                                                         break;
1533                                                 case 2:
1534                                                         subtype = "Filter";
1535                                                         break;
1536                                                 case 3:
1537                                                         subtype = "FIFO, buffer";
1538                                                         break;
1539                                                 }
1540                                                 break;
1541                                         case 3:
1542                                                 major = "Trace Source";
1543                                                 switch (minor) {
1544                                                 case 0:
1545                                                         subtype = "other";
1546                                                         break;
1547                                                 case 1:
1548                                                         subtype = "Processor";
1549                                                         break;
1550                                                 case 2:
1551                                                         subtype = "DSP";
1552                                                         break;
1553                                                 case 3:
1554                                                         subtype = "Engine/Coprocessor";
1555                                                         break;
1556                                                 case 4:
1557                                                         subtype = "Bus";
1558                                                         break;
1559                                                 }
1560                                                 break;
1561                                         case 4:
1562                                                 major = "Debug Control";
1563                                                 switch (minor) {
1564                                                 case 0:
1565                                                         subtype = "other";
1566                                                         break;
1567                                                 case 1:
1568                                                         subtype = "Trigger Matrix";
1569                                                         break;
1570                                                 case 2:
1571                                                         subtype = "Debug Auth";
1572                                                         break;
1573                                                 }
1574                                                 break;
1575                                         case 5:
1576                                                 major = "Debug Logic";
1577                                                 switch (minor) {
1578                                                 case 0:
1579                                                         subtype = "other";
1580                                                         break;
1581                                                 case 1:
1582                                                         subtype = "Processor";
1583                                                         break;
1584                                                 case 2:
1585                                                         subtype = "DSP";
1586                                                         break;
1587                                                 case 3:
1588                                                         subtype = "Engine/Coprocessor";
1589                                                         break;
1590                                                 }
1591                                                 break;
1592                                         }
1593                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1594                                                         (unsigned) (devtype & 0xff),
1595                                                         major, subtype);
1596                                         /* REVISIT also show 0xfc8 DevId */
1597                                 }
1598
1599                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1600                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1601                                                         ", CID2 0x%2.2" PRIx32
1602                                                         ", CID1 0x%2.2" PRIx32
1603                                                         ", CID0 0x%2.2" PRIx32,
1604                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1605                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1606                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1607                                                 (int) c_pid4,
1608                                                 (int) c_pid3, (int) c_pid2,
1609                                                 (int) c_pid1, (int) c_pid0);
1610
1611                                 /* Part number interpretations are from Cortex
1612                                  * core specs, the CoreSight components TRM
1613                                  * (ARM DDI 0314H), and ETM specs; also from
1614                                  * chip observation (e.g. TI SDTI).
1615                                  */
1616                                 part_num = c_pid0 & 0xff;
1617                                 part_num |= (c_pid1 & 0x0f) << 8;
1618                                 switch (part_num) {
1619                                 case 0x000:
1620                                         type = "Cortex-M3 NVIC";
1621                                         full = "(Interrupt Controller)";
1622                                         break;
1623                                 case 0x001:
1624                                         type = "Cortex-M3 ITM";
1625                                         full = "(Instrumentation Trace Module)";
1626                                         break;
1627                                 case 0x002:
1628                                         type = "Cortex-M3 DWT";
1629                                         full = "(Data Watchpoint and Trace)";
1630                                         break;
1631                                 case 0x003:
1632                                         type = "Cortex-M3 FBP";
1633                                         full = "(Flash Patch and Breakpoint)";
1634                                         break;
1635                                 case 0x00d:
1636                                         type = "CoreSight ETM11";
1637                                         full = "(Embedded Trace)";
1638                                         break;
1639                                 // case 0x113: what?
1640                                 case 0x120:             /* from OMAP3 memmap */
1641                                         type = "TI SDTI";
1642                                         full = "(System Debug Trace Interface)";
1643                                         break;
1644                                 case 0x343:             /* from OMAP3 memmap */
1645                                         type = "TI DAPCTL";
1646                                         full = "";
1647                                         break;
1648                                 case 0x906:
1649                                         type = "Coresight CTI";
1650                                         full = "(Cross Trigger)";
1651                                         break;
1652                                 case 0x907:
1653                                         type = "Coresight ETB";
1654                                         full = "(Trace Buffer)";
1655                                         break;
1656                                 case 0x908:
1657                                         type = "Coresight CSTF";
1658                                         full = "(Trace Funnel)";
1659                                         break;
1660                                 case 0x910:
1661                                         type = "CoreSight ETM9";
1662                                         full = "(Embedded Trace)";
1663                                         break;
1664                                 case 0x912:
1665                                         type = "Coresight TPIU";
1666                                         full = "(Trace Port Interface Unit)";
1667                                         break;
1668                                 case 0x921:
1669                                         type = "Cortex-A8 ETM";
1670                                         full = "(Embedded Trace)";
1671                                         break;
1672                                 case 0x922:
1673                                         type = "Cortex-A8 CTI";
1674                                         full = "(Cross Trigger)";
1675                                         break;
1676                                 case 0x923:
1677                                         type = "Cortex-M3 TPIU";
1678                                         full = "(Trace Port Interface Unit)";
1679                                         break;
1680                                 case 0x924:
1681                                         type = "Cortex-M3 ETM";
1682                                         full = "(Embedded Trace)";
1683                                         break;
1684                                 case 0xc08:
1685                                         type = "Cortex-A8 Debug";
1686                                         full = "(Debug Unit)";
1687                                         break;
1688                                 default:
1689                                         type = "-*- unrecognized -*-";
1690                                         full = "";
1691                                         break;
1692                                 }
1693                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1694                                                 type, full);
1695                         }
1696                         else
1697                         {
1698                                 if (romentry)
1699                                         command_print(cmd_ctx, "\t\tComponent not present");
1700                                 else
1701                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1702                         }
1703                         entry_offset += 4;
1704                 } while (romentry > 0);
1705         }
1706         else
1707         {
1708                 command_print(cmd_ctx, "\tNo ROM table present");
1709         }
1710         dap_ap_select(swjdp, apselold);
1711
1712         return ERROR_OK;
1713 }
1714
1715 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1716 {
1717         uint32_t apsel, apselsave, baseaddr;
1718         int retval;
1719
1720         apselsave = swjdp->apsel;
1721         switch (CMD_ARGC) {
1722         case 0:
1723                 apsel = swjdp->apsel;
1724                 break;
1725         case 1:
1726                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1727                 /* AP address is in bits 31:24 of DP_SELECT */
1728                 if (apsel >= 256)
1729                         return ERROR_INVALID_ARGUMENTS;
1730                 break;
1731         default:
1732                 return ERROR_COMMAND_SYNTAX_ERROR;
1733         }
1734
1735         if (apselsave != apsel)
1736                 dap_ap_select(swjdp, apsel);
1737
1738         /* NOTE:  assumes we're talking to a MEM-AP, which
1739          * has a base address.  There are other kinds of AP,
1740          * though they're not common for now.  This should
1741          * use the ID register to verify it's a MEM-AP.
1742          */
1743         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1744         retval = jtagdp_transaction_endcheck(swjdp);
1745         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1746
1747         if (apselsave != apsel)
1748                 dap_ap_select(swjdp, apselsave);
1749
1750         return retval;
1751 }
1752
1753 DAP_COMMAND_HANDLER(dap_memaccess_command)
1754 {
1755         uint32_t memaccess_tck;
1756
1757         switch (CMD_ARGC) {
1758         case 0:
1759                 memaccess_tck = swjdp->memaccess_tck;
1760                 break;
1761         case 1:
1762                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1763                 break;
1764         default:
1765                 return ERROR_COMMAND_SYNTAX_ERROR;
1766         }
1767         swjdp->memaccess_tck = memaccess_tck;
1768
1769         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1770                         swjdp->memaccess_tck);
1771
1772         return ERROR_OK;
1773 }
1774
1775 DAP_COMMAND_HANDLER(dap_apsel_command)
1776 {
1777         uint32_t apsel, apid;
1778         int retval;
1779
1780         switch (CMD_ARGC) {
1781         case 0:
1782                 apsel = 0;
1783                 break;
1784         case 1:
1785                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1786                 /* AP address is in bits 31:24 of DP_SELECT */
1787                 if (apsel >= 256)
1788                         return ERROR_INVALID_ARGUMENTS;
1789                 break;
1790         default:
1791                 return ERROR_COMMAND_SYNTAX_ERROR;
1792         }
1793
1794         dap_ap_select(swjdp, apsel);
1795         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1796         retval = jtagdp_transaction_endcheck(swjdp);
1797         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1798                         apsel, apid);
1799
1800         return retval;
1801 }
1802
1803 DAP_COMMAND_HANDLER(dap_apid_command)
1804 {
1805         uint32_t apsel, apselsave, apid;
1806         int retval;
1807
1808         apselsave = swjdp->apsel;
1809         switch (CMD_ARGC) {
1810         case 0:
1811                 apsel = swjdp->apsel;
1812                 break;
1813         case 1:
1814                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1815                 /* AP address is in bits 31:24 of DP_SELECT */
1816                 if (apsel >= 256)
1817                         return ERROR_INVALID_ARGUMENTS;
1818                 break;
1819         default:
1820                 return ERROR_COMMAND_SYNTAX_ERROR;
1821         }
1822
1823         if (apselsave != apsel)
1824                 dap_ap_select(swjdp, apsel);
1825
1826         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1827         retval = jtagdp_transaction_endcheck(swjdp);
1828         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1829         if (apselsave != apsel)
1830                 dap_ap_select(swjdp, apselsave);
1831
1832         return retval;
1833 }
1834
1835 /*
1836  * This represents the bits which must be sent out on TMS/SWDIO to
1837  * switch a DAP implemented using an SWJ-DP module into SWD mode.
1838  * These bits are stored (and transmitted) LSB-first.
1839  *
1840  * See the DAP-Lite specification, section 2.2.5 for information
1841  * about making the debug link select SWD or JTAG.  (Similar info
1842  * is in a few other ARM documents.)
1843  */
1844 static const uint8_t jtag2swd_bitseq[] = {
1845         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1846          * putting both JTAG and SWD logic into reset state.
1847          */
1848         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1849         /* Switching sequence enables SWD and disables JTAG
1850          * NOTE: bits in the DP's IDCODE may expose the need for
1851          * an old/deprecated sequence (0xb6 0xed).
1852          */
1853         0x9e, 0xe7,
1854         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1855          * putting both JTAG and SWD logic into reset state.
1856          */
1857         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1858 };
1859
1860 /**
1861  * Put the debug link into SWD mode, if the target supports it.
1862  * The link's initial mode may be either JTAG (for example,
1863  * with SWJ-DP after reset) or SWD.
1864  *
1865  * @param target Enters SWD mode (if possible).
1866  *
1867  * Note that targets using the JTAG-DP do not support SWD, and that
1868  * some targets which could otherwise support it may have have been
1869  * configured to disable SWD signaling
1870  *
1871  * @return ERROR_OK or else a fault code.
1872  */
1873 int dap_to_swd(struct target *target)
1874 {
1875         int retval;
1876
1877         LOG_DEBUG("Enter SWD mode");
1878
1879         /* REVISIT it's nasty to need to make calls to a "jtag"
1880          * subsystem if the link isn't in JTAG mode...
1881          */
1882
1883         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
1884                         jtag2swd_bitseq, TAP_INVALID);
1885         if (retval == ERROR_OK)
1886                 retval = jtag_execute_queue();
1887
1888         /* REVISIT set up the DAP's ops vector for SWD mode. */
1889
1890         return retval;
1891 }
1892
1893 /**
1894  * This represents the bits which must be sent out on TMS/SWDIO to
1895  * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1896  * These bits are stored (and transmitted) LSB-first.
1897  *
1898  * These bits are stored (and transmitted) LSB-first.
1899  */
1900 static const uint8_t swd2jtag_bitseq[] = {
1901         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1902          * putting both JTAG and SWD logic into reset state.
1903          */
1904         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1905         /* Switching equence disables SWD and enables JTAG
1906          * NOTE: bits in the DP's IDCODE can expose the need for
1907          * the old/deprecated sequence (0xae 0xde).
1908          */
1909         0x3c, 0xe7,
1910         /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1911          * putting both JTAG and SWD logic into reset state.
1912          * NOTE:  some docs say "at least 5".
1913          */
1914         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1915 };
1916
1917 /** Put the debug link into JTAG mode, if the target supports it.
1918  * The link's initial mode may be either SWD or JTAG.
1919  *
1920  * @param target Enters JTAG mode (if possible).
1921  *
1922  * Note that targets implemented with SW-DP do not support JTAG, and
1923  * that some targets which could otherwise support it may have been
1924  * configured to disable JTAG signaling
1925  *
1926  * @return ERROR_OK or else a fault code.
1927  */
1928 int dap_to_jtag(struct target *target)
1929 {
1930         int retval;
1931
1932         LOG_DEBUG("Enter JTAG mode");
1933
1934         /* REVISIT it's nasty to need to make calls to a "jtag"
1935          * subsystem if the link isn't in JTAG mode...
1936          */
1937
1938         retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
1939                         swd2jtag_bitseq, TAP_RESET);
1940         if (retval == ERROR_OK)
1941                 retval = jtag_execute_queue();
1942
1943         /* REVISIT set up the DAP's ops vector for JTAG mode. */
1944
1945         return retval;
1946 }