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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76
  77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  78
  79 /*
  80         uint32_t tar_block_size(uint32_t address)
  81         Return the largest block starting at address that does not cross a tar block size alignment boundary
  82 */
  83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  84 {
  85         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  86 }
  87
  88 /***************************************************************************
  89  *                                                                         *
  90  * DP and MEM-AP  register access  through APACC and DPACC                 *
  91  *                                                                         *
  92 ***************************************************************************/
  93
  94 /**
  95  * Select one of the APs connected to the specified DAP.  The
  96  * selection is implicitly used with future AP transactions.
  97  * This is a NOP if the specified AP is already selected.
  98  *
  99  * @param dap The DAP
 100  * @param apsel Number of the AP to (implicitly) use with further
 101  *      transactions.  This normally identifies a MEM-AP.
 102  */
 103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
 104 {
 105         uint32_t select_apsel = (apsel << 24) & 0xFF000000;
 106
 107         if (select_apsel != dap->apsel)
 108         {
 109                 dap->apsel = select_apsel;
 110                 /* Switching AP invalidates cached values.
 111                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 112                  */
 113                 dap->ap_bank_value = -1;
 114                 dap->ap_csw_value = -1;
 115                 dap->ap_tar_value = -1;
 116         }
 117 }
 118
 119 /**
 120  * Queue transactions setting up transfer parameters for the
 121  * currently selected MEM-AP.
 122  *
 123  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 124  * initiate data reads or writes using memory or peripheral addresses.
 125  * If the CSW is configured for it, the TAR may be automatically
 126  * incremented after each transfer.
 127  *
 128  * @todo Rename to reflect it being specifically a MEM-AP function.
 129  *
 130  * @param dap The DAP connected to the MEM-AP.
 131  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 132  *      matches the cached value, the register is not changed.
 133  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 134  *      matches the cached address, the register is not changed.
 135  *
 136  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 137  */
 138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 139 {
 140         int retval;
 141
 142         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 143         if (csw != dap->ap_csw_value)
 144         {
 145                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 146                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 147                 if (retval != ERROR_OK)
 148                         return retval;
 149                 dap->ap_csw_value = csw;
 150         }
 151         if (tar != dap->ap_tar_value)
 152         {
 153                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 154                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 155                 if (retval != ERROR_OK)
 156                         return retval;
 157                 dap->ap_tar_value = tar;
 158         }
 159         /* Disable TAR cache when autoincrementing */
 160         if (csw & CSW_ADDRINC_MASK)
 161                 dap->ap_tar_value = -1;
 162         return ERROR_OK;
 163 }
 164
 165 /**
 166  * Asynchronous (queued) read of a word from memory or a system register.
 167  *
 168  * @param dap The DAP connected to the MEM-AP performing the read.
 169  * @param address Address of the 32-bit word to read; it must be
 170  *      readable by the currently selected MEM-AP.
 171  * @param value points to where the word will be stored when the
 172  *      transaction queue is flushed (assuming no errors).
 173  *
 174  * @return ERROR_OK for success.  Otherwise a fault code.
 175  */
 176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 177                 uint32_t *value)
 178 {
 179         int retval;
 180
 181         /* Use banked addressing (REG_BDx) to avoid some link traffic
 182          * (updating TAR) when reading several consecutive addresses.
 183          */
 184         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 185                         address & 0xFFFFFFF0);
 186         if (retval != ERROR_OK)
 187                 return retval;
 188
 189         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 190 }
 191
 192 /**
 193  * Synchronous read of a word from memory or a system register.
 194  * As a side effect, this flushes any queued transactions.
 195  *
 196  * @param dap The DAP connected to the MEM-AP performing the read.
 197  * @param address Address of the 32-bit word to read; it must be
 198  *      readable by the currently selected MEM-AP.
 199  * @param value points to where the result will be stored.
 200  *
 201  * @return ERROR_OK for success; *value holds the result.
 202  * Otherwise a fault code.
 203  */
 204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 205                 uint32_t *value)
 206 {
 207         int retval;
 208
 209         retval = mem_ap_read_u32(dap, address, value);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         return dap_run(dap);
 214 }
 215
 216 /**
 217  * Asynchronous (queued) write of a word to memory or a system register.
 218  *
 219  * @param dap The DAP connected to the MEM-AP.
 220  * @param address Address to be written; it must be writable by
 221  *      the currently selected MEM-AP.
 222  * @param value Word that will be written to the address when transaction
 223  *      queue is flushed (assuming no errors).
 224  *
 225  * @return ERROR_OK for success.  Otherwise a fault code.
 226  */
 227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 228                 uint32_t value)
 229 {
 230         int retval;
 231
 232         /* Use banked addressing (REG_BDx) to avoid some link traffic
 233          * (updating TAR) when writing several consecutive addresses.
 234          */
 235         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 236                         address & 0xFFFFFFF0);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 241                         value);
 242 }
 243
 244 /**
 245  * Synchronous write of a word to memory or a system register.
 246  * As a side effect, this flushes any queued transactions.
 247  *
 248  * @param dap The DAP connected to the MEM-AP.
 249  * @param address Address to be written; it must be writable by
 250  *      the currently selected MEM-AP.
 251  * @param value Word that will be written.
 252  *
 253  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 254  */
 255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 256                 uint32_t value)
 257 {
 258         int retval = mem_ap_write_u32(dap, address, value);
 259
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         return dap_run(dap);
 264 }
 265
 266 /*****************************************************************************
 267 *                                                                            *
 268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 269 *                                                                            *
 270 * Write a buffer in target order (little endian)                             *
 271 *                                                                            *
 272 *****************************************************************************/
 273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 274 {
 275         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 276         uint32_t adr = address;
 277         uint8_t* pBuffer = buffer;
 278
 279         count >>= 2;
 280         wcount = count;
 281
 282         /* if we have an unaligned access - reorder data */
 283         if (adr & 0x3u)
 284         {
 285                 for (writecount = 0; writecount < count; writecount++)
 286                 {
 287                         int i;
 288                         uint32_t outvalue;
 289                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 290
 291                         for (i = 0; i < 4; i++)
 292                         {
 293                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 294                                 outvalue >>= 8;
 295                                 adr++;
 296                         }
 297                         pBuffer += sizeof(uint32_t);
 298                 }
 299         }
 300
 301         while (wcount > 0)
 302         {
 303                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 304                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 305                 if (wcount < blocksize)
 306                         blocksize = wcount;
 307
 308                 /* handle unaligned data at 4k boundary */
 309                 if (blocksize == 0)
 310                         blocksize = 1;
 311
 312                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315
 316                 for (writecount = 0; writecount < blocksize; writecount++)
 317                 {
 318                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 319                                 *(uint32_t *) (buffer + 4 * writecount));
 320                         if (retval != ERROR_OK)
 321                                 break;
 322                 }
 323
 324                 if (dap_run(dap) == ERROR_OK)
 325                 {
 326                         wcount = wcount - blocksize;
 327                         address = address + 4 * blocksize;
 328                         buffer = buffer + 4 * blocksize;
 329                 }
 330                 else
 331                 {
 332                         errorcount++;
 333                 }
 334
 335                 if (errorcount > 1)
 336                 {
 337                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 338                         /* REVISIT return the *actual* fault code */
 339                         return ERROR_JTAG_DEVICE_ERROR;
 340                 }
 341         }
 342
 343         return retval;
 344 }
 345
 346 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 347                 uint8_t *buffer, int count, uint32_t address)
 348 {
 349         int retval = ERROR_OK;
 350         int wcount, blocksize, writecount, i;
 351
 352         wcount = count >> 1;
 353
 354         while (wcount > 0)
 355         {
 356                 int nbytes;
 357
 358                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 359                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 360
 361                 if (wcount < blocksize)
 362                         blocksize = wcount;
 363
 364                 /* handle unaligned data at 4k boundary */
 365                 if (blocksize == 0)
 366                         blocksize = 1;
 367
 368                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 369                 if (retval != ERROR_OK)
 370                         return retval;
 371                 writecount = blocksize;
 372
 373                 do
 374                 {
 375                         nbytes = MIN((writecount << 1), 4);
 376
 377                         if (nbytes < 4)
 378                         {
 379                                 retval = mem_ap_write_buf_u16(dap, buffer,
 380                                                 nbytes, address);
 381                                 if (retval != ERROR_OK)
 382                                 {
 383                                         LOG_WARNING("Block write error address "
 384                                                 "0x%" PRIx32 ", count 0x%x",
 385                                                 address, count);
 386                                         return retval;
 387                                 }
 388
 389                                 address += nbytes >> 1;
 390                         }
 391                         else
 392                         {
 393                                 uint32_t outvalue;
 394                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 395
 396                                 for (i = 0; i < nbytes; i++)
 397                                 {
 398                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 399                                         outvalue >>= 8;
 400                                         address++;
 401                                 }
 402
 403                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 404                                 retval = dap_queue_ap_write(dap,
 405                                                 AP_REG_DRW, outvalue);
 406                                 if (retval != ERROR_OK)
 407                                         break;
 408
 409                                 if (dap_run(dap) != ERROR_OK)
 410                                 {
 411                                         LOG_WARNING("Block write error address "
 412                                                 "0x%" PRIx32 ", count 0x%x",
 413                                                 address, count);
 414                                         /* REVISIT return *actual* fault code */
 415                                         return ERROR_JTAG_DEVICE_ERROR;
 416                                 }
 417                         }
 418
 419                         buffer += nbytes >> 1;
 420                         writecount -= nbytes >> 1;
 421
 422                 } while (writecount);
 423                 wcount -= blocksize;
 424         }
 425
 426         return retval;
 427 }
 428
 429 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 430 {
 431         int retval = ERROR_OK;
 432
 433         if (count >= 4)
 434                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 435
 436         while (count > 0)
 437         {
 438                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 439                 if (retval != ERROR_OK)
 440                         return retval;
 441                 uint16_t svalue;
 442                 memcpy(&svalue, buffer, sizeof(uint16_t));
 443                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 444                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 445                 if (retval != ERROR_OK)
 446                         break;
 447
 448                 retval = dap_run(dap);
 449                 if (retval != ERROR_OK)
 450                         break;
 451
 452                 count -= 2;
 453                 address += 2;
 454                 buffer += 2;
 455         }
 456
 457         return retval;
 458 }
 459
 460 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 461                 uint8_t *buffer, int count, uint32_t address)
 462 {
 463         int retval = ERROR_OK;
 464         int wcount, blocksize, writecount, i;
 465
 466         wcount = count;
 467
 468         while (wcount > 0)
 469         {
 470                 int nbytes;
 471
 472                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 473                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 474
 475                 if (wcount < blocksize)
 476                         blocksize = wcount;
 477
 478                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 479                 if (retval != ERROR_OK)
 480                         return retval;
 481                 writecount = blocksize;
 482
 483                 do
 484                 {
 485                         nbytes = MIN(writecount, 4);
 486
 487                         if (nbytes < 4)
 488                         {
 489                                 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
 490                                 if (retval != ERROR_OK)
 491                                 {
 492                                         LOG_WARNING("Block write error address "
 493                                                 "0x%" PRIx32 ", count 0x%x",
 494                                                 address, count);
 495                                         return retval;
 496                                 }
 497
 498                                 address += nbytes;
 499                         }
 500                         else
 501                         {
 502                                 uint32_t outvalue;
 503                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 504
 505                                 for (i = 0; i < nbytes; i++)
 506                                 {
 507                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 508                                         outvalue >>= 8;
 509                                         address++;
 510                                 }
 511
 512                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 513                                 retval = dap_queue_ap_write(dap,
 514                                                 AP_REG_DRW, outvalue);
 515                                 if (retval != ERROR_OK)
 516                                         break;
 517
 518                                 if (dap_run(dap) != ERROR_OK)
 519                                 {
 520                                         LOG_WARNING("Block write error address "
 521                                                 "0x%" PRIx32 ", count 0x%x",
 522                                                 address, count);
 523                                         /* REVISIT return *actual* fault code */
 524                                         return ERROR_JTAG_DEVICE_ERROR;
 525                                 }
 526                         }
 527
 528                         buffer += nbytes;
 529                         writecount -= nbytes;
 530
 531                 } while (writecount);
 532                 wcount -= blocksize;
 533         }
 534
 535         return retval;
 536 }
 537
 538 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 539 {
 540         int retval = ERROR_OK;
 541
 542         if (count >= 4)
 543                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 544
 545         while (count > 0)
 546         {
 547                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 548                 if (retval != ERROR_OK)
 549                         return retval;
 550                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 551                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 552                 if (retval != ERROR_OK)
 553                         break;
 554
 555                 retval = dap_run(dap);
 556                 if (retval != ERROR_OK)
 557                         break;
 558
 559                 count--;
 560                 address++;
 561                 buffer++;
 562         }
 563
 564         return retval;
 565 }
 566
 567 /* FIXME don't import ... this is a temporary workaround for the
 568  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 569  */
 570 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 571                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 572                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 573
 574 /**
 575  * Synchronously read a block of 32-bit words into a buffer
 576  * @param dap The DAP connected to the MEM-AP.
 577  * @param buffer where the words will be stored (in host byte order).
 578  * @param count How many words to read.
 579  * @param address Memory address from which to read words; all the
 580  *      words must be readable by the currently selected MEM-AP.
 581  */
 582 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 583                 int count, uint32_t address)
 584 {
 585         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 586         uint32_t adr = address;
 587         uint8_t* pBuffer = buffer;
 588
 589         count >>= 2;
 590         wcount = count;
 591
 592         while (wcount > 0)
 593         {
 594                 /* Adjust to read blocks within boundaries aligned to the
 595                  * TAR autoincrement size (at least 2^10).  Autoincrement
 596                  * mode avoids an extra per-word roundtrip to update TAR.
 597                  */
 598                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 599                                 address);
 600                 if (wcount < blocksize)
 601                         blocksize = wcount;
 602
 603                 /* handle unaligned data at 4k boundary */
 604                 if (blocksize == 0)
 605                         blocksize = 1;
 606
 607                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 608                                 address);
 609                 if (retval != ERROR_OK)
 610                         return retval;
 611
 612                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 613                  * so this routine becomes transport-neutral.  Be careful
 614                  * not to cause performance problems with JTAG; would it
 615                  * suffice to loop over dap_queue_ap_read(), or would that
 616                  * be slower when JTAG is the chosen transport?
 617                  */
 618
 619                 /* Scan out first read */
 620                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 621                                 DPAP_READ, 0, NULL, NULL);
 622                 if (retval != ERROR_OK)
 623                         return retval;
 624                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 625                 {
 626                         /* Scan out next read; scan in posted value for the
 627                          * previous one.  Assumes read is acked "OK/FAULT",
 628                          * and CTRL_STAT says that meant "OK".
 629                          */
 630                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 631                                         DPAP_READ, 0, buffer + 4 * readcount,
 632                                         &dap->ack);
 633                         if (retval != ERROR_OK)
 634                                 return retval;
 635                 }
 636
 637                 /* Scan in last posted value; RDBUFF has no other effect,
 638                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 639                  */
 640                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 641                                 DPAP_READ, 0, buffer + 4 * readcount,
 642                                 &dap->ack);
 643                 if (retval != ERROR_OK)
 644                         return retval;
 645
 646                 retval = dap_run(dap);
 647                 if (retval != ERROR_OK)
 648                 {
 649                         errorcount++;
 650                         if (errorcount <= 1)
 651                         {
 652                                 /* try again */
 653                                 continue;
 654                         }
 655                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 656                         return retval;
 657                 }
 658                 wcount = wcount - blocksize;
 659                 address += 4 * blocksize;
 660                 buffer += 4 * blocksize;
 661         }
 662
 663         /* if we have an unaligned access - reorder data */
 664         if (adr & 0x3u)
 665         {
 666                 for (readcount = 0; readcount < count; readcount++)
 667                 {
 668                         int i;
 669                         uint32_t data;
 670                         memcpy(&data, pBuffer, sizeof(uint32_t));
 671
 672                         for (i = 0; i < 4; i++)
 673                         {
 674                                 *((uint8_t*)pBuffer) =
 675                                                 (data >> 8 * (adr & 0x3));
 676                                 pBuffer++;
 677                                 adr++;
 678                         }
 679                 }
 680         }
 681
 682         return retval;
 683 }
 684
 685 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 686                 uint8_t *buffer, int count, uint32_t address)
 687 {
 688         uint32_t invalue;
 689         int retval = ERROR_OK;
 690         int wcount, blocksize, readcount, i;
 691
 692         wcount = count >> 1;
 693
 694         while (wcount > 0)
 695         {
 696                 int nbytes;
 697
 698                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 699                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 700                 if (wcount < blocksize)
 701                         blocksize = wcount;
 702
 703                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 704                 if (retval != ERROR_OK)
 705                         return retval;
 706
 707                 /* handle unaligned data at 4k boundary */
 708                 if (blocksize == 0)
 709                         blocksize = 1;
 710                 readcount = blocksize;
 711
 712                 do
 713                 {
 714                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 715                         if (dap_run(dap) != ERROR_OK)
 716                         {
 717                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 718                                 /* REVISIT return the *actual* fault code */
 719                                 return ERROR_JTAG_DEVICE_ERROR;
 720                         }
 721
 722                         nbytes = MIN((readcount << 1), 4);
 723
 724                         for (i = 0; i < nbytes; i++)
 725                         {
 726                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 727                                 buffer++;
 728                                 address++;
 729                         }
 730
 731                         readcount -= (nbytes >> 1);
 732                 } while (readcount);
 733                 wcount -= blocksize;
 734         }
 735
 736         return retval;
 737 }
 738
 739 /**
 740  * Synchronously read a block of 16-bit halfwords into a buffer
 741  * @param dap The DAP connected to the MEM-AP.
 742  * @param buffer where the halfwords will be stored (in host byte order).
 743  * @param count How many halfwords to read.
 744  * @param address Memory address from which to read words; all the
 745  *      words must be readable by the currently selected MEM-AP.
 746  */
 747 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 748                 int count, uint32_t address)
 749 {
 750         uint32_t invalue, i;
 751         int retval = ERROR_OK;
 752
 753         if (count >= 4)
 754                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 755
 756         while (count > 0)
 757         {
 758                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 759                 if (retval != ERROR_OK)
 760                         return retval;
 761                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 762                 if (retval != ERROR_OK)
 763                         break;
 764
 765                 retval = dap_run(dap);
 766                 if (retval != ERROR_OK)
 767                         break;
 768
 769                 if (address & 0x1)
 770                 {
 771                         for (i = 0; i < 2; i++)
 772                         {
 773                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 774                                 buffer++;
 775                                 address++;
 776                         }
 777                 }
 778                 else
 779                 {
 780                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 781                         memcpy(buffer, &svalue, sizeof(uint16_t));
 782                         address += 2;
 783                         buffer += 2;
 784                 }
 785                 count -= 2;
 786         }
 787
 788         return retval;
 789 }
 790
 791 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 792  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 793  *
 794  * The solution is to arrange for a large out/in scan in this loop and
 795  * and convert data afterwards.
 796  */
 797 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 798                 uint8_t *buffer, int count, uint32_t address)
 799 {
 800         uint32_t invalue;
 801         int retval = ERROR_OK;
 802         int wcount, blocksize, readcount, i;
 803
 804         wcount = count;
 805
 806         while (wcount > 0)
 807         {
 808                 int nbytes;
 809
 810                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 811                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 812
 813                 if (wcount < blocksize)
 814                         blocksize = wcount;
 815
 816                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 817                 if (retval != ERROR_OK)
 818                         return retval;
 819                 readcount = blocksize;
 820
 821                 do
 822                 {
 823                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 824                         if (dap_run(dap) != ERROR_OK)
 825                         {
 826                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 827                                 /* REVISIT return the *actual* fault code */
 828                                 return ERROR_JTAG_DEVICE_ERROR;
 829                         }
 830
 831                         nbytes = MIN(readcount, 4);
 832
 833                         for (i = 0; i < nbytes; i++)
 834                         {
 835                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 836                                 buffer++;
 837                                 address++;
 838                         }
 839
 840                         readcount -= nbytes;
 841                 } while (readcount);
 842                 wcount -= blocksize;
 843         }
 844
 845         return retval;
 846 }
 847
 848 /**
 849  * Synchronously read a block of bytes into a buffer
 850  * @param dap The DAP connected to the MEM-AP.
 851  * @param buffer where the bytes will be stored.
 852  * @param count How many bytes to read.
 853  * @param address Memory address from which to read data; all the
 854  *      data must be readable by the currently selected MEM-AP.
 855  */
 856 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 857                 int count, uint32_t address)
 858 {
 859         uint32_t invalue;
 860         int retval = ERROR_OK;
 861
 862         if (count >= 4)
 863                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 864
 865         while (count > 0)
 866         {
 867                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 868                 if (retval != ERROR_OK)
 869                         return retval;
 870                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 871                 if (retval != ERROR_OK)
 872                         return retval;
 873                 retval = dap_run(dap);
 874                 if (retval != ERROR_OK)
 875                         break;
 876
 877                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 878                 count--;
 879                 address++;
 880                 buffer++;
 881         }
 882
 883         return retval;
 884 }
 885
 886 /*--------------------------------------------------------------------------*/
 887
 888
 889 /* FIXME don't import ... just initialize as
 890  * part of DAP transport setup
 891 */
 892 extern const struct dap_ops jtag_dp_ops;
 893
 894 /*--------------------------------------------------------------------------*/
 895
 896 /**
 897  * Initialize a DAP.  This sets up the power domains, prepares the DP
 898  * for further use, and arranges to use AP #0 for all AP operations
 899  * until dap_ap-select() changes that policy.
 900  *
 901  * @param dap The DAP being initialized.
 902  *
 903  * @todo Rename this.  We also need an initialization scheme which account
 904  * for SWD transports not just JTAG; that will need to address differences
 905  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 906  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 907  */
 908 int ahbap_debugport_init(struct adiv5_dap *dap)
 909 {
 910         uint32_t idreg, romaddr, dummy;
 911         uint32_t ctrlstat;
 912         int cnt = 0;
 913         int retval;
 914
 915         LOG_DEBUG(" ");
 916
 917         /* JTAG-DP or SWJ-DP, in JTAG mode */
 918         dap->ops = &jtag_dp_ops;
 919
 920         /* Default MEM-AP setup.
 921          *
 922          * REVISIT AP #0 may be an inappropriate default for this.
 923          * Should we probe, or take a hint from the caller?
 924          * Presumably we can ignore the possibility of multiple APs.
 925          */
 926         dap->apsel = !0;
 927         dap_ap_select(dap, 0);
 928
 929         /* DP initialization */
 930
 931         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 932         if (retval != ERROR_OK)
 933                 return retval;
 934
 935         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 936         if (retval != ERROR_OK)
 937                 return retval;
 938
 939         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 940         if (retval != ERROR_OK)
 941                 return retval;
 942
 943         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 944         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 945         if (retval != ERROR_OK)
 946                 return retval;
 947
 948         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 949         if (retval != ERROR_OK)
 950                 return retval;
 951         if ((retval = dap_run(dap)) != ERROR_OK)
 952                 return retval;
 953
 954         /* Check that we have debug power domains activated */
 955         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
 956         {
 957                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 958                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 959                 if (retval != ERROR_OK)
 960                         return retval;
 961                 if ((retval = dap_run(dap)) != ERROR_OK)
 962                         return retval;
 963                 alive_sleep(10);
 964         }
 965
 966         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
 967         {
 968                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 969                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 970                 if (retval != ERROR_OK)
 971                         return retval;
 972                 if ((retval = dap_run(dap)) != ERROR_OK)
 973                         return retval;
 974                 alive_sleep(10);
 975         }
 976
 977         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 978         if (retval != ERROR_OK)
 979                 return retval;
 980         /* With debug power on we can activate OVERRUN checking */
 981         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 982         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 983         if (retval != ERROR_OK)
 984                 return retval;
 985         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 986         if (retval != ERROR_OK)
 987                 return retval;
 988
 989         /*
 990          * REVISIT this isn't actually *initializing* anything in an AP,
 991          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
 992          * Should it?  If the ROM address is valid, is this the right
 993          * place to scan the table and do any topology detection?
 994          */
 995         retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
 996         retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
 997
 998         if ((retval = dap_run(dap)) != ERROR_OK)
 999                 return retval;
1000
1001         LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
1002                 ", Debug ROM Address 0x%" PRIx32,
1003                 dap->apsel, idreg, romaddr);
1004
1005         return ERROR_OK;
1006 }
1007
1008 /* CID interpretation -- see ARM IHI 0029B section 3
1009  * and ARM IHI 0031A table 13-3.
1010  */
1011 static const char *class_description[16] ={
1012         "Reserved", "ROM table", "Reserved", "Reserved",
1013         "Reserved", "Reserved", "Reserved", "Reserved",
1014         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1015         "Reserved", "OptimoDE DESS",
1016                 "Generic IP component", "PrimeCell or System component"
1017 };
1018
1019 static bool
1020 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1021 {
1022         return cid3 == 0xb1 && cid2 == 0x05
1023                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1024 }
1025
1026 static int dap_info_command(struct command_context *cmd_ctx,
1027                 struct adiv5_dap *dap, int apsel)
1028 {
1029         int retval;
1030         uint32_t dbgbase, apid;
1031         int romtable_present = 0;
1032         uint8_t mem_ap;
1033         uint32_t apselold;
1034
1035         /* AP address is in bits 31:24 of DP_SELECT */
1036         if (apsel >= 256)
1037                 return ERROR_INVALID_ARGUMENTS;
1038
1039         apselold = dap->apsel;
1040         dap_ap_select(dap, apsel);
1041         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1042         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1043         retval = dap_run(dap);
1044         if (retval != ERROR_OK)
1045                 return retval;
1046
1047         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1048         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1049         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1050         if (apid)
1051         {
1052                 switch (apid&0x0F)
1053                 {
1054                         case 0:
1055                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1056                                 break;
1057                         case 1:
1058                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1059                                 break;
1060                         case 2:
1061                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1062                                 break;
1063                         default:
1064                                 command_print(cmd_ctx, "\tUnknown AP type");
1065                                 break;
1066                 }
1067
1068                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1069                  * not a ROM table ... or have no such components at all.
1070                  */
1071                 if (mem_ap)
1072                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1073                                         dbgbase);
1074         }
1075         else
1076         {
1077                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1078         }
1079
1080         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1081         if (romtable_present)
1082         {
1083                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1084                 uint16_t entry_offset;
1085
1086                 /* bit 16 of apid indicates a memory access port */
1087                 if (dbgbase & 0x02)
1088                         command_print(cmd_ctx, "\tValid ROM table present");
1089                 else
1090                         command_print(cmd_ctx, "\tROM table in legacy format");
1091
1092                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1093                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1094                 if (retval != ERROR_OK)
1095                         return retval;
1096                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1097                 if (retval != ERROR_OK)
1098                         return retval;
1099                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1100                 if (retval != ERROR_OK)
1101                         return retval;
1102                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1103                 if (retval != ERROR_OK)
1104                         return retval;
1105                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1106                 if (retval != ERROR_OK)
1107                         return retval;
1108                 retval = dap_run(dap);
1109                 if (retval != ERROR_OK)
1110                         return retval;
1111
1112                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1113                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1114                                         ", CID2 0x%2.2x"
1115                                         ", CID1 0x%2.2x"
1116                                         ", CID0 0x%2.2x",
1117                                         (unsigned) cid3, (unsigned)cid2,
1118                                         (unsigned) cid1, (unsigned) cid0);
1119                 if (memtype & 0x01)
1120                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1121                 else
1122                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1123                                         "Dedicated debug bus.");
1124
1125                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1126                 entry_offset = 0;
1127                 do
1128                 {
1129                         retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1130                         if (retval != ERROR_OK)
1131                                 return retval;
1132                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1133                         if (romentry&0x01)
1134                         {
1135                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1136                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1137                                 uint32_t component_base;
1138                                 unsigned part_num;
1139                                 char *type, *full;
1140
1141                                 component_base = (dbgbase & 0xFFFFF000)
1142                                                 + (romentry & 0xFFFFF000);
1143
1144                                 /* IDs are in last 4K section */
1145
1146
1147                                 retval = mem_ap_read_atomic_u32(dap,
1148                                         component_base + 0xFE0, &c_pid0);
1149                                 if (retval != ERROR_OK)
1150                                         return retval;
1151                                 c_pid0 &= 0xff;
1152                                 retval = mem_ap_read_atomic_u32(dap,
1153                                         component_base + 0xFE4, &c_pid1);
1154                                 if (retval != ERROR_OK)
1155                                         return retval;
1156                                 c_pid1 &= 0xff;
1157                                 retval = mem_ap_read_atomic_u32(dap,
1158                                         component_base + 0xFE8, &c_pid2);
1159                                 if (retval != ERROR_OK)
1160                                         return retval;
1161                                 c_pid2 &= 0xff;
1162                                 retval = mem_ap_read_atomic_u32(dap,
1163                                         component_base + 0xFEC, &c_pid3);
1164                                 if (retval != ERROR_OK)
1165                                         return retval;
1166                                 c_pid3 &= 0xff;
1167                                 retval = mem_ap_read_atomic_u32(dap,
1168                                         component_base + 0xFD0, &c_pid4);
1169                                 if (retval != ERROR_OK)
1170                                         return retval;
1171                                 c_pid4 &= 0xff;
1172
1173                                 retval = mem_ap_read_atomic_u32(dap,
1174                                         component_base + 0xFF0, &c_cid0);
1175                                 if (retval != ERROR_OK)
1176                                         return retval;
1177                                 c_cid0 &= 0xff;
1178                                 retval = mem_ap_read_atomic_u32(dap,
1179                                         component_base + 0xFF4, &c_cid1);
1180                                 if (retval != ERROR_OK)
1181                                         return retval;
1182                                 c_cid1 &= 0xff;
1183                                 retval = mem_ap_read_atomic_u32(dap,
1184                                         component_base + 0xFF8, &c_cid2);
1185                                 if (retval != ERROR_OK)
1186                                         return retval;
1187                                 c_cid2 &= 0xff;
1188                                 retval = mem_ap_read_atomic_u32(dap,
1189                                         component_base + 0xFFC, &c_cid3);
1190                                 if (retval != ERROR_OK)
1191                                         return retval;
1192                                 c_cid3 &= 0xff;
1193
1194
1195                                 command_print(cmd_ctx,
1196                                 "\t\tComponent base address 0x%" PRIx32
1197                                         ", start address 0x%" PRIx32,
1198                                                 component_base,
1199                                 /* component may take multiple 4K pages */
1200                                 component_base - 0x1000*(c_pid4 >> 4));
1201                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1202                                                 (int) (c_cid1 >> 4) & 0xf,
1203                                                 /* See ARM IHI 0029B Table 3-3 */
1204                                                 class_description[(c_cid1 >> 4) & 0xf]);
1205
1206                                 /* CoreSight component? */
1207                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1208                                         uint32_t devtype;
1209                                         unsigned minor;
1210                                         char *major = "Reserved", *subtype = "Reserved";
1211
1212                                         retval = mem_ap_read_atomic_u32(dap,
1213                                                         (component_base & 0xfffff000) | 0xfcc,
1214                                                         &devtype);
1215                                         if (retval != ERROR_OK)
1216                                                 return retval;
1217                                         minor = (devtype >> 4) & 0x0f;
1218                                         switch (devtype & 0x0f) {
1219                                         case 0:
1220                                                 major = "Miscellaneous";
1221                                                 switch (minor) {
1222                                                 case 0:
1223                                                         subtype = "other";
1224                                                         break;
1225                                                 case 4:
1226                                                         subtype = "Validation component";
1227                                                         break;
1228                                                 }
1229                                                 break;
1230                                         case 1:
1231                                                 major = "Trace Sink";
1232                                                 switch (minor) {
1233                                                 case 0:
1234                                                         subtype = "other";
1235                                                         break;
1236                                                 case 1:
1237                                                         subtype = "Port";
1238                                                         break;
1239                                                 case 2:
1240                                                         subtype = "Buffer";
1241                                                         break;
1242                                                 }
1243                                                 break;
1244                                         case 2:
1245                                                 major = "Trace Link";
1246                                                 switch (minor) {
1247                                                 case 0:
1248                                                         subtype = "other";
1249                                                         break;
1250                                                 case 1:
1251                                                         subtype = "Funnel, router";
1252                                                         break;
1253                                                 case 2:
1254                                                         subtype = "Filter";
1255                                                         break;
1256                                                 case 3:
1257                                                         subtype = "FIFO, buffer";
1258                                                         break;
1259                                                 }
1260                                                 break;
1261                                         case 3:
1262                                                 major = "Trace Source";
1263                                                 switch (minor) {
1264                                                 case 0:
1265                                                         subtype = "other";
1266                                                         break;
1267                                                 case 1:
1268                                                         subtype = "Processor";
1269                                                         break;
1270                                                 case 2:
1271                                                         subtype = "DSP";
1272                                                         break;
1273                                                 case 3:
1274                                                         subtype = "Engine/Coprocessor";
1275                                                         break;
1276                                                 case 4:
1277                                                         subtype = "Bus";
1278                                                         break;
1279                                                 }
1280                                                 break;
1281                                         case 4:
1282                                                 major = "Debug Control";
1283                                                 switch (minor) {
1284                                                 case 0:
1285                                                         subtype = "other";
1286                                                         break;
1287                                                 case 1:
1288                                                         subtype = "Trigger Matrix";
1289                                                         break;
1290                                                 case 2:
1291                                                         subtype = "Debug Auth";
1292                                                         break;
1293                                                 }
1294                                                 break;
1295                                         case 5:
1296                                                 major = "Debug Logic";
1297                                                 switch (minor) {
1298                                                 case 0:
1299                                                         subtype = "other";
1300                                                         break;
1301                                                 case 1:
1302                                                         subtype = "Processor";
1303                                                         break;
1304                                                 case 2:
1305                                                         subtype = "DSP";
1306                                                         break;
1307                                                 case 3:
1308                                                         subtype = "Engine/Coprocessor";
1309                                                         break;
1310                                                 }
1311                                                 break;
1312                                         }
1313                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1314                                                         (unsigned) (devtype & 0xff),
1315                                                         major, subtype);
1316                                         /* REVISIT also show 0xfc8 DevId */
1317                                 }
1318
1319                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1320                                         command_print(cmd_ctx,
1321                                                       "\t\tCID3 0%2.2x"
1322                                                         ", CID2 0%2.2x"
1323                                                         ", CID1 0%2.2x"
1324                                                         ", CID0 0%2.2x",
1325                                                         (int) c_cid3,
1326                                                         (int) c_cid2,
1327                                                         (int)c_cid1,
1328                                                         (int)c_cid0);
1329                                 command_print(cmd_ctx,
1330                                 "\t\tPeripheral ID[4..0] = hex "
1331                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1332                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1333                                 (int) c_pid1, (int) c_pid0);
1334
1335                                 /* Part number interpretations are from Cortex
1336                                  * core specs, the CoreSight components TRM
1337                                  * (ARM DDI 0314H), and ETM specs; also from
1338                                  * chip observation (e.g. TI SDTI).
1339                                  */
1340                                 part_num = (c_pid0 & 0xff);
1341                                 part_num |= (c_pid1 & 0x0f) << 8;
1342                                 switch (part_num) {
1343                                 case 0x000:
1344                                         type = "Cortex-M3 NVIC";
1345                                         full = "(Interrupt Controller)";
1346                                         break;
1347                                 case 0x001:
1348                                         type = "Cortex-M3 ITM";
1349                                         full = "(Instrumentation Trace Module)";
1350                                         break;
1351                                 case 0x002:
1352                                         type = "Cortex-M3 DWT";
1353                                         full = "(Data Watchpoint and Trace)";
1354                                         break;
1355                                 case 0x003:
1356                                         type = "Cortex-M3 FBP";
1357                                         full = "(Flash Patch and Breakpoint)";
1358                                         break;
1359                                 case 0x00d:
1360                                         type = "CoreSight ETM11";
1361                                         full = "(Embedded Trace)";
1362                                         break;
1363                                 // case 0x113: what?
1364                                 case 0x120:             /* from OMAP3 memmap */
1365                                         type = "TI SDTI";
1366                                         full = "(System Debug Trace Interface)";
1367                                         break;
1368                                 case 0x343:             /* from OMAP3 memmap */
1369                                         type = "TI DAPCTL";
1370                                         full = "";
1371                                         break;
1372                                 case 0x906:
1373                                         type = "Coresight CTI";
1374                                         full = "(Cross Trigger)";
1375                                         break;
1376                                 case 0x907:
1377                                         type = "Coresight ETB";
1378                                         full = "(Trace Buffer)";
1379                                         break;
1380                                 case 0x908:
1381                                         type = "Coresight CSTF";
1382                                         full = "(Trace Funnel)";
1383                                         break;
1384                                 case 0x910:
1385                                         type = "CoreSight ETM9";
1386                                         full = "(Embedded Trace)";
1387                                         break;
1388                                 case 0x912:
1389                                         type = "Coresight TPIU";
1390                                         full = "(Trace Port Interface Unit)";
1391                                         break;
1392                                 case 0x921:
1393                                         type = "Cortex-A8 ETM";
1394                                         full = "(Embedded Trace)";
1395                                         break;
1396                                 case 0x922:
1397                                         type = "Cortex-A8 CTI";
1398                                         full = "(Cross Trigger)";
1399                                         break;
1400                                 case 0x923:
1401                                         type = "Cortex-M3 TPIU";
1402                                         full = "(Trace Port Interface Unit)";
1403                                         break;
1404                                 case 0x924:
1405                                         type = "Cortex-M3 ETM";
1406                                         full = "(Embedded Trace)";
1407                                         break;
1408                                 case 0xc08:
1409                                         type = "Cortex-A8 Debug";
1410                                         full = "(Debug Unit)";
1411                                         break;
1412                                 default:
1413                                         type = "-*- unrecognized -*-";
1414                                         full = "";
1415                                         break;
1416                                 }
1417                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1418                                                 type, full);
1419                         }
1420                         else
1421                         {
1422                                 if (romentry)
1423                                         command_print(cmd_ctx, "\t\tComponent not present");
1424                                 else
1425                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1426                         }
1427                         entry_offset += 4;
1428                 } while (romentry > 0);
1429         }
1430         else
1431         {
1432                 command_print(cmd_ctx, "\tNo ROM table present");
1433         }
1434         dap_ap_select(dap, apselold);
1435
1436         return ERROR_OK;
1437 }
1438
1439 COMMAND_HANDLER(handle_dap_info_command)
1440 {
1441         struct target *target = get_current_target(CMD_CTX);
1442         struct arm *arm = target_to_arm(target);
1443         struct adiv5_dap *dap = arm->dap;
1444         uint32_t apsel;
1445
1446         switch (CMD_ARGC) {
1447         case 0:
1448                 apsel = dap->apsel;
1449                 break;
1450         case 1:
1451                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1452                 break;
1453         default:
1454                 return ERROR_COMMAND_SYNTAX_ERROR;
1455         }
1456
1457         return dap_info_command(CMD_CTX, dap, apsel);
1458 }
1459
1460 COMMAND_HANDLER(dap_baseaddr_command)
1461 {
1462         struct target *target = get_current_target(CMD_CTX);
1463         struct arm *arm = target_to_arm(target);
1464         struct adiv5_dap *dap = arm->dap;
1465
1466         uint32_t apsel, apselsave, baseaddr;
1467         int retval;
1468
1469         apselsave = dap->apsel;
1470         switch (CMD_ARGC) {
1471         case 0:
1472                 apsel = dap->apsel;
1473                 break;
1474         case 1:
1475                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1476                 /* AP address is in bits 31:24 of DP_SELECT */
1477                 if (apsel >= 256)
1478                         return ERROR_INVALID_ARGUMENTS;
1479                 break;
1480         default:
1481                 return ERROR_COMMAND_SYNTAX_ERROR;
1482         }
1483
1484         if (apselsave != apsel)
1485                 dap_ap_select(dap, apsel);
1486
1487         /* NOTE:  assumes we're talking to a MEM-AP, which
1488          * has a base address.  There are other kinds of AP,
1489          * though they're not common for now.  This should
1490          * use the ID register to verify it's a MEM-AP.
1491          */
1492         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1493         retval = dap_run(dap);
1494         if (retval != ERROR_OK)
1495                 return retval;
1496
1497         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1498
1499         if (apselsave != apsel)
1500                 dap_ap_select(dap, apselsave);
1501
1502         return retval;
1503 }
1504
1505 COMMAND_HANDLER(dap_memaccess_command)
1506 {
1507         struct target *target = get_current_target(CMD_CTX);
1508         struct arm *arm = target_to_arm(target);
1509         struct adiv5_dap *dap = arm->dap;
1510
1511         uint32_t memaccess_tck;
1512
1513         switch (CMD_ARGC) {
1514         case 0:
1515                 memaccess_tck = dap->memaccess_tck;
1516                 break;
1517         case 1:
1518                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1519                 break;
1520         default:
1521                 return ERROR_COMMAND_SYNTAX_ERROR;
1522         }
1523         dap->memaccess_tck = memaccess_tck;
1524
1525         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1526                         dap->memaccess_tck);
1527
1528         return ERROR_OK;
1529 }
1530
1531 COMMAND_HANDLER(dap_apsel_command)
1532 {
1533         struct target *target = get_current_target(CMD_CTX);
1534         struct arm *arm = target_to_arm(target);
1535         struct adiv5_dap *dap = arm->dap;
1536
1537         uint32_t apsel, apid;
1538         int retval;
1539
1540         switch (CMD_ARGC) {
1541         case 0:
1542                 apsel = 0;
1543                 break;
1544         case 1:
1545                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1546                 /* AP address is in bits 31:24 of DP_SELECT */
1547                 if (apsel >= 256)
1548                         return ERROR_INVALID_ARGUMENTS;
1549                 break;
1550         default:
1551                 return ERROR_COMMAND_SYNTAX_ERROR;
1552         }
1553
1554         dap_ap_select(dap, apsel);
1555         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1556         retval = dap_run(dap);
1557         if (retval != ERROR_OK)
1558                 return retval;
1559
1560         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1561                         apsel, apid);
1562
1563         return retval;
1564 }
1565
1566 COMMAND_HANDLER(dap_apid_command)
1567 {
1568         struct target *target = get_current_target(CMD_CTX);
1569         struct arm *arm = target_to_arm(target);
1570         struct adiv5_dap *dap = arm->dap;
1571
1572         uint32_t apsel, apselsave, apid;
1573         int retval;
1574
1575         apselsave = dap->apsel;
1576         switch (CMD_ARGC) {
1577         case 0:
1578                 apsel = dap->apsel;
1579                 break;
1580         case 1:
1581                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1582                 /* AP address is in bits 31:24 of DP_SELECT */
1583                 if (apsel >= 256)
1584                         return ERROR_INVALID_ARGUMENTS;
1585                 break;
1586         default:
1587                 return ERROR_COMMAND_SYNTAX_ERROR;
1588         }
1589
1590         if (apselsave != apsel)
1591                 dap_ap_select(dap, apsel);
1592
1593         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1594         retval = dap_run(dap);
1595         if (retval != ERROR_OK)
1596                 return retval;
1597
1598         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1599         if (apselsave != apsel)
1600                 dap_ap_select(dap, apselsave);
1601
1602         return retval;
1603 }
1604
1605 static const struct command_registration dap_commands[] = {
1606         {
1607                 .name = "info",
1608                 .handler = handle_dap_info_command,
1609                 .mode = COMMAND_EXEC,
1610                 .help = "display ROM table for MEM-AP "
1611                         "(default currently selected AP)",
1612                 .usage = "[ap_num]",
1613         },
1614         {
1615                 .name = "apsel",
1616                 .handler = dap_apsel_command,
1617                 .mode = COMMAND_EXEC,
1618                 .help = "Set the currently selected AP (default 0) "
1619                         "and display the result",
1620                 .usage = "[ap_num]",
1621         },
1622         {
1623                 .name = "apid",
1624                 .handler = dap_apid_command,
1625                 .mode = COMMAND_EXEC,
1626                 .help = "return ID register from AP "
1627                         "(default currently selected AP)",
1628                 .usage = "[ap_num]",
1629         },
1630         {
1631                 .name = "baseaddr",
1632                 .handler = dap_baseaddr_command,
1633                 .mode = COMMAND_EXEC,
1634                 .help = "return debug base address from MEM-AP "
1635                         "(default currently selected AP)",
1636                 .usage = "[ap_num]",
1637         },
1638         {
1639                 .name = "memaccess",
1640                 .handler = dap_memaccess_command,
1641                 .mode = COMMAND_EXEC,
1642                 .help = "set/get number of extra tck for MEM-AP memory "
1643                         "bus access [0-255]",
1644                 .usage = "[cycles]",
1645         },
1646         COMMAND_REGISTRATION_DONE
1647 };
1648
1649 const struct command_registration dap_command_handlers[] = {
1650         {
1651                 .name = "dap",
1652                 .mode = COMMAND_EXEC,
1653                 .help = "DAP command group",
1654                 .chain = dap_commands,
1655         },
1656         COMMAND_REGISTRATION_DONE
1657 };
1658
1659