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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 /**
  28  * @file
  29  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  30  * debugging architecture.  Compared with previous versions, this includes
  31  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  32  * transport, and focusses on memory mapped resources as defined by the
  33  * CoreSight architecture.
  34  *
  35  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  36  * basic components:  a Debug Port (DP) transporting messages to and from a
  37  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  38  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  39  * One uses only SWD for communication, and is called SW-DP.  The third can
  40  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  41  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  42  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  43  */
  44
  45 /*
  46  * Relevant specifications from ARM include:
  47  *
  48  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  49  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  50  *
  51  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  52  * Cortex-M3(tm) TRM, ARM DDI 0337G
  53  */
  54
  55 #ifdef HAVE_CONFIG_H
  56 #include "config.h"
  57 #endif
  58
  59 #include "arm_adi_v5.h"
  60 #include <helper/time_support.h>
  61
  62 /*
  63  * Transaction Mode:
  64  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  66  * result checking until swjdp_end_transaction()
  67  * This must be done before using or deallocating any return variables.
  68  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  69  * All reads and writes to the AHB bus are checked for valid completion, and return values
  70  * are immediatley available.
  71 */
  72
  73
  74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  75
  76 /*
  77         uint32_t tar_block_size(uint32_t address)
  78         Return the largest block starting at address that does not cross a tar block size alignment boundary
  79 */
  80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  81 {
  82         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  83 }
  84
  85 /***************************************************************************
  86  *                                                                         *
  87  * DPACC and APACC scanchain access through JTAG-DP                        *
  88  *                                                                         *
  89 ***************************************************************************/
  90
  91 /* Scan out and in from target ordered uint8_t buffers */
  92 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
  93                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
  94                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
  95 {
  96         struct arm_jtag *jtag_info = swjdp->jtag_info;
  97         struct scan_field fields[2];
  98         uint8_t out_addr_buf;
  99
 100         jtag_set_end_state(TAP_IDLE);
 101         arm_jtag_set_instr(jtag_info, instr, NULL);
 102
 103         /* Add specified number of tck clocks before accessing memory bus */
 104         if ((instr == JTAG_DP_APACC)
 105                         && ((reg_addr == AP_REG_DRW)
 106                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 107                         && (swjdp->memaccess_tck != 0))
 108                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 109
 110         fields[0].tap = jtag_info->tap;
 111         fields[0].num_bits = 3;
 112         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 113         fields[0].out_value = &out_addr_buf;
 114         fields[0].in_value = ack;
 115
 116         fields[1].tap = jtag_info->tap;
 117         fields[1].num_bits = 32;
 118         fields[1].out_value = outvalue;
 119         fields[1].in_value = invalue;
 120
 121         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 122
 123         return ERROR_OK;
 124 }
 125
 126 /* Scan out and in from host ordered uint32_t variables */
 127 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 128                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 129                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 130 {
 131         struct arm_jtag *jtag_info = swjdp->jtag_info;
 132         struct scan_field fields[2];
 133         uint8_t out_value_buf[4];
 134         uint8_t out_addr_buf;
 135
 136         jtag_set_end_state(TAP_IDLE);
 137         arm_jtag_set_instr(jtag_info, instr, NULL);
 138
 139         /* Add specified number of tck clocks before accessing memory bus */
 140         if ((instr == JTAG_DP_APACC)
 141                         && ((reg_addr == AP_REG_DRW)
 142                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 143                         && (swjdp->memaccess_tck != 0))
 144                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 145
 146         fields[0].tap = jtag_info->tap;
 147         fields[0].num_bits = 3;
 148         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 149         fields[0].out_value = &out_addr_buf;
 150         fields[0].in_value = ack;
 151
 152         fields[1].tap = jtag_info->tap;
 153         fields[1].num_bits = 32;
 154         buf_set_u32(out_value_buf, 0, 32, outvalue);
 155         fields[1].out_value = out_value_buf;
 156         fields[1].in_value = NULL;
 157
 158         if (invalue)
 159         {
 160                 fields[1].in_value = (uint8_t *)invalue;
 161                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 162
 163                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 164         } else
 165         {
 166
 167                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 168         }
 169
 170         return ERROR_OK;
 171 }
 172
 173 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 174 static int scan_inout_check(struct swjdp_common *swjdp,
 175                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 176                 uint8_t *outvalue, uint8_t *invalue)
 177 {
 178         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 179
 180         if ((RnW == DPAP_READ) && (invalue != NULL))
 181                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 182                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 183
 184         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 185          * ack = OK/FAULT and the check CTRL_STAT
 186          */
 187         if ((instr == JTAG_DP_APACC)
 188                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 189                 return swjdp_transaction_endcheck(swjdp);
 190
 191         return ERROR_OK;
 192 }
 193
 194 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 195                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 196                 uint32_t outvalue, uint32_t *invalue)
 197 {
 198         /* Issue the read or write */
 199         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 200
 201         /* For reads,  collect posted value; RDBUFF has no other effect.
 202          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 203          */
 204         if ((RnW == DPAP_READ) && (invalue != NULL))
 205                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 206                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 207
 208         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 209          * ack = OK/FAULT and then check CTRL_STAT
 210          */
 211         if ((instr == JTAG_DP_APACC)
 212                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 213                 return swjdp_transaction_endcheck(swjdp);
 214
 215         return ERROR_OK;
 216 }
 217
 218 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 219 {
 220         int retval;
 221         uint32_t ctrlstat;
 222
 223         /* too expensive to call keep_alive() here */
 224
 225 #if 0
 226         /* Danger!!!! BROKEN!!!! */
 227         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 228                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 229         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 230         R956 introduced the check on return value here and now Michael Schwingen reports
 231         that this code no longer works....
 232
 233         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 234         */
 235         if ((retval = jtag_execute_queue()) != ERROR_OK)
 236         {
 237                 LOG_ERROR("BUG: Why does this fail the first time????");
 238         }
 239         /* Why??? second time it works??? */
 240 #endif
 241
 242         /* Post CTRL/STAT read; discard any previous posted read value
 243          * but collect its ACK status.
 244          */
 245         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 246                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 247         if ((retval = jtag_execute_queue()) != ERROR_OK)
 248                 return retval;
 249
 250         swjdp->ack = swjdp->ack & 0x7;
 251
 252         if (swjdp->ack != 2)
 253         {
 254                 long long then = timeval_ms();
 255                 while (swjdp->ack != 2)
 256                 {
 257                         if (swjdp->ack == 1)
 258                         {
 259                                 if ((timeval_ms()-then) > 1000)
 260                                 {
 261                                         /* NOTE:  this would be a good spot
 262                                          * to use JTAG_DP_ABORT.
 263                                          */
 264                                         LOG_WARNING("Timeout (1000ms) waiting "
 265                                                 "for ACK=OK/FAULT "
 266                                                 "in JTAG-DP transaction");
 267                                         return ERROR_JTAG_DEVICE_ERROR;
 268                                 }
 269                         }
 270                         else
 271                         {
 272                                 LOG_WARNING("Invalid ACK "
 273                                                 "in JTAG-DP transaction");
 274                                 return ERROR_JTAG_DEVICE_ERROR;
 275                         }
 276
 277                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 278                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 279                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 280                                 return retval;
 281                         swjdp->ack = swjdp->ack & 0x7;
 282                 }
 283         } else
 284         {
 285                 /* common code path avoids fn to timeval_ms() */
 286         }
 287
 288         /* Check for STICKYERR and STICKYORUN */
 289         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 290         {
 291                 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
 292                 /* Check power to debug regions */
 293                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 294                 {
 295                          ahbap_debugport_init(swjdp);
 296                 }
 297                 else
 298                 {
 299                         uint32_t mem_ap_csw, mem_ap_tar;
 300
 301                         /* Print information about last AHBAP access */
 302                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
 303                         if (ctrlstat & SSTICKYORUN)
 304                                 LOG_ERROR("JTAG-DP OVERRUN - "
 305                                         "check clock or reduce jtag speed");
 306
 307                         if (ctrlstat & SSTICKYERR)
 308                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 309
 310                         /* Clear Sticky Error Bits */
 311                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 312                                         DP_CTRL_STAT, DPAP_WRITE,
 313                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 314                                                 | SSTICKYERR, NULL);
 315                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 316                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 317                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 318                                 return retval;
 319
 320                         LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
 321
 322                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 323                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 324                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 325                                 return retval;
 326                         LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
 327
 328                 }
 329                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 330                         return retval;
 331                 return ERROR_JTAG_DEVICE_ERROR;
 332         }
 333
 334         return ERROR_OK;
 335 }
 336
 337 /***************************************************************************
 338  *                                                                         *
 339  * DP and MEM-AP  register access  through APACC and DPACC                 *
 340  *                                                                         *
 341 ***************************************************************************/
 342
 343 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 344                 uint32_t value, uint8_t reg_addr)
 345 {
 346         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 347                         reg_addr, DPAP_WRITE, value, NULL);
 348 }
 349
 350 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 351                 uint32_t *value, uint8_t reg_addr)
 352 {
 353         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 354                         reg_addr, DPAP_READ, 0, value);
 355 }
 356
 357 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 358 {
 359         uint32_t select;
 360         select = (apsel << 24) & 0xFF000000;
 361
 362         if (select != swjdp->apsel)
 363         {
 364                 swjdp->apsel = select;
 365                 /* Switching AP invalidates cached values */
 366                 swjdp->dp_select_value = -1;
 367                 swjdp->ap_csw_value = -1;
 368                 swjdp->ap_tar_value = -1;
 369         }
 370
 371         return ERROR_OK;
 372 }
 373
 374 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 375 {
 376         uint32_t select;
 377         select = (ap_reg & 0x000000F0);
 378
 379         if (select != swjdp->dp_select_value)
 380         {
 381                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 382                 swjdp->dp_select_value = select;
 383         }
 384
 385         return ERROR_OK;
 386 }
 387
 388 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 389                 uint32_t reg_addr, uint8_t *out_value_buf)
 390 {
 391         dap_dp_bankselect(swjdp, reg_addr);
 392         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 393                         DPAP_WRITE, out_value_buf, NULL);
 394
 395         return ERROR_OK;
 396 }
 397
 398 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 399 {
 400         uint8_t out_value_buf[4];
 401
 402         buf_set_u32(out_value_buf, 0, 32, value);
 403         dap_dp_bankselect(swjdp, reg_addr);
 404         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 405                         DPAP_WRITE, out_value_buf, NULL);
 406
 407         return ERROR_OK;
 408 }
 409
 410 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 411 {
 412         dap_dp_bankselect(swjdp, reg_addr);
 413         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 414                         DPAP_READ, 0, value);
 415
 416         return ERROR_OK;
 417 }
 418
 419 /***************************************************************************
 420  *                                                                         *
 421  * AHB-AP access to memory and system registers on AHB bus                 *
 422  *                                                                         *
 423 ***************************************************************************/
 424
 425 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 426 {
 427         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 428         if (csw != swjdp->ap_csw_value)
 429         {
 430                 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
 431                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 432                 swjdp->ap_csw_value = csw;
 433         }
 434         if (tar != swjdp->ap_tar_value)
 435         {
 436                 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
 437                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 438                 swjdp->ap_tar_value = tar;
 439         }
 440         if (csw & CSW_ADDRINC_MASK)
 441         {
 442                 /* Do not cache TAR value when autoincrementing */
 443                 swjdp->ap_tar_value = -1;
 444         }
 445         return ERROR_OK;
 446 }
 447
 448 /*****************************************************************************
 449 *                                                                            *
 450 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 451 *                                                                            *
 452 * Read a uint32_t value from memory or system register                            *
 453 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 454 * but with less overhead                                                     *
 455 *****************************************************************************/
 456 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 457 {
 458         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 459
 460         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 461         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 462
 463         return ERROR_OK;
 464 }
 465
 466 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 467 {
 468         mem_ap_read_u32(swjdp, address, value);
 469
 470         return swjdp_transaction_endcheck(swjdp);
 471 }
 472
 473 /*****************************************************************************
 474 *                                                                            *
 475 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 476 *                                                                            *
 477 * Write a uint32_t value to memory or memory mapped register                              *
 478 *                                                                            *
 479 *****************************************************************************/
 480 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 481 {
 482         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 483
 484         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 485         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 486
 487         return ERROR_OK;
 488 }
 489
 490 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 491 {
 492         mem_ap_write_u32(swjdp, address, value);
 493
 494         return swjdp_transaction_endcheck(swjdp);
 495 }
 496
 497 /*****************************************************************************
 498 *                                                                            *
 499 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 500 *                                                                            *
 501 * Write a buffer in target order (little endian)                             *
 502 *                                                                            *
 503 *****************************************************************************/
 504 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 505 {
 506         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 507         uint32_t adr = address;
 508         uint8_t* pBuffer = buffer;
 509
 510         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 511
 512         count >>= 2;
 513         wcount = count;
 514
 515         /* if we have an unaligned access - reorder data */
 516         if (adr & 0x3u)
 517         {
 518                 for (writecount = 0; writecount < count; writecount++)
 519                 {
 520                         int i;
 521                         uint32_t outvalue;
 522                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 523
 524                         for (i = 0; i < 4; i++)
 525                         {
 526                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 527                                 outvalue >>= 8;
 528                                 adr++;
 529                         }
 530                         pBuffer += sizeof(uint32_t);
 531                 }
 532         }
 533
 534         while (wcount > 0)
 535         {
 536                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 537                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 538                 if (wcount < blocksize)
 539                         blocksize = wcount;
 540
 541                 /* handle unaligned data at 4k boundary */
 542                 if (blocksize == 0)
 543                         blocksize = 1;
 544
 545                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 546
 547                 for (writecount = 0; writecount < blocksize; writecount++)
 548                 {
 549                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 550                 }
 551
 552                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 553                 {
 554                         wcount = wcount - blocksize;
 555                         address = address + 4 * blocksize;
 556                         buffer = buffer + 4 * blocksize;
 557                 }
 558                 else
 559                 {
 560                         errorcount++;
 561                 }
 562
 563                 if (errorcount > 1)
 564                 {
 565                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 566                         return ERROR_JTAG_DEVICE_ERROR;
 567                 }
 568         }
 569
 570         return retval;
 571 }
 572
 573 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 574                 uint8_t *buffer, int count, uint32_t address)
 575 {
 576         int retval = ERROR_OK;
 577         int wcount, blocksize, writecount, i;
 578
 579         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 580
 581         wcount = count >> 1;
 582
 583         while (wcount > 0)
 584         {
 585                 int nbytes;
 586
 587                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 588                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 589
 590                 if (wcount < blocksize)
 591                         blocksize = wcount;
 592
 593                 /* handle unaligned data at 4k boundary */
 594                 if (blocksize == 0)
 595                         blocksize = 1;
 596
 597                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 598                 writecount = blocksize;
 599
 600                 do
 601                 {
 602                         nbytes = MIN((writecount << 1), 4);
 603
 604                         if (nbytes < 4)
 605                         {
 606                                 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
 607                                 {
 608                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 609                                         return ERROR_JTAG_DEVICE_ERROR;
 610                                 }
 611
 612                                 address += nbytes >> 1;
 613                         }
 614                         else
 615                         {
 616                                 uint32_t outvalue;
 617                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 618
 619                                 for (i = 0; i < nbytes; i++)
 620                                 {
 621                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 622                                         outvalue >>= 8;
 623                                         address++;
 624                                 }
 625
 626                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 627                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 628                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 629                                 {
 630                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 631                                         return ERROR_JTAG_DEVICE_ERROR;
 632                                 }
 633                         }
 634
 635                         buffer += nbytes >> 1;
 636                         writecount -= nbytes >> 1;
 637
 638                 } while (writecount);
 639                 wcount -= blocksize;
 640         }
 641
 642         return retval;
 643 }
 644
 645 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 646 {
 647         int retval = ERROR_OK;
 648
 649         if (count >= 4)
 650                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 651
 652         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 653
 654         while (count > 0)
 655         {
 656                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 657                 uint16_t svalue;
 658                 memcpy(&svalue, buffer, sizeof(uint16_t));
 659                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 660                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 661                 retval = swjdp_transaction_endcheck(swjdp);
 662                 count -= 2;
 663                 address += 2;
 664                 buffer += 2;
 665         }
 666
 667         return retval;
 668 }
 669
 670 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 671                 uint8_t *buffer, int count, uint32_t address)
 672 {
 673         int retval = ERROR_OK;
 674         int wcount, blocksize, writecount, i;
 675
 676         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 677
 678         wcount = count;
 679
 680         while (wcount > 0)
 681         {
 682                 int nbytes;
 683
 684                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 685                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 686
 687                 if (wcount < blocksize)
 688                         blocksize = wcount;
 689
 690                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 691                 writecount = blocksize;
 692
 693                 do
 694                 {
 695                         nbytes = MIN(writecount, 4);
 696
 697                         if (nbytes < 4)
 698                         {
 699                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 700                                 {
 701                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 702                                         return ERROR_JTAG_DEVICE_ERROR;
 703                                 }
 704
 705                                 address += nbytes;
 706                         }
 707                         else
 708                         {
 709                                 uint32_t outvalue;
 710                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 711
 712                                 for (i = 0; i < nbytes; i++)
 713                                 {
 714                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 715                                         outvalue >>= 8;
 716                                         address++;
 717                                 }
 718
 719                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 720                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 721                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 722                                 {
 723                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 724                                         return ERROR_JTAG_DEVICE_ERROR;
 725                                 }
 726                         }
 727
 728                         buffer += nbytes;
 729                         writecount -= nbytes;
 730
 731                 } while (writecount);
 732                 wcount -= blocksize;
 733         }
 734
 735         return retval;
 736 }
 737
 738 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 739 {
 740         int retval = ERROR_OK;
 741
 742         if (count >= 4)
 743                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 744
 745         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 746
 747         while (count > 0)
 748         {
 749                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 750                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 751                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 752                 retval = swjdp_transaction_endcheck(swjdp);
 753                 count--;
 754                 address++;
 755                 buffer++;
 756         }
 757
 758         return retval;
 759 }
 760
 761 /*********************************************************************************
 762 *                                                                                *
 763 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 764 *                                                                                *
 765 * Read block fast in target order (little endian) into a buffer                  *
 766 *                                                                                *
 767 **********************************************************************************/
 768 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 769 {
 770         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 771         uint32_t adr = address;
 772         uint8_t* pBuffer = buffer;
 773
 774         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 775
 776         count >>= 2;
 777         wcount = count;
 778
 779         while (wcount > 0)
 780         {
 781                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 782                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 783                 if (wcount < blocksize)
 784                         blocksize = wcount;
 785
 786                 /* handle unaligned data at 4k boundary */
 787                 if (blocksize == 0)
 788                         blocksize = 1;
 789
 790                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 791
 792                 /* Scan out first read */
 793                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 794                                 DPAP_READ, 0, NULL, NULL);
 795                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 796                 {
 797                         /* Scan out next read; scan in posted value for the
 798                          * previous one.  Assumes read is acked "OK/FAULT",
 799                          * and CTRL_STAT says that meant "OK".
 800                          */
 801                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 802                                         DPAP_READ, 0, buffer + 4 * readcount,
 803                                         &swjdp->ack);
 804                 }
 805
 806                 /* Scan in last posted value; RDBUFF has no other effect,
 807                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 808                  */
 809                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 810                                 DPAP_READ, 0, buffer + 4 * readcount,
 811                                 &swjdp->ack);
 812                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 813                 {
 814                         wcount = wcount - blocksize;
 815                         address += 4 * blocksize;
 816                         buffer += 4 * blocksize;
 817                 }
 818                 else
 819                 {
 820                         errorcount++;
 821                 }
 822
 823                 if (errorcount > 1)
 824                 {
 825                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 826                         return ERROR_JTAG_DEVICE_ERROR;
 827                 }
 828         }
 829
 830         /* if we have an unaligned access - reorder data */
 831         if (adr & 0x3u)
 832         {
 833                 for (readcount = 0; readcount < count; readcount++)
 834                 {
 835                         int i;
 836                         uint32_t data;
 837                         memcpy(&data, pBuffer, sizeof(uint32_t));
 838
 839                         for (i = 0; i < 4; i++)
 840                         {
 841                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 842                                 pBuffer++;
 843                                 adr++;
 844                         }
 845                 }
 846         }
 847
 848         return retval;
 849 }
 850
 851 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 852                 uint8_t *buffer, int count, uint32_t address)
 853 {
 854         uint32_t invalue;
 855         int retval = ERROR_OK;
 856         int wcount, blocksize, readcount, i;
 857
 858         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 859
 860         wcount = count >> 1;
 861
 862         while (wcount > 0)
 863         {
 864                 int nbytes;
 865
 866                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 867                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 868                 if (wcount < blocksize)
 869                         blocksize = wcount;
 870
 871                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 872
 873                 /* handle unaligned data at 4k boundary */
 874                 if (blocksize == 0)
 875                         blocksize = 1;
 876                 readcount = blocksize;
 877
 878                 do
 879                 {
 880                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 881                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 882                         {
 883                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 884                                 return ERROR_JTAG_DEVICE_ERROR;
 885                         }
 886
 887                         nbytes = MIN((readcount << 1), 4);
 888
 889                         for (i = 0; i < nbytes; i++)
 890                         {
 891                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 892                                 buffer++;
 893                                 address++;
 894                         }
 895
 896                         readcount -= (nbytes >> 1);
 897                 } while (readcount);
 898                 wcount -= blocksize;
 899         }
 900
 901         return retval;
 902 }
 903
 904 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 905 {
 906         uint32_t invalue, i;
 907         int retval = ERROR_OK;
 908
 909         if (count >= 4)
 910                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 911
 912         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 913
 914         while (count > 0)
 915         {
 916                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 917                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 918                 retval = swjdp_transaction_endcheck(swjdp);
 919                 if (address & 0x1)
 920                 {
 921                         for (i = 0; i < 2; i++)
 922                         {
 923                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 924                                 buffer++;
 925                                 address++;
 926                         }
 927                 }
 928                 else
 929                 {
 930                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 931                         memcpy(buffer, &svalue, sizeof(uint16_t));
 932                         address += 2;
 933                         buffer += 2;
 934                 }
 935                 count -= 2;
 936         }
 937
 938         return retval;
 939 }
 940
 941 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 942  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 943  *
 944  * The solution is to arrange for a large out/in scan in this loop and
 945  * and convert data afterwards.
 946  */
 947 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 948                 uint8_t *buffer, int count, uint32_t address)
 949 {
 950         uint32_t invalue;
 951         int retval = ERROR_OK;
 952         int wcount, blocksize, readcount, i;
 953
 954         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 955
 956         wcount = count;
 957
 958         while (wcount > 0)
 959         {
 960                 int nbytes;
 961
 962                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 963                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 964
 965                 if (wcount < blocksize)
 966                         blocksize = wcount;
 967
 968                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 969                 readcount = blocksize;
 970
 971                 do
 972                 {
 973                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 974                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 975                         {
 976                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 977                                 return ERROR_JTAG_DEVICE_ERROR;
 978                         }
 979
 980                         nbytes = MIN(readcount, 4);
 981
 982                         for (i = 0; i < nbytes; i++)
 983                         {
 984                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 985                                 buffer++;
 986                                 address++;
 987                         }
 988
 989                         readcount -= nbytes;
 990                 } while (readcount);
 991                 wcount -= blocksize;
 992         }
 993
 994         return retval;
 995 }
 996
 997 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 998 {
 999         uint32_t invalue;
1000         int retval = ERROR_OK;
1001
1002         if (count >= 4)
1003                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1004
1005         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1006
1007         while (count > 0)
1008         {
1009                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1010                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1011                 retval = swjdp_transaction_endcheck(swjdp);
1012                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1013                 count--;
1014                 address++;
1015                 buffer++;
1016         }
1017
1018         return retval;
1019 }
1020
1021 /**
1022  * Initialize a DAP.
1023  *
1024  * @todo Rename this.  We also need an initialization scheme which account
1025  * for SWD transports not just JTAG; that will need to address differences
1026  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1027  */
1028 int ahbap_debugport_init(struct swjdp_common *swjdp)
1029 {
1030         uint32_t idreg, romaddr, dummy;
1031         uint32_t ctrlstat;
1032         int cnt = 0;
1033         int retval;
1034
1035         LOG_DEBUG(" ");
1036
1037         /* Default MEM-AP setup.
1038          *
1039          * REVISIT AP #0 may be an inappropriate default for this.
1040          * Should we probe, or receve a hint from the caller?
1041          * Presumably we can ignore the possibility of multiple APs.
1042          */
1043         swjdp->apsel = 0;
1044         swjdp->ap_csw_value = -1;
1045         swjdp->ap_tar_value = -1;
1046
1047         /* DP initialization */
1048         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1049         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1050         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1051         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1052
1053         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1054
1055         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1056         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1057         if ((retval = jtag_execute_queue()) != ERROR_OK)
1058                 return retval;
1059
1060         /* Check that we have debug power domains activated */
1061         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1062         {
1063                 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1064                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1065                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1066                         return retval;
1067                 alive_sleep(10);
1068         }
1069
1070         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1071         {
1072                 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1073                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1074                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1075                         return retval;
1076                 alive_sleep(10);
1077         }
1078
1079         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1080         /* With debug power on we can activate OVERRUN checking */
1081         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1082         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1083         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1084
1085         /*
1086          * REVISIT this isn't actually *initializing* anything in an AP,
1087          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1088          * Should it?  If the ROM address is valid, is this the right
1089          * place to scan the table and do any topology detection?
1090          */
1091         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1092         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1093
1094         LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1095
1096         return ERROR_OK;
1097 }
1098
1099 /* CID interpretation -- see ARM IHI 0029B section 3
1100  * and ARM IHI 0031A table 13-3.
1101  */
1102 static const char *class_description[16] ={
1103         "Reserved", "ROM table", "Reserved", "Reserved",
1104         "Reserved", "Reserved", "Reserved", "Reserved",
1105         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1106         "Reserved", "OptimoDE DESS",
1107                 "Generic IP component", "PrimeCell or System component"
1108 };
1109
1110 static bool
1111 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1112 {
1113         return cid3 == 0xb1 && cid2 == 0x05
1114                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1115 }
1116
1117 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1118 {
1119
1120         uint32_t dbgbase, apid;
1121         int romtable_present = 0;
1122         uint8_t mem_ap;
1123         uint32_t apselold;
1124
1125         apselold = swjdp->apsel;
1126         dap_ap_select(swjdp, apsel);
1127         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1128         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1129         swjdp_transaction_endcheck(swjdp);
1130         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1131         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1132         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1133         if (apid)
1134         {
1135                 switch (apid&0x0F)
1136                 {
1137                         case 0:
1138                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1139                                 break;
1140                         case 1:
1141                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1142                                 break;
1143                         case 2:
1144                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1145                                 break;
1146                         default:
1147                                 command_print(cmd_ctx, "\tUnknown AP type");
1148                                 break;
1149                 }
1150
1151                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1152                  * not a ROM table ... or have no such components at all.
1153                  */
1154                 if (mem_ap)
1155                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1156                                         dbgbase);
1157         }
1158         else
1159         {
1160                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1161         }
1162
1163         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1164         if (romtable_present)
1165         {
1166                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1167                 uint16_t entry_offset;
1168
1169                 /* bit 16 of apid indicates a memory access port */
1170                 if (dbgbase & 0x02)
1171                         command_print(cmd_ctx, "\tValid ROM table present");
1172                 else
1173                         command_print(cmd_ctx, "\tROM table in legacy format");
1174
1175                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1176                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1177                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1178                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1179                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1180                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1181                 swjdp_transaction_endcheck(swjdp);
1182                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1183                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1184                                         ", CID2 0x%2.2" PRIx32
1185                                         ", CID1 0x%2.2" PRIx32
1186                                         ", CID0 0x%2.2" PRIx32,
1187                                         cid3, cid2, cid1, cid0);
1188                 if (memtype & 0x01)
1189                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1190                 else
1191                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1192                                         "Dedicated debug bus.");
1193
1194                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1195                 entry_offset = 0;
1196                 do
1197                 {
1198                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1199                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1200                         if (romentry&0x01)
1201                         {
1202                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1203                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1204                                 uint32_t component_start, component_base;
1205                                 unsigned part_num;
1206                                 char *type, *full;
1207
1208                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1209                                                 + (int)(romentry & 0xFFFFF000));
1210                                 mem_ap_read_atomic_u32(swjdp,
1211                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1212                                 mem_ap_read_atomic_u32(swjdp,
1213                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1214                                 mem_ap_read_atomic_u32(swjdp,
1215                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1216                                 mem_ap_read_atomic_u32(swjdp,
1217                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1218                                 mem_ap_read_atomic_u32(swjdp,
1219                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1220                                 mem_ap_read_atomic_u32(swjdp,
1221                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1222                                 mem_ap_read_atomic_u32(swjdp,
1223                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1224                                 mem_ap_read_atomic_u32(swjdp,
1225                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1226                                 mem_ap_read_atomic_u32(swjdp,
1227                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1228                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1229
1230                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1231                                                 ", start address 0x%" PRIx32,
1232                                                 component_base, component_start);
1233                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1234                                                 (int) (c_cid1 >> 4) & 0xf,
1235                                                 /* See ARM IHI 0029B Table 3-3 */
1236                                                 class_description[(c_cid1 >> 4) & 0xf]);
1237
1238                                 /* CoreSight component? */
1239                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1240                                         uint32_t devtype;
1241                                         unsigned minor;
1242                                         char *major = "Reserved", *subtype = "Reserved";
1243
1244                                         mem_ap_read_atomic_u32(swjdp,
1245                                                         (component_base & 0xfffff000) | 0xfcc,
1246                                                         &devtype);
1247                                         minor = (devtype >> 4) & 0x0f;
1248                                         switch (devtype & 0x0f) {
1249                                         case 0:
1250                                                 major = "Miscellaneous";
1251                                                 switch (minor) {
1252                                                 case 0:
1253                                                         subtype = "other";
1254                                                         break;
1255                                                 case 4:
1256                                                         subtype = "Validation component";
1257                                                         break;
1258                                                 }
1259                                                 break;
1260                                         case 1:
1261                                                 major = "Trace Sink";
1262                                                 switch (minor) {
1263                                                 case 0:
1264                                                         subtype = "other";
1265                                                         break;
1266                                                 case 1:
1267                                                         subtype = "Port";
1268                                                         break;
1269                                                 case 2:
1270                                                         subtype = "Buffer";
1271                                                         break;
1272                                                 }
1273                                                 break;
1274                                         case 2:
1275                                                 major = "Trace Link";
1276                                                 switch (minor) {
1277                                                 case 0:
1278                                                         subtype = "other";
1279                                                         break;
1280                                                 case 1:
1281                                                         subtype = "Funnel, router";
1282                                                         break;
1283                                                 case 2:
1284                                                         subtype = "Filter";
1285                                                         break;
1286                                                 case 3:
1287                                                         subtype = "FIFO, buffer";
1288                                                         break;
1289                                                 }
1290                                                 break;
1291                                         case 3:
1292                                                 major = "Trace Source";
1293                                                 switch (minor) {
1294                                                 case 0:
1295                                                         subtype = "other";
1296                                                         break;
1297                                                 case 1:
1298                                                         subtype = "Processor";
1299                                                         break;
1300                                                 case 2:
1301                                                         subtype = "DSP";
1302                                                         break;
1303                                                 case 3:
1304                                                         subtype = "Engine/Coprocessor";
1305                                                         break;
1306                                                 case 4:
1307                                                         subtype = "Bus";
1308                                                         break;
1309                                                 }
1310                                                 break;
1311                                         case 4:
1312                                                 major = "Debug Control";
1313                                                 switch (minor) {
1314                                                 case 0:
1315                                                         subtype = "other";
1316                                                         break;
1317                                                 case 1:
1318                                                         subtype = "Trigger Matrix";
1319                                                         break;
1320                                                 case 2:
1321                                                         subtype = "Debug Auth";
1322                                                         break;
1323                                                 }
1324                                                 break;
1325                                         case 5:
1326                                                 major = "Debug Logic";
1327                                                 switch (minor) {
1328                                                 case 0:
1329                                                         subtype = "other";
1330                                                         break;
1331                                                 case 1:
1332                                                         subtype = "Processor";
1333                                                         break;
1334                                                 case 2:
1335                                                         subtype = "DSP";
1336                                                         break;
1337                                                 case 3:
1338                                                         subtype = "Engine/Coprocessor";
1339                                                         break;
1340                                                 }
1341                                                 break;
1342                                         }
1343                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1344                                                         (unsigned) (devtype & 0xff),
1345                                                         major, subtype);
1346                                         /* REVISIT also show 0xfc8 DevId */
1347                                 }
1348
1349                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1350                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1351                                                         ", CID2 0x%2.2" PRIx32
1352                                                         ", CID1 0x%2.2" PRIx32
1353                                                         ", CID0 0x%2.2" PRIx32,
1354                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1355                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1356                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1357                                                 (int) c_pid4,
1358                                                 (int) c_pid3, (int) c_pid2,
1359                                                 (int) c_pid1, (int) c_pid0);
1360
1361                                 /* Part number interpretations are from Cortex
1362                                  * core specs, the CoreSight components TRM
1363                                  * (ARM DDI 0314H), and ETM specs; also from
1364                                  * chip observation (e.g. TI SDTI).
1365                                  */
1366                                 part_num = c_pid0 & 0xff;
1367                                 part_num |= (c_pid1 & 0x0f) << 8;
1368                                 switch (part_num) {
1369                                 case 0x000:
1370                                         type = "Cortex-M3 NVIC";
1371                                         full = "(Interrupt Controller)";
1372                                         break;
1373                                 case 0x001:
1374                                         type = "Cortex-M3 ITM";
1375                                         full = "(Instrumentation Trace Module)";
1376                                         break;
1377                                 case 0x002:
1378                                         type = "Cortex-M3 DWT";
1379                                         full = "(Data Watchpoint and Trace)";
1380                                         break;
1381                                 case 0x003:
1382                                         type = "Cortex-M3 FBP";
1383                                         full = "(Flash Patch and Breakpoint)";
1384                                         break;
1385                                 case 0x00d:
1386                                         type = "CoreSight ETM11";
1387                                         full = "(Embedded Trace)";
1388                                         break;
1389                                 // case 0x113: what?
1390                                 case 0x120:             /* from OMAP3 memmap */
1391                                         type = "TI SDTI";
1392                                         full = "(System Debug Trace Interface)";
1393                                         break;
1394                                 case 0x343:             /* from OMAP3 memmap */
1395                                         type = "TI DAPCTL";
1396                                         full = "";
1397                                         break;
1398                                 case 0x4e0:
1399                                         type = "Cortex-M3 ETM";
1400                                         full = "(Embedded Trace)";
1401                                         break;
1402                                 case 0x906:
1403                                         type = "Coresight CTI";
1404                                         full = "(Cross Trigger)";
1405                                         break;
1406                                 case 0x907:
1407                                         type = "Coresight ETB";
1408                                         full = "(Trace Buffer)";
1409                                         break;
1410                                 case 0x908:
1411                                         type = "Coresight CSTF";
1412                                         full = "(Trace Funnel)";
1413                                         break;
1414                                 case 0x910:
1415                                         type = "CoreSight ETM9";
1416                                         full = "(Embedded Trace)";
1417                                         break;
1418                                 case 0x912:
1419                                         type = "Coresight TPIU";
1420                                         full = "(Trace Port Interface Unit)";
1421                                         break;
1422                                 case 0x921:
1423                                         type = "Cortex-A8 ETM";
1424                                         full = "(Embedded Trace)";
1425                                         break;
1426                                 case 0x922:
1427                                         type = "Cortex-A8 CTI";
1428                                         full = "(Cross Trigger)";
1429                                         break;
1430                                 case 0x923:
1431                                         type = "Cortex-M3 TPIU";
1432                                         full = "(Trace Port Interface Unit)";
1433                                         break;
1434                                 case 0xc08:
1435                                         type = "Cortex-A8 Debug";
1436                                         full = "(Debug Unit)";
1437                                         break;
1438                                 default:
1439                                         type = "-*- unrecognized -*-";
1440                                         full = "";
1441                                         break;
1442                                 }
1443                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1444                                                 type, full);
1445                         }
1446                         else
1447                         {
1448                                 if (romentry)
1449                                         command_print(cmd_ctx, "\t\tComponent not present");
1450                                 else
1451                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1452                         }
1453                         entry_offset += 4;
1454                 } while (romentry > 0);
1455         }
1456         else
1457         {
1458                 command_print(cmd_ctx, "\tNo ROM table present");
1459         }
1460         dap_ap_select(swjdp, apselold);
1461
1462         return ERROR_OK;
1463 }
1464
1465 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1466 {
1467         uint32_t apsel, apselsave, baseaddr;
1468         int retval;
1469
1470         apselsave = swjdp->apsel;
1471         switch (CMD_ARGC) {
1472         case 0:
1473                 apsel = swjdp->apsel;
1474                 break;
1475         case 1:
1476                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1477                 break;
1478         default:
1479                 return ERROR_COMMAND_SYNTAX_ERROR;
1480         }
1481
1482         if (apselsave != apsel)
1483                 dap_ap_select(swjdp, apsel);
1484
1485         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1486         retval = swjdp_transaction_endcheck(swjdp);
1487         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1488
1489         if (apselsave != apsel)
1490                 dap_ap_select(swjdp, apselsave);
1491
1492         return retval;
1493 }
1494
1495 DAP_COMMAND_HANDLER(dap_memaccess_command)
1496 {
1497         uint32_t memaccess_tck;
1498
1499         switch (CMD_ARGC) {
1500         case 0:
1501                 memaccess_tck = swjdp->memaccess_tck;
1502                 break;
1503         case 1:
1504                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1505                 break;
1506         default:
1507                 return ERROR_COMMAND_SYNTAX_ERROR;
1508         }
1509         swjdp->memaccess_tck = memaccess_tck;
1510
1511         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1512                         swjdp->memaccess_tck);
1513
1514         return ERROR_OK;
1515 }
1516
1517 DAP_COMMAND_HANDLER(dap_apsel_command)
1518 {
1519         uint32_t apsel, apid;
1520         int retval;
1521
1522         switch (CMD_ARGC) {
1523         case 0:
1524                 apsel = 0;
1525                 break;
1526         case 1:
1527                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1528                 break;
1529         default:
1530                 return ERROR_COMMAND_SYNTAX_ERROR;
1531         }
1532
1533         dap_ap_select(swjdp, apsel);
1534         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1535         retval = swjdp_transaction_endcheck(swjdp);
1536         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1537                         apsel, apid);
1538
1539         return retval;
1540 }
1541
1542 DAP_COMMAND_HANDLER(dap_apid_command)
1543 {
1544         uint32_t apsel, apselsave, apid;
1545         int retval;
1546
1547         apselsave = swjdp->apsel;
1548         switch (CMD_ARGC) {
1549         case 0:
1550                 apsel = swjdp->apsel;
1551                 break;
1552         case 1:
1553                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1554                 break;
1555         default:
1556                 return ERROR_COMMAND_SYNTAX_ERROR;
1557         }
1558
1559         if (apselsave != apsel)
1560                 dap_ap_select(swjdp, apsel);
1561
1562         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1563         retval = swjdp_transaction_endcheck(swjdp);
1564         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1565         if (apselsave != apsel)
1566                 dap_ap_select(swjdp, apselsave);
1567
1568         return retval;
1569 }