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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * @todo Remove modality (queued/nonqueued, via DAP trans_mode) from all
  47  * procedure interfaces.  Modal programming interfaces are very error prone.
  48  * Procedures should be either queued, or synchronous.  Otherwise input
  49  * and output constraints are context-sensitive, and it's hard to know
  50  * what a block of code will do just by reading it.
  51  */
  52
  53 /*
  54  * Relevant specifications from ARM include:
  55  *
  56  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  57  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  58  *
  59  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  60  * Cortex-M3(tm) TRM, ARM DDI 0337G
  61  */
  62
  63 #ifdef HAVE_CONFIG_H
  64 #include "config.h"
  65 #endif
  66
  67 #include "arm_adi_v5.h"
  68 #include <helper/time_support.h>
  69
  70 /*
  71  * Transaction Mode:
  72  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  73  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  74  * result checking until swjdp_end_transaction()
  75  * This must be done before using or deallocating any return variables.
  76  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  77  * All reads and writes to the AHB bus are checked for valid completion, and return values
  78  * are immediatley available.
  79 */
  80
  81
  82 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  83
  84 /*
  85         uint32_t tar_block_size(uint32_t address)
  86         Return the largest block starting at address that does not cross a tar block size alignment boundary
  87 */
  88 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  89 {
  90         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  91 }
  92
  93 /***************************************************************************
  94  *                                                                         *
  95  * DPACC and APACC scanchain access through JTAG-DP                        *
  96  *                                                                         *
  97 ***************************************************************************/
  98
  99 /**
 100  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
 101  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
 102  * discusses operations which access these registers.
 103  *
 104  * Note that only one scan is performed.  If RnW is set, a separate scan
 105  * will be needed to collect the data which was read; the "invalue" collects
 106  * the posted result of a preceding operation, not the current one.
 107  *
 108  * @param swjdp the DAP
 109  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 110  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 111  *      SELECT register has more addressing bits.
 112  * @param RnW false iff outvalue will be written to the DP or AP
 113  * @param outvalue points to a 32-bit (little-endian) integer
 114  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 115  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 116  */
 117 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 118                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 119                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 120 {
 121         struct arm_jtag *jtag_info = swjdp->jtag_info;
 122         struct scan_field fields[2];
 123         uint8_t out_addr_buf;
 124
 125         jtag_set_end_state(TAP_IDLE);
 126         arm_jtag_set_instr(jtag_info, instr, NULL);
 127
 128         /* Add specified number of tck clocks before accessing memory bus */
 129
 130         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 131          * they provide more time for the (MEM) AP to complete the read ...
 132          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 133          */
 134         if ((instr == JTAG_DP_APACC)
 135                         && ((reg_addr == AP_REG_DRW)
 136                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 137                         && (swjdp->memaccess_tck != 0))
 138                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 139
 140         /* Scan out a read or write operation using some DP or AP register.
 141          * For APACC access with any sticky error flag set, this is discarded.
 142          */
 143         fields[0].tap = jtag_info->tap;
 144         fields[0].num_bits = 3;
 145         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 146         fields[0].out_value = &out_addr_buf;
 147         fields[0].in_value = ack;
 148
 149         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 150          * complete; data we write is discarded, data we read is unpredictable.
 151          * When overrun detect is active, STICKYORUN is set.
 152          */
 153
 154         fields[1].tap = jtag_info->tap;
 155         fields[1].num_bits = 32;
 156         fields[1].out_value = outvalue;
 157         fields[1].in_value = invalue;
 158
 159         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 160
 161         return ERROR_OK;
 162 }
 163
 164 /* Scan out and in from host ordered uint32_t variables */
 165 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 166                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 167                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 168 {
 169         struct arm_jtag *jtag_info = swjdp->jtag_info;
 170         struct scan_field fields[2];
 171         uint8_t out_value_buf[4];
 172         uint8_t out_addr_buf;
 173
 174         jtag_set_end_state(TAP_IDLE);
 175         arm_jtag_set_instr(jtag_info, instr, NULL);
 176
 177         /* Add specified number of tck clocks before accessing memory bus */
 178
 179         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 180          * they provide more time for the (MEM) AP to complete the read ...
 181          */
 182         if ((instr == JTAG_DP_APACC)
 183                         && ((reg_addr == AP_REG_DRW)
 184                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 185                         && (swjdp->memaccess_tck != 0))
 186                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 187
 188         fields[0].tap = jtag_info->tap;
 189         fields[0].num_bits = 3;
 190         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 191         fields[0].out_value = &out_addr_buf;
 192         fields[0].in_value = ack;
 193
 194         fields[1].tap = jtag_info->tap;
 195         fields[1].num_bits = 32;
 196         buf_set_u32(out_value_buf, 0, 32, outvalue);
 197         fields[1].out_value = out_value_buf;
 198         fields[1].in_value = NULL;
 199
 200         if (invalue)
 201         {
 202                 fields[1].in_value = (uint8_t *)invalue;
 203                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 204
 205                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 206         } else
 207         {
 208
 209                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 210         }
 211
 212         return ERROR_OK;
 213 }
 214
 215 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 216 static int scan_inout_check(struct swjdp_common *swjdp,
 217                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 218                 uint8_t *outvalue, uint8_t *invalue)
 219 {
 220         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 221
 222         if ((RnW == DPAP_READ) && (invalue != NULL))
 223                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 224                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 225
 226         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 227          * ack = OK/FAULT and the check CTRL_STAT
 228          */
 229         if ((instr == JTAG_DP_APACC)
 230                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 231                 return jtagdp_transaction_endcheck(swjdp);
 232
 233         return ERROR_OK;
 234 }
 235
 236 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 237                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 238                 uint32_t outvalue, uint32_t *invalue)
 239 {
 240         /* Issue the read or write */
 241         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 242
 243         /* For reads,  collect posted value; RDBUFF has no other effect.
 244          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 245          */
 246         if ((RnW == DPAP_READ) && (invalue != NULL))
 247                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 248                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 249
 250         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 251          * ack = OK/FAULT and then check CTRL_STAT
 252          */
 253         if ((instr == JTAG_DP_APACC)
 254                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 255                 return jtagdp_transaction_endcheck(swjdp);
 256
 257         return ERROR_OK;
 258 }
 259
 260 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 261 {
 262         int retval;
 263         uint32_t ctrlstat;
 264
 265         /* too expensive to call keep_alive() here */
 266
 267 #if 0
 268         /* Danger!!!! BROKEN!!!! */
 269         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 270                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 271         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 272         R956 introduced the check on return value here and now Michael Schwingen reports
 273         that this code no longer works....
 274
 275         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 276         */
 277         if ((retval = jtag_execute_queue()) != ERROR_OK)
 278         {
 279                 LOG_ERROR("BUG: Why does this fail the first time????");
 280         }
 281         /* Why??? second time it works??? */
 282 #endif
 283
 284         /* Post CTRL/STAT read; discard any previous posted read value
 285          * but collect its ACK status.
 286          */
 287         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 288                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 289         if ((retval = jtag_execute_queue()) != ERROR_OK)
 290                 return retval;
 291
 292         swjdp->ack = swjdp->ack & 0x7;
 293
 294         /* common code path avoids calling timeval_ms() */
 295         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 296         {
 297                 long long then = timeval_ms();
 298
 299                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 300                 {
 301                         if (swjdp->ack == JTAG_ACK_WAIT)
 302                         {
 303                                 if ((timeval_ms()-then) > 1000)
 304                                 {
 305                                         /* NOTE:  this would be a good spot
 306                                          * to use JTAG_DP_ABORT.
 307                                          */
 308                                         LOG_WARNING("Timeout (1000ms) waiting "
 309                                                 "for ACK=OK/FAULT "
 310                                                 "in JTAG-DP transaction");
 311                                         return ERROR_JTAG_DEVICE_ERROR;
 312                                 }
 313                         }
 314                         else
 315                         {
 316                                 LOG_WARNING("Invalid ACK %#x "
 317                                                 "in JTAG-DP transaction",
 318                                                 swjdp->ack);
 319                                 return ERROR_JTAG_DEVICE_ERROR;
 320                         }
 321
 322                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 323                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 324                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 325                                 return retval;
 326                         swjdp->ack = swjdp->ack & 0x7;
 327                 }
 328         }
 329
 330         /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 331
 332         /* Check for STICKYERR and STICKYORUN */
 333         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 334         {
 335                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 336                 /* Check power to debug regions */
 337                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 338                          ahbap_debugport_init(swjdp);
 339                 else
 340                 {
 341                         uint32_t mem_ap_csw, mem_ap_tar;
 342
 343                         /* Maybe print information about last intended
 344                          * MEM-AP access; but not if autoincrementing.
 345                          * *Real* CSW and TAR values are always shown.
 346                          */
 347                         if (swjdp->ap_tar_value != (uint32_t) -1)
 348                                 LOG_DEBUG("MEM-AP Cached values: "
 349                                         "ap_bank 0x%" PRIx32
 350                                         ", ap_csw 0x%" PRIx32
 351                                         ", ap_tar 0x%" PRIx32,
 352                                         swjdp->ap_bank_value,
 353                                         swjdp->ap_csw_value,
 354                                         swjdp->ap_tar_value);
 355
 356                         if (ctrlstat & SSTICKYORUN)
 357                                 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 358                                         "memaccess, or reduce jtag speed");
 359
 360                         if (ctrlstat & SSTICKYERR)
 361                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 362
 363                         /* Clear Sticky Error Bits */
 364                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 365                                         DP_CTRL_STAT, DPAP_WRITE,
 366                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 367                                                 | SSTICKYERR, NULL);
 368                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 369                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 370                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 371                                 return retval;
 372
 373                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 374
 375                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 376                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 377                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 378                                 return retval;
 379                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 380                                         PRIx32, mem_ap_csw, mem_ap_tar);
 381
 382                 }
 383                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 384                         return retval;
 385                 return ERROR_JTAG_DEVICE_ERROR;
 386         }
 387
 388         return ERROR_OK;
 389 }
 390
 391 /***************************************************************************
 392  *                                                                         *
 393  * DP and MEM-AP  register access  through APACC and DPACC                 *
 394  *                                                                         *
 395 ***************************************************************************/
 396
 397 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 398                 uint32_t value, uint8_t reg_addr)
 399 {
 400         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 401                         reg_addr, DPAP_WRITE, value, NULL);
 402 }
 403
 404 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 405                 uint32_t *value, uint8_t reg_addr)
 406 {
 407         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 408                         reg_addr, DPAP_READ, 0, value);
 409 }
 410
 411 /**
 412  * Select one of the APs connected to the specified DAP.  The
 413  * selection is implicitly used with future AP transactions.
 414  * This is a NOP if the specified AP is already selected.
 415  *
 416  * @param swjdp The DAP
 417  * @param apsel Number of the AP to (implicitly) use with further
 418  *      transactions.  This normally identifies a MEM-AP.
 419  */
 420 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 421 {
 422         uint32_t select = (apsel << 24) & 0xFF000000;
 423
 424         if (select != swjdp->apsel)
 425         {
 426                 swjdp->apsel = select;
 427                 /* Switching AP invalidates cached values.
 428                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 429                  */
 430                 swjdp->ap_bank_value = -1;
 431                 swjdp->ap_csw_value = -1;
 432                 swjdp->ap_tar_value = -1;
 433         }
 434 }
 435
 436 /** Select the AP register bank matching bits 7:4 of ap_reg. */
 437 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 438 {
 439         uint32_t select = (ap_reg & 0x000000F0);
 440
 441         if (select != swjdp->ap_bank_value)
 442         {
 443                 swjdp->ap_bank_value = select;
 444                 select |= swjdp->apsel;
 445                 return dap_dp_write_reg(swjdp, select, DP_SELECT);
 446         } else
 447                 return ERROR_OK;
 448 }
 449
 450 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 451                 uint32_t reg_addr, uint8_t *out_value_buf)
 452 {
 453         int retval;
 454
 455         retval = dap_ap_bankselect(swjdp, reg_addr);
 456         if (retval != ERROR_OK)
 457                 return retval;
 458
 459         return scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 460                         DPAP_WRITE, out_value_buf, NULL);
 461 }
 462
 463 /**
 464  * Write an AP register value.
 465  * This is synchronous iff the mode is set to ATOMIC, in which
 466  * case any queued transactions are flushed.
 467  *
 468  * @param swjdp The DAP whose currently selected AP will be written.
 469  * @param reg_addr Eight bit AP register address.
 470  * @param value Word to be written at reg_addr
 471  *
 472  * @return In synchronous mode: ERROR_OK for success, and the register holds
 473  * the specified value; else a fault code.  In asynchronous mode, a status
 474  * code reflecting whether the transaction was properly queued.
 475  */
 476 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 477                 uint32_t reg_addr, uint32_t value)
 478 {
 479         uint8_t out_value_buf[4];
 480
 481         buf_set_u32(out_value_buf, 0, 32, value);
 482         return dap_ap_write_reg(swjdp,
 483                         reg_addr, out_value_buf);
 484 }
 485
 486 /**
 487  * Read an AP register value.
 488  * This is synchronous iff the mode is set to ATOMIC, in which
 489  * case any queued transactions are flushed.
 490  *
 491  * @param swjdp The DAP whose currently selected AP will be read.
 492  * @param reg_addr Eight bit AP register address.
 493  * @param value Points to where the 32-bit (little-endian) word will be stored.
 494  *
 495  * @return In synchronous mode: ERROR_OK for success, and *value holds
 496  * the specified value; else a fault code.  In asynchronous mode, a status
 497  * code reflecting whether the transaction was properly queued.
 498  */
 499 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 500                 uint32_t reg_addr, uint32_t *value)
 501 {
 502         int retval;
 503
 504         retval = dap_ap_bankselect(swjdp, reg_addr);
 505         if (retval != ERROR_OK)
 506                 return retval;
 507
 508         return scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 509                         DPAP_READ, 0, value);
 510 }
 511
 512 /**
 513  * Set up transfer parameters for the currently selected MEM-AP.
 514  * This is synchronous iff the mode is set to ATOMIC, in which
 515  * case any queued transactions are flushed.
 516  *
 517  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 518  * initiate data reads or writes using memory or peripheral addresses.
 519  * If the CSW is configured for it, the TAR may be automatically
 520  * incremented after each transfer.
 521  *
 522  * @todo Rename to reflect it being specifically a MEM-AP function.
 523  *
 524  * @param swjdp The DAP connected to the MEM-AP.
 525  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 526  *      matches the cached value, the register is not changed.
 527  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 528  *      matches the cached address, the register is not changed.
 529  *
 530  * @return In synchronous mode: ERROR_OK for success, and the AP is set
 531  * up as requested else a fault code.  In asynchronous mode, a status
 532  * code reflecting whether the transaction was properly queued.
 533  */
 534 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 535 {
 536         int retval;
 537
 538         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 539         if (csw != swjdp->ap_csw_value)
 540         {
 541                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 542                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 543                 if (retval != ERROR_OK)
 544                         return retval;
 545                 swjdp->ap_csw_value = csw;
 546         }
 547         if (tar != swjdp->ap_tar_value)
 548         {
 549                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 550                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 551                 if (retval != ERROR_OK)
 552                         return retval;
 553                 swjdp->ap_tar_value = tar;
 554         }
 555         /* Disable TAR cache when autoincrementing */
 556         if (csw & CSW_ADDRINC_MASK)
 557                 swjdp->ap_tar_value = -1;
 558         return ERROR_OK;
 559 }
 560
 561 /**
 562  * Asynchronous (queued) read of a word from memory or a system register.
 563  *
 564  * @param swjdp The DAP connected to the MEM-AP performing the read.
 565  * @param address Address of the 32-bit word to read; it must be
 566  *      readable by the currently selected MEM-AP.
 567  * @param value points to where the word will be stored when the
 568  *      transaction queue is flushed (assuming no errors).
 569  *
 570  * @return ERROR_OK for success.  Otherwise a fault code.
 571  */
 572 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
 573                 uint32_t *value)
 574 {
 575         int retval;
 576
 577         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 578
 579         /* Use banked addressing (REG_BDx) to avoid some link traffic
 580          * (updating TAR) when reading several consecutive addresses.
 581          */
 582         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 583                         address & 0xFFFFFFF0);
 584         if (retval != ERROR_OK)
 585                 return retval;
 586
 587         return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 588 }
 589
 590 /**
 591  * Synchronous read of a word from memory or a system register.
 592  * As a side effect, this flushes any queued transactions.
 593  *
 594  * @param swjdp The DAP connected to the MEM-AP performing the read.
 595  * @param address Address of the 32-bit word to read; it must be
 596  *      readable by the currently selected MEM-AP.
 597  * @param value points to where the result will be stored.
 598  *
 599  * @return ERROR_OK for success; *value holds the result.
 600  * Otherwise a fault code.
 601  */
 602 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 603                 uint32_t *value)
 604 {
 605         int retval;
 606
 607         retval = mem_ap_read_u32(swjdp, address, value);
 608         if (retval != ERROR_OK)
 609                 return retval;
 610
 611         return jtagdp_transaction_endcheck(swjdp);
 612 }
 613
 614 /**
 615  * Asynchronous (queued) write of a word to memory or a system register.
 616  *
 617  * @param swjdp The DAP connected to the MEM-AP.
 618  * @param address Address to be written; it must be writable by
 619  *      the currently selected MEM-AP.
 620  * @param value Word that will be written to the address when transaction
 621  *      queue is flushed (assuming no errors).
 622  *
 623  * @return ERROR_OK for success.  Otherwise a fault code.
 624  */
 625 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
 626                 uint32_t value)
 627 {
 628         int retval;
 629
 630         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 631
 632         /* Use banked addressing (REG_BDx) to avoid some link traffic
 633          * (updating TAR) when writing several consecutive addresses.
 634          */
 635         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 636                         address & 0xFFFFFFF0);
 637         if (retval != ERROR_OK)
 638                 return retval;
 639
 640         return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
 641                         value);
 642 }
 643
 644 /**
 645  * Synchronous write of a word to memory or a system register.
 646  * As a side effect, this flushes any queued transactions.
 647  *
 648  * @param swjdp The DAP connected to the MEM-AP.
 649  * @param address Address to be written; it must be writable by
 650  *      the currently selected MEM-AP.
 651  * @param value Word that will be written.
 652  *
 653  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 654  */
 655 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 656                 uint32_t value)
 657 {
 658         int retval = mem_ap_write_u32(swjdp, address, value);
 659
 660         if (retval != ERROR_OK)
 661                 return retval;
 662
 663         return jtagdp_transaction_endcheck(swjdp);
 664 }
 665
 666 /*****************************************************************************
 667 *                                                                            *
 668 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 669 *                                                                            *
 670 * Write a buffer in target order (little endian)                             *
 671 *                                                                            *
 672 *****************************************************************************/
 673 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 674 {
 675         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 676         uint32_t adr = address;
 677         uint8_t* pBuffer = buffer;
 678
 679         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 680
 681         count >>= 2;
 682         wcount = count;
 683
 684         /* if we have an unaligned access - reorder data */
 685         if (adr & 0x3u)
 686         {
 687                 for (writecount = 0; writecount < count; writecount++)
 688                 {
 689                         int i;
 690                         uint32_t outvalue;
 691                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 692
 693                         for (i = 0; i < 4; i++)
 694                         {
 695                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 696                                 outvalue >>= 8;
 697                                 adr++;
 698                         }
 699                         pBuffer += sizeof(uint32_t);
 700                 }
 701         }
 702
 703         while (wcount > 0)
 704         {
 705                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 706                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 707                 if (wcount < blocksize)
 708                         blocksize = wcount;
 709
 710                 /* handle unaligned data at 4k boundary */
 711                 if (blocksize == 0)
 712                         blocksize = 1;
 713
 714                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 715
 716                 for (writecount = 0; writecount < blocksize; writecount++)
 717                 {
 718                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 719                 }
 720
 721                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 722                 {
 723                         wcount = wcount - blocksize;
 724                         address = address + 4 * blocksize;
 725                         buffer = buffer + 4 * blocksize;
 726                 }
 727                 else
 728                 {
 729                         errorcount++;
 730                 }
 731
 732                 if (errorcount > 1)
 733                 {
 734                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 735                         return ERROR_JTAG_DEVICE_ERROR;
 736                 }
 737         }
 738
 739         return retval;
 740 }
 741
 742 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 743                 uint8_t *buffer, int count, uint32_t address)
 744 {
 745         int retval = ERROR_OK;
 746         int wcount, blocksize, writecount, i;
 747
 748         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 749
 750         wcount = count >> 1;
 751
 752         while (wcount > 0)
 753         {
 754                 int nbytes;
 755
 756                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 757                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 758
 759                 if (wcount < blocksize)
 760                         blocksize = wcount;
 761
 762                 /* handle unaligned data at 4k boundary */
 763                 if (blocksize == 0)
 764                         blocksize = 1;
 765
 766                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 767                 writecount = blocksize;
 768
 769                 do
 770                 {
 771                         nbytes = MIN((writecount << 1), 4);
 772
 773                         if (nbytes < 4)
 774                         {
 775                                 if (mem_ap_write_buf_u16(swjdp, buffer,
 776                                                 nbytes, address) != ERROR_OK)
 777                                 {
 778                                         LOG_WARNING("Block write error address "
 779                                                 "0x%" PRIx32 ", count 0x%x",
 780                                                 address, count);
 781                                         return ERROR_JTAG_DEVICE_ERROR;
 782                                 }
 783
 784                                 address += nbytes >> 1;
 785                         }
 786                         else
 787                         {
 788                                 uint32_t outvalue;
 789                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 790
 791                                 for (i = 0; i < nbytes; i++)
 792                                 {
 793                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 794                                         outvalue >>= 8;
 795                                         address++;
 796                                 }
 797
 798                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 799                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 800                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 801                                 {
 802                                         LOG_WARNING("Block write error address "
 803                                                 "0x%" PRIx32 ", count 0x%x",
 804                                                 address, count);
 805                                         return ERROR_JTAG_DEVICE_ERROR;
 806                                 }
 807                         }
 808
 809                         buffer += nbytes >> 1;
 810                         writecount -= nbytes >> 1;
 811
 812                 } while (writecount);
 813                 wcount -= blocksize;
 814         }
 815
 816         return retval;
 817 }
 818
 819 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 820 {
 821         int retval = ERROR_OK;
 822
 823         if (count >= 4)
 824                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 825
 826         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 827
 828         while (count > 0)
 829         {
 830                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 831                 uint16_t svalue;
 832                 memcpy(&svalue, buffer, sizeof(uint16_t));
 833                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 834                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 835                 retval = jtagdp_transaction_endcheck(swjdp);
 836                 count -= 2;
 837                 address += 2;
 838                 buffer += 2;
 839         }
 840
 841         return retval;
 842 }
 843
 844 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 845                 uint8_t *buffer, int count, uint32_t address)
 846 {
 847         int retval = ERROR_OK;
 848         int wcount, blocksize, writecount, i;
 849
 850         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 851
 852         wcount = count;
 853
 854         while (wcount > 0)
 855         {
 856                 int nbytes;
 857
 858                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 859                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 860
 861                 if (wcount < blocksize)
 862                         blocksize = wcount;
 863
 864                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 865                 writecount = blocksize;
 866
 867                 do
 868                 {
 869                         nbytes = MIN(writecount, 4);
 870
 871                         if (nbytes < 4)
 872                         {
 873                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 874                                 {
 875                                         LOG_WARNING("Block write error address "
 876                                                 "0x%" PRIx32 ", count 0x%x",
 877                                                 address, count);
 878                                         return ERROR_JTAG_DEVICE_ERROR;
 879                                 }
 880
 881                                 address += nbytes;
 882                         }
 883                         else
 884                         {
 885                                 uint32_t outvalue;
 886                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 887
 888                                 for (i = 0; i < nbytes; i++)
 889                                 {
 890                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 891                                         outvalue >>= 8;
 892                                         address++;
 893                                 }
 894
 895                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 896                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 897                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 898                                 {
 899                                         LOG_WARNING("Block write error address "
 900                                                 "0x%" PRIx32 ", count 0x%x",
 901                                                 address, count);
 902                                         return ERROR_JTAG_DEVICE_ERROR;
 903                                 }
 904                         }
 905
 906                         buffer += nbytes;
 907                         writecount -= nbytes;
 908
 909                 } while (writecount);
 910                 wcount -= blocksize;
 911         }
 912
 913         return retval;
 914 }
 915
 916 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 917 {
 918         int retval = ERROR_OK;
 919
 920         if (count >= 4)
 921                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 922
 923         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 924
 925         while (count > 0)
 926         {
 927                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 928                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 929                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 930                 retval = jtagdp_transaction_endcheck(swjdp);
 931                 count--;
 932                 address++;
 933                 buffer++;
 934         }
 935
 936         return retval;
 937 }
 938
 939 /*********************************************************************************
 940 *                                                                                *
 941 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 942 *                                                                                *
 943 * Read block fast in target order (little endian) into a buffer                  *
 944 *                                                                                *
 945 **********************************************************************************/
 946 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 947 {
 948         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 949         uint32_t adr = address;
 950         uint8_t* pBuffer = buffer;
 951
 952         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 953
 954         count >>= 2;
 955         wcount = count;
 956
 957         while (wcount > 0)
 958         {
 959                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 960                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 961                 if (wcount < blocksize)
 962                         blocksize = wcount;
 963
 964                 /* handle unaligned data at 4k boundary */
 965                 if (blocksize == 0)
 966                         blocksize = 1;
 967
 968                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 969
 970                 /* Scan out first read */
 971                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 972                                 DPAP_READ, 0, NULL, NULL);
 973                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 974                 {
 975                         /* Scan out next read; scan in posted value for the
 976                          * previous one.  Assumes read is acked "OK/FAULT",
 977                          * and CTRL_STAT says that meant "OK".
 978                          */
 979                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 980                                         DPAP_READ, 0, buffer + 4 * readcount,
 981                                         &swjdp->ack);
 982                 }
 983
 984                 /* Scan in last posted value; RDBUFF has no other effect,
 985                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 986                  */
 987                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 988                                 DPAP_READ, 0, buffer + 4 * readcount,
 989                                 &swjdp->ack);
 990                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 991                 {
 992                         wcount = wcount - blocksize;
 993                         address += 4 * blocksize;
 994                         buffer += 4 * blocksize;
 995                 }
 996                 else
 997                 {
 998                         errorcount++;
 999                 }
1000
1001                 if (errorcount > 1)
1002                 {
1003                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1004                         return ERROR_JTAG_DEVICE_ERROR;
1005                 }
1006         }
1007
1008         /* if we have an unaligned access - reorder data */
1009         if (adr & 0x3u)
1010         {
1011                 for (readcount = 0; readcount < count; readcount++)
1012                 {
1013                         int i;
1014                         uint32_t data;
1015                         memcpy(&data, pBuffer, sizeof(uint32_t));
1016
1017                         for (i = 0; i < 4; i++)
1018                         {
1019                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
1020                                 pBuffer++;
1021                                 adr++;
1022                         }
1023                 }
1024         }
1025
1026         return retval;
1027 }
1028
1029 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
1030                 uint8_t *buffer, int count, uint32_t address)
1031 {
1032         uint32_t invalue;
1033         int retval = ERROR_OK;
1034         int wcount, blocksize, readcount, i;
1035
1036         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1037
1038         wcount = count >> 1;
1039
1040         while (wcount > 0)
1041         {
1042                 int nbytes;
1043
1044                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1045                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1046                 if (wcount < blocksize)
1047                         blocksize = wcount;
1048
1049                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
1050
1051                 /* handle unaligned data at 4k boundary */
1052                 if (blocksize == 0)
1053                         blocksize = 1;
1054                 readcount = blocksize;
1055
1056                 do
1057                 {
1058                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1059                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1060                         {
1061                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1062                                 return ERROR_JTAG_DEVICE_ERROR;
1063                         }
1064
1065                         nbytes = MIN((readcount << 1), 4);
1066
1067                         for (i = 0; i < nbytes; i++)
1068                         {
1069                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1070                                 buffer++;
1071                                 address++;
1072                         }
1073
1074                         readcount -= (nbytes >> 1);
1075                 } while (readcount);
1076                 wcount -= blocksize;
1077         }
1078
1079         return retval;
1080 }
1081
1082 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1083 {
1084         uint32_t invalue, i;
1085         int retval = ERROR_OK;
1086
1087         if (count >= 4)
1088                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1089
1090         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1091
1092         while (count > 0)
1093         {
1094                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1095                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1096                 retval = jtagdp_transaction_endcheck(swjdp);
1097                 if (address & 0x1)
1098                 {
1099                         for (i = 0; i < 2; i++)
1100                         {
1101                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1102                                 buffer++;
1103                                 address++;
1104                         }
1105                 }
1106                 else
1107                 {
1108                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
1109                         memcpy(buffer, &svalue, sizeof(uint16_t));
1110                         address += 2;
1111                         buffer += 2;
1112                 }
1113                 count -= 2;
1114         }
1115
1116         return retval;
1117 }
1118
1119 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1120  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1121  *
1122  * The solution is to arrange for a large out/in scan in this loop and
1123  * and convert data afterwards.
1124  */
1125 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1126                 uint8_t *buffer, int count, uint32_t address)
1127 {
1128         uint32_t invalue;
1129         int retval = ERROR_OK;
1130         int wcount, blocksize, readcount, i;
1131
1132         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1133
1134         wcount = count;
1135
1136         while (wcount > 0)
1137         {
1138                 int nbytes;
1139
1140                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1141                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1142
1143                 if (wcount < blocksize)
1144                         blocksize = wcount;
1145
1146                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1147                 readcount = blocksize;
1148
1149                 do
1150                 {
1151                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1152                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1153                         {
1154                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1155                                 return ERROR_JTAG_DEVICE_ERROR;
1156                         }
1157
1158                         nbytes = MIN(readcount, 4);
1159
1160                         for (i = 0; i < nbytes; i++)
1161                         {
1162                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1163                                 buffer++;
1164                                 address++;
1165                         }
1166
1167                         readcount -= nbytes;
1168                 } while (readcount);
1169                 wcount -= blocksize;
1170         }
1171
1172         return retval;
1173 }
1174
1175 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1176 {
1177         uint32_t invalue;
1178         int retval = ERROR_OK;
1179
1180         if (count >= 4)
1181                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1182
1183         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1184
1185         while (count > 0)
1186         {
1187                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1188                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1189                 retval = jtagdp_transaction_endcheck(swjdp);
1190                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1191                 count--;
1192                 address++;
1193                 buffer++;
1194         }
1195
1196         return retval;
1197 }
1198
1199 /**
1200  * Initialize a DAP.  This sets up the power domains, prepares the DP
1201  * for further use, and arranges to use AP #0 for all AP operations
1202  * until dap_ap-select() changes that policy.
1203  *
1204  * @param swjdp The DAP being initialized.
1205  *
1206  * @todo Rename this.  We also need an initialization scheme which account
1207  * for SWD transports not just JTAG; that will need to address differences
1208  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1209  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1210  */
1211 int ahbap_debugport_init(struct swjdp_common *swjdp)
1212 {
1213         uint32_t idreg, romaddr, dummy;
1214         uint32_t ctrlstat;
1215         int cnt = 0;
1216         int retval;
1217
1218         LOG_DEBUG(" ");
1219
1220         /* Default MEM-AP setup.
1221          *
1222          * REVISIT AP #0 may be an inappropriate default for this.
1223          * Should we probe, or take a hint from the caller?
1224          * Presumably we can ignore the possibility of multiple APs.
1225          */
1226         swjdp->apsel = !0;
1227         dap_ap_select(swjdp, 0);
1228
1229         /* DP initialization */
1230         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1231         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1232         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1233         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1234
1235         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1236
1237         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1238         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1239         if ((retval = jtag_execute_queue()) != ERROR_OK)
1240                 return retval;
1241
1242         /* Check that we have debug power domains activated */
1243         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1244         {
1245                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1246                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1247                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1248                         return retval;
1249                 alive_sleep(10);
1250         }
1251
1252         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1253         {
1254                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1255                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1256                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1257                         return retval;
1258                 alive_sleep(10);
1259         }
1260
1261         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1262         /* With debug power on we can activate OVERRUN checking */
1263         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1264         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1265         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1266
1267         /*
1268          * REVISIT this isn't actually *initializing* anything in an AP,
1269          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1270          * Should it?  If the ROM address is valid, is this the right
1271          * place to scan the table and do any topology detection?
1272          */
1273         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1274         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1275
1276         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1277                 ", Debug ROM Address 0x%" PRIx32,
1278                 swjdp->apsel, idreg, romaddr);
1279
1280         return ERROR_OK;
1281 }
1282
1283 /* CID interpretation -- see ARM IHI 0029B section 3
1284  * and ARM IHI 0031A table 13-3.
1285  */
1286 static const char *class_description[16] ={
1287         "Reserved", "ROM table", "Reserved", "Reserved",
1288         "Reserved", "Reserved", "Reserved", "Reserved",
1289         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1290         "Reserved", "OptimoDE DESS",
1291                 "Generic IP component", "PrimeCell or System component"
1292 };
1293
1294 static bool
1295 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1296 {
1297         return cid3 == 0xb1 && cid2 == 0x05
1298                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1299 }
1300
1301 int dap_info_command(struct command_context *cmd_ctx,
1302                 struct swjdp_common *swjdp, int apsel)
1303 {
1304
1305         uint32_t dbgbase, apid;
1306         int romtable_present = 0;
1307         uint8_t mem_ap;
1308         uint32_t apselold;
1309
1310         /* AP address is in bits 31:24 of DP_SELECT */
1311         if (apsel >= 256)
1312                 return ERROR_INVALID_ARGUMENTS;
1313
1314         apselold = swjdp->apsel;
1315         dap_ap_select(swjdp, apsel);
1316         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1317         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1318         jtagdp_transaction_endcheck(swjdp);
1319         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1320         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1321         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1322         if (apid)
1323         {
1324                 switch (apid&0x0F)
1325                 {
1326                         case 0:
1327                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1328                                 break;
1329                         case 1:
1330                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1331                                 break;
1332                         case 2:
1333                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1334                                 break;
1335                         default:
1336                                 command_print(cmd_ctx, "\tUnknown AP type");
1337                                 break;
1338                 }
1339
1340                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1341                  * not a ROM table ... or have no such components at all.
1342                  */
1343                 if (mem_ap)
1344                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1345                                         dbgbase);
1346         }
1347         else
1348         {
1349                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1350         }
1351
1352         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1353         if (romtable_present)
1354         {
1355                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1356                 uint16_t entry_offset;
1357
1358                 /* bit 16 of apid indicates a memory access port */
1359                 if (dbgbase & 0x02)
1360                         command_print(cmd_ctx, "\tValid ROM table present");
1361                 else
1362                         command_print(cmd_ctx, "\tROM table in legacy format");
1363
1364                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1365                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1366                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1367                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1368                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1369                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1370                 jtagdp_transaction_endcheck(swjdp);
1371                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1372                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1373                                         ", CID2 0x%2.2" PRIx32
1374                                         ", CID1 0x%2.2" PRIx32
1375                                         ", CID0 0x%2.2" PRIx32,
1376                                         cid3, cid2, cid1, cid0);
1377                 if (memtype & 0x01)
1378                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1379                 else
1380                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1381                                         "Dedicated debug bus.");
1382
1383                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1384                 entry_offset = 0;
1385                 do
1386                 {
1387                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1388                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1389                         if (romentry&0x01)
1390                         {
1391                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1392                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1393                                 uint32_t component_start, component_base;
1394                                 unsigned part_num;
1395                                 char *type, *full;
1396
1397                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1398                                                 + (int)(romentry & 0xFFFFF000));
1399                                 mem_ap_read_atomic_u32(swjdp,
1400                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1401                                 mem_ap_read_atomic_u32(swjdp,
1402                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1403                                 mem_ap_read_atomic_u32(swjdp,
1404                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1405                                 mem_ap_read_atomic_u32(swjdp,
1406                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1407                                 mem_ap_read_atomic_u32(swjdp,
1408                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1409                                 mem_ap_read_atomic_u32(swjdp,
1410                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1411                                 mem_ap_read_atomic_u32(swjdp,
1412                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1413                                 mem_ap_read_atomic_u32(swjdp,
1414                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1415                                 mem_ap_read_atomic_u32(swjdp,
1416                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1417                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1418
1419                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1420                                                 ", start address 0x%" PRIx32,
1421                                                 component_base, component_start);
1422                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1423                                                 (int) (c_cid1 >> 4) & 0xf,
1424                                                 /* See ARM IHI 0029B Table 3-3 */
1425                                                 class_description[(c_cid1 >> 4) & 0xf]);
1426
1427                                 /* CoreSight component? */
1428                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1429                                         uint32_t devtype;
1430                                         unsigned minor;
1431                                         char *major = "Reserved", *subtype = "Reserved";
1432
1433                                         mem_ap_read_atomic_u32(swjdp,
1434                                                         (component_base & 0xfffff000) | 0xfcc,
1435                                                         &devtype);
1436                                         minor = (devtype >> 4) & 0x0f;
1437                                         switch (devtype & 0x0f) {
1438                                         case 0:
1439                                                 major = "Miscellaneous";
1440                                                 switch (minor) {
1441                                                 case 0:
1442                                                         subtype = "other";
1443                                                         break;
1444                                                 case 4:
1445                                                         subtype = "Validation component";
1446                                                         break;
1447                                                 }
1448                                                 break;
1449                                         case 1:
1450                                                 major = "Trace Sink";
1451                                                 switch (minor) {
1452                                                 case 0:
1453                                                         subtype = "other";
1454                                                         break;
1455                                                 case 1:
1456                                                         subtype = "Port";
1457                                                         break;
1458                                                 case 2:
1459                                                         subtype = "Buffer";
1460                                                         break;
1461                                                 }
1462                                                 break;
1463                                         case 2:
1464                                                 major = "Trace Link";
1465                                                 switch (minor) {
1466                                                 case 0:
1467                                                         subtype = "other";
1468                                                         break;
1469                                                 case 1:
1470                                                         subtype = "Funnel, router";
1471                                                         break;
1472                                                 case 2:
1473                                                         subtype = "Filter";
1474                                                         break;
1475                                                 case 3:
1476                                                         subtype = "FIFO, buffer";
1477                                                         break;
1478                                                 }
1479                                                 break;
1480                                         case 3:
1481                                                 major = "Trace Source";
1482                                                 switch (minor) {
1483                                                 case 0:
1484                                                         subtype = "other";
1485                                                         break;
1486                                                 case 1:
1487                                                         subtype = "Processor";
1488                                                         break;
1489                                                 case 2:
1490                                                         subtype = "DSP";
1491                                                         break;
1492                                                 case 3:
1493                                                         subtype = "Engine/Coprocessor";
1494                                                         break;
1495                                                 case 4:
1496                                                         subtype = "Bus";
1497                                                         break;
1498                                                 }
1499                                                 break;
1500                                         case 4:
1501                                                 major = "Debug Control";
1502                                                 switch (minor) {
1503                                                 case 0:
1504                                                         subtype = "other";
1505                                                         break;
1506                                                 case 1:
1507                                                         subtype = "Trigger Matrix";
1508                                                         break;
1509                                                 case 2:
1510                                                         subtype = "Debug Auth";
1511                                                         break;
1512                                                 }
1513                                                 break;
1514                                         case 5:
1515                                                 major = "Debug Logic";
1516                                                 switch (minor) {
1517                                                 case 0:
1518                                                         subtype = "other";
1519                                                         break;
1520                                                 case 1:
1521                                                         subtype = "Processor";
1522                                                         break;
1523                                                 case 2:
1524                                                         subtype = "DSP";
1525                                                         break;
1526                                                 case 3:
1527                                                         subtype = "Engine/Coprocessor";
1528                                                         break;
1529                                                 }
1530                                                 break;
1531                                         }
1532                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1533                                                         (unsigned) (devtype & 0xff),
1534                                                         major, subtype);
1535                                         /* REVISIT also show 0xfc8 DevId */
1536                                 }
1537
1538                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1539                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1540                                                         ", CID2 0x%2.2" PRIx32
1541                                                         ", CID1 0x%2.2" PRIx32
1542                                                         ", CID0 0x%2.2" PRIx32,
1543                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1544                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1545                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1546                                                 (int) c_pid4,
1547                                                 (int) c_pid3, (int) c_pid2,
1548                                                 (int) c_pid1, (int) c_pid0);
1549
1550                                 /* Part number interpretations are from Cortex
1551                                  * core specs, the CoreSight components TRM
1552                                  * (ARM DDI 0314H), and ETM specs; also from
1553                                  * chip observation (e.g. TI SDTI).
1554                                  */
1555                                 part_num = c_pid0 & 0xff;
1556                                 part_num |= (c_pid1 & 0x0f) << 8;
1557                                 switch (part_num) {
1558                                 case 0x000:
1559                                         type = "Cortex-M3 NVIC";
1560                                         full = "(Interrupt Controller)";
1561                                         break;
1562                                 case 0x001:
1563                                         type = "Cortex-M3 ITM";
1564                                         full = "(Instrumentation Trace Module)";
1565                                         break;
1566                                 case 0x002:
1567                                         type = "Cortex-M3 DWT";
1568                                         full = "(Data Watchpoint and Trace)";
1569                                         break;
1570                                 case 0x003:
1571                                         type = "Cortex-M3 FBP";
1572                                         full = "(Flash Patch and Breakpoint)";
1573                                         break;
1574                                 case 0x00d:
1575                                         type = "CoreSight ETM11";
1576                                         full = "(Embedded Trace)";
1577                                         break;
1578                                 // case 0x113: what?
1579                                 case 0x120:             /* from OMAP3 memmap */
1580                                         type = "TI SDTI";
1581                                         full = "(System Debug Trace Interface)";
1582                                         break;
1583                                 case 0x343:             /* from OMAP3 memmap */
1584                                         type = "TI DAPCTL";
1585                                         full = "";
1586                                         break;
1587                                 case 0x4e0:
1588                                         type = "Cortex-M3 ETM";
1589                                         full = "(Embedded Trace)";
1590                                         break;
1591                                 case 0x906:
1592                                         type = "Coresight CTI";
1593                                         full = "(Cross Trigger)";
1594                                         break;
1595                                 case 0x907:
1596                                         type = "Coresight ETB";
1597                                         full = "(Trace Buffer)";
1598                                         break;
1599                                 case 0x908:
1600                                         type = "Coresight CSTF";
1601                                         full = "(Trace Funnel)";
1602                                         break;
1603                                 case 0x910:
1604                                         type = "CoreSight ETM9";
1605                                         full = "(Embedded Trace)";
1606                                         break;
1607                                 case 0x912:
1608                                         type = "Coresight TPIU";
1609                                         full = "(Trace Port Interface Unit)";
1610                                         break;
1611                                 case 0x921:
1612                                         type = "Cortex-A8 ETM";
1613                                         full = "(Embedded Trace)";
1614                                         break;
1615                                 case 0x922:
1616                                         type = "Cortex-A8 CTI";
1617                                         full = "(Cross Trigger)";
1618                                         break;
1619                                 case 0x923:
1620                                         type = "Cortex-M3 TPIU";
1621                                         full = "(Trace Port Interface Unit)";
1622                                         break;
1623                                 case 0xc08:
1624                                         type = "Cortex-A8 Debug";
1625                                         full = "(Debug Unit)";
1626                                         break;
1627                                 default:
1628                                         type = "-*- unrecognized -*-";
1629                                         full = "";
1630                                         break;
1631                                 }
1632                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1633                                                 type, full);
1634                         }
1635                         else
1636                         {
1637                                 if (romentry)
1638                                         command_print(cmd_ctx, "\t\tComponent not present");
1639                                 else
1640                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1641                         }
1642                         entry_offset += 4;
1643                 } while (romentry > 0);
1644         }
1645         else
1646         {
1647                 command_print(cmd_ctx, "\tNo ROM table present");
1648         }
1649         dap_ap_select(swjdp, apselold);
1650
1651         return ERROR_OK;
1652 }
1653
1654 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1655 {
1656         uint32_t apsel, apselsave, baseaddr;
1657         int retval;
1658
1659         apselsave = swjdp->apsel;
1660         switch (CMD_ARGC) {
1661         case 0:
1662                 apsel = swjdp->apsel;
1663                 break;
1664         case 1:
1665                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1666                 /* AP address is in bits 31:24 of DP_SELECT */
1667                 if (apsel >= 256)
1668                         return ERROR_INVALID_ARGUMENTS;
1669                 break;
1670         default:
1671                 return ERROR_COMMAND_SYNTAX_ERROR;
1672         }
1673
1674         if (apselsave != apsel)
1675                 dap_ap_select(swjdp, apsel);
1676
1677         /* NOTE:  assumes we're talking to a MEM-AP, which
1678          * has a base address.  There are other kinds of AP,
1679          * though they're not common for now.  This should
1680          * use the ID register to verify it's a MEM-AP.
1681          */
1682         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1683         retval = jtagdp_transaction_endcheck(swjdp);
1684         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1685
1686         if (apselsave != apsel)
1687                 dap_ap_select(swjdp, apselsave);
1688
1689         return retval;
1690 }
1691
1692 DAP_COMMAND_HANDLER(dap_memaccess_command)
1693 {
1694         uint32_t memaccess_tck;
1695
1696         switch (CMD_ARGC) {
1697         case 0:
1698                 memaccess_tck = swjdp->memaccess_tck;
1699                 break;
1700         case 1:
1701                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1702                 break;
1703         default:
1704                 return ERROR_COMMAND_SYNTAX_ERROR;
1705         }
1706         swjdp->memaccess_tck = memaccess_tck;
1707
1708         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1709                         swjdp->memaccess_tck);
1710
1711         return ERROR_OK;
1712 }
1713
1714 DAP_COMMAND_HANDLER(dap_apsel_command)
1715 {
1716         uint32_t apsel, apid;
1717         int retval;
1718
1719         switch (CMD_ARGC) {
1720         case 0:
1721                 apsel = 0;
1722                 break;
1723         case 1:
1724                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1725                 /* AP address is in bits 31:24 of DP_SELECT */
1726                 if (apsel >= 256)
1727                         return ERROR_INVALID_ARGUMENTS;
1728                 break;
1729         default:
1730                 return ERROR_COMMAND_SYNTAX_ERROR;
1731         }
1732
1733         dap_ap_select(swjdp, apsel);
1734         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1735         retval = jtagdp_transaction_endcheck(swjdp);
1736         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1737                         apsel, apid);
1738
1739         return retval;
1740 }
1741
1742 DAP_COMMAND_HANDLER(dap_apid_command)
1743 {
1744         uint32_t apsel, apselsave, apid;
1745         int retval;
1746
1747         apselsave = swjdp->apsel;
1748         switch (CMD_ARGC) {
1749         case 0:
1750                 apsel = swjdp->apsel;
1751                 break;
1752         case 1:
1753                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1754                 /* AP address is in bits 31:24 of DP_SELECT */
1755                 if (apsel >= 256)
1756                         return ERROR_INVALID_ARGUMENTS;
1757                 break;
1758         default:
1759                 return ERROR_COMMAND_SYNTAX_ERROR;
1760         }
1761
1762         if (apselsave != apsel)
1763                 dap_ap_select(swjdp, apsel);
1764
1765         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1766         retval = jtagdp_transaction_endcheck(swjdp);
1767         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1768         if (apselsave != apsel)
1769                 dap_ap_select(swjdp, apselsave);
1770
1771         return retval;
1772 }