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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76
  77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  78
  79 /*
  80         uint32_t tar_block_size(uint32_t address)
  81         Return the largest block starting at address that does not cross a tar block size alignment boundary
  82 */
  83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  84 {
  85         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  86 }
  87
  88 /***************************************************************************
  89  *                                                                         *
  90  * DP and MEM-AP  register access  through APACC and DPACC                 *
  91  *                                                                         *
  92 ***************************************************************************/
  93
  94 /**
  95  * Select one of the APs connected to the specified DAP.  The
  96  * selection is implicitly used with future AP transactions.
  97  * This is a NOP if the specified AP is already selected.
  98  *
  99  * @param dap The DAP
 100  * @param apsel Number of the AP to (implicitly) use with further
 101  *      transactions.  This normally identifies a MEM-AP.
 102  */
 103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
 104 {
 105         uint32_t select_apsel = (apsel << 24) & 0xFF000000;
 106
 107         if (select_apsel != dap->apsel)
 108         {
 109                 dap->apsel = select_apsel;
 110                 /* Switching AP invalidates cached values.
 111                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 112                  */
 113                 dap->ap_bank_value = -1;
 114                 dap->ap_csw_value = -1;
 115                 dap->ap_tar_value = -1;
 116         }
 117 }
 118
 119 /**
 120  * Queue transactions setting up transfer parameters for the
 121  * currently selected MEM-AP.
 122  *
 123  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 124  * initiate data reads or writes using memory or peripheral addresses.
 125  * If the CSW is configured for it, the TAR may be automatically
 126  * incremented after each transfer.
 127  *
 128  * @todo Rename to reflect it being specifically a MEM-AP function.
 129  *
 130  * @param dap The DAP connected to the MEM-AP.
 131  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 132  *      matches the cached value, the register is not changed.
 133  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 134  *      matches the cached address, the register is not changed.
 135  *
 136  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 137  */
 138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 139 {
 140         int retval;
 141
 142         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 143         if (csw != dap->ap_csw_value)
 144         {
 145                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 146                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 147                 if (retval != ERROR_OK)
 148                         return retval;
 149                 dap->ap_csw_value = csw;
 150         }
 151         if (tar != dap->ap_tar_value)
 152         {
 153                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 154                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 155                 if (retval != ERROR_OK)
 156                         return retval;
 157                 dap->ap_tar_value = tar;
 158         }
 159         /* Disable TAR cache when autoincrementing */
 160         if (csw & CSW_ADDRINC_MASK)
 161                 dap->ap_tar_value = -1;
 162         return ERROR_OK;
 163 }
 164
 165 /**
 166  * Asynchronous (queued) read of a word from memory or a system register.
 167  *
 168  * @param dap The DAP connected to the MEM-AP performing the read.
 169  * @param address Address of the 32-bit word to read; it must be
 170  *      readable by the currently selected MEM-AP.
 171  * @param value points to where the word will be stored when the
 172  *      transaction queue is flushed (assuming no errors).
 173  *
 174  * @return ERROR_OK for success.  Otherwise a fault code.
 175  */
 176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 177                 uint32_t *value)
 178 {
 179         int retval;
 180
 181         /* Use banked addressing (REG_BDx) to avoid some link traffic
 182          * (updating TAR) when reading several consecutive addresses.
 183          */
 184         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 185                         address & 0xFFFFFFF0);
 186         if (retval != ERROR_OK)
 187                 return retval;
 188
 189         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 190 }
 191
 192 /**
 193  * Synchronous read of a word from memory or a system register.
 194  * As a side effect, this flushes any queued transactions.
 195  *
 196  * @param dap The DAP connected to the MEM-AP performing the read.
 197  * @param address Address of the 32-bit word to read; it must be
 198  *      readable by the currently selected MEM-AP.
 199  * @param value points to where the result will be stored.
 200  *
 201  * @return ERROR_OK for success; *value holds the result.
 202  * Otherwise a fault code.
 203  */
 204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 205                 uint32_t *value)
 206 {
 207         int retval;
 208
 209         retval = mem_ap_read_u32(dap, address, value);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         return dap_run(dap);
 214 }
 215
 216 /**
 217  * Asynchronous (queued) write of a word to memory or a system register.
 218  *
 219  * @param dap The DAP connected to the MEM-AP.
 220  * @param address Address to be written; it must be writable by
 221  *      the currently selected MEM-AP.
 222  * @param value Word that will be written to the address when transaction
 223  *      queue is flushed (assuming no errors).
 224  *
 225  * @return ERROR_OK for success.  Otherwise a fault code.
 226  */
 227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 228                 uint32_t value)
 229 {
 230         int retval;
 231
 232         /* Use banked addressing (REG_BDx) to avoid some link traffic
 233          * (updating TAR) when writing several consecutive addresses.
 234          */
 235         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 236                         address & 0xFFFFFFF0);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 241                         value);
 242 }
 243
 244 /**
 245  * Synchronous write of a word to memory or a system register.
 246  * As a side effect, this flushes any queued transactions.
 247  *
 248  * @param dap The DAP connected to the MEM-AP.
 249  * @param address Address to be written; it must be writable by
 250  *      the currently selected MEM-AP.
 251  * @param value Word that will be written.
 252  *
 253  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 254  */
 255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 256                 uint32_t value)
 257 {
 258         int retval = mem_ap_write_u32(dap, address, value);
 259
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         return dap_run(dap);
 264 }
 265
 266 /*****************************************************************************
 267 *                                                                            *
 268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 269 *                                                                            *
 270 * Write a buffer in target order (little endian)                             *
 271 *                                                                            *
 272 *****************************************************************************/
 273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 274 {
 275         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 276         uint32_t adr = address;
 277         uint8_t* pBuffer = buffer;
 278
 279         count >>= 2;
 280         wcount = count;
 281
 282         /* if we have an unaligned access - reorder data */
 283         if (adr & 0x3u)
 284         {
 285                 for (writecount = 0; writecount < count; writecount++)
 286                 {
 287                         int i;
 288                         uint32_t outvalue;
 289                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 290
 291                         for (i = 0; i < 4; i++)
 292                         {
 293                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 294                                 outvalue >>= 8;
 295                                 adr++;
 296                         }
 297                         pBuffer += sizeof(uint32_t);
 298                 }
 299         }
 300
 301         while (wcount > 0)
 302         {
 303                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 304                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 305                 if (wcount < blocksize)
 306                         blocksize = wcount;
 307
 308                 /* handle unaligned data at 4k boundary */
 309                 if (blocksize == 0)
 310                         blocksize = 1;
 311
 312                 dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 313
 314                 for (writecount = 0; writecount < blocksize; writecount++)
 315                 {
 316                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 317                                 *(uint32_t *) (buffer + 4 * writecount));
 318                         if (retval != ERROR_OK)
 319                                 break;
 320                 }
 321
 322                 if (dap_run(dap) == ERROR_OK)
 323                 {
 324                         wcount = wcount - blocksize;
 325                         address = address + 4 * blocksize;
 326                         buffer = buffer + 4 * blocksize;
 327                 }
 328                 else
 329                 {
 330                         errorcount++;
 331                 }
 332
 333                 if (errorcount > 1)
 334                 {
 335                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 336                         /* REVISIT return the *actual* fault code */
 337                         return ERROR_JTAG_DEVICE_ERROR;
 338                 }
 339         }
 340
 341         return retval;
 342 }
 343
 344 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 345                 uint8_t *buffer, int count, uint32_t address)
 346 {
 347         int retval = ERROR_OK;
 348         int wcount, blocksize, writecount, i;
 349
 350         wcount = count >> 1;
 351
 352         while (wcount > 0)
 353         {
 354                 int nbytes;
 355
 356                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 357                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 358
 359                 if (wcount < blocksize)
 360                         blocksize = wcount;
 361
 362                 /* handle unaligned data at 4k boundary */
 363                 if (blocksize == 0)
 364                         blocksize = 1;
 365
 366                 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 367                 writecount = blocksize;
 368
 369                 do
 370                 {
 371                         nbytes = MIN((writecount << 1), 4);
 372
 373                         if (nbytes < 4)
 374                         {
 375                                 if (mem_ap_write_buf_u16(dap, buffer,
 376                                                 nbytes, address) != ERROR_OK)
 377                                 {
 378                                         LOG_WARNING("Block write error address "
 379                                                 "0x%" PRIx32 ", count 0x%x",
 380                                                 address, count);
 381                                         return ERROR_JTAG_DEVICE_ERROR;
 382                                 }
 383
 384                                 address += nbytes >> 1;
 385                         }
 386                         else
 387                         {
 388                                 uint32_t outvalue;
 389                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 390
 391                                 for (i = 0; i < nbytes; i++)
 392                                 {
 393                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 394                                         outvalue >>= 8;
 395                                         address++;
 396                                 }
 397
 398                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 399                                 retval = dap_queue_ap_write(dap,
 400                                                 AP_REG_DRW, outvalue);
 401                                 if (retval != ERROR_OK)
 402                                         break;
 403
 404                                 if (dap_run(dap) != ERROR_OK)
 405                                 {
 406                                         LOG_WARNING("Block write error address "
 407                                                 "0x%" PRIx32 ", count 0x%x",
 408                                                 address, count);
 409                                         /* REVISIT return *actual* fault code */
 410                                         return ERROR_JTAG_DEVICE_ERROR;
 411                                 }
 412                         }
 413
 414                         buffer += nbytes >> 1;
 415                         writecount -= nbytes >> 1;
 416
 417                 } while (writecount);
 418                 wcount -= blocksize;
 419         }
 420
 421         return retval;
 422 }
 423
 424 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 425 {
 426         int retval = ERROR_OK;
 427
 428         if (count >= 4)
 429                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 430
 431         while (count > 0)
 432         {
 433                 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 434                 uint16_t svalue;
 435                 memcpy(&svalue, buffer, sizeof(uint16_t));
 436                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 437                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 438                 if (retval != ERROR_OK)
 439                         break;
 440
 441                 retval = dap_run(dap);
 442                 if (retval != ERROR_OK)
 443                         break;
 444
 445                 count -= 2;
 446                 address += 2;
 447                 buffer += 2;
 448         }
 449
 450         return retval;
 451 }
 452
 453 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 454                 uint8_t *buffer, int count, uint32_t address)
 455 {
 456         int retval = ERROR_OK;
 457         int wcount, blocksize, writecount, i;
 458
 459         wcount = count;
 460
 461         while (wcount > 0)
 462         {
 463                 int nbytes;
 464
 465                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 466                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 467
 468                 if (wcount < blocksize)
 469                         blocksize = wcount;
 470
 471                 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 472                 writecount = blocksize;
 473
 474                 do
 475                 {
 476                         nbytes = MIN(writecount, 4);
 477
 478                         if (nbytes < 4)
 479                         {
 480                                 if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
 481                                 {
 482                                         LOG_WARNING("Block write error address "
 483                                                 "0x%" PRIx32 ", count 0x%x",
 484                                                 address, count);
 485                                         return ERROR_JTAG_DEVICE_ERROR;
 486                                 }
 487
 488                                 address += nbytes;
 489                         }
 490                         else
 491                         {
 492                                 uint32_t outvalue;
 493                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 494
 495                                 for (i = 0; i < nbytes; i++)
 496                                 {
 497                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 498                                         outvalue >>= 8;
 499                                         address++;
 500                                 }
 501
 502                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 503                                 retval = dap_queue_ap_write(dap,
 504                                                 AP_REG_DRW, outvalue);
 505                                 if (retval != ERROR_OK)
 506                                         break;
 507
 508                                 if (dap_run(dap) != ERROR_OK)
 509                                 {
 510                                         LOG_WARNING("Block write error address "
 511                                                 "0x%" PRIx32 ", count 0x%x",
 512                                                 address, count);
 513                                         /* REVISIT return *actual* fault code */
 514                                         return ERROR_JTAG_DEVICE_ERROR;
 515                                 }
 516                         }
 517
 518                         buffer += nbytes;
 519                         writecount -= nbytes;
 520
 521                 } while (writecount);
 522                 wcount -= blocksize;
 523         }
 524
 525         return retval;
 526 }
 527
 528 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 529 {
 530         int retval = ERROR_OK;
 531
 532         if (count >= 4)
 533                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 534
 535         while (count > 0)
 536         {
 537                 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 538                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 539                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 540                 if (retval != ERROR_OK)
 541                         break;
 542
 543                 retval = dap_run(dap);
 544                 if (retval != ERROR_OK)
 545                         break;
 546
 547                 count--;
 548                 address++;
 549                 buffer++;
 550         }
 551
 552         return retval;
 553 }
 554
 555 /* FIXME don't import ... this is a temporary workaround for the
 556  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 557  */
 558 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 559                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 560                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 561
 562 /**
 563  * Synchronously read a block of 32-bit words into a buffer
 564  * @param dap The DAP connected to the MEM-AP.
 565  * @param buffer where the words will be stored (in host byte order).
 566  * @param count How many words to read.
 567  * @param address Memory address from which to read words; all the
 568  *      words must be readable by the currently selected MEM-AP.
 569  */
 570 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 571                 int count, uint32_t address)
 572 {
 573         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 574         uint32_t adr = address;
 575         uint8_t* pBuffer = buffer;
 576
 577         count >>= 2;
 578         wcount = count;
 579
 580         while (wcount > 0)
 581         {
 582                 /* Adjust to read blocks within boundaries aligned to the
 583                  * TAR autoincrement size (at least 2^10).  Autoincrement
 584                  * mode avoids an extra per-word roundtrip to update TAR.
 585                  */
 586                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 587                                 address);
 588                 if (wcount < blocksize)
 589                         blocksize = wcount;
 590
 591                 /* handle unaligned data at 4k boundary */
 592                 if (blocksize == 0)
 593                         blocksize = 1;
 594
 595                 dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 596                                 address);
 597
 598                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 599                  * so this routine becomes transport-neutral.  Be careful
 600                  * not to cause performance problems with JTAG; would it
 601                  * suffice to loop over dap_queue_ap_read(), or would that
 602                  * be slower when JTAG is the chosen transport?
 603                  */
 604
 605                 /* Scan out first read */
 606                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 607                                 DPAP_READ, 0, NULL, NULL);
 608                 if (retval != ERROR_OK)
 609                         return retval;
 610                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 611                 {
 612                         /* Scan out next read; scan in posted value for the
 613                          * previous one.  Assumes read is acked "OK/FAULT",
 614                          * and CTRL_STAT says that meant "OK".
 615                          */
 616                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 617                                         DPAP_READ, 0, buffer + 4 * readcount,
 618                                         &dap->ack);
 619                         if (retval != ERROR_OK)
 620                                 return retval;
 621                 }
 622
 623                 /* Scan in last posted value; RDBUFF has no other effect,
 624                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 625                  */
 626                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 627                                 DPAP_READ, 0, buffer + 4 * readcount,
 628                                 &dap->ack);
 629                 if (retval != ERROR_OK)
 630                         return retval;
 631
 632                 retval = dap_run(dap);
 633                 if (retval != ERROR_OK)
 634                 {
 635                         errorcount++;
 636                         if (errorcount <= 1)
 637                         {
 638                                 /* try again */
 639                                 continue;
 640                         }
 641                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 642                         return retval;
 643                 }
 644                 wcount = wcount - blocksize;
 645                 address += 4 * blocksize;
 646                 buffer += 4 * blocksize;
 647         }
 648
 649         /* if we have an unaligned access - reorder data */
 650         if (adr & 0x3u)
 651         {
 652                 for (readcount = 0; readcount < count; readcount++)
 653                 {
 654                         int i;
 655                         uint32_t data;
 656                         memcpy(&data, pBuffer, sizeof(uint32_t));
 657
 658                         for (i = 0; i < 4; i++)
 659                         {
 660                                 *((uint8_t*)pBuffer) =
 661                                                 (data >> 8 * (adr & 0x3));
 662                                 pBuffer++;
 663                                 adr++;
 664                         }
 665                 }
 666         }
 667
 668         return retval;
 669 }
 670
 671 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 672                 uint8_t *buffer, int count, uint32_t address)
 673 {
 674         uint32_t invalue;
 675         int retval = ERROR_OK;
 676         int wcount, blocksize, readcount, i;
 677
 678         wcount = count >> 1;
 679
 680         while (wcount > 0)
 681         {
 682                 int nbytes;
 683
 684                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 685                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 686                 if (wcount < blocksize)
 687                         blocksize = wcount;
 688
 689                 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 690
 691                 /* handle unaligned data at 4k boundary */
 692                 if (blocksize == 0)
 693                         blocksize = 1;
 694                 readcount = blocksize;
 695
 696                 do
 697                 {
 698                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 699                         if (dap_run(dap) != ERROR_OK)
 700                         {
 701                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 702                                 /* REVISIT return the *actual* fault code */
 703                                 return ERROR_JTAG_DEVICE_ERROR;
 704                         }
 705
 706                         nbytes = MIN((readcount << 1), 4);
 707
 708                         for (i = 0; i < nbytes; i++)
 709                         {
 710                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 711                                 buffer++;
 712                                 address++;
 713                         }
 714
 715                         readcount -= (nbytes >> 1);
 716                 } while (readcount);
 717                 wcount -= blocksize;
 718         }
 719
 720         return retval;
 721 }
 722
 723 /**
 724  * Synchronously read a block of 16-bit halfwords into a buffer
 725  * @param dap The DAP connected to the MEM-AP.
 726  * @param buffer where the halfwords will be stored (in host byte order).
 727  * @param count How many halfwords to read.
 728  * @param address Memory address from which to read words; all the
 729  *      words must be readable by the currently selected MEM-AP.
 730  */
 731 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 732                 int count, uint32_t address)
 733 {
 734         uint32_t invalue, i;
 735         int retval = ERROR_OK;
 736
 737         if (count >= 4)
 738                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 739
 740         while (count > 0)
 741         {
 742                 dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 743                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 744                 if (retval != ERROR_OK)
 745                         break;
 746
 747                 retval = dap_run(dap);
 748                 if (retval != ERROR_OK)
 749                         break;
 750
 751                 if (address & 0x1)
 752                 {
 753                         for (i = 0; i < 2; i++)
 754                         {
 755                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 756                                 buffer++;
 757                                 address++;
 758                         }
 759                 }
 760                 else
 761                 {
 762                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 763                         memcpy(buffer, &svalue, sizeof(uint16_t));
 764                         address += 2;
 765                         buffer += 2;
 766                 }
 767                 count -= 2;
 768         }
 769
 770         return retval;
 771 }
 772
 773 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 774  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 775  *
 776  * The solution is to arrange for a large out/in scan in this loop and
 777  * and convert data afterwards.
 778  */
 779 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 780                 uint8_t *buffer, int count, uint32_t address)
 781 {
 782         uint32_t invalue;
 783         int retval = ERROR_OK;
 784         int wcount, blocksize, readcount, i;
 785
 786         wcount = count;
 787
 788         while (wcount > 0)
 789         {
 790                 int nbytes;
 791
 792                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 793                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 794
 795                 if (wcount < blocksize)
 796                         blocksize = wcount;
 797
 798                 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 799                 readcount = blocksize;
 800
 801                 do
 802                 {
 803                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 804                         if (dap_run(dap) != ERROR_OK)
 805                         {
 806                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 807                                 /* REVISIT return the *actual* fault code */
 808                                 return ERROR_JTAG_DEVICE_ERROR;
 809                         }
 810
 811                         nbytes = MIN(readcount, 4);
 812
 813                         for (i = 0; i < nbytes; i++)
 814                         {
 815                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 816                                 buffer++;
 817                                 address++;
 818                         }
 819
 820                         readcount -= nbytes;
 821                 } while (readcount);
 822                 wcount -= blocksize;
 823         }
 824
 825         return retval;
 826 }
 827
 828 /**
 829  * Synchronously read a block of bytes into a buffer
 830  * @param dap The DAP connected to the MEM-AP.
 831  * @param buffer where the bytes will be stored.
 832  * @param count How many bytes to read.
 833  * @param address Memory address from which to read data; all the
 834  *      data must be readable by the currently selected MEM-AP.
 835  */
 836 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 837                 int count, uint32_t address)
 838 {
 839         uint32_t invalue;
 840         int retval = ERROR_OK;
 841
 842         if (count >= 4)
 843                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 844
 845         while (count > 0)
 846         {
 847                 dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 848                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 849                 retval = dap_run(dap);
 850                 if (retval != ERROR_OK)
 851                         break;
 852
 853                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 854                 count--;
 855                 address++;
 856                 buffer++;
 857         }
 858
 859         return retval;
 860 }
 861
 862 /*--------------------------------------------------------------------------*/
 863
 864
 865 /* FIXME don't import ... just initialize as
 866  * part of DAP transport setup
 867 */
 868 extern const struct dap_ops jtag_dp_ops;
 869
 870 /*--------------------------------------------------------------------------*/
 871
 872 /**
 873  * Initialize a DAP.  This sets up the power domains, prepares the DP
 874  * for further use, and arranges to use AP #0 for all AP operations
 875  * until dap_ap-select() changes that policy.
 876  *
 877  * @param dap The DAP being initialized.
 878  *
 879  * @todo Rename this.  We also need an initialization scheme which account
 880  * for SWD transports not just JTAG; that will need to address differences
 881  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 882  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 883  */
 884 int ahbap_debugport_init(struct adiv5_dap *dap)
 885 {
 886         uint32_t idreg, romaddr, dummy;
 887         uint32_t ctrlstat;
 888         int cnt = 0;
 889         int retval;
 890
 891         LOG_DEBUG(" ");
 892
 893         /* JTAG-DP or SWJ-DP, in JTAG mode */
 894         dap->ops = &jtag_dp_ops;
 895
 896         /* Default MEM-AP setup.
 897          *
 898          * REVISIT AP #0 may be an inappropriate default for this.
 899          * Should we probe, or take a hint from the caller?
 900          * Presumably we can ignore the possibility of multiple APs.
 901          */
 902         dap->apsel = !0;
 903         dap_ap_select(dap, 0);
 904
 905         /* DP initialization */
 906
 907         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 908         if (retval != ERROR_OK)
 909                 return retval;
 910
 911         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 912         if (retval != ERROR_OK)
 913                 return retval;
 914
 915         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 916         if (retval != ERROR_OK)
 917                 return retval;
 918
 919         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 920         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 921         if (retval != ERROR_OK)
 922                 return retval;
 923
 924         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 925         if (retval != ERROR_OK)
 926                 return retval;
 927         if ((retval = dap_run(dap)) != ERROR_OK)
 928                 return retval;
 929
 930         /* Check that we have debug power domains activated */
 931         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
 932         {
 933                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 934                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 935                 if (retval != ERROR_OK)
 936                         return retval;
 937                 if ((retval = dap_run(dap)) != ERROR_OK)
 938                         return retval;
 939                 alive_sleep(10);
 940         }
 941
 942         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
 943         {
 944                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 945                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 946                 if (retval != ERROR_OK)
 947                         return retval;
 948                 if ((retval = dap_run(dap)) != ERROR_OK)
 949                         return retval;
 950                 alive_sleep(10);
 951         }
 952
 953         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 954         if (retval != ERROR_OK)
 955                 return retval;
 956         /* With debug power on we can activate OVERRUN checking */
 957         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 958         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 962         if (retval != ERROR_OK)
 963                 return retval;
 964
 965         /*
 966          * REVISIT this isn't actually *initializing* anything in an AP,
 967          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
 968          * Should it?  If the ROM address is valid, is this the right
 969          * place to scan the table and do any topology detection?
 970          */
 971         retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
 972         retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
 973
 974         if ((retval = dap_run(dap)) != ERROR_OK)
 975                 return retval;
 976
 977         LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
 978                 ", Debug ROM Address 0x%" PRIx32,
 979                 dap->apsel, idreg, romaddr);
 980
 981         return ERROR_OK;
 982 }
 983
 984 /* CID interpretation -- see ARM IHI 0029B section 3
 985  * and ARM IHI 0031A table 13-3.
 986  */
 987 static const char *class_description[16] ={
 988         "Reserved", "ROM table", "Reserved", "Reserved",
 989         "Reserved", "Reserved", "Reserved", "Reserved",
 990         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 991         "Reserved", "OptimoDE DESS",
 992                 "Generic IP component", "PrimeCell or System component"
 993 };
 994
 995 static bool
 996 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 997 {
 998         return cid3 == 0xb1 && cid2 == 0x05
 999                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1000 }
1001
1002 static int dap_info_command(struct command_context *cmd_ctx,
1003                 struct adiv5_dap *dap, int apsel)
1004 {
1005         int retval;
1006         uint32_t dbgbase, apid;
1007         int romtable_present = 0;
1008         uint8_t mem_ap;
1009         uint32_t apselold;
1010
1011         /* AP address is in bits 31:24 of DP_SELECT */
1012         if (apsel >= 256)
1013                 return ERROR_INVALID_ARGUMENTS;
1014
1015         apselold = dap->apsel;
1016         dap_ap_select(dap, apsel);
1017         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1018         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1019         retval = dap_run(dap);
1020         if (retval != ERROR_OK)
1021                 return retval;
1022
1023         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1024         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1025         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1026         if (apid)
1027         {
1028                 switch (apid&0x0F)
1029                 {
1030                         case 0:
1031                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1032                                 break;
1033                         case 1:
1034                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1035                                 break;
1036                         case 2:
1037                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1038                                 break;
1039                         default:
1040                                 command_print(cmd_ctx, "\tUnknown AP type");
1041                                 break;
1042                 }
1043
1044                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1045                  * not a ROM table ... or have no such components at all.
1046                  */
1047                 if (mem_ap)
1048                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1049                                         dbgbase);
1050         }
1051         else
1052         {
1053                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1054         }
1055
1056         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1057         if (romtable_present)
1058         {
1059                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1060                 uint16_t entry_offset;
1061
1062                 /* bit 16 of apid indicates a memory access port */
1063                 if (dbgbase & 0x02)
1064                         command_print(cmd_ctx, "\tValid ROM table present");
1065                 else
1066                         command_print(cmd_ctx, "\tROM table in legacy format");
1067
1068                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1069                 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1070                 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1071                 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1072                 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1073                 mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1074                 retval = dap_run(dap);
1075                 if (retval != ERROR_OK)
1076                         return retval;
1077
1078                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1079                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1080                                         ", CID2 0x%2.2x"
1081                                         ", CID1 0x%2.2x"
1082                                         ", CID0 0x%2.2x",
1083                                         (unsigned) cid3, (unsigned)cid2,
1084                                         (unsigned) cid1, (unsigned) cid0);
1085                 if (memtype & 0x01)
1086                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1087                 else
1088                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1089                                         "Dedicated debug bus.");
1090
1091                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1092                 entry_offset = 0;
1093                 do
1094                 {
1095                         mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1096                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1097                         if (romentry&0x01)
1098                         {
1099                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1100                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1101                                 uint32_t component_base;
1102                                 unsigned part_num;
1103                                 char *type, *full;
1104
1105                                 component_base = (dbgbase & 0xFFFFF000)
1106                                                 + (romentry & 0xFFFFF000);
1107
1108                                 /* IDs are in last 4K section */
1109
1110
1111                                 mem_ap_read_atomic_u32(dap,
1112                                         component_base + 0xFE0, &c_pid0);
1113                                 c_pid0 &= 0xff;
1114                                 mem_ap_read_atomic_u32(dap,
1115                                         component_base + 0xFE4, &c_pid1);
1116                                 c_pid1 &= 0xff;
1117                                 mem_ap_read_atomic_u32(dap,
1118                                         component_base + 0xFE8, &c_pid2);
1119                                 c_pid2 &= 0xff;
1120                                 mem_ap_read_atomic_u32(dap,
1121                                         component_base + 0xFEC, &c_pid3);
1122                                 c_pid3 &= 0xff;
1123                                 mem_ap_read_atomic_u32(dap,
1124                                         component_base + 0xFD0, &c_pid4);
1125                                 c_pid4 &= 0xff;
1126
1127                                 mem_ap_read_atomic_u32(dap,
1128                                         component_base + 0xFF0, &c_cid0);
1129                                 c_cid0 &= 0xff;
1130                                 mem_ap_read_atomic_u32(dap,
1131                                         component_base + 0xFF4, &c_cid1);
1132                                 c_cid1 &= 0xff;
1133                                 mem_ap_read_atomic_u32(dap,
1134                                         component_base + 0xFF8, &c_cid2);
1135                                 c_cid2 &= 0xff;
1136                                 mem_ap_read_atomic_u32(dap,
1137                                         component_base + 0xFFC, &c_cid3);
1138                                 c_cid3 &= 0xff;
1139
1140
1141                                 command_print(cmd_ctx,
1142                                 "\t\tComponent base address 0x%" PRIx32
1143                                         ", start address 0x%" PRIx32,
1144                                                 component_base,
1145                                 /* component may take multiple 4K pages */
1146                                 component_base - 0x1000*(c_pid4 >> 4));
1147                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1148                                                 (int) (c_cid1 >> 4) & 0xf,
1149                                                 /* See ARM IHI 0029B Table 3-3 */
1150                                                 class_description[(c_cid1 >> 4) & 0xf]);
1151
1152                                 /* CoreSight component? */
1153                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1154                                         uint32_t devtype;
1155                                         unsigned minor;
1156                                         char *major = "Reserved", *subtype = "Reserved";
1157
1158                                         mem_ap_read_atomic_u32(dap,
1159                                                         (component_base & 0xfffff000) | 0xfcc,
1160                                                         &devtype);
1161                                         minor = (devtype >> 4) & 0x0f;
1162                                         switch (devtype & 0x0f) {
1163                                         case 0:
1164                                                 major = "Miscellaneous";
1165                                                 switch (minor) {
1166                                                 case 0:
1167                                                         subtype = "other";
1168                                                         break;
1169                                                 case 4:
1170                                                         subtype = "Validation component";
1171                                                         break;
1172                                                 }
1173                                                 break;
1174                                         case 1:
1175                                                 major = "Trace Sink";
1176                                                 switch (minor) {
1177                                                 case 0:
1178                                                         subtype = "other";
1179                                                         break;
1180                                                 case 1:
1181                                                         subtype = "Port";
1182                                                         break;
1183                                                 case 2:
1184                                                         subtype = "Buffer";
1185                                                         break;
1186                                                 }
1187                                                 break;
1188                                         case 2:
1189                                                 major = "Trace Link";
1190                                                 switch (minor) {
1191                                                 case 0:
1192                                                         subtype = "other";
1193                                                         break;
1194                                                 case 1:
1195                                                         subtype = "Funnel, router";
1196                                                         break;
1197                                                 case 2:
1198                                                         subtype = "Filter";
1199                                                         break;
1200                                                 case 3:
1201                                                         subtype = "FIFO, buffer";
1202                                                         break;
1203                                                 }
1204                                                 break;
1205                                         case 3:
1206                                                 major = "Trace Source";
1207                                                 switch (minor) {
1208                                                 case 0:
1209                                                         subtype = "other";
1210                                                         break;
1211                                                 case 1:
1212                                                         subtype = "Processor";
1213                                                         break;
1214                                                 case 2:
1215                                                         subtype = "DSP";
1216                                                         break;
1217                                                 case 3:
1218                                                         subtype = "Engine/Coprocessor";
1219                                                         break;
1220                                                 case 4:
1221                                                         subtype = "Bus";
1222                                                         break;
1223                                                 }
1224                                                 break;
1225                                         case 4:
1226                                                 major = "Debug Control";
1227                                                 switch (minor) {
1228                                                 case 0:
1229                                                         subtype = "other";
1230                                                         break;
1231                                                 case 1:
1232                                                         subtype = "Trigger Matrix";
1233                                                         break;
1234                                                 case 2:
1235                                                         subtype = "Debug Auth";
1236                                                         break;
1237                                                 }
1238                                                 break;
1239                                         case 5:
1240                                                 major = "Debug Logic";
1241                                                 switch (minor) {
1242                                                 case 0:
1243                                                         subtype = "other";
1244                                                         break;
1245                                                 case 1:
1246                                                         subtype = "Processor";
1247                                                         break;
1248                                                 case 2:
1249                                                         subtype = "DSP";
1250                                                         break;
1251                                                 case 3:
1252                                                         subtype = "Engine/Coprocessor";
1253                                                         break;
1254                                                 }
1255                                                 break;
1256                                         }
1257                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1258                                                         (unsigned) (devtype & 0xff),
1259                                                         major, subtype);
1260                                         /* REVISIT also show 0xfc8 DevId */
1261                                 }
1262
1263                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1264                                         command_print(cmd_ctx,
1265                                                       "\t\tCID3 0%2.2x"
1266                                                         ", CID2 0%2.2x"
1267                                                         ", CID1 0%2.2x"
1268                                                         ", CID0 0%2.2x",
1269                                                         (int) c_cid3,
1270                                                         (int) c_cid2,
1271                                                         (int)c_cid1,
1272                                                         (int)c_cid0);
1273                                 command_print(cmd_ctx,
1274                                 "\t\tPeripheral ID[4..0] = hex "
1275                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1276                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1277                                 (int) c_pid1, (int) c_pid0);
1278
1279                                 /* Part number interpretations are from Cortex
1280                                  * core specs, the CoreSight components TRM
1281                                  * (ARM DDI 0314H), and ETM specs; also from
1282                                  * chip observation (e.g. TI SDTI).
1283                                  */
1284                                 part_num = (c_pid0 & 0xff);
1285                                 part_num |= (c_pid1 & 0x0f) << 8;
1286                                 switch (part_num) {
1287                                 case 0x000:
1288                                         type = "Cortex-M3 NVIC";
1289                                         full = "(Interrupt Controller)";
1290                                         break;
1291                                 case 0x001:
1292                                         type = "Cortex-M3 ITM";
1293                                         full = "(Instrumentation Trace Module)";
1294                                         break;
1295                                 case 0x002:
1296                                         type = "Cortex-M3 DWT";
1297                                         full = "(Data Watchpoint and Trace)";
1298                                         break;
1299                                 case 0x003:
1300                                         type = "Cortex-M3 FBP";
1301                                         full = "(Flash Patch and Breakpoint)";
1302                                         break;
1303                                 case 0x00d:
1304                                         type = "CoreSight ETM11";
1305                                         full = "(Embedded Trace)";
1306                                         break;
1307                                 // case 0x113: what?
1308                                 case 0x120:             /* from OMAP3 memmap */
1309                                         type = "TI SDTI";
1310                                         full = "(System Debug Trace Interface)";
1311                                         break;
1312                                 case 0x343:             /* from OMAP3 memmap */
1313                                         type = "TI DAPCTL";
1314                                         full = "";
1315                                         break;
1316                                 case 0x906:
1317                                         type = "Coresight CTI";
1318                                         full = "(Cross Trigger)";
1319                                         break;
1320                                 case 0x907:
1321                                         type = "Coresight ETB";
1322                                         full = "(Trace Buffer)";
1323                                         break;
1324                                 case 0x908:
1325                                         type = "Coresight CSTF";
1326                                         full = "(Trace Funnel)";
1327                                         break;
1328                                 case 0x910:
1329                                         type = "CoreSight ETM9";
1330                                         full = "(Embedded Trace)";
1331                                         break;
1332                                 case 0x912:
1333                                         type = "Coresight TPIU";
1334                                         full = "(Trace Port Interface Unit)";
1335                                         break;
1336                                 case 0x921:
1337                                         type = "Cortex-A8 ETM";
1338                                         full = "(Embedded Trace)";
1339                                         break;
1340                                 case 0x922:
1341                                         type = "Cortex-A8 CTI";
1342                                         full = "(Cross Trigger)";
1343                                         break;
1344                                 case 0x923:
1345                                         type = "Cortex-M3 TPIU";
1346                                         full = "(Trace Port Interface Unit)";
1347                                         break;
1348                                 case 0x924:
1349                                         type = "Cortex-M3 ETM";
1350                                         full = "(Embedded Trace)";
1351                                         break;
1352                                 case 0xc08:
1353                                         type = "Cortex-A8 Debug";
1354                                         full = "(Debug Unit)";
1355                                         break;
1356                                 default:
1357                                         type = "-*- unrecognized -*-";
1358                                         full = "";
1359                                         break;
1360                                 }
1361                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1362                                                 type, full);
1363                         }
1364                         else
1365                         {
1366                                 if (romentry)
1367                                         command_print(cmd_ctx, "\t\tComponent not present");
1368                                 else
1369                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1370                         }
1371                         entry_offset += 4;
1372                 } while (romentry > 0);
1373         }
1374         else
1375         {
1376                 command_print(cmd_ctx, "\tNo ROM table present");
1377         }
1378         dap_ap_select(dap, apselold);
1379
1380         return ERROR_OK;
1381 }
1382
1383 COMMAND_HANDLER(handle_dap_info_command)
1384 {
1385         struct target *target = get_current_target(CMD_CTX);
1386         struct arm *arm = target_to_arm(target);
1387         struct adiv5_dap *dap = arm->dap;
1388         uint32_t apsel;
1389
1390         switch (CMD_ARGC) {
1391         case 0:
1392                 apsel = dap->apsel;
1393                 break;
1394         case 1:
1395                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1396                 break;
1397         default:
1398                 return ERROR_COMMAND_SYNTAX_ERROR;
1399         }
1400
1401         return dap_info_command(CMD_CTX, dap, apsel);
1402 }
1403
1404 COMMAND_HANDLER(dap_baseaddr_command)
1405 {
1406         struct target *target = get_current_target(CMD_CTX);
1407         struct arm *arm = target_to_arm(target);
1408         struct adiv5_dap *dap = arm->dap;
1409
1410         uint32_t apsel, apselsave, baseaddr;
1411         int retval;
1412
1413         apselsave = dap->apsel;
1414         switch (CMD_ARGC) {
1415         case 0:
1416                 apsel = dap->apsel;
1417                 break;
1418         case 1:
1419                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1420                 /* AP address is in bits 31:24 of DP_SELECT */
1421                 if (apsel >= 256)
1422                         return ERROR_INVALID_ARGUMENTS;
1423                 break;
1424         default:
1425                 return ERROR_COMMAND_SYNTAX_ERROR;
1426         }
1427
1428         if (apselsave != apsel)
1429                 dap_ap_select(dap, apsel);
1430
1431         /* NOTE:  assumes we're talking to a MEM-AP, which
1432          * has a base address.  There are other kinds of AP,
1433          * though they're not common for now.  This should
1434          * use the ID register to verify it's a MEM-AP.
1435          */
1436         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1437         retval = dap_run(dap);
1438         if (retval != ERROR_OK)
1439                 return retval;
1440
1441         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1442
1443         if (apselsave != apsel)
1444                 dap_ap_select(dap, apselsave);
1445
1446         return retval;
1447 }
1448
1449 COMMAND_HANDLER(dap_memaccess_command)
1450 {
1451         struct target *target = get_current_target(CMD_CTX);
1452         struct arm *arm = target_to_arm(target);
1453         struct adiv5_dap *dap = arm->dap;
1454
1455         uint32_t memaccess_tck;
1456
1457         switch (CMD_ARGC) {
1458         case 0:
1459                 memaccess_tck = dap->memaccess_tck;
1460                 break;
1461         case 1:
1462                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1463                 break;
1464         default:
1465                 return ERROR_COMMAND_SYNTAX_ERROR;
1466         }
1467         dap->memaccess_tck = memaccess_tck;
1468
1469         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1470                         dap->memaccess_tck);
1471
1472         return ERROR_OK;
1473 }
1474
1475 COMMAND_HANDLER(dap_apsel_command)
1476 {
1477         struct target *target = get_current_target(CMD_CTX);
1478         struct arm *arm = target_to_arm(target);
1479         struct adiv5_dap *dap = arm->dap;
1480
1481         uint32_t apsel, apid;
1482         int retval;
1483
1484         switch (CMD_ARGC) {
1485         case 0:
1486                 apsel = 0;
1487                 break;
1488         case 1:
1489                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1490                 /* AP address is in bits 31:24 of DP_SELECT */
1491                 if (apsel >= 256)
1492                         return ERROR_INVALID_ARGUMENTS;
1493                 break;
1494         default:
1495                 return ERROR_COMMAND_SYNTAX_ERROR;
1496         }
1497
1498         dap_ap_select(dap, apsel);
1499         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1500         retval = dap_run(dap);
1501         if (retval != ERROR_OK)
1502                 return retval;
1503
1504         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1505                         apsel, apid);
1506
1507         return retval;
1508 }
1509
1510 COMMAND_HANDLER(dap_apid_command)
1511 {
1512         struct target *target = get_current_target(CMD_CTX);
1513         struct arm *arm = target_to_arm(target);
1514         struct adiv5_dap *dap = arm->dap;
1515
1516         uint32_t apsel, apselsave, apid;
1517         int retval;
1518
1519         apselsave = dap->apsel;
1520         switch (CMD_ARGC) {
1521         case 0:
1522                 apsel = dap->apsel;
1523                 break;
1524         case 1:
1525                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1526                 /* AP address is in bits 31:24 of DP_SELECT */
1527                 if (apsel >= 256)
1528                         return ERROR_INVALID_ARGUMENTS;
1529                 break;
1530         default:
1531                 return ERROR_COMMAND_SYNTAX_ERROR;
1532         }
1533
1534         if (apselsave != apsel)
1535                 dap_ap_select(dap, apsel);
1536
1537         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1538         retval = dap_run(dap);
1539         if (retval != ERROR_OK)
1540                 return retval;
1541
1542         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1543         if (apselsave != apsel)
1544                 dap_ap_select(dap, apselsave);
1545
1546         return retval;
1547 }
1548
1549 static const struct command_registration dap_commands[] = {
1550         {
1551                 .name = "info",
1552                 .handler = handle_dap_info_command,
1553                 .mode = COMMAND_EXEC,
1554                 .help = "display ROM table for MEM-AP "
1555                         "(default currently selected AP)",
1556                 .usage = "[ap_num]",
1557         },
1558         {
1559                 .name = "apsel",
1560                 .handler = dap_apsel_command,
1561                 .mode = COMMAND_EXEC,
1562                 .help = "Set the currently selected AP (default 0) "
1563                         "and display the result",
1564                 .usage = "[ap_num]",
1565         },
1566         {
1567                 .name = "apid",
1568                 .handler = dap_apid_command,
1569                 .mode = COMMAND_EXEC,
1570                 .help = "return ID register from AP "
1571                         "(default currently selected AP)",
1572                 .usage = "[ap_num]",
1573         },
1574         {
1575                 .name = "baseaddr",
1576                 .handler = dap_baseaddr_command,
1577                 .mode = COMMAND_EXEC,
1578                 .help = "return debug base address from MEM-AP "
1579                         "(default currently selected AP)",
1580                 .usage = "[ap_num]",
1581         },
1582         {
1583                 .name = "memaccess",
1584                 .handler = dap_memaccess_command,
1585                 .mode = COMMAND_EXEC,
1586                 .help = "set/get number of extra tck for MEM-AP memory "
1587                         "bus access [0-255]",
1588                 .usage = "[cycles]",
1589         },
1590         COMMAND_REGISTRATION_DONE
1591 };
1592
1593 const struct command_registration dap_command_handlers[] = {
1594         {
1595                 .name = "dap",
1596                 .mode = COMMAND_EXEC,
1597                 .help = "DAP command group",
1598                 .chain = dap_commands,
1599         },
1600         COMMAND_REGISTRATION_DONE
1601 };
1602
1603