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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 /**
  28  * @file
  29  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  30  * debugging architecture.  Compared with previous versions, this includes
  31  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  32  * transport, and focusses on memory mapped resources as defined by the
  33  * CoreSight architecture.
  34  *
  35  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  36  * basic components:  a Debug Port (DP) transporting messages to and from a
  37  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  38  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  39  * One uses only SWD for communication, and is called SW-DP.  The third can
  40  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  41  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  42  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  43  */
  44
  45 /*
  46  * Relevant specifications from ARM include:
  47  *
  48  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  49  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  50  *
  51  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  52  * Cortex-M3(tm) TRM, ARM DDI 0337G
  53  */
  54
  55 #ifdef HAVE_CONFIG_H
  56 #include "config.h"
  57 #endif
  58
  59 #include "arm_adi_v5.h"
  60 #include <helper/time_support.h>
  61
  62 /*
  63  * Transaction Mode:
  64  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  66  * result checking until swjdp_end_transaction()
  67  * This must be done before using or deallocating any return variables.
  68  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  69  * All reads and writes to the AHB bus are checked for valid completion, and return values
  70  * are immediatley available.
  71 */
  72
  73
  74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  75
  76 /*
  77         uint32_t tar_block_size(uint32_t address)
  78         Return the largest block starting at address that does not cross a tar block size alignment boundary
  79 */
  80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  81 {
  82         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  83 }
  84
  85 /***************************************************************************
  86  *                                                                         *
  87  * DPACC and APACC scanchain access through JTAG-DP                        *
  88  *                                                                         *
  89 ***************************************************************************/
  90
  91 /**
  92  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  93  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  94  * discusses operations which access these registers.
  95  *
  96  * Note that only one scan is performed.  If RnW is set, a separate scan
  97  * will be needed to collect the data which was read; the "invalue" collects
  98  * the posted result of a preceding operation, not the current one.
  99  *
 100  * @param swjdp the DAP
 101  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 102  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 103  *      SELECT register has more addressing bits.
 104  * @param RnW false iff outvalue will be written to the DP or AP
 105  * @param outvalue points to a 32-bit (little-endian) integer
 106  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 107  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 108  */
 109 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 110                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 111                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 112 {
 113         struct arm_jtag *jtag_info = swjdp->jtag_info;
 114         struct scan_field fields[2];
 115         uint8_t out_addr_buf;
 116
 117         jtag_set_end_state(TAP_IDLE);
 118         arm_jtag_set_instr(jtag_info, instr, NULL);
 119
 120         /* Add specified number of tck clocks before accessing memory bus */
 121
 122         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 123          * they provide more time for the (MEM) AP to complete the read ...
 124          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 125          */
 126         if ((instr == JTAG_DP_APACC)
 127                         && ((reg_addr == AP_REG_DRW)
 128                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 129                         && (swjdp->memaccess_tck != 0))
 130                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 131
 132         /* Scan out a read or write operation using some DP or AP register.
 133          * For APACC access with any sticky error flag set, this is discarded.
 134          */
 135         fields[0].tap = jtag_info->tap;
 136         fields[0].num_bits = 3;
 137         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 138         fields[0].out_value = &out_addr_buf;
 139         fields[0].in_value = ack;
 140
 141         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 142          * complete; data we write is discarded, data we read is unpredictable.
 143          * When overrun detect is active, STICKYORUN is set.
 144          */
 145
 146         fields[1].tap = jtag_info->tap;
 147         fields[1].num_bits = 32;
 148         fields[1].out_value = outvalue;
 149         fields[1].in_value = invalue;
 150
 151         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 152
 153         return ERROR_OK;
 154 }
 155
 156 /* Scan out and in from host ordered uint32_t variables */
 157 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 158                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 159                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 160 {
 161         struct arm_jtag *jtag_info = swjdp->jtag_info;
 162         struct scan_field fields[2];
 163         uint8_t out_value_buf[4];
 164         uint8_t out_addr_buf;
 165
 166         jtag_set_end_state(TAP_IDLE);
 167         arm_jtag_set_instr(jtag_info, instr, NULL);
 168
 169         /* Add specified number of tck clocks before accessing memory bus */
 170
 171         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 172          * they provide more time for the (MEM) AP to complete the read ...
 173          */
 174         if ((instr == JTAG_DP_APACC)
 175                         && ((reg_addr == AP_REG_DRW)
 176                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 177                         && (swjdp->memaccess_tck != 0))
 178                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 179
 180         fields[0].tap = jtag_info->tap;
 181         fields[0].num_bits = 3;
 182         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 183         fields[0].out_value = &out_addr_buf;
 184         fields[0].in_value = ack;
 185
 186         fields[1].tap = jtag_info->tap;
 187         fields[1].num_bits = 32;
 188         buf_set_u32(out_value_buf, 0, 32, outvalue);
 189         fields[1].out_value = out_value_buf;
 190         fields[1].in_value = NULL;
 191
 192         if (invalue)
 193         {
 194                 fields[1].in_value = (uint8_t *)invalue;
 195                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 196
 197                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 198         } else
 199         {
 200
 201                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 202         }
 203
 204         return ERROR_OK;
 205 }
 206
 207 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 208 static int scan_inout_check(struct swjdp_common *swjdp,
 209                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 210                 uint8_t *outvalue, uint8_t *invalue)
 211 {
 212         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 213
 214         if ((RnW == DPAP_READ) && (invalue != NULL))
 215                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 216                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 217
 218         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 219          * ack = OK/FAULT and the check CTRL_STAT
 220          */
 221         if ((instr == JTAG_DP_APACC)
 222                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 223                 return swjdp_transaction_endcheck(swjdp);
 224
 225         return ERROR_OK;
 226 }
 227
 228 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 229                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 230                 uint32_t outvalue, uint32_t *invalue)
 231 {
 232         /* Issue the read or write */
 233         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 234
 235         /* For reads,  collect posted value; RDBUFF has no other effect.
 236          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 237          */
 238         if ((RnW == DPAP_READ) && (invalue != NULL))
 239                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 240                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 241
 242         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 243          * ack = OK/FAULT and then check CTRL_STAT
 244          */
 245         if ((instr == JTAG_DP_APACC)
 246                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 247                 return swjdp_transaction_endcheck(swjdp);
 248
 249         return ERROR_OK;
 250 }
 251
 252 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 253 {
 254         int retval;
 255         uint32_t ctrlstat;
 256
 257         /* too expensive to call keep_alive() here */
 258
 259 #if 0
 260         /* Danger!!!! BROKEN!!!! */
 261         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 262                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 263         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 264         R956 introduced the check on return value here and now Michael Schwingen reports
 265         that this code no longer works....
 266
 267         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 268         */
 269         if ((retval = jtag_execute_queue()) != ERROR_OK)
 270         {
 271                 LOG_ERROR("BUG: Why does this fail the first time????");
 272         }
 273         /* Why??? second time it works??? */
 274 #endif
 275
 276         /* Post CTRL/STAT read; discard any previous posted read value
 277          * but collect its ACK status.
 278          */
 279         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 280                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 281         if ((retval = jtag_execute_queue()) != ERROR_OK)
 282                 return retval;
 283
 284         swjdp->ack = swjdp->ack & 0x7;
 285
 286         /* common code path avoids calling timeval_ms() */
 287         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 288         {
 289                 long long then = timeval_ms();
 290
 291                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 292                 {
 293                         if (swjdp->ack == JTAG_ACK_WAIT)
 294                         {
 295                                 if ((timeval_ms()-then) > 1000)
 296                                 {
 297                                         /* NOTE:  this would be a good spot
 298                                          * to use JTAG_DP_ABORT.
 299                                          */
 300                                         LOG_WARNING("Timeout (1000ms) waiting "
 301                                                 "for ACK=OK/FAULT "
 302                                                 "in JTAG-DP transaction");
 303                                         return ERROR_JTAG_DEVICE_ERROR;
 304                                 }
 305                         }
 306                         else
 307                         {
 308                                 LOG_WARNING("Invalid ACK "
 309                                                 "in JTAG-DP transaction");
 310                                 return ERROR_JTAG_DEVICE_ERROR;
 311                         }
 312
 313                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 314                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 315                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 316                                 return retval;
 317                         swjdp->ack = swjdp->ack & 0x7;
 318                 }
 319         }
 320
 321         /* Check for STICKYERR and STICKYORUN */
 322         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 323         {
 324                 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
 325                 /* Check power to debug regions */
 326                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 327                 {
 328                          ahbap_debugport_init(swjdp);
 329                 }
 330                 else
 331                 {
 332                         uint32_t mem_ap_csw, mem_ap_tar;
 333
 334                         /* Print information about last AHBAP access */
 335                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
 336                         if (ctrlstat & SSTICKYORUN)
 337                                 LOG_ERROR("JTAG-DP OVERRUN - "
 338                                         "check clock or reduce jtag speed");
 339
 340                         if (ctrlstat & SSTICKYERR)
 341                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 342
 343                         /* Clear Sticky Error Bits */
 344                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 345                                         DP_CTRL_STAT, DPAP_WRITE,
 346                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 347                                                 | SSTICKYERR, NULL);
 348                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 349                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 350                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 351                                 return retval;
 352
 353                         LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
 354
 355                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 356                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 357                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 358                                 return retval;
 359                         LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
 360
 361                 }
 362                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 363                         return retval;
 364                 return ERROR_JTAG_DEVICE_ERROR;
 365         }
 366
 367         return ERROR_OK;
 368 }
 369
 370 /***************************************************************************
 371  *                                                                         *
 372  * DP and MEM-AP  register access  through APACC and DPACC                 *
 373  *                                                                         *
 374 ***************************************************************************/
 375
 376 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 377                 uint32_t value, uint8_t reg_addr)
 378 {
 379         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 380                         reg_addr, DPAP_WRITE, value, NULL);
 381 }
 382
 383 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 384                 uint32_t *value, uint8_t reg_addr)
 385 {
 386         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 387                         reg_addr, DPAP_READ, 0, value);
 388 }
 389
 390 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 391 {
 392         uint32_t select;
 393         select = (apsel << 24) & 0xFF000000;
 394
 395         if (select != swjdp->apsel)
 396         {
 397                 swjdp->apsel = select;
 398                 /* Switching AP invalidates cached values */
 399                 swjdp->dp_select_value = -1;
 400                 swjdp->ap_csw_value = -1;
 401                 swjdp->ap_tar_value = -1;
 402         }
 403
 404         return ERROR_OK;
 405 }
 406
 407 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 408 {
 409         uint32_t select;
 410         select = (ap_reg & 0x000000F0);
 411
 412         if (select != swjdp->dp_select_value)
 413         {
 414                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 415                 swjdp->dp_select_value = select;
 416         }
 417
 418         return ERROR_OK;
 419 }
 420
 421 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 422                 uint32_t reg_addr, uint8_t *out_value_buf)
 423 {
 424         dap_dp_bankselect(swjdp, reg_addr);
 425         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 426                         DPAP_WRITE, out_value_buf, NULL);
 427
 428         return ERROR_OK;
 429 }
 430
 431 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 432 {
 433         uint8_t out_value_buf[4];
 434
 435         buf_set_u32(out_value_buf, 0, 32, value);
 436         dap_dp_bankselect(swjdp, reg_addr);
 437         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 438                         DPAP_WRITE, out_value_buf, NULL);
 439
 440         return ERROR_OK;
 441 }
 442
 443 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 444 {
 445         dap_dp_bankselect(swjdp, reg_addr);
 446         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 447                         DPAP_READ, 0, value);
 448
 449         return ERROR_OK;
 450 }
 451
 452 /***************************************************************************
 453  *                                                                         *
 454  * AHB-AP access to memory and system registers on AHB bus                 *
 455  *                                                                         *
 456 ***************************************************************************/
 457
 458 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 459 {
 460         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 461         if (csw != swjdp->ap_csw_value)
 462         {
 463                 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
 464                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 465                 swjdp->ap_csw_value = csw;
 466         }
 467         if (tar != swjdp->ap_tar_value)
 468         {
 469                 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
 470                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 471                 swjdp->ap_tar_value = tar;
 472         }
 473         if (csw & CSW_ADDRINC_MASK)
 474         {
 475                 /* Do not cache TAR value when autoincrementing */
 476                 swjdp->ap_tar_value = -1;
 477         }
 478         return ERROR_OK;
 479 }
 480
 481 /*****************************************************************************
 482 *                                                                            *
 483 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 484 *                                                                            *
 485 * Read a uint32_t value from memory or system register                            *
 486 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 487 * but with less overhead                                                     *
 488 *****************************************************************************/
 489 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 490 {
 491         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 492
 493         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 494         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 495
 496         return ERROR_OK;
 497 }
 498
 499 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 500 {
 501         mem_ap_read_u32(swjdp, address, value);
 502
 503         return swjdp_transaction_endcheck(swjdp);
 504 }
 505
 506 /*****************************************************************************
 507 *                                                                            *
 508 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 509 *                                                                            *
 510 * Write a uint32_t value to memory or memory mapped register                              *
 511 *                                                                            *
 512 *****************************************************************************/
 513 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 514 {
 515         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 516
 517         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 518         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 519
 520         return ERROR_OK;
 521 }
 522
 523 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 524 {
 525         mem_ap_write_u32(swjdp, address, value);
 526
 527         return swjdp_transaction_endcheck(swjdp);
 528 }
 529
 530 /*****************************************************************************
 531 *                                                                            *
 532 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 533 *                                                                            *
 534 * Write a buffer in target order (little endian)                             *
 535 *                                                                            *
 536 *****************************************************************************/
 537 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 538 {
 539         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 540         uint32_t adr = address;
 541         uint8_t* pBuffer = buffer;
 542
 543         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 544
 545         count >>= 2;
 546         wcount = count;
 547
 548         /* if we have an unaligned access - reorder data */
 549         if (adr & 0x3u)
 550         {
 551                 for (writecount = 0; writecount < count; writecount++)
 552                 {
 553                         int i;
 554                         uint32_t outvalue;
 555                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 556
 557                         for (i = 0; i < 4; i++)
 558                         {
 559                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 560                                 outvalue >>= 8;
 561                                 adr++;
 562                         }
 563                         pBuffer += sizeof(uint32_t);
 564                 }
 565         }
 566
 567         while (wcount > 0)
 568         {
 569                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 570                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 571                 if (wcount < blocksize)
 572                         blocksize = wcount;
 573
 574                 /* handle unaligned data at 4k boundary */
 575                 if (blocksize == 0)
 576                         blocksize = 1;
 577
 578                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 579
 580                 for (writecount = 0; writecount < blocksize; writecount++)
 581                 {
 582                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 583                 }
 584
 585                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 586                 {
 587                         wcount = wcount - blocksize;
 588                         address = address + 4 * blocksize;
 589                         buffer = buffer + 4 * blocksize;
 590                 }
 591                 else
 592                 {
 593                         errorcount++;
 594                 }
 595
 596                 if (errorcount > 1)
 597                 {
 598                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 599                         return ERROR_JTAG_DEVICE_ERROR;
 600                 }
 601         }
 602
 603         return retval;
 604 }
 605
 606 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 607                 uint8_t *buffer, int count, uint32_t address)
 608 {
 609         int retval = ERROR_OK;
 610         int wcount, blocksize, writecount, i;
 611
 612         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 613
 614         wcount = count >> 1;
 615
 616         while (wcount > 0)
 617         {
 618                 int nbytes;
 619
 620                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 621                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 622
 623                 if (wcount < blocksize)
 624                         blocksize = wcount;
 625
 626                 /* handle unaligned data at 4k boundary */
 627                 if (blocksize == 0)
 628                         blocksize = 1;
 629
 630                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 631                 writecount = blocksize;
 632
 633                 do
 634                 {
 635                         nbytes = MIN((writecount << 1), 4);
 636
 637                         if (nbytes < 4)
 638                         {
 639                                 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
 640                                 {
 641                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 642                                         return ERROR_JTAG_DEVICE_ERROR;
 643                                 }
 644
 645                                 address += nbytes >> 1;
 646                         }
 647                         else
 648                         {
 649                                 uint32_t outvalue;
 650                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 651
 652                                 for (i = 0; i < nbytes; i++)
 653                                 {
 654                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 655                                         outvalue >>= 8;
 656                                         address++;
 657                                 }
 658
 659                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 660                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 661                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 662                                 {
 663                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 664                                         return ERROR_JTAG_DEVICE_ERROR;
 665                                 }
 666                         }
 667
 668                         buffer += nbytes >> 1;
 669                         writecount -= nbytes >> 1;
 670
 671                 } while (writecount);
 672                 wcount -= blocksize;
 673         }
 674
 675         return retval;
 676 }
 677
 678 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 679 {
 680         int retval = ERROR_OK;
 681
 682         if (count >= 4)
 683                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 684
 685         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 686
 687         while (count > 0)
 688         {
 689                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 690                 uint16_t svalue;
 691                 memcpy(&svalue, buffer, sizeof(uint16_t));
 692                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 693                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 694                 retval = swjdp_transaction_endcheck(swjdp);
 695                 count -= 2;
 696                 address += 2;
 697                 buffer += 2;
 698         }
 699
 700         return retval;
 701 }
 702
 703 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 704                 uint8_t *buffer, int count, uint32_t address)
 705 {
 706         int retval = ERROR_OK;
 707         int wcount, blocksize, writecount, i;
 708
 709         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 710
 711         wcount = count;
 712
 713         while (wcount > 0)
 714         {
 715                 int nbytes;
 716
 717                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 718                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 719
 720                 if (wcount < blocksize)
 721                         blocksize = wcount;
 722
 723                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 724                 writecount = blocksize;
 725
 726                 do
 727                 {
 728                         nbytes = MIN(writecount, 4);
 729
 730                         if (nbytes < 4)
 731                         {
 732                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 733                                 {
 734                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 735                                         return ERROR_JTAG_DEVICE_ERROR;
 736                                 }
 737
 738                                 address += nbytes;
 739                         }
 740                         else
 741                         {
 742                                 uint32_t outvalue;
 743                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 744
 745                                 for (i = 0; i < nbytes; i++)
 746                                 {
 747                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 748                                         outvalue >>= 8;
 749                                         address++;
 750                                 }
 751
 752                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 753                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 754                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 755                                 {
 756                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 757                                         return ERROR_JTAG_DEVICE_ERROR;
 758                                 }
 759                         }
 760
 761                         buffer += nbytes;
 762                         writecount -= nbytes;
 763
 764                 } while (writecount);
 765                 wcount -= blocksize;
 766         }
 767
 768         return retval;
 769 }
 770
 771 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 772 {
 773         int retval = ERROR_OK;
 774
 775         if (count >= 4)
 776                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 777
 778         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 779
 780         while (count > 0)
 781         {
 782                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 783                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 784                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 785                 retval = swjdp_transaction_endcheck(swjdp);
 786                 count--;
 787                 address++;
 788                 buffer++;
 789         }
 790
 791         return retval;
 792 }
 793
 794 /*********************************************************************************
 795 *                                                                                *
 796 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 797 *                                                                                *
 798 * Read block fast in target order (little endian) into a buffer                  *
 799 *                                                                                *
 800 **********************************************************************************/
 801 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 802 {
 803         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 804         uint32_t adr = address;
 805         uint8_t* pBuffer = buffer;
 806
 807         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 808
 809         count >>= 2;
 810         wcount = count;
 811
 812         while (wcount > 0)
 813         {
 814                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 815                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 816                 if (wcount < blocksize)
 817                         blocksize = wcount;
 818
 819                 /* handle unaligned data at 4k boundary */
 820                 if (blocksize == 0)
 821                         blocksize = 1;
 822
 823                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 824
 825                 /* Scan out first read */
 826                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 827                                 DPAP_READ, 0, NULL, NULL);
 828                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 829                 {
 830                         /* Scan out next read; scan in posted value for the
 831                          * previous one.  Assumes read is acked "OK/FAULT",
 832                          * and CTRL_STAT says that meant "OK".
 833                          */
 834                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 835                                         DPAP_READ, 0, buffer + 4 * readcount,
 836                                         &swjdp->ack);
 837                 }
 838
 839                 /* Scan in last posted value; RDBUFF has no other effect,
 840                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 841                  */
 842                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 843                                 DPAP_READ, 0, buffer + 4 * readcount,
 844                                 &swjdp->ack);
 845                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 846                 {
 847                         wcount = wcount - blocksize;
 848                         address += 4 * blocksize;
 849                         buffer += 4 * blocksize;
 850                 }
 851                 else
 852                 {
 853                         errorcount++;
 854                 }
 855
 856                 if (errorcount > 1)
 857                 {
 858                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 859                         return ERROR_JTAG_DEVICE_ERROR;
 860                 }
 861         }
 862
 863         /* if we have an unaligned access - reorder data */
 864         if (adr & 0x3u)
 865         {
 866                 for (readcount = 0; readcount < count; readcount++)
 867                 {
 868                         int i;
 869                         uint32_t data;
 870                         memcpy(&data, pBuffer, sizeof(uint32_t));
 871
 872                         for (i = 0; i < 4; i++)
 873                         {
 874                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 875                                 pBuffer++;
 876                                 adr++;
 877                         }
 878                 }
 879         }
 880
 881         return retval;
 882 }
 883
 884 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 885                 uint8_t *buffer, int count, uint32_t address)
 886 {
 887         uint32_t invalue;
 888         int retval = ERROR_OK;
 889         int wcount, blocksize, readcount, i;
 890
 891         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 892
 893         wcount = count >> 1;
 894
 895         while (wcount > 0)
 896         {
 897                 int nbytes;
 898
 899                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 900                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 901                 if (wcount < blocksize)
 902                         blocksize = wcount;
 903
 904                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 905
 906                 /* handle unaligned data at 4k boundary */
 907                 if (blocksize == 0)
 908                         blocksize = 1;
 909                 readcount = blocksize;
 910
 911                 do
 912                 {
 913                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 914                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 915                         {
 916                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 917                                 return ERROR_JTAG_DEVICE_ERROR;
 918                         }
 919
 920                         nbytes = MIN((readcount << 1), 4);
 921
 922                         for (i = 0; i < nbytes; i++)
 923                         {
 924                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 925                                 buffer++;
 926                                 address++;
 927                         }
 928
 929                         readcount -= (nbytes >> 1);
 930                 } while (readcount);
 931                 wcount -= blocksize;
 932         }
 933
 934         return retval;
 935 }
 936
 937 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 938 {
 939         uint32_t invalue, i;
 940         int retval = ERROR_OK;
 941
 942         if (count >= 4)
 943                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 944
 945         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 946
 947         while (count > 0)
 948         {
 949                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 950                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 951                 retval = swjdp_transaction_endcheck(swjdp);
 952                 if (address & 0x1)
 953                 {
 954                         for (i = 0; i < 2; i++)
 955                         {
 956                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 957                                 buffer++;
 958                                 address++;
 959                         }
 960                 }
 961                 else
 962                 {
 963                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 964                         memcpy(buffer, &svalue, sizeof(uint16_t));
 965                         address += 2;
 966                         buffer += 2;
 967                 }
 968                 count -= 2;
 969         }
 970
 971         return retval;
 972 }
 973
 974 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 975  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 976  *
 977  * The solution is to arrange for a large out/in scan in this loop and
 978  * and convert data afterwards.
 979  */
 980 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 981                 uint8_t *buffer, int count, uint32_t address)
 982 {
 983         uint32_t invalue;
 984         int retval = ERROR_OK;
 985         int wcount, blocksize, readcount, i;
 986
 987         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 988
 989         wcount = count;
 990
 991         while (wcount > 0)
 992         {
 993                 int nbytes;
 994
 995                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 996                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 997
 998                 if (wcount < blocksize)
 999                         blocksize = wcount;
1000
1001                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1002                 readcount = blocksize;
1003
1004                 do
1005                 {
1006                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1007                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
1008                         {
1009                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1010                                 return ERROR_JTAG_DEVICE_ERROR;
1011                         }
1012
1013                         nbytes = MIN(readcount, 4);
1014
1015                         for (i = 0; i < nbytes; i++)
1016                         {
1017                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1018                                 buffer++;
1019                                 address++;
1020                         }
1021
1022                         readcount -= nbytes;
1023                 } while (readcount);
1024                 wcount -= blocksize;
1025         }
1026
1027         return retval;
1028 }
1029
1030 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1031 {
1032         uint32_t invalue;
1033         int retval = ERROR_OK;
1034
1035         if (count >= 4)
1036                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1037
1038         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1039
1040         while (count > 0)
1041         {
1042                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1043                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1044                 retval = swjdp_transaction_endcheck(swjdp);
1045                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1046                 count--;
1047                 address++;
1048                 buffer++;
1049         }
1050
1051         return retval;
1052 }
1053
1054 /**
1055  * Initialize a DAP.
1056  *
1057  * @todo Rename this.  We also need an initialization scheme which account
1058  * for SWD transports not just JTAG; that will need to address differences
1059  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1060  */
1061 int ahbap_debugport_init(struct swjdp_common *swjdp)
1062 {
1063         uint32_t idreg, romaddr, dummy;
1064         uint32_t ctrlstat;
1065         int cnt = 0;
1066         int retval;
1067
1068         LOG_DEBUG(" ");
1069
1070         /* Default MEM-AP setup.
1071          *
1072          * REVISIT AP #0 may be an inappropriate default for this.
1073          * Should we probe, or receve a hint from the caller?
1074          * Presumably we can ignore the possibility of multiple APs.
1075          */
1076         swjdp->apsel = 0;
1077         swjdp->ap_csw_value = -1;
1078         swjdp->ap_tar_value = -1;
1079
1080         /* DP initialization */
1081         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1082         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1083         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1084         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1085
1086         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1087
1088         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1089         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1090         if ((retval = jtag_execute_queue()) != ERROR_OK)
1091                 return retval;
1092
1093         /* Check that we have debug power domains activated */
1094         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1095         {
1096                 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1097                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1098                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1099                         return retval;
1100                 alive_sleep(10);
1101         }
1102
1103         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1104         {
1105                 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1106                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1107                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1108                         return retval;
1109                 alive_sleep(10);
1110         }
1111
1112         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1113         /* With debug power on we can activate OVERRUN checking */
1114         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1115         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1116         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1117
1118         /*
1119          * REVISIT this isn't actually *initializing* anything in an AP,
1120          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1121          * Should it?  If the ROM address is valid, is this the right
1122          * place to scan the table and do any topology detection?
1123          */
1124         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1125         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1126
1127         LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1128
1129         return ERROR_OK;
1130 }
1131
1132 /* CID interpretation -- see ARM IHI 0029B section 3
1133  * and ARM IHI 0031A table 13-3.
1134  */
1135 static const char *class_description[16] ={
1136         "Reserved", "ROM table", "Reserved", "Reserved",
1137         "Reserved", "Reserved", "Reserved", "Reserved",
1138         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1139         "Reserved", "OptimoDE DESS",
1140                 "Generic IP component", "PrimeCell or System component"
1141 };
1142
1143 static bool
1144 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1145 {
1146         return cid3 == 0xb1 && cid2 == 0x05
1147                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1148 }
1149
1150 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1151 {
1152
1153         uint32_t dbgbase, apid;
1154         int romtable_present = 0;
1155         uint8_t mem_ap;
1156         uint32_t apselold;
1157
1158         apselold = swjdp->apsel;
1159         dap_ap_select(swjdp, apsel);
1160         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1161         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1162         swjdp_transaction_endcheck(swjdp);
1163         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1164         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1165         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1166         if (apid)
1167         {
1168                 switch (apid&0x0F)
1169                 {
1170                         case 0:
1171                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1172                                 break;
1173                         case 1:
1174                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1175                                 break;
1176                         case 2:
1177                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1178                                 break;
1179                         default:
1180                                 command_print(cmd_ctx, "\tUnknown AP type");
1181                                 break;
1182                 }
1183
1184                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1185                  * not a ROM table ... or have no such components at all.
1186                  */
1187                 if (mem_ap)
1188                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1189                                         dbgbase);
1190         }
1191         else
1192         {
1193                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1194         }
1195
1196         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1197         if (romtable_present)
1198         {
1199                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1200                 uint16_t entry_offset;
1201
1202                 /* bit 16 of apid indicates a memory access port */
1203                 if (dbgbase & 0x02)
1204                         command_print(cmd_ctx, "\tValid ROM table present");
1205                 else
1206                         command_print(cmd_ctx, "\tROM table in legacy format");
1207
1208                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1209                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1210                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1211                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1212                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1213                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1214                 swjdp_transaction_endcheck(swjdp);
1215                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1216                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1217                                         ", CID2 0x%2.2" PRIx32
1218                                         ", CID1 0x%2.2" PRIx32
1219                                         ", CID0 0x%2.2" PRIx32,
1220                                         cid3, cid2, cid1, cid0);
1221                 if (memtype & 0x01)
1222                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1223                 else
1224                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1225                                         "Dedicated debug bus.");
1226
1227                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1228                 entry_offset = 0;
1229                 do
1230                 {
1231                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1232                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1233                         if (romentry&0x01)
1234                         {
1235                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1236                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1237                                 uint32_t component_start, component_base;
1238                                 unsigned part_num;
1239                                 char *type, *full;
1240
1241                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1242                                                 + (int)(romentry & 0xFFFFF000));
1243                                 mem_ap_read_atomic_u32(swjdp,
1244                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1245                                 mem_ap_read_atomic_u32(swjdp,
1246                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1247                                 mem_ap_read_atomic_u32(swjdp,
1248                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1249                                 mem_ap_read_atomic_u32(swjdp,
1250                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1251                                 mem_ap_read_atomic_u32(swjdp,
1252                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1253                                 mem_ap_read_atomic_u32(swjdp,
1254                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1255                                 mem_ap_read_atomic_u32(swjdp,
1256                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1257                                 mem_ap_read_atomic_u32(swjdp,
1258                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1259                                 mem_ap_read_atomic_u32(swjdp,
1260                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1261                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1262
1263                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1264                                                 ", start address 0x%" PRIx32,
1265                                                 component_base, component_start);
1266                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1267                                                 (int) (c_cid1 >> 4) & 0xf,
1268                                                 /* See ARM IHI 0029B Table 3-3 */
1269                                                 class_description[(c_cid1 >> 4) & 0xf]);
1270
1271                                 /* CoreSight component? */
1272                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1273                                         uint32_t devtype;
1274                                         unsigned minor;
1275                                         char *major = "Reserved", *subtype = "Reserved";
1276
1277                                         mem_ap_read_atomic_u32(swjdp,
1278                                                         (component_base & 0xfffff000) | 0xfcc,
1279                                                         &devtype);
1280                                         minor = (devtype >> 4) & 0x0f;
1281                                         switch (devtype & 0x0f) {
1282                                         case 0:
1283                                                 major = "Miscellaneous";
1284                                                 switch (minor) {
1285                                                 case 0:
1286                                                         subtype = "other";
1287                                                         break;
1288                                                 case 4:
1289                                                         subtype = "Validation component";
1290                                                         break;
1291                                                 }
1292                                                 break;
1293                                         case 1:
1294                                                 major = "Trace Sink";
1295                                                 switch (minor) {
1296                                                 case 0:
1297                                                         subtype = "other";
1298                                                         break;
1299                                                 case 1:
1300                                                         subtype = "Port";
1301                                                         break;
1302                                                 case 2:
1303                                                         subtype = "Buffer";
1304                                                         break;
1305                                                 }
1306                                                 break;
1307                                         case 2:
1308                                                 major = "Trace Link";
1309                                                 switch (minor) {
1310                                                 case 0:
1311                                                         subtype = "other";
1312                                                         break;
1313                                                 case 1:
1314                                                         subtype = "Funnel, router";
1315                                                         break;
1316                                                 case 2:
1317                                                         subtype = "Filter";
1318                                                         break;
1319                                                 case 3:
1320                                                         subtype = "FIFO, buffer";
1321                                                         break;
1322                                                 }
1323                                                 break;
1324                                         case 3:
1325                                                 major = "Trace Source";
1326                                                 switch (minor) {
1327                                                 case 0:
1328                                                         subtype = "other";
1329                                                         break;
1330                                                 case 1:
1331                                                         subtype = "Processor";
1332                                                         break;
1333                                                 case 2:
1334                                                         subtype = "DSP";
1335                                                         break;
1336                                                 case 3:
1337                                                         subtype = "Engine/Coprocessor";
1338                                                         break;
1339                                                 case 4:
1340                                                         subtype = "Bus";
1341                                                         break;
1342                                                 }
1343                                                 break;
1344                                         case 4:
1345                                                 major = "Debug Control";
1346                                                 switch (minor) {
1347                                                 case 0:
1348                                                         subtype = "other";
1349                                                         break;
1350                                                 case 1:
1351                                                         subtype = "Trigger Matrix";
1352                                                         break;
1353                                                 case 2:
1354                                                         subtype = "Debug Auth";
1355                                                         break;
1356                                                 }
1357                                                 break;
1358                                         case 5:
1359                                                 major = "Debug Logic";
1360                                                 switch (minor) {
1361                                                 case 0:
1362                                                         subtype = "other";
1363                                                         break;
1364                                                 case 1:
1365                                                         subtype = "Processor";
1366                                                         break;
1367                                                 case 2:
1368                                                         subtype = "DSP";
1369                                                         break;
1370                                                 case 3:
1371                                                         subtype = "Engine/Coprocessor";
1372                                                         break;
1373                                                 }
1374                                                 break;
1375                                         }
1376                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1377                                                         (unsigned) (devtype & 0xff),
1378                                                         major, subtype);
1379                                         /* REVISIT also show 0xfc8 DevId */
1380                                 }
1381
1382                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1383                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1384                                                         ", CID2 0x%2.2" PRIx32
1385                                                         ", CID1 0x%2.2" PRIx32
1386                                                         ", CID0 0x%2.2" PRIx32,
1387                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1388                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1389                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1390                                                 (int) c_pid4,
1391                                                 (int) c_pid3, (int) c_pid2,
1392                                                 (int) c_pid1, (int) c_pid0);
1393
1394                                 /* Part number interpretations are from Cortex
1395                                  * core specs, the CoreSight components TRM
1396                                  * (ARM DDI 0314H), and ETM specs; also from
1397                                  * chip observation (e.g. TI SDTI).
1398                                  */
1399                                 part_num = c_pid0 & 0xff;
1400                                 part_num |= (c_pid1 & 0x0f) << 8;
1401                                 switch (part_num) {
1402                                 case 0x000:
1403                                         type = "Cortex-M3 NVIC";
1404                                         full = "(Interrupt Controller)";
1405                                         break;
1406                                 case 0x001:
1407                                         type = "Cortex-M3 ITM";
1408                                         full = "(Instrumentation Trace Module)";
1409                                         break;
1410                                 case 0x002:
1411                                         type = "Cortex-M3 DWT";
1412                                         full = "(Data Watchpoint and Trace)";
1413                                         break;
1414                                 case 0x003:
1415                                         type = "Cortex-M3 FBP";
1416                                         full = "(Flash Patch and Breakpoint)";
1417                                         break;
1418                                 case 0x00d:
1419                                         type = "CoreSight ETM11";
1420                                         full = "(Embedded Trace)";
1421                                         break;
1422                                 // case 0x113: what?
1423                                 case 0x120:             /* from OMAP3 memmap */
1424                                         type = "TI SDTI";
1425                                         full = "(System Debug Trace Interface)";
1426                                         break;
1427                                 case 0x343:             /* from OMAP3 memmap */
1428                                         type = "TI DAPCTL";
1429                                         full = "";
1430                                         break;
1431                                 case 0x4e0:
1432                                         type = "Cortex-M3 ETM";
1433                                         full = "(Embedded Trace)";
1434                                         break;
1435                                 case 0x906:
1436                                         type = "Coresight CTI";
1437                                         full = "(Cross Trigger)";
1438                                         break;
1439                                 case 0x907:
1440                                         type = "Coresight ETB";
1441                                         full = "(Trace Buffer)";
1442                                         break;
1443                                 case 0x908:
1444                                         type = "Coresight CSTF";
1445                                         full = "(Trace Funnel)";
1446                                         break;
1447                                 case 0x910:
1448                                         type = "CoreSight ETM9";
1449                                         full = "(Embedded Trace)";
1450                                         break;
1451                                 case 0x912:
1452                                         type = "Coresight TPIU";
1453                                         full = "(Trace Port Interface Unit)";
1454                                         break;
1455                                 case 0x921:
1456                                         type = "Cortex-A8 ETM";
1457                                         full = "(Embedded Trace)";
1458                                         break;
1459                                 case 0x922:
1460                                         type = "Cortex-A8 CTI";
1461                                         full = "(Cross Trigger)";
1462                                         break;
1463                                 case 0x923:
1464                                         type = "Cortex-M3 TPIU";
1465                                         full = "(Trace Port Interface Unit)";
1466                                         break;
1467                                 case 0xc08:
1468                                         type = "Cortex-A8 Debug";
1469                                         full = "(Debug Unit)";
1470                                         break;
1471                                 default:
1472                                         type = "-*- unrecognized -*-";
1473                                         full = "";
1474                                         break;
1475                                 }
1476                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1477                                                 type, full);
1478                         }
1479                         else
1480                         {
1481                                 if (romentry)
1482                                         command_print(cmd_ctx, "\t\tComponent not present");
1483                                 else
1484                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1485                         }
1486                         entry_offset += 4;
1487                 } while (romentry > 0);
1488         }
1489         else
1490         {
1491                 command_print(cmd_ctx, "\tNo ROM table present");
1492         }
1493         dap_ap_select(swjdp, apselold);
1494
1495         return ERROR_OK;
1496 }
1497
1498 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1499 {
1500         uint32_t apsel, apselsave, baseaddr;
1501         int retval;
1502
1503         apselsave = swjdp->apsel;
1504         switch (CMD_ARGC) {
1505         case 0:
1506                 apsel = swjdp->apsel;
1507                 break;
1508         case 1:
1509                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1510                 break;
1511         default:
1512                 return ERROR_COMMAND_SYNTAX_ERROR;
1513         }
1514
1515         if (apselsave != apsel)
1516                 dap_ap_select(swjdp, apsel);
1517
1518         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1519         retval = swjdp_transaction_endcheck(swjdp);
1520         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1521
1522         if (apselsave != apsel)
1523                 dap_ap_select(swjdp, apselsave);
1524
1525         return retval;
1526 }
1527
1528 DAP_COMMAND_HANDLER(dap_memaccess_command)
1529 {
1530         uint32_t memaccess_tck;
1531
1532         switch (CMD_ARGC) {
1533         case 0:
1534                 memaccess_tck = swjdp->memaccess_tck;
1535                 break;
1536         case 1:
1537                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1538                 break;
1539         default:
1540                 return ERROR_COMMAND_SYNTAX_ERROR;
1541         }
1542         swjdp->memaccess_tck = memaccess_tck;
1543
1544         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1545                         swjdp->memaccess_tck);
1546
1547         return ERROR_OK;
1548 }
1549
1550 DAP_COMMAND_HANDLER(dap_apsel_command)
1551 {
1552         uint32_t apsel, apid;
1553         int retval;
1554
1555         switch (CMD_ARGC) {
1556         case 0:
1557                 apsel = 0;
1558                 break;
1559         case 1:
1560                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1561                 break;
1562         default:
1563                 return ERROR_COMMAND_SYNTAX_ERROR;
1564         }
1565
1566         dap_ap_select(swjdp, apsel);
1567         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1568         retval = swjdp_transaction_endcheck(swjdp);
1569         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1570                         apsel, apid);
1571
1572         return retval;
1573 }
1574
1575 DAP_COMMAND_HANDLER(dap_apid_command)
1576 {
1577         uint32_t apsel, apselsave, apid;
1578         int retval;
1579
1580         apselsave = swjdp->apsel;
1581         switch (CMD_ARGC) {
1582         case 0:
1583                 apsel = swjdp->apsel;
1584                 break;
1585         case 1:
1586                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1587                 break;
1588         default:
1589                 return ERROR_COMMAND_SYNTAX_ERROR;
1590         }
1591
1592         if (apselsave != apsel)
1593                 dap_ap_select(swjdp, apsel);
1594
1595         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1596         retval = swjdp_transaction_endcheck(swjdp);
1597         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1598         if (apselsave != apsel)
1599                 dap_ap_select(swjdp, apselsave);
1600
1601         return retval;
1602 }