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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76
  77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  78
  79 /*
  80         uint32_t tar_block_size(uint32_t address)
  81         Return the largest block starting at address that does not cross a tar block size alignment boundary
  82 */
  83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  84 {
  85         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  86 }
  87
  88 /***************************************************************************
  89  *                                                                         *
  90  * DP and MEM-AP  register access  through APACC and DPACC                 *
  91  *                                                                         *
  92 ***************************************************************************/
  93
  94 /**
  95  * Select one of the APs connected to the specified DAP.  The
  96  * selection is implicitly used with future AP transactions.
  97  * This is a NOP if the specified AP is already selected.
  98  *
  99  * @param dap The DAP
 100  * @param apsel Number of the AP to (implicitly) use with further
 101  *      transactions.  This normally identifies a MEM-AP.
 102  */
 103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
 104 {
 105         uint32_t select_apsel = (apsel << 24) & 0xFF000000;
 106
 107         if (select_apsel != dap->apsel)
 108         {
 109                 dap->apsel = select_apsel;
 110                 /* Switching AP invalidates cached values.
 111                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 112                  */
 113                 dap->ap_bank_value = -1;
 114                 dap->ap_csw_value = -1;
 115                 dap->ap_tar_value = -1;
 116         }
 117 }
 118
 119 /**
 120  * Queue transactions setting up transfer parameters for the
 121  * currently selected MEM-AP.
 122  *
 123  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 124  * initiate data reads or writes using memory or peripheral addresses.
 125  * If the CSW is configured for it, the TAR may be automatically
 126  * incremented after each transfer.
 127  *
 128  * @todo Rename to reflect it being specifically a MEM-AP function.
 129  *
 130  * @param dap The DAP connected to the MEM-AP.
 131  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 132  *      matches the cached value, the register is not changed.
 133  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 134  *      matches the cached address, the register is not changed.
 135  *
 136  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 137  */
 138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 139 {
 140         int retval;
 141
 142         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 143         if (csw != dap->ap_csw_value)
 144         {
 145                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 146                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 147                 if (retval != ERROR_OK)
 148                         return retval;
 149                 dap->ap_csw_value = csw;
 150         }
 151         if (tar != dap->ap_tar_value)
 152         {
 153                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 154                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 155                 if (retval != ERROR_OK)
 156                         return retval;
 157                 dap->ap_tar_value = tar;
 158         }
 159         /* Disable TAR cache when autoincrementing */
 160         if (csw & CSW_ADDRINC_MASK)
 161                 dap->ap_tar_value = -1;
 162         return ERROR_OK;
 163 }
 164
 165 /**
 166  * Asynchronous (queued) read of a word from memory or a system register.
 167  *
 168  * @param dap The DAP connected to the MEM-AP performing the read.
 169  * @param address Address of the 32-bit word to read; it must be
 170  *      readable by the currently selected MEM-AP.
 171  * @param value points to where the word will be stored when the
 172  *      transaction queue is flushed (assuming no errors).
 173  *
 174  * @return ERROR_OK for success.  Otherwise a fault code.
 175  */
 176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 177                 uint32_t *value)
 178 {
 179         int retval;
 180
 181         /* Use banked addressing (REG_BDx) to avoid some link traffic
 182          * (updating TAR) when reading several consecutive addresses.
 183          */
 184         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 185                         address & 0xFFFFFFF0);
 186         if (retval != ERROR_OK)
 187                 return retval;
 188
 189         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 190 }
 191
 192 /**
 193  * Synchronous read of a word from memory or a system register.
 194  * As a side effect, this flushes any queued transactions.
 195  *
 196  * @param dap The DAP connected to the MEM-AP performing the read.
 197  * @param address Address of the 32-bit word to read; it must be
 198  *      readable by the currently selected MEM-AP.
 199  * @param value points to where the result will be stored.
 200  *
 201  * @return ERROR_OK for success; *value holds the result.
 202  * Otherwise a fault code.
 203  */
 204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 205                 uint32_t *value)
 206 {
 207         int retval;
 208
 209         retval = mem_ap_read_u32(dap, address, value);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         return dap_run(dap);
 214 }
 215
 216 /**
 217  * Asynchronous (queued) write of a word to memory or a system register.
 218  *
 219  * @param dap The DAP connected to the MEM-AP.
 220  * @param address Address to be written; it must be writable by
 221  *      the currently selected MEM-AP.
 222  * @param value Word that will be written to the address when transaction
 223  *      queue is flushed (assuming no errors).
 224  *
 225  * @return ERROR_OK for success.  Otherwise a fault code.
 226  */
 227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 228                 uint32_t value)
 229 {
 230         int retval;
 231
 232         /* Use banked addressing (REG_BDx) to avoid some link traffic
 233          * (updating TAR) when writing several consecutive addresses.
 234          */
 235         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 236                         address & 0xFFFFFFF0);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 241                         value);
 242 }
 243
 244 /**
 245  * Synchronous write of a word to memory or a system register.
 246  * As a side effect, this flushes any queued transactions.
 247  *
 248  * @param dap The DAP connected to the MEM-AP.
 249  * @param address Address to be written; it must be writable by
 250  *      the currently selected MEM-AP.
 251  * @param value Word that will be written.
 252  *
 253  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 254  */
 255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 256                 uint32_t value)
 257 {
 258         int retval = mem_ap_write_u32(dap, address, value);
 259
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         return dap_run(dap);
 264 }
 265
 266 /*****************************************************************************
 267 *                                                                            *
 268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 269 *                                                                            *
 270 * Write a buffer in target order (little endian)                             *
 271 *                                                                            *
 272 *****************************************************************************/
 273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 274 {
 275         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 276         uint32_t adr = address;
 277         uint8_t* pBuffer = buffer;
 278
 279         count >>= 2;
 280         wcount = count;
 281
 282         /* if we have an unaligned access - reorder data */
 283         if (adr & 0x3u)
 284         {
 285                 for (writecount = 0; writecount < count; writecount++)
 286                 {
 287                         int i;
 288                         uint32_t outvalue;
 289                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 290
 291                         for (i = 0; i < 4; i++)
 292                         {
 293                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 294                                 outvalue >>= 8;
 295                                 adr++;
 296                         }
 297                         pBuffer += sizeof(uint32_t);
 298                 }
 299         }
 300
 301         while (wcount > 0)
 302         {
 303                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 304                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 305                 if (wcount < blocksize)
 306                         blocksize = wcount;
 307
 308                 /* handle unaligned data at 4k boundary */
 309                 if (blocksize == 0)
 310                         blocksize = 1;
 311
 312                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315
 316                 for (writecount = 0; writecount < blocksize; writecount++)
 317                 {
 318                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 319                                 *(uint32_t *) ((void *) (buffer + 4 * writecount)));
 320                         if (retval != ERROR_OK)
 321                                 break;
 322                 }
 323
 324                 if ((retval = dap_run(dap)) == ERROR_OK)
 325                 {
 326                         wcount = wcount - blocksize;
 327                         address = address + 4 * blocksize;
 328                         buffer = buffer + 4 * blocksize;
 329                 }
 330                 else
 331                 {
 332                         errorcount++;
 333                 }
 334
 335                 if (errorcount > 1)
 336                 {
 337                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 338                         return retval;
 339                 }
 340         }
 341
 342         return retval;
 343 }
 344
 345 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 346                 uint8_t *buffer, int count, uint32_t address)
 347 {
 348         int retval = ERROR_OK;
 349         int wcount, blocksize, writecount, i;
 350
 351         wcount = count >> 1;
 352
 353         while (wcount > 0)
 354         {
 355                 int nbytes;
 356
 357                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 358                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 359
 360                 if (wcount < blocksize)
 361                         blocksize = wcount;
 362
 363                 /* handle unaligned data at 4k boundary */
 364                 if (blocksize == 0)
 365                         blocksize = 1;
 366
 367                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 368                 if (retval != ERROR_OK)
 369                         return retval;
 370                 writecount = blocksize;
 371
 372                 do
 373                 {
 374                         nbytes = MIN((writecount << 1), 4);
 375
 376                         if (nbytes < 4)
 377                         {
 378                                 retval = mem_ap_write_buf_u16(dap, buffer,
 379                                                 nbytes, address);
 380                                 if (retval != ERROR_OK)
 381                                 {
 382                                         LOG_WARNING("Block write error address "
 383                                                 "0x%" PRIx32 ", count 0x%x",
 384                                                 address, count);
 385                                         return retval;
 386                                 }
 387
 388                                 address += nbytes >> 1;
 389                         }
 390                         else
 391                         {
 392                                 uint32_t outvalue;
 393                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 394
 395                                 for (i = 0; i < nbytes; i++)
 396                                 {
 397                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 398                                         outvalue >>= 8;
 399                                         address++;
 400                                 }
 401
 402                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 403                                 retval = dap_queue_ap_write(dap,
 404                                                 AP_REG_DRW, outvalue);
 405                                 if (retval != ERROR_OK)
 406                                         break;
 407
 408                                 if ((retval = dap_run(dap)) != ERROR_OK)
 409                                 {
 410                                         LOG_WARNING("Block write error address "
 411                                                 "0x%" PRIx32 ", count 0x%x",
 412                                                 address, count);
 413                                         return retval;
 414                                 }
 415                         }
 416
 417                         buffer += nbytes >> 1;
 418                         writecount -= nbytes >> 1;
 419
 420                 } while (writecount);
 421                 wcount -= blocksize;
 422         }
 423
 424         return retval;
 425 }
 426
 427 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 428 {
 429         int retval = ERROR_OK;
 430
 431         if (count >= 4)
 432                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 433
 434         while (count > 0)
 435         {
 436                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 437                 if (retval != ERROR_OK)
 438                         return retval;
 439                 uint16_t svalue;
 440                 memcpy(&svalue, buffer, sizeof(uint16_t));
 441                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 442                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 443                 if (retval != ERROR_OK)
 444                         break;
 445
 446                 retval = dap_run(dap);
 447                 if (retval != ERROR_OK)
 448                         break;
 449
 450                 count -= 2;
 451                 address += 2;
 452                 buffer += 2;
 453         }
 454
 455         return retval;
 456 }
 457
 458 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 459                 uint8_t *buffer, int count, uint32_t address)
 460 {
 461         int retval = ERROR_OK;
 462         int wcount, blocksize, writecount, i;
 463
 464         wcount = count;
 465
 466         while (wcount > 0)
 467         {
 468                 int nbytes;
 469
 470                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 471                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 472
 473                 if (wcount < blocksize)
 474                         blocksize = wcount;
 475
 476                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 477                 if (retval != ERROR_OK)
 478                         return retval;
 479                 writecount = blocksize;
 480
 481                 do
 482                 {
 483                         nbytes = MIN(writecount, 4);
 484
 485                         if (nbytes < 4)
 486                         {
 487                                 retval = mem_ap_write_buf_u8(dap, buffer, nbytes, address);
 488                                 if (retval != ERROR_OK)
 489                                 {
 490                                         LOG_WARNING("Block write error address "
 491                                                 "0x%" PRIx32 ", count 0x%x",
 492                                                 address, count);
 493                                         return retval;
 494                                 }
 495
 496                                 address += nbytes;
 497                         }
 498                         else
 499                         {
 500                                 uint32_t outvalue;
 501                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 502
 503                                 for (i = 0; i < nbytes; i++)
 504                                 {
 505                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 506                                         outvalue >>= 8;
 507                                         address++;
 508                                 }
 509
 510                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 511                                 retval = dap_queue_ap_write(dap,
 512                                                 AP_REG_DRW, outvalue);
 513                                 if (retval != ERROR_OK)
 514                                         break;
 515
 516                                 if ((retval = dap_run(dap)) != ERROR_OK)
 517                                 {
 518                                         LOG_WARNING("Block write error address "
 519                                                 "0x%" PRIx32 ", count 0x%x",
 520                                                 address, count);
 521                                         return retval;
 522                                 }
 523                         }
 524
 525                         buffer += nbytes;
 526                         writecount -= nbytes;
 527
 528                 } while (writecount);
 529                 wcount -= blocksize;
 530         }
 531
 532         return retval;
 533 }
 534
 535 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 536 {
 537         int retval = ERROR_OK;
 538
 539         if (count >= 4)
 540                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 541
 542         while (count > 0)
 543         {
 544                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 545                 if (retval != ERROR_OK)
 546                         return retval;
 547                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 548                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 549                 if (retval != ERROR_OK)
 550                         break;
 551
 552                 retval = dap_run(dap);
 553                 if (retval != ERROR_OK)
 554                         break;
 555
 556                 count--;
 557                 address++;
 558                 buffer++;
 559         }
 560
 561         return retval;
 562 }
 563
 564 /* FIXME don't import ... this is a temporary workaround for the
 565  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 566  */
 567 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 568                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 569                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 570
 571 /**
 572  * Synchronously read a block of 32-bit words into a buffer
 573  * @param dap The DAP connected to the MEM-AP.
 574  * @param buffer where the words will be stored (in host byte order).
 575  * @param count How many words to read.
 576  * @param address Memory address from which to read words; all the
 577  *      words must be readable by the currently selected MEM-AP.
 578  */
 579 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 580                 int count, uint32_t address)
 581 {
 582         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 583         uint32_t adr = address;
 584         uint8_t* pBuffer = buffer;
 585
 586         count >>= 2;
 587         wcount = count;
 588
 589         while (wcount > 0)
 590         {
 591                 /* Adjust to read blocks within boundaries aligned to the
 592                  * TAR autoincrement size (at least 2^10).  Autoincrement
 593                  * mode avoids an extra per-word roundtrip to update TAR.
 594                  */
 595                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 596                                 address);
 597                 if (wcount < blocksize)
 598                         blocksize = wcount;
 599
 600                 /* handle unaligned data at 4k boundary */
 601                 if (blocksize == 0)
 602                         blocksize = 1;
 603
 604                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 605                                 address);
 606                 if (retval != ERROR_OK)
 607                         return retval;
 608
 609                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 610                  * so this routine becomes transport-neutral.  Be careful
 611                  * not to cause performance problems with JTAG; would it
 612                  * suffice to loop over dap_queue_ap_read(), or would that
 613                  * be slower when JTAG is the chosen transport?
 614                  */
 615
 616                 /* Scan out first read */
 617                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 618                                 DPAP_READ, 0, NULL, NULL);
 619                 if (retval != ERROR_OK)
 620                         return retval;
 621                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 622                 {
 623                         /* Scan out next read; scan in posted value for the
 624                          * previous one.  Assumes read is acked "OK/FAULT",
 625                          * and CTRL_STAT says that meant "OK".
 626                          */
 627                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 628                                         DPAP_READ, 0, buffer + 4 * readcount,
 629                                         &dap->ack);
 630                         if (retval != ERROR_OK)
 631                                 return retval;
 632                 }
 633
 634                 /* Scan in last posted value; RDBUFF has no other effect,
 635                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 636                  */
 637                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 638                                 DPAP_READ, 0, buffer + 4 * readcount,
 639                                 &dap->ack);
 640                 if (retval != ERROR_OK)
 641                         return retval;
 642
 643                 retval = dap_run(dap);
 644                 if (retval != ERROR_OK)
 645                 {
 646                         errorcount++;
 647                         if (errorcount <= 1)
 648                         {
 649                                 /* try again */
 650                                 continue;
 651                         }
 652                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 653                         return retval;
 654                 }
 655                 wcount = wcount - blocksize;
 656                 address += 4 * blocksize;
 657                 buffer += 4 * blocksize;
 658         }
 659
 660         /* if we have an unaligned access - reorder data */
 661         if (adr & 0x3u)
 662         {
 663                 for (readcount = 0; readcount < count; readcount++)
 664                 {
 665                         int i;
 666                         uint32_t data;
 667                         memcpy(&data, pBuffer, sizeof(uint32_t));
 668
 669                         for (i = 0; i < 4; i++)
 670                         {
 671                                 *((uint8_t*)pBuffer) =
 672                                                 (data >> 8 * (adr & 0x3));
 673                                 pBuffer++;
 674                                 adr++;
 675                         }
 676                 }
 677         }
 678
 679         return retval;
 680 }
 681
 682 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 683                 uint8_t *buffer, int count, uint32_t address)
 684 {
 685         uint32_t invalue;
 686         int retval = ERROR_OK;
 687         int wcount, blocksize, readcount, i;
 688
 689         wcount = count >> 1;
 690
 691         while (wcount > 0)
 692         {
 693                 int nbytes;
 694
 695                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 696                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 697                 if (wcount < blocksize)
 698                         blocksize = wcount;
 699
 700                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 701                 if (retval != ERROR_OK)
 702                         return retval;
 703
 704                 /* handle unaligned data at 4k boundary */
 705                 if (blocksize == 0)
 706                         blocksize = 1;
 707                 readcount = blocksize;
 708
 709                 do
 710                 {
 711                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 712                         if (retval != ERROR_OK)
 713                                 return retval;
 714                         if ((retval = dap_run(dap)) != ERROR_OK)
 715                         {
 716                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 717                                 return retval;
 718                         }
 719
 720                         nbytes = MIN((readcount << 1), 4);
 721
 722                         for (i = 0; i < nbytes; i++)
 723                         {
 724                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 725                                 buffer++;
 726                                 address++;
 727                         }
 728
 729                         readcount -= (nbytes >> 1);
 730                 } while (readcount);
 731                 wcount -= blocksize;
 732         }
 733
 734         return retval;
 735 }
 736
 737 /**
 738  * Synchronously read a block of 16-bit halfwords into a buffer
 739  * @param dap The DAP connected to the MEM-AP.
 740  * @param buffer where the halfwords will be stored (in host byte order).
 741  * @param count How many halfwords to read.
 742  * @param address Memory address from which to read words; all the
 743  *      words must be readable by the currently selected MEM-AP.
 744  */
 745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 746                 int count, uint32_t address)
 747 {
 748         uint32_t invalue, i;
 749         int retval = ERROR_OK;
 750
 751         if (count >= 4)
 752                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 753
 754         while (count > 0)
 755         {
 756                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 757                 if (retval != ERROR_OK)
 758                         return retval;
 759                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 760                 if (retval != ERROR_OK)
 761                         break;
 762
 763                 retval = dap_run(dap);
 764                 if (retval != ERROR_OK)
 765                         break;
 766
 767                 if (address & 0x1)
 768                 {
 769                         for (i = 0; i < 2; i++)
 770                         {
 771                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 772                                 buffer++;
 773                                 address++;
 774                         }
 775                 }
 776                 else
 777                 {
 778                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 779                         memcpy(buffer, &svalue, sizeof(uint16_t));
 780                         address += 2;
 781                         buffer += 2;
 782                 }
 783                 count -= 2;
 784         }
 785
 786         return retval;
 787 }
 788
 789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 790  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 791  *
 792  * The solution is to arrange for a large out/in scan in this loop and
 793  * and convert data afterwards.
 794  */
 795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 796                 uint8_t *buffer, int count, uint32_t address)
 797 {
 798         uint32_t invalue;
 799         int retval = ERROR_OK;
 800         int wcount, blocksize, readcount, i;
 801
 802         wcount = count;
 803
 804         while (wcount > 0)
 805         {
 806                 int nbytes;
 807
 808                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 809                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 810
 811                 if (wcount < blocksize)
 812                         blocksize = wcount;
 813
 814                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 815                 if (retval != ERROR_OK)
 816                         return retval;
 817                 readcount = blocksize;
 818
 819                 do
 820                 {
 821                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 822                         if (retval != ERROR_OK)
 823                                 return retval;
 824                         if ((retval = dap_run(dap)) != ERROR_OK)
 825                         {
 826                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 827                                 return retval;
 828                         }
 829
 830                         nbytes = MIN(readcount, 4);
 831
 832                         for (i = 0; i < nbytes; i++)
 833                         {
 834                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 835                                 buffer++;
 836                                 address++;
 837                         }
 838
 839                         readcount -= nbytes;
 840                 } while (readcount);
 841                 wcount -= blocksize;
 842         }
 843
 844         return retval;
 845 }
 846
 847 /**
 848  * Synchronously read a block of bytes into a buffer
 849  * @param dap The DAP connected to the MEM-AP.
 850  * @param buffer where the bytes will be stored.
 851  * @param count How many bytes to read.
 852  * @param address Memory address from which to read data; all the
 853  *      data must be readable by the currently selected MEM-AP.
 854  */
 855 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 856                 int count, uint32_t address)
 857 {
 858         uint32_t invalue;
 859         int retval = ERROR_OK;
 860
 861         if (count >= 4)
 862                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 863
 864         while (count > 0)
 865         {
 866                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 867                 if (retval != ERROR_OK)
 868                         return retval;
 869                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 870                 if (retval != ERROR_OK)
 871                         return retval;
 872                 retval = dap_run(dap);
 873                 if (retval != ERROR_OK)
 874                         break;
 875
 876                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 877                 count--;
 878                 address++;
 879                 buffer++;
 880         }
 881
 882         return retval;
 883 }
 884
 885 /*--------------------------------------------------------------------------*/
 886
 887
 888 /* FIXME don't import ... just initialize as
 889  * part of DAP transport setup
 890 */
 891 extern const struct dap_ops jtag_dp_ops;
 892
 893 /*--------------------------------------------------------------------------*/
 894
 895 /**
 896  * Initialize a DAP.  This sets up the power domains, prepares the DP
 897  * for further use, and arranges to use AP #0 for all AP operations
 898  * until dap_ap-select() changes that policy.
 899  *
 900  * @param dap The DAP being initialized.
 901  *
 902  * @todo Rename this.  We also need an initialization scheme which account
 903  * for SWD transports not just JTAG; that will need to address differences
 904  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 905  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 906  */
 907 int ahbap_debugport_init(struct adiv5_dap *dap)
 908 {
 909         uint32_t dummy;
 910         uint32_t ctrlstat;
 911         int cnt = 0;
 912         int retval;
 913
 914         LOG_DEBUG(" ");
 915
 916         /* JTAG-DP or SWJ-DP, in JTAG mode */
 917         dap->ops = &jtag_dp_ops;
 918
 919         /* Default MEM-AP setup.
 920          *
 921          * REVISIT AP #0 may be an inappropriate default for this.
 922          * Should we probe, or take a hint from the caller?
 923          * Presumably we can ignore the possibility of multiple APs.
 924          */
 925         dap->apsel = !0;
 926         dap_ap_select(dap, 0);
 927
 928         /* DP initialization */
 929
 930         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 931         if (retval != ERROR_OK)
 932                 return retval;
 933
 934         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 935         if (retval != ERROR_OK)
 936                 return retval;
 937
 938         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 939         if (retval != ERROR_OK)
 940                 return retval;
 941
 942         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 943         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 944         if (retval != ERROR_OK)
 945                 return retval;
 946
 947         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 948         if (retval != ERROR_OK)
 949                 return retval;
 950         if ((retval = dap_run(dap)) != ERROR_OK)
 951                 return retval;
 952
 953         /* Check that we have debug power domains activated */
 954         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
 955         {
 956                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 957                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 958                 if (retval != ERROR_OK)
 959                         return retval;
 960                 if ((retval = dap_run(dap)) != ERROR_OK)
 961                         return retval;
 962                 alive_sleep(10);
 963         }
 964
 965         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
 966         {
 967                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 968                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 969                 if (retval != ERROR_OK)
 970                         return retval;
 971                 if ((retval = dap_run(dap)) != ERROR_OK)
 972                         return retval;
 973                 alive_sleep(10);
 974         }
 975
 976         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 977         if (retval != ERROR_OK)
 978                 return retval;
 979         /* With debug power on we can activate OVERRUN checking */
 980         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 981         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 982         if (retval != ERROR_OK)
 983                 return retval;
 984         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 985         if (retval != ERROR_OK)
 986                 return retval;
 987
 988         return ERROR_OK;
 989 }
 990
 991 /* CID interpretation -- see ARM IHI 0029B section 3
 992  * and ARM IHI 0031A table 13-3.
 993  */
 994 static const char *class_description[16] ={
 995         "Reserved", "ROM table", "Reserved", "Reserved",
 996         "Reserved", "Reserved", "Reserved", "Reserved",
 997         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 998         "Reserved", "OptimoDE DESS",
 999                 "Generic IP component", "PrimeCell or System component"
1000 };
1001
1002 static bool
1003 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1004 {
1005         return cid3 == 0xb1 && cid2 == 0x05
1006                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1007 }
1008
1009 struct broken_cpu {
1010         uint32_t        dbgbase;
1011         uint32_t        apid;
1012         uint32_t        correct_dbgbase;
1013         char            *model;
1014 } broken_cpus[] = {
1015         { 0x80000000, 0x04770002, 0x60000000, "imx51" },
1016 };
1017
1018 int dap_get_debugbase(struct adiv5_dap *dap, int apsel,
1019                         uint32_t *out_dbgbase, uint32_t *out_apid)
1020 {
1021         uint32_t apselold;
1022         int retval;
1023         unsigned int i;
1024         uint32_t dbgbase, apid;
1025
1026         /* AP address is in bits 31:24 of DP_SELECT */
1027         if (apsel >= 256)
1028                 return ERROR_INVALID_ARGUMENTS;
1029
1030         apselold = dap->apsel;
1031         dap_ap_select(dap, apsel);
1032
1033         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1034         if (retval != ERROR_OK)
1035                 return retval;
1036         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1037         if (retval != ERROR_OK)
1038                 return retval;
1039         retval = dap_run(dap);
1040         if (retval != ERROR_OK)
1041                 return retval;
1042
1043         /* Some CPUs are messed up, so fixup if needed. */
1044         for (i = 0; i < sizeof(broken_cpus)/sizeof(struct broken_cpu); i++)
1045                 if (broken_cpus[i].dbgbase == dbgbase &&
1046                         broken_cpus[i].apid == apid) {
1047                         LOG_WARNING("Found broken CPU (%s), trying to fixup "
1048                                 "ROM Table location from 0x%08x to 0x%08x",
1049                                 broken_cpus[i].model, dbgbase,
1050                                 broken_cpus[i].correct_dbgbase);
1051                         dbgbase = broken_cpus[i].correct_dbgbase;
1052                         break;
1053                 }
1054
1055         dap_ap_select(dap, apselold);
1056
1057         /* The asignment happens only here to prevent modification of these
1058          * values before they are certain. */
1059         *out_dbgbase = dbgbase;
1060         *out_apid = apid;
1061
1062         return ERROR_OK;
1063 }
1064
1065 int dap_lookup_cs_component(struct adiv5_dap *dap, int apsel,
1066                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
1067 {
1068         uint32_t apselold;
1069         uint32_t romentry, entry_offset = 0, component_base, devtype;
1070         int retval = ERROR_FAIL;
1071
1072         if (apsel >= 256)
1073                 return ERROR_INVALID_ARGUMENTS;
1074
1075         apselold = dap->apsel;
1076         dap_ap_select(dap, apsel);
1077
1078         do
1079         {
1080                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1081                                                 entry_offset, &romentry);
1082                 if (retval != ERROR_OK)
1083                         return retval;
1084
1085                 component_base = (dbgbase & 0xFFFFF000)
1086                         + (romentry & 0xFFFFF000);
1087
1088                 if (romentry & 0x1) {
1089                         retval = mem_ap_read_atomic_u32(dap,
1090                                         (component_base & 0xfffff000) | 0xfcc,
1091                                         &devtype);
1092                         if ((devtype & 0xff) == type) {
1093                                 *addr = component_base;
1094                                 retval = ERROR_OK;
1095                                 break;
1096                         }
1097                 }
1098                 entry_offset += 4;
1099         } while (romentry > 0);
1100
1101         dap_ap_select(dap, apselold);
1102
1103         return retval;
1104 }
1105
1106 static int dap_info_command(struct command_context *cmd_ctx,
1107                 struct adiv5_dap *dap, int apsel)
1108 {
1109         int retval;
1110         uint32_t dbgbase, apid;
1111         int romtable_present = 0;
1112         uint8_t mem_ap;
1113         uint32_t apselold;
1114
1115         retval = dap_get_debugbase(dap, apsel, &dbgbase, &apid);
1116         if (retval != ERROR_OK)
1117                 return retval;
1118
1119         apselold = dap->apsel;
1120         dap_ap_select(dap, apsel);
1121
1122         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1123         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1124         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1125         if (apid)
1126         {
1127                 switch (apid&0x0F)
1128                 {
1129                         case 0:
1130                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1131                                 break;
1132                         case 1:
1133                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1134                                 break;
1135                         case 2:
1136                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1137                                 break;
1138                         default:
1139                                 command_print(cmd_ctx, "\tUnknown AP type");
1140                                 break;
1141                 }
1142
1143                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1144                  * not a ROM table ... or have no such components at all.
1145                  */
1146                 if (mem_ap)
1147                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1148                                         dbgbase);
1149         }
1150         else
1151         {
1152                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1153         }
1154
1155         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1156         if (romtable_present)
1157         {
1158                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1159                 uint16_t entry_offset;
1160
1161                 /* bit 16 of apid indicates a memory access port */
1162                 if (dbgbase & 0x02)
1163                         command_print(cmd_ctx, "\tValid ROM table present");
1164                 else
1165                         command_print(cmd_ctx, "\tROM table in legacy format");
1166
1167                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1168                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1169                 if (retval != ERROR_OK)
1170                         return retval;
1171                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1172                 if (retval != ERROR_OK)
1173                         return retval;
1174                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1175                 if (retval != ERROR_OK)
1176                         return retval;
1177                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1178                 if (retval != ERROR_OK)
1179                         return retval;
1180                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1181                 if (retval != ERROR_OK)
1182                         return retval;
1183                 retval = dap_run(dap);
1184                 if (retval != ERROR_OK)
1185                         return retval;
1186
1187                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1188                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1189                                         ", CID2 0x%2.2x"
1190                                         ", CID1 0x%2.2x"
1191                                         ", CID0 0x%2.2x",
1192                                         (unsigned) cid3, (unsigned)cid2,
1193                                         (unsigned) cid1, (unsigned) cid0);
1194                 if (memtype & 0x01)
1195                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1196                 else
1197                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1198                                         "Dedicated debug bus.");
1199
1200                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1201                 entry_offset = 0;
1202                 do
1203                 {
1204                         retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1205                         if (retval != ERROR_OK)
1206                                 return retval;
1207                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1208                         if (romentry&0x01)
1209                         {
1210                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1211                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1212                                 uint32_t component_base;
1213                                 unsigned part_num;
1214                                 char *type, *full;
1215
1216                                 component_base = (dbgbase & 0xFFFFF000)
1217                                                 + (romentry & 0xFFFFF000);
1218
1219                                 /* IDs are in last 4K section */
1220
1221
1222                                 retval = mem_ap_read_atomic_u32(dap,
1223                                         component_base + 0xFE0, &c_pid0);
1224                                 if (retval != ERROR_OK)
1225                                         return retval;
1226                                 c_pid0 &= 0xff;
1227                                 retval = mem_ap_read_atomic_u32(dap,
1228                                         component_base + 0xFE4, &c_pid1);
1229                                 if (retval != ERROR_OK)
1230                                         return retval;
1231                                 c_pid1 &= 0xff;
1232                                 retval = mem_ap_read_atomic_u32(dap,
1233                                         component_base + 0xFE8, &c_pid2);
1234                                 if (retval != ERROR_OK)
1235                                         return retval;
1236                                 c_pid2 &= 0xff;
1237                                 retval = mem_ap_read_atomic_u32(dap,
1238                                         component_base + 0xFEC, &c_pid3);
1239                                 if (retval != ERROR_OK)
1240                                         return retval;
1241                                 c_pid3 &= 0xff;
1242                                 retval = mem_ap_read_atomic_u32(dap,
1243                                         component_base + 0xFD0, &c_pid4);
1244                                 if (retval != ERROR_OK)
1245                                         return retval;
1246                                 c_pid4 &= 0xff;
1247
1248                                 retval = mem_ap_read_atomic_u32(dap,
1249                                         component_base + 0xFF0, &c_cid0);
1250                                 if (retval != ERROR_OK)
1251                                         return retval;
1252                                 c_cid0 &= 0xff;
1253                                 retval = mem_ap_read_atomic_u32(dap,
1254                                         component_base + 0xFF4, &c_cid1);
1255                                 if (retval != ERROR_OK)
1256                                         return retval;
1257                                 c_cid1 &= 0xff;
1258                                 retval = mem_ap_read_atomic_u32(dap,
1259                                         component_base + 0xFF8, &c_cid2);
1260                                 if (retval != ERROR_OK)
1261                                         return retval;
1262                                 c_cid2 &= 0xff;
1263                                 retval = mem_ap_read_atomic_u32(dap,
1264                                         component_base + 0xFFC, &c_cid3);
1265                                 if (retval != ERROR_OK)
1266                                         return retval;
1267                                 c_cid3 &= 0xff;
1268
1269
1270                                 command_print(cmd_ctx,
1271                                 "\t\tComponent base address 0x%" PRIx32
1272                                         ", start address 0x%" PRIx32,
1273                                                 component_base,
1274                                 /* component may take multiple 4K pages */
1275                                 component_base - 0x1000*(c_pid4 >> 4));
1276                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1277                                                 (int) (c_cid1 >> 4) & 0xf,
1278                                                 /* See ARM IHI 0029B Table 3-3 */
1279                                                 class_description[(c_cid1 >> 4) & 0xf]);
1280
1281                                 /* CoreSight component? */
1282                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1283                                         uint32_t devtype;
1284                                         unsigned minor;
1285                                         char *major = "Reserved", *subtype = "Reserved";
1286
1287                                         retval = mem_ap_read_atomic_u32(dap,
1288                                                         (component_base & 0xfffff000) | 0xfcc,
1289                                                         &devtype);
1290                                         if (retval != ERROR_OK)
1291                                                 return retval;
1292                                         minor = (devtype >> 4) & 0x0f;
1293                                         switch (devtype & 0x0f) {
1294                                         case 0:
1295                                                 major = "Miscellaneous";
1296                                                 switch (minor) {
1297                                                 case 0:
1298                                                         subtype = "other";
1299                                                         break;
1300                                                 case 4:
1301                                                         subtype = "Validation component";
1302                                                         break;
1303                                                 }
1304                                                 break;
1305                                         case 1:
1306                                                 major = "Trace Sink";
1307                                                 switch (minor) {
1308                                                 case 0:
1309                                                         subtype = "other";
1310                                                         break;
1311                                                 case 1:
1312                                                         subtype = "Port";
1313                                                         break;
1314                                                 case 2:
1315                                                         subtype = "Buffer";
1316                                                         break;
1317                                                 }
1318                                                 break;
1319                                         case 2:
1320                                                 major = "Trace Link";
1321                                                 switch (minor) {
1322                                                 case 0:
1323                                                         subtype = "other";
1324                                                         break;
1325                                                 case 1:
1326                                                         subtype = "Funnel, router";
1327                                                         break;
1328                                                 case 2:
1329                                                         subtype = "Filter";
1330                                                         break;
1331                                                 case 3:
1332                                                         subtype = "FIFO, buffer";
1333                                                         break;
1334                                                 }
1335                                                 break;
1336                                         case 3:
1337                                                 major = "Trace Source";
1338                                                 switch (minor) {
1339                                                 case 0:
1340                                                         subtype = "other";
1341                                                         break;
1342                                                 case 1:
1343                                                         subtype = "Processor";
1344                                                         break;
1345                                                 case 2:
1346                                                         subtype = "DSP";
1347                                                         break;
1348                                                 case 3:
1349                                                         subtype = "Engine/Coprocessor";
1350                                                         break;
1351                                                 case 4:
1352                                                         subtype = "Bus";
1353                                                         break;
1354                                                 }
1355                                                 break;
1356                                         case 4:
1357                                                 major = "Debug Control";
1358                                                 switch (minor) {
1359                                                 case 0:
1360                                                         subtype = "other";
1361                                                         break;
1362                                                 case 1:
1363                                                         subtype = "Trigger Matrix";
1364                                                         break;
1365                                                 case 2:
1366                                                         subtype = "Debug Auth";
1367                                                         break;
1368                                                 }
1369                                                 break;
1370                                         case 5:
1371                                                 major = "Debug Logic";
1372                                                 switch (minor) {
1373                                                 case 0:
1374                                                         subtype = "other";
1375                                                         break;
1376                                                 case 1:
1377                                                         subtype = "Processor";
1378                                                         break;
1379                                                 case 2:
1380                                                         subtype = "DSP";
1381                                                         break;
1382                                                 case 3:
1383                                                         subtype = "Engine/Coprocessor";
1384                                                         break;
1385                                                 }
1386                                                 break;
1387                                         }
1388                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1389                                                         (unsigned) (devtype & 0xff),
1390                                                         major, subtype);
1391                                         /* REVISIT also show 0xfc8 DevId */
1392                                 }
1393
1394                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1395                                         command_print(cmd_ctx,
1396                                                       "\t\tCID3 0%2.2x"
1397                                                         ", CID2 0%2.2x"
1398                                                         ", CID1 0%2.2x"
1399                                                         ", CID0 0%2.2x",
1400                                                         (int) c_cid3,
1401                                                         (int) c_cid2,
1402                                                         (int)c_cid1,
1403                                                         (int)c_cid0);
1404                                 command_print(cmd_ctx,
1405                                 "\t\tPeripheral ID[4..0] = hex "
1406                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1407                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1408                                 (int) c_pid1, (int) c_pid0);
1409
1410                                 /* Part number interpretations are from Cortex
1411                                  * core specs, the CoreSight components TRM
1412                                  * (ARM DDI 0314H), and ETM specs; also from
1413                                  * chip observation (e.g. TI SDTI).
1414                                  */
1415                                 part_num = (c_pid0 & 0xff);
1416                                 part_num |= (c_pid1 & 0x0f) << 8;
1417                                 switch (part_num) {
1418                                 case 0x000:
1419                                         type = "Cortex-M3 NVIC";
1420                                         full = "(Interrupt Controller)";
1421                                         break;
1422                                 case 0x001:
1423                                         type = "Cortex-M3 ITM";
1424                                         full = "(Instrumentation Trace Module)";
1425                                         break;
1426                                 case 0x002:
1427                                         type = "Cortex-M3 DWT";
1428                                         full = "(Data Watchpoint and Trace)";
1429                                         break;
1430                                 case 0x003:
1431                                         type = "Cortex-M3 FBP";
1432                                         full = "(Flash Patch and Breakpoint)";
1433                                         break;
1434                                 case 0x00d:
1435                                         type = "CoreSight ETM11";
1436                                         full = "(Embedded Trace)";
1437                                         break;
1438                                 // case 0x113: what?
1439                                 case 0x120:             /* from OMAP3 memmap */
1440                                         type = "TI SDTI";
1441                                         full = "(System Debug Trace Interface)";
1442                                         break;
1443                                 case 0x343:             /* from OMAP3 memmap */
1444                                         type = "TI DAPCTL";
1445                                         full = "";
1446                                         break;
1447                                 case 0x906:
1448                                         type = "Coresight CTI";
1449                                         full = "(Cross Trigger)";
1450                                         break;
1451                                 case 0x907:
1452                                         type = "Coresight ETB";
1453                                         full = "(Trace Buffer)";
1454                                         break;
1455                                 case 0x908:
1456                                         type = "Coresight CSTF";
1457                                         full = "(Trace Funnel)";
1458                                         break;
1459                                 case 0x910:
1460                                         type = "CoreSight ETM9";
1461                                         full = "(Embedded Trace)";
1462                                         break;
1463                                 case 0x912:
1464                                         type = "Coresight TPIU";
1465                                         full = "(Trace Port Interface Unit)";
1466                                         break;
1467                                 case 0x921:
1468                                         type = "Cortex-A8 ETM";
1469                                         full = "(Embedded Trace)";
1470                                         break;
1471                                 case 0x922:
1472                                         type = "Cortex-A8 CTI";
1473                                         full = "(Cross Trigger)";
1474                                         break;
1475                                 case 0x923:
1476                                         type = "Cortex-M3 TPIU";
1477                                         full = "(Trace Port Interface Unit)";
1478                                         break;
1479                                 case 0x924:
1480                                         type = "Cortex-M3 ETM";
1481                                         full = "(Embedded Trace)";
1482                                         break;
1483                                 case 0xc08:
1484                                         type = "Cortex-A8 Debug";
1485                                         full = "(Debug Unit)";
1486                                         break;
1487                                 default:
1488                                         type = "-*- unrecognized -*-";
1489                                         full = "";
1490                                         break;
1491                                 }
1492                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1493                                                 type, full);
1494                         }
1495                         else
1496                         {
1497                                 if (romentry)
1498                                         command_print(cmd_ctx, "\t\tComponent not present");
1499                                 else
1500                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1501                         }
1502                         entry_offset += 4;
1503                 } while (romentry > 0);
1504         }
1505         else
1506         {
1507                 command_print(cmd_ctx, "\tNo ROM table present");
1508         }
1509         dap_ap_select(dap, apselold);
1510
1511         return ERROR_OK;
1512 }
1513
1514 COMMAND_HANDLER(handle_dap_info_command)
1515 {
1516         struct target *target = get_current_target(CMD_CTX);
1517         struct arm *arm = target_to_arm(target);
1518         struct adiv5_dap *dap = arm->dap;
1519         uint32_t apsel;
1520
1521         switch (CMD_ARGC) {
1522         case 0:
1523                 apsel = dap->apsel;
1524                 break;
1525         case 1:
1526                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1527                 break;
1528         default:
1529                 return ERROR_COMMAND_SYNTAX_ERROR;
1530         }
1531
1532         return dap_info_command(CMD_CTX, dap, apsel);
1533 }
1534
1535 COMMAND_HANDLER(dap_baseaddr_command)
1536 {
1537         struct target *target = get_current_target(CMD_CTX);
1538         struct arm *arm = target_to_arm(target);
1539         struct adiv5_dap *dap = arm->dap;
1540
1541         uint32_t apsel, apselsave, baseaddr;
1542         int retval;
1543
1544         apselsave = dap->apsel;
1545         switch (CMD_ARGC) {
1546         case 0:
1547                 apsel = dap->apsel;
1548                 break;
1549         case 1:
1550                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1551                 /* AP address is in bits 31:24 of DP_SELECT */
1552                 if (apsel >= 256)
1553                         return ERROR_INVALID_ARGUMENTS;
1554                 break;
1555         default:
1556                 return ERROR_COMMAND_SYNTAX_ERROR;
1557         }
1558
1559         if (apselsave != apsel)
1560                 dap_ap_select(dap, apsel);
1561
1562         /* NOTE:  assumes we're talking to a MEM-AP, which
1563          * has a base address.  There are other kinds of AP,
1564          * though they're not common for now.  This should
1565          * use the ID register to verify it's a MEM-AP.
1566          */
1567         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1568         if (retval != ERROR_OK)
1569                 return retval;
1570         retval = dap_run(dap);
1571         if (retval != ERROR_OK)
1572                 return retval;
1573
1574         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1575
1576         if (apselsave != apsel)
1577                 dap_ap_select(dap, apselsave);
1578
1579         return retval;
1580 }
1581
1582 COMMAND_HANDLER(dap_memaccess_command)
1583 {
1584         struct target *target = get_current_target(CMD_CTX);
1585         struct arm *arm = target_to_arm(target);
1586         struct adiv5_dap *dap = arm->dap;
1587
1588         uint32_t memaccess_tck;
1589
1590         switch (CMD_ARGC) {
1591         case 0:
1592                 memaccess_tck = dap->memaccess_tck;
1593                 break;
1594         case 1:
1595                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1596                 break;
1597         default:
1598                 return ERROR_COMMAND_SYNTAX_ERROR;
1599         }
1600         dap->memaccess_tck = memaccess_tck;
1601
1602         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1603                         dap->memaccess_tck);
1604
1605         return ERROR_OK;
1606 }
1607
1608 COMMAND_HANDLER(dap_apsel_command)
1609 {
1610         struct target *target = get_current_target(CMD_CTX);
1611         struct arm *arm = target_to_arm(target);
1612         struct adiv5_dap *dap = arm->dap;
1613
1614         uint32_t apsel, apid;
1615         int retval;
1616
1617         switch (CMD_ARGC) {
1618         case 0:
1619                 apsel = 0;
1620                 break;
1621         case 1:
1622                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1623                 /* AP address is in bits 31:24 of DP_SELECT */
1624                 if (apsel >= 256)
1625                         return ERROR_INVALID_ARGUMENTS;
1626                 break;
1627         default:
1628                 return ERROR_COMMAND_SYNTAX_ERROR;
1629         }
1630
1631         dap_ap_select(dap, apsel);
1632         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1633         if (retval != ERROR_OK)
1634                 return retval;
1635         retval = dap_run(dap);
1636         if (retval != ERROR_OK)
1637                 return retval;
1638
1639         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1640                         apsel, apid);
1641
1642         return retval;
1643 }
1644
1645 COMMAND_HANDLER(dap_apid_command)
1646 {
1647         struct target *target = get_current_target(CMD_CTX);
1648         struct arm *arm = target_to_arm(target);
1649         struct adiv5_dap *dap = arm->dap;
1650
1651         uint32_t apsel, apselsave, apid;
1652         int retval;
1653
1654         apselsave = dap->apsel;
1655         switch (CMD_ARGC) {
1656         case 0:
1657                 apsel = dap->apsel;
1658                 break;
1659         case 1:
1660                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1661                 /* AP address is in bits 31:24 of DP_SELECT */
1662                 if (apsel >= 256)
1663                         return ERROR_INVALID_ARGUMENTS;
1664                 break;
1665         default:
1666                 return ERROR_COMMAND_SYNTAX_ERROR;
1667         }
1668
1669         if (apselsave != apsel)
1670                 dap_ap_select(dap, apsel);
1671
1672         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1673         if (retval != ERROR_OK)
1674                 return retval;
1675         retval = dap_run(dap);
1676         if (retval != ERROR_OK)
1677                 return retval;
1678
1679         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1680         if (apselsave != apsel)
1681                 dap_ap_select(dap, apselsave);
1682
1683         return retval;
1684 }
1685
1686 static const struct command_registration dap_commands[] = {
1687         {
1688                 .name = "info",
1689                 .handler = handle_dap_info_command,
1690                 .mode = COMMAND_EXEC,
1691                 .help = "display ROM table for MEM-AP "
1692                         "(default currently selected AP)",
1693                 .usage = "[ap_num]",
1694         },
1695         {
1696                 .name = "apsel",
1697                 .handler = dap_apsel_command,
1698                 .mode = COMMAND_EXEC,
1699                 .help = "Set the currently selected AP (default 0) "
1700                         "and display the result",
1701                 .usage = "[ap_num]",
1702         },
1703         {
1704                 .name = "apid",
1705                 .handler = dap_apid_command,
1706                 .mode = COMMAND_EXEC,
1707                 .help = "return ID register from AP "
1708                         "(default currently selected AP)",
1709                 .usage = "[ap_num]",
1710         },
1711         {
1712                 .name = "baseaddr",
1713                 .handler = dap_baseaddr_command,
1714                 .mode = COMMAND_EXEC,
1715                 .help = "return debug base address from MEM-AP "
1716                         "(default currently selected AP)",
1717                 .usage = "[ap_num]",
1718         },
1719         {
1720                 .name = "memaccess",
1721                 .handler = dap_memaccess_command,
1722                 .mode = COMMAND_EXEC,
1723                 .help = "set/get number of extra tck for MEM-AP memory "
1724                         "bus access [0-255]",
1725                 .usage = "[cycles]",
1726         },
1727         COMMAND_REGISTRATION_DONE
1728 };
1729
1730 const struct command_registration dap_command_handlers[] = {
1731         {
1732                 .name = "dap",
1733                 .mode = COMMAND_EXEC,
1734                 .help = "DAP command group",
1735                 .chain = dap_commands,
1736         },
1737         COMMAND_REGISTRATION_DONE
1738 };
1739
1740