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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  */
  46
  47 /*
  48  * Relevant specifications from ARM include:
  49  *
  50  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  51  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  52  *
  53  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  54  * Cortex-M3(tm) TRM, ARM DDI 0337G
  55  */
  56
  57 #ifdef HAVE_CONFIG_H
  58 #include "config.h"
  59 #endif
  60
  61 #include "arm_adi_v5.h"
  62 #include <helper/time_support.h>
  63
  64 /*
  65  * Transaction Mode:
  66  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  67  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  68  * result checking until swjdp_end_transaction()
  69  * This must be done before using or deallocating any return variables.
  70  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  71  * All reads and writes to the AHB bus are checked for valid completion, and return values
  72  * are immediatley available.
  73 */
  74
  75
  76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  77
  78 /*
  79         uint32_t tar_block_size(uint32_t address)
  80         Return the largest block starting at address that does not cross a tar block size alignment boundary
  81 */
  82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  83 {
  84         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  85 }
  86
  87 /***************************************************************************
  88  *                                                                         *
  89  * DPACC and APACC scanchain access through JTAG-DP                        *
  90  *                                                                         *
  91 ***************************************************************************/
  92
  93 /**
  94  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  95  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  96  * discusses operations which access these registers.
  97  *
  98  * Note that only one scan is performed.  If RnW is set, a separate scan
  99  * will be needed to collect the data which was read; the "invalue" collects
 100  * the posted result of a preceding operation, not the current one.
 101  *
 102  * @param swjdp the DAP
 103  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 104  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 105  *      SELECT register has more addressing bits.
 106  * @param RnW false iff outvalue will be written to the DP or AP
 107  * @param outvalue points to a 32-bit (little-endian) integer
 108  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 109  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 110  */
 111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 112                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 113                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 114 {
 115         struct arm_jtag *jtag_info = swjdp->jtag_info;
 116         struct scan_field fields[2];
 117         uint8_t out_addr_buf;
 118
 119         jtag_set_end_state(TAP_IDLE);
 120         arm_jtag_set_instr(jtag_info, instr, NULL);
 121
 122         /* Add specified number of tck clocks before accessing memory bus */
 123
 124         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 125          * they provide more time for the (MEM) AP to complete the read ...
 126          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 127          */
 128         if ((instr == JTAG_DP_APACC)
 129                         && ((reg_addr == AP_REG_DRW)
 130                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 131                         && (swjdp->memaccess_tck != 0))
 132                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 133
 134         /* Scan out a read or write operation using some DP or AP register.
 135          * For APACC access with any sticky error flag set, this is discarded.
 136          */
 137         fields[0].tap = jtag_info->tap;
 138         fields[0].num_bits = 3;
 139         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 140         fields[0].out_value = &out_addr_buf;
 141         fields[0].in_value = ack;
 142
 143         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 144          * complete; data we write is discarded, data we read is unpredictable.
 145          * When overrun detect is active, STICKYORUN is set.
 146          */
 147
 148         fields[1].tap = jtag_info->tap;
 149         fields[1].num_bits = 32;
 150         fields[1].out_value = outvalue;
 151         fields[1].in_value = invalue;
 152
 153         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 154
 155         return ERROR_OK;
 156 }
 157
 158 /* Scan out and in from host ordered uint32_t variables */
 159 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 160                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 161                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 162 {
 163         struct arm_jtag *jtag_info = swjdp->jtag_info;
 164         struct scan_field fields[2];
 165         uint8_t out_value_buf[4];
 166         uint8_t out_addr_buf;
 167
 168         jtag_set_end_state(TAP_IDLE);
 169         arm_jtag_set_instr(jtag_info, instr, NULL);
 170
 171         /* Add specified number of tck clocks before accessing memory bus */
 172
 173         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 174          * they provide more time for the (MEM) AP to complete the read ...
 175          */
 176         if ((instr == JTAG_DP_APACC)
 177                         && ((reg_addr == AP_REG_DRW)
 178                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 179                         && (swjdp->memaccess_tck != 0))
 180                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 181
 182         fields[0].tap = jtag_info->tap;
 183         fields[0].num_bits = 3;
 184         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 185         fields[0].out_value = &out_addr_buf;
 186         fields[0].in_value = ack;
 187
 188         fields[1].tap = jtag_info->tap;
 189         fields[1].num_bits = 32;
 190         buf_set_u32(out_value_buf, 0, 32, outvalue);
 191         fields[1].out_value = out_value_buf;
 192         fields[1].in_value = NULL;
 193
 194         if (invalue)
 195         {
 196                 fields[1].in_value = (uint8_t *)invalue;
 197                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 198
 199                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 200         } else
 201         {
 202
 203                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 204         }
 205
 206         return ERROR_OK;
 207 }
 208
 209 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 210 static int scan_inout_check(struct swjdp_common *swjdp,
 211                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 212                 uint8_t *outvalue, uint8_t *invalue)
 213 {
 214         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 215
 216         if ((RnW == DPAP_READ) && (invalue != NULL))
 217                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 218                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 219
 220         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 221          * ack = OK/FAULT and the check CTRL_STAT
 222          */
 223         if ((instr == JTAG_DP_APACC)
 224                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 225                 return jtagdp_transaction_endcheck(swjdp);
 226
 227         return ERROR_OK;
 228 }
 229
 230 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 231                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 232                 uint32_t outvalue, uint32_t *invalue)
 233 {
 234         /* Issue the read or write */
 235         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 236
 237         /* For reads,  collect posted value; RDBUFF has no other effect.
 238          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 239          */
 240         if ((RnW == DPAP_READ) && (invalue != NULL))
 241                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 242                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 243
 244         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 245          * ack = OK/FAULT and then check CTRL_STAT
 246          */
 247         if ((instr == JTAG_DP_APACC)
 248                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 249                 return jtagdp_transaction_endcheck(swjdp);
 250
 251         return ERROR_OK;
 252 }
 253
 254 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 255 {
 256         int retval;
 257         uint32_t ctrlstat;
 258
 259         /* too expensive to call keep_alive() here */
 260
 261 #if 0
 262         /* Danger!!!! BROKEN!!!! */
 263         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 264                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 265         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 266         R956 introduced the check on return value here and now Michael Schwingen reports
 267         that this code no longer works....
 268
 269         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 270         */
 271         if ((retval = jtag_execute_queue()) != ERROR_OK)
 272         {
 273                 LOG_ERROR("BUG: Why does this fail the first time????");
 274         }
 275         /* Why??? second time it works??? */
 276 #endif
 277
 278         /* Post CTRL/STAT read; discard any previous posted read value
 279          * but collect its ACK status.
 280          */
 281         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 282                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 283         if ((retval = jtag_execute_queue()) != ERROR_OK)
 284                 return retval;
 285
 286         swjdp->ack = swjdp->ack & 0x7;
 287
 288         /* common code path avoids calling timeval_ms() */
 289         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 290         {
 291                 long long then = timeval_ms();
 292
 293                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 294                 {
 295                         if (swjdp->ack == JTAG_ACK_WAIT)
 296                         {
 297                                 if ((timeval_ms()-then) > 1000)
 298                                 {
 299                                         /* NOTE:  this would be a good spot
 300                                          * to use JTAG_DP_ABORT.
 301                                          */
 302                                         LOG_WARNING("Timeout (1000ms) waiting "
 303                                                 "for ACK=OK/FAULT "
 304                                                 "in JTAG-DP transaction");
 305                                         return ERROR_JTAG_DEVICE_ERROR;
 306                                 }
 307                         }
 308                         else
 309                         {
 310                                 LOG_WARNING("Invalid ACK %#x "
 311                                                 "in JTAG-DP transaction",
 312                                                 swjdp->ack);
 313                                 return ERROR_JTAG_DEVICE_ERROR;
 314                         }
 315
 316                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 317                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 318                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 319                                 return retval;
 320                         swjdp->ack = swjdp->ack & 0x7;
 321                 }
 322         }
 323
 324         /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 325
 326         /* Check for STICKYERR and STICKYORUN */
 327         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 328         {
 329                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 330                 /* Check power to debug regions */
 331                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 332                          ahbap_debugport_init(swjdp);
 333                 else
 334                 {
 335                         uint32_t mem_ap_csw, mem_ap_tar;
 336
 337                         /* Maybe print information about last intended
 338                          * MEM-AP access; but not if autoincrementing.
 339                          * *Real* CSW and TAR values are always shown.
 340                          */
 341                         if (swjdp->ap_tar_value != (uint32_t) -1)
 342                                 LOG_DEBUG("MEM-AP Cached values: "
 343                                         "ap_bank 0x%" PRIx32
 344                                         ", ap_csw 0x%" PRIx32
 345                                         ", ap_tar 0x%" PRIx32,
 346                                         swjdp->dp_select_value,
 347                                         swjdp->ap_csw_value,
 348                                         swjdp->ap_tar_value);
 349
 350                         if (ctrlstat & SSTICKYORUN)
 351                                 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 352                                         "memaccess, or reduce jtag speed");
 353
 354                         if (ctrlstat & SSTICKYERR)
 355                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 356
 357                         /* Clear Sticky Error Bits */
 358                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 359                                         DP_CTRL_STAT, DPAP_WRITE,
 360                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 361                                                 | SSTICKYERR, NULL);
 362                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 363                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 364                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 365                                 return retval;
 366
 367                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 368
 369                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 370                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 371                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 372                                 return retval;
 373                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 374                                         PRIx32, mem_ap_csw, mem_ap_tar);
 375
 376                 }
 377                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 378                         return retval;
 379                 return ERROR_JTAG_DEVICE_ERROR;
 380         }
 381
 382         return ERROR_OK;
 383 }
 384
 385 /***************************************************************************
 386  *                                                                         *
 387  * DP and MEM-AP  register access  through APACC and DPACC                 *
 388  *                                                                         *
 389 ***************************************************************************/
 390
 391 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 392                 uint32_t value, uint8_t reg_addr)
 393 {
 394         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 395                         reg_addr, DPAP_WRITE, value, NULL);
 396 }
 397
 398 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 399                 uint32_t *value, uint8_t reg_addr)
 400 {
 401         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 402                         reg_addr, DPAP_READ, 0, value);
 403 }
 404
 405 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 406 {
 407         uint32_t select;
 408         select = (apsel << 24) & 0xFF000000;
 409
 410         if (select != swjdp->apsel)
 411         {
 412                 swjdp->apsel = select;
 413                 /* Switching AP invalidates cached values */
 414                 swjdp->dp_select_value = -1;
 415                 swjdp->ap_csw_value = -1;
 416                 swjdp->ap_tar_value = -1;
 417         }
 418
 419         return ERROR_OK;
 420 }
 421
 422 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 423 {
 424         uint32_t select;
 425         select = (ap_reg & 0x000000F0);
 426
 427         if (select != swjdp->dp_select_value)
 428         {
 429                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 430                 swjdp->dp_select_value = select;
 431         }
 432
 433         return ERROR_OK;
 434 }
 435
 436 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 437                 uint32_t reg_addr, uint8_t *out_value_buf)
 438 {
 439         dap_dp_bankselect(swjdp, reg_addr);
 440         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 441                         DPAP_WRITE, out_value_buf, NULL);
 442
 443         return ERROR_OK;
 444 }
 445
 446 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 447 {
 448         uint8_t out_value_buf[4];
 449
 450         buf_set_u32(out_value_buf, 0, 32, value);
 451         dap_dp_bankselect(swjdp, reg_addr);
 452         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 453                         DPAP_WRITE, out_value_buf, NULL);
 454
 455         return ERROR_OK;
 456 }
 457
 458 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 459 {
 460         dap_dp_bankselect(swjdp, reg_addr);
 461         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 462                         DPAP_READ, 0, value);
 463
 464         return ERROR_OK;
 465 }
 466
 467 /**
 468  * Set up transfer parameters for the currently selected MEM-AP.
 469  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 470  * initiate data reads or writes using memory or peripheral addresses.
 471  * If the CSW is configured for it, the TAR may be automatically
 472  * incremented after each transfer.
 473  *
 474  * @todo Rename to reflect it being specifically a MEM-AP function.
 475  *
 476  * @param swjdp The DAP connected to the MEM-AP.
 477  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 478  *      matches the cached value, the register is not changed.
 479  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 480  *      matches the cached address, the register is not changed.
 481  */
 482 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 483 {
 484         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 485         if (csw != swjdp->ap_csw_value)
 486         {
 487                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 488                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 489                 swjdp->ap_csw_value = csw;
 490         }
 491         if (tar != swjdp->ap_tar_value)
 492         {
 493                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 494                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 495                 swjdp->ap_tar_value = tar;
 496         }
 497         /* Disable TAR cache when autoincrementing */
 498         if (csw & CSW_ADDRINC_MASK)
 499                 swjdp->ap_tar_value = -1;
 500         return ERROR_OK;
 501 }
 502
 503 /*****************************************************************************
 504 *                                                                            *
 505 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 506 *                                                                            *
 507 * Read a uint32_t value from memory or system register                            *
 508 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 509 * but with less overhead                                                     *
 510 *****************************************************************************/
 511 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 512 {
 513         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 514
 515         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 516         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 517
 518         return ERROR_OK;
 519 }
 520
 521 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 522 {
 523         mem_ap_read_u32(swjdp, address, value);
 524
 525         return jtagdp_transaction_endcheck(swjdp);
 526 }
 527
 528 /*****************************************************************************
 529 *                                                                            *
 530 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 531 *                                                                            *
 532 * Write a uint32_t value to memory or memory mapped register                              *
 533 *                                                                            *
 534 *****************************************************************************/
 535 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 536 {
 537         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 538
 539         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 540         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 541
 542         return ERROR_OK;
 543 }
 544
 545 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 546 {
 547         mem_ap_write_u32(swjdp, address, value);
 548
 549         return jtagdp_transaction_endcheck(swjdp);
 550 }
 551
 552 /*****************************************************************************
 553 *                                                                            *
 554 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 555 *                                                                            *
 556 * Write a buffer in target order (little endian)                             *
 557 *                                                                            *
 558 *****************************************************************************/
 559 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 560 {
 561         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 562         uint32_t adr = address;
 563         uint8_t* pBuffer = buffer;
 564
 565         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 566
 567         count >>= 2;
 568         wcount = count;
 569
 570         /* if we have an unaligned access - reorder data */
 571         if (adr & 0x3u)
 572         {
 573                 for (writecount = 0; writecount < count; writecount++)
 574                 {
 575                         int i;
 576                         uint32_t outvalue;
 577                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 578
 579                         for (i = 0; i < 4; i++)
 580                         {
 581                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 582                                 outvalue >>= 8;
 583                                 adr++;
 584                         }
 585                         pBuffer += sizeof(uint32_t);
 586                 }
 587         }
 588
 589         while (wcount > 0)
 590         {
 591                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 592                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 593                 if (wcount < blocksize)
 594                         blocksize = wcount;
 595
 596                 /* handle unaligned data at 4k boundary */
 597                 if (blocksize == 0)
 598                         blocksize = 1;
 599
 600                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 601
 602                 for (writecount = 0; writecount < blocksize; writecount++)
 603                 {
 604                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 605                 }
 606
 607                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 608                 {
 609                         wcount = wcount - blocksize;
 610                         address = address + 4 * blocksize;
 611                         buffer = buffer + 4 * blocksize;
 612                 }
 613                 else
 614                 {
 615                         errorcount++;
 616                 }
 617
 618                 if (errorcount > 1)
 619                 {
 620                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 621                         return ERROR_JTAG_DEVICE_ERROR;
 622                 }
 623         }
 624
 625         return retval;
 626 }
 627
 628 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 629                 uint8_t *buffer, int count, uint32_t address)
 630 {
 631         int retval = ERROR_OK;
 632         int wcount, blocksize, writecount, i;
 633
 634         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 635
 636         wcount = count >> 1;
 637
 638         while (wcount > 0)
 639         {
 640                 int nbytes;
 641
 642                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 643                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 644
 645                 if (wcount < blocksize)
 646                         blocksize = wcount;
 647
 648                 /* handle unaligned data at 4k boundary */
 649                 if (blocksize == 0)
 650                         blocksize = 1;
 651
 652                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 653                 writecount = blocksize;
 654
 655                 do
 656                 {
 657                         nbytes = MIN((writecount << 1), 4);
 658
 659                         if (nbytes < 4)
 660                         {
 661                                 if (mem_ap_write_buf_u16(swjdp, buffer,
 662                                                 nbytes, address) != ERROR_OK)
 663                                 {
 664                                         LOG_WARNING("Block write error address "
 665                                                 "0x%" PRIx32 ", count 0x%x",
 666                                                 address, count);
 667                                         return ERROR_JTAG_DEVICE_ERROR;
 668                                 }
 669
 670                                 address += nbytes >> 1;
 671                         }
 672                         else
 673                         {
 674                                 uint32_t outvalue;
 675                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 676
 677                                 for (i = 0; i < nbytes; i++)
 678                                 {
 679                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 680                                         outvalue >>= 8;
 681                                         address++;
 682                                 }
 683
 684                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 685                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 686                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 687                                 {
 688                                         LOG_WARNING("Block write error address "
 689                                                 "0x%" PRIx32 ", count 0x%x",
 690                                                 address, count);
 691                                         return ERROR_JTAG_DEVICE_ERROR;
 692                                 }
 693                         }
 694
 695                         buffer += nbytes >> 1;
 696                         writecount -= nbytes >> 1;
 697
 698                 } while (writecount);
 699                 wcount -= blocksize;
 700         }
 701
 702         return retval;
 703 }
 704
 705 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 706 {
 707         int retval = ERROR_OK;
 708
 709         if (count >= 4)
 710                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 711
 712         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 713
 714         while (count > 0)
 715         {
 716                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 717                 uint16_t svalue;
 718                 memcpy(&svalue, buffer, sizeof(uint16_t));
 719                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 720                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 721                 retval = jtagdp_transaction_endcheck(swjdp);
 722                 count -= 2;
 723                 address += 2;
 724                 buffer += 2;
 725         }
 726
 727         return retval;
 728 }
 729
 730 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 731                 uint8_t *buffer, int count, uint32_t address)
 732 {
 733         int retval = ERROR_OK;
 734         int wcount, blocksize, writecount, i;
 735
 736         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 737
 738         wcount = count;
 739
 740         while (wcount > 0)
 741         {
 742                 int nbytes;
 743
 744                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 745                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 746
 747                 if (wcount < blocksize)
 748                         blocksize = wcount;
 749
 750                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 751                 writecount = blocksize;
 752
 753                 do
 754                 {
 755                         nbytes = MIN(writecount, 4);
 756
 757                         if (nbytes < 4)
 758                         {
 759                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 760                                 {
 761                                         LOG_WARNING("Block write error address "
 762                                                 "0x%" PRIx32 ", count 0x%x",
 763                                                 address, count);
 764                                         return ERROR_JTAG_DEVICE_ERROR;
 765                                 }
 766
 767                                 address += nbytes;
 768                         }
 769                         else
 770                         {
 771                                 uint32_t outvalue;
 772                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 773
 774                                 for (i = 0; i < nbytes; i++)
 775                                 {
 776                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 777                                         outvalue >>= 8;
 778                                         address++;
 779                                 }
 780
 781                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 782                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 783                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 784                                 {
 785                                         LOG_WARNING("Block write error address "
 786                                                 "0x%" PRIx32 ", count 0x%x",
 787                                                 address, count);
 788                                         return ERROR_JTAG_DEVICE_ERROR;
 789                                 }
 790                         }
 791
 792                         buffer += nbytes;
 793                         writecount -= nbytes;
 794
 795                 } while (writecount);
 796                 wcount -= blocksize;
 797         }
 798
 799         return retval;
 800 }
 801
 802 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 803 {
 804         int retval = ERROR_OK;
 805
 806         if (count >= 4)
 807                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 808
 809         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 810
 811         while (count > 0)
 812         {
 813                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 814                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 815                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 816                 retval = jtagdp_transaction_endcheck(swjdp);
 817                 count--;
 818                 address++;
 819                 buffer++;
 820         }
 821
 822         return retval;
 823 }
 824
 825 /*********************************************************************************
 826 *                                                                                *
 827 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 828 *                                                                                *
 829 * Read block fast in target order (little endian) into a buffer                  *
 830 *                                                                                *
 831 **********************************************************************************/
 832 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 833 {
 834         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 835         uint32_t adr = address;
 836         uint8_t* pBuffer = buffer;
 837
 838         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 839
 840         count >>= 2;
 841         wcount = count;
 842
 843         while (wcount > 0)
 844         {
 845                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 846                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 847                 if (wcount < blocksize)
 848                         blocksize = wcount;
 849
 850                 /* handle unaligned data at 4k boundary */
 851                 if (blocksize == 0)
 852                         blocksize = 1;
 853
 854                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 855
 856                 /* Scan out first read */
 857                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 858                                 DPAP_READ, 0, NULL, NULL);
 859                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 860                 {
 861                         /* Scan out next read; scan in posted value for the
 862                          * previous one.  Assumes read is acked "OK/FAULT",
 863                          * and CTRL_STAT says that meant "OK".
 864                          */
 865                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 866                                         DPAP_READ, 0, buffer + 4 * readcount,
 867                                         &swjdp->ack);
 868                 }
 869
 870                 /* Scan in last posted value; RDBUFF has no other effect,
 871                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 872                  */
 873                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 874                                 DPAP_READ, 0, buffer + 4 * readcount,
 875                                 &swjdp->ack);
 876                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 877                 {
 878                         wcount = wcount - blocksize;
 879                         address += 4 * blocksize;
 880                         buffer += 4 * blocksize;
 881                 }
 882                 else
 883                 {
 884                         errorcount++;
 885                 }
 886
 887                 if (errorcount > 1)
 888                 {
 889                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 890                         return ERROR_JTAG_DEVICE_ERROR;
 891                 }
 892         }
 893
 894         /* if we have an unaligned access - reorder data */
 895         if (adr & 0x3u)
 896         {
 897                 for (readcount = 0; readcount < count; readcount++)
 898                 {
 899                         int i;
 900                         uint32_t data;
 901                         memcpy(&data, pBuffer, sizeof(uint32_t));
 902
 903                         for (i = 0; i < 4; i++)
 904                         {
 905                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 906                                 pBuffer++;
 907                                 adr++;
 908                         }
 909                 }
 910         }
 911
 912         return retval;
 913 }
 914
 915 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 916                 uint8_t *buffer, int count, uint32_t address)
 917 {
 918         uint32_t invalue;
 919         int retval = ERROR_OK;
 920         int wcount, blocksize, readcount, i;
 921
 922         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 923
 924         wcount = count >> 1;
 925
 926         while (wcount > 0)
 927         {
 928                 int nbytes;
 929
 930                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 931                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 932                 if (wcount < blocksize)
 933                         blocksize = wcount;
 934
 935                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 936
 937                 /* handle unaligned data at 4k boundary */
 938                 if (blocksize == 0)
 939                         blocksize = 1;
 940                 readcount = blocksize;
 941
 942                 do
 943                 {
 944                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 945                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 946                         {
 947                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 948                                 return ERROR_JTAG_DEVICE_ERROR;
 949                         }
 950
 951                         nbytes = MIN((readcount << 1), 4);
 952
 953                         for (i = 0; i < nbytes; i++)
 954                         {
 955                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 956                                 buffer++;
 957                                 address++;
 958                         }
 959
 960                         readcount -= (nbytes >> 1);
 961                 } while (readcount);
 962                 wcount -= blocksize;
 963         }
 964
 965         return retval;
 966 }
 967
 968 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 969 {
 970         uint32_t invalue, i;
 971         int retval = ERROR_OK;
 972
 973         if (count >= 4)
 974                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 975
 976         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 977
 978         while (count > 0)
 979         {
 980                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 981                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 982                 retval = jtagdp_transaction_endcheck(swjdp);
 983                 if (address & 0x1)
 984                 {
 985                         for (i = 0; i < 2; i++)
 986                         {
 987                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 988                                 buffer++;
 989                                 address++;
 990                         }
 991                 }
 992                 else
 993                 {
 994                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 995                         memcpy(buffer, &svalue, sizeof(uint16_t));
 996                         address += 2;
 997                         buffer += 2;
 998                 }
 999                 count -= 2;
1000         }
1001
1002         return retval;
1003 }
1004
1005 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1006  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1007  *
1008  * The solution is to arrange for a large out/in scan in this loop and
1009  * and convert data afterwards.
1010  */
1011 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1012                 uint8_t *buffer, int count, uint32_t address)
1013 {
1014         uint32_t invalue;
1015         int retval = ERROR_OK;
1016         int wcount, blocksize, readcount, i;
1017
1018         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1019
1020         wcount = count;
1021
1022         while (wcount > 0)
1023         {
1024                 int nbytes;
1025
1026                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1027                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1028
1029                 if (wcount < blocksize)
1030                         blocksize = wcount;
1031
1032                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1033                 readcount = blocksize;
1034
1035                 do
1036                 {
1037                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1038                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1039                         {
1040                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1041                                 return ERROR_JTAG_DEVICE_ERROR;
1042                         }
1043
1044                         nbytes = MIN(readcount, 4);
1045
1046                         for (i = 0; i < nbytes; i++)
1047                         {
1048                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1049                                 buffer++;
1050                                 address++;
1051                         }
1052
1053                         readcount -= nbytes;
1054                 } while (readcount);
1055                 wcount -= blocksize;
1056         }
1057
1058         return retval;
1059 }
1060
1061 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1062 {
1063         uint32_t invalue;
1064         int retval = ERROR_OK;
1065
1066         if (count >= 4)
1067                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1068
1069         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1070
1071         while (count > 0)
1072         {
1073                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1074                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1075                 retval = jtagdp_transaction_endcheck(swjdp);
1076                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1077                 count--;
1078                 address++;
1079                 buffer++;
1080         }
1081
1082         return retval;
1083 }
1084
1085 /**
1086  * Initialize a DAP.
1087  *
1088  * @todo Rename this.  We also need an initialization scheme which account
1089  * for SWD transports not just JTAG; that will need to address differences
1090  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1091  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1092  */
1093 int ahbap_debugport_init(struct swjdp_common *swjdp)
1094 {
1095         uint32_t idreg, romaddr, dummy;
1096         uint32_t ctrlstat;
1097         int cnt = 0;
1098         int retval;
1099
1100         LOG_DEBUG(" ");
1101
1102         /* Default MEM-AP setup.
1103          *
1104          * REVISIT AP #0 may be an inappropriate default for this.
1105          * Should we probe, or receve a hint from the caller?
1106          * Presumably we can ignore the possibility of multiple APs.
1107          */
1108         swjdp->apsel = 0;
1109         swjdp->ap_csw_value = -1;
1110         swjdp->ap_tar_value = -1;
1111
1112         /* DP initialization */
1113         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1114         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1115         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1116         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1117
1118         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1119
1120         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1121         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1122         if ((retval = jtag_execute_queue()) != ERROR_OK)
1123                 return retval;
1124
1125         /* Check that we have debug power domains activated */
1126         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1127         {
1128                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1129                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1130                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1131                         return retval;
1132                 alive_sleep(10);
1133         }
1134
1135         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1136         {
1137                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1138                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1139                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1140                         return retval;
1141                 alive_sleep(10);
1142         }
1143
1144         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1145         /* With debug power on we can activate OVERRUN checking */
1146         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1147         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1148         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1149
1150         /*
1151          * REVISIT this isn't actually *initializing* anything in an AP,
1152          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1153          * Should it?  If the ROM address is valid, is this the right
1154          * place to scan the table and do any topology detection?
1155          */
1156         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1157         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1158
1159         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1160                 ", Debug ROM Address 0x%" PRIx32,
1161                 swjdp->apsel, idreg, romaddr);
1162
1163         return ERROR_OK;
1164 }
1165
1166 /* CID interpretation -- see ARM IHI 0029B section 3
1167  * and ARM IHI 0031A table 13-3.
1168  */
1169 static const char *class_description[16] ={
1170         "Reserved", "ROM table", "Reserved", "Reserved",
1171         "Reserved", "Reserved", "Reserved", "Reserved",
1172         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1173         "Reserved", "OptimoDE DESS",
1174                 "Generic IP component", "PrimeCell or System component"
1175 };
1176
1177 static bool
1178 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1179 {
1180         return cid3 == 0xb1 && cid2 == 0x05
1181                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1182 }
1183
1184 int dap_info_command(struct command_context *cmd_ctx,
1185                 struct swjdp_common *swjdp, int apsel)
1186 {
1187
1188         uint32_t dbgbase, apid;
1189         int romtable_present = 0;
1190         uint8_t mem_ap;
1191         uint32_t apselold;
1192
1193         /* AP address is in bits 31:24 of DP_SELECT */
1194         if (apsel >= 256)
1195                 return ERROR_INVALID_ARGUMENTS;
1196
1197         apselold = swjdp->apsel;
1198         dap_ap_select(swjdp, apsel);
1199         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1200         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1201         jtagdp_transaction_endcheck(swjdp);
1202         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1203         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1204         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1205         if (apid)
1206         {
1207                 switch (apid&0x0F)
1208                 {
1209                         case 0:
1210                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1211                                 break;
1212                         case 1:
1213                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1214                                 break;
1215                         case 2:
1216                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1217                                 break;
1218                         default:
1219                                 command_print(cmd_ctx, "\tUnknown AP type");
1220                                 break;
1221                 }
1222
1223                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1224                  * not a ROM table ... or have no such components at all.
1225                  */
1226                 if (mem_ap)
1227                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1228                                         dbgbase);
1229         }
1230         else
1231         {
1232                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1233         }
1234
1235         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1236         if (romtable_present)
1237         {
1238                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1239                 uint16_t entry_offset;
1240
1241                 /* bit 16 of apid indicates a memory access port */
1242                 if (dbgbase & 0x02)
1243                         command_print(cmd_ctx, "\tValid ROM table present");
1244                 else
1245                         command_print(cmd_ctx, "\tROM table in legacy format");
1246
1247                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1248                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1249                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1250                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1251                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1252                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1253                 jtagdp_transaction_endcheck(swjdp);
1254                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1255                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1256                                         ", CID2 0x%2.2" PRIx32
1257                                         ", CID1 0x%2.2" PRIx32
1258                                         ", CID0 0x%2.2" PRIx32,
1259                                         cid3, cid2, cid1, cid0);
1260                 if (memtype & 0x01)
1261                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1262                 else
1263                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1264                                         "Dedicated debug bus.");
1265
1266                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1267                 entry_offset = 0;
1268                 do
1269                 {
1270                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1271                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1272                         if (romentry&0x01)
1273                         {
1274                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1275                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1276                                 uint32_t component_start, component_base;
1277                                 unsigned part_num;
1278                                 char *type, *full;
1279
1280                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1281                                                 + (int)(romentry & 0xFFFFF000));
1282                                 mem_ap_read_atomic_u32(swjdp,
1283                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1284                                 mem_ap_read_atomic_u32(swjdp,
1285                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1286                                 mem_ap_read_atomic_u32(swjdp,
1287                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1288                                 mem_ap_read_atomic_u32(swjdp,
1289                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1290                                 mem_ap_read_atomic_u32(swjdp,
1291                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1292                                 mem_ap_read_atomic_u32(swjdp,
1293                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1294                                 mem_ap_read_atomic_u32(swjdp,
1295                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1296                                 mem_ap_read_atomic_u32(swjdp,
1297                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1298                                 mem_ap_read_atomic_u32(swjdp,
1299                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1300                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1301
1302                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1303                                                 ", start address 0x%" PRIx32,
1304                                                 component_base, component_start);
1305                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1306                                                 (int) (c_cid1 >> 4) & 0xf,
1307                                                 /* See ARM IHI 0029B Table 3-3 */
1308                                                 class_description[(c_cid1 >> 4) & 0xf]);
1309
1310                                 /* CoreSight component? */
1311                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1312                                         uint32_t devtype;
1313                                         unsigned minor;
1314                                         char *major = "Reserved", *subtype = "Reserved";
1315
1316                                         mem_ap_read_atomic_u32(swjdp,
1317                                                         (component_base & 0xfffff000) | 0xfcc,
1318                                                         &devtype);
1319                                         minor = (devtype >> 4) & 0x0f;
1320                                         switch (devtype & 0x0f) {
1321                                         case 0:
1322                                                 major = "Miscellaneous";
1323                                                 switch (minor) {
1324                                                 case 0:
1325                                                         subtype = "other";
1326                                                         break;
1327                                                 case 4:
1328                                                         subtype = "Validation component";
1329                                                         break;
1330                                                 }
1331                                                 break;
1332                                         case 1:
1333                                                 major = "Trace Sink";
1334                                                 switch (minor) {
1335                                                 case 0:
1336                                                         subtype = "other";
1337                                                         break;
1338                                                 case 1:
1339                                                         subtype = "Port";
1340                                                         break;
1341                                                 case 2:
1342                                                         subtype = "Buffer";
1343                                                         break;
1344                                                 }
1345                                                 break;
1346                                         case 2:
1347                                                 major = "Trace Link";
1348                                                 switch (minor) {
1349                                                 case 0:
1350                                                         subtype = "other";
1351                                                         break;
1352                                                 case 1:
1353                                                         subtype = "Funnel, router";
1354                                                         break;
1355                                                 case 2:
1356                                                         subtype = "Filter";
1357                                                         break;
1358                                                 case 3:
1359                                                         subtype = "FIFO, buffer";
1360                                                         break;
1361                                                 }
1362                                                 break;
1363                                         case 3:
1364                                                 major = "Trace Source";
1365                                                 switch (minor) {
1366                                                 case 0:
1367                                                         subtype = "other";
1368                                                         break;
1369                                                 case 1:
1370                                                         subtype = "Processor";
1371                                                         break;
1372                                                 case 2:
1373                                                         subtype = "DSP";
1374                                                         break;
1375                                                 case 3:
1376                                                         subtype = "Engine/Coprocessor";
1377                                                         break;
1378                                                 case 4:
1379                                                         subtype = "Bus";
1380                                                         break;
1381                                                 }
1382                                                 break;
1383                                         case 4:
1384                                                 major = "Debug Control";
1385                                                 switch (minor) {
1386                                                 case 0:
1387                                                         subtype = "other";
1388                                                         break;
1389                                                 case 1:
1390                                                         subtype = "Trigger Matrix";
1391                                                         break;
1392                                                 case 2:
1393                                                         subtype = "Debug Auth";
1394                                                         break;
1395                                                 }
1396                                                 break;
1397                                         case 5:
1398                                                 major = "Debug Logic";
1399                                                 switch (minor) {
1400                                                 case 0:
1401                                                         subtype = "other";
1402                                                         break;
1403                                                 case 1:
1404                                                         subtype = "Processor";
1405                                                         break;
1406                                                 case 2:
1407                                                         subtype = "DSP";
1408                                                         break;
1409                                                 case 3:
1410                                                         subtype = "Engine/Coprocessor";
1411                                                         break;
1412                                                 }
1413                                                 break;
1414                                         }
1415                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1416                                                         (unsigned) (devtype & 0xff),
1417                                                         major, subtype);
1418                                         /* REVISIT also show 0xfc8 DevId */
1419                                 }
1420
1421                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1422                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1423                                                         ", CID2 0x%2.2" PRIx32
1424                                                         ", CID1 0x%2.2" PRIx32
1425                                                         ", CID0 0x%2.2" PRIx32,
1426                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1427                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1428                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1429                                                 (int) c_pid4,
1430                                                 (int) c_pid3, (int) c_pid2,
1431                                                 (int) c_pid1, (int) c_pid0);
1432
1433                                 /* Part number interpretations are from Cortex
1434                                  * core specs, the CoreSight components TRM
1435                                  * (ARM DDI 0314H), and ETM specs; also from
1436                                  * chip observation (e.g. TI SDTI).
1437                                  */
1438                                 part_num = c_pid0 & 0xff;
1439                                 part_num |= (c_pid1 & 0x0f) << 8;
1440                                 switch (part_num) {
1441                                 case 0x000:
1442                                         type = "Cortex-M3 NVIC";
1443                                         full = "(Interrupt Controller)";
1444                                         break;
1445                                 case 0x001:
1446                                         type = "Cortex-M3 ITM";
1447                                         full = "(Instrumentation Trace Module)";
1448                                         break;
1449                                 case 0x002:
1450                                         type = "Cortex-M3 DWT";
1451                                         full = "(Data Watchpoint and Trace)";
1452                                         break;
1453                                 case 0x003:
1454                                         type = "Cortex-M3 FBP";
1455                                         full = "(Flash Patch and Breakpoint)";
1456                                         break;
1457                                 case 0x00d:
1458                                         type = "CoreSight ETM11";
1459                                         full = "(Embedded Trace)";
1460                                         break;
1461                                 // case 0x113: what?
1462                                 case 0x120:             /* from OMAP3 memmap */
1463                                         type = "TI SDTI";
1464                                         full = "(System Debug Trace Interface)";
1465                                         break;
1466                                 case 0x343:             /* from OMAP3 memmap */
1467                                         type = "TI DAPCTL";
1468                                         full = "";
1469                                         break;
1470                                 case 0x4e0:
1471                                         type = "Cortex-M3 ETM";
1472                                         full = "(Embedded Trace)";
1473                                         break;
1474                                 case 0x906:
1475                                         type = "Coresight CTI";
1476                                         full = "(Cross Trigger)";
1477                                         break;
1478                                 case 0x907:
1479                                         type = "Coresight ETB";
1480                                         full = "(Trace Buffer)";
1481                                         break;
1482                                 case 0x908:
1483                                         type = "Coresight CSTF";
1484                                         full = "(Trace Funnel)";
1485                                         break;
1486                                 case 0x910:
1487                                         type = "CoreSight ETM9";
1488                                         full = "(Embedded Trace)";
1489                                         break;
1490                                 case 0x912:
1491                                         type = "Coresight TPIU";
1492                                         full = "(Trace Port Interface Unit)";
1493                                         break;
1494                                 case 0x921:
1495                                         type = "Cortex-A8 ETM";
1496                                         full = "(Embedded Trace)";
1497                                         break;
1498                                 case 0x922:
1499                                         type = "Cortex-A8 CTI";
1500                                         full = "(Cross Trigger)";
1501                                         break;
1502                                 case 0x923:
1503                                         type = "Cortex-M3 TPIU";
1504                                         full = "(Trace Port Interface Unit)";
1505                                         break;
1506                                 case 0xc08:
1507                                         type = "Cortex-A8 Debug";
1508                                         full = "(Debug Unit)";
1509                                         break;
1510                                 default:
1511                                         type = "-*- unrecognized -*-";
1512                                         full = "";
1513                                         break;
1514                                 }
1515                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1516                                                 type, full);
1517                         }
1518                         else
1519                         {
1520                                 if (romentry)
1521                                         command_print(cmd_ctx, "\t\tComponent not present");
1522                                 else
1523                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1524                         }
1525                         entry_offset += 4;
1526                 } while (romentry > 0);
1527         }
1528         else
1529         {
1530                 command_print(cmd_ctx, "\tNo ROM table present");
1531         }
1532         dap_ap_select(swjdp, apselold);
1533
1534         return ERROR_OK;
1535 }
1536
1537 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1538 {
1539         uint32_t apsel, apselsave, baseaddr;
1540         int retval;
1541
1542         apselsave = swjdp->apsel;
1543         switch (CMD_ARGC) {
1544         case 0:
1545                 apsel = swjdp->apsel;
1546                 break;
1547         case 1:
1548                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1549                 /* AP address is in bits 31:24 of DP_SELECT */
1550                 if (apsel >= 256)
1551                         return ERROR_INVALID_ARGUMENTS;
1552                 break;
1553         default:
1554                 return ERROR_COMMAND_SYNTAX_ERROR;
1555         }
1556
1557         if (apselsave != apsel)
1558                 dap_ap_select(swjdp, apsel);
1559
1560         /* NOTE:  assumes we're talking to a MEM-AP, which
1561          * has a base address.  There are other kinds of AP,
1562          * though they're not common for now.  This should
1563          * use the ID register to verify it's a MEM-AP.
1564          */
1565         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1566         retval = jtagdp_transaction_endcheck(swjdp);
1567         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1568
1569         if (apselsave != apsel)
1570                 dap_ap_select(swjdp, apselsave);
1571
1572         return retval;
1573 }
1574
1575 DAP_COMMAND_HANDLER(dap_memaccess_command)
1576 {
1577         uint32_t memaccess_tck;
1578
1579         switch (CMD_ARGC) {
1580         case 0:
1581                 memaccess_tck = swjdp->memaccess_tck;
1582                 break;
1583         case 1:
1584                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1585                 break;
1586         default:
1587                 return ERROR_COMMAND_SYNTAX_ERROR;
1588         }
1589         swjdp->memaccess_tck = memaccess_tck;
1590
1591         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1592                         swjdp->memaccess_tck);
1593
1594         return ERROR_OK;
1595 }
1596
1597 DAP_COMMAND_HANDLER(dap_apsel_command)
1598 {
1599         uint32_t apsel, apid;
1600         int retval;
1601
1602         switch (CMD_ARGC) {
1603         case 0:
1604                 apsel = 0;
1605                 break;
1606         case 1:
1607                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1608                 /* AP address is in bits 31:24 of DP_SELECT */
1609                 if (apsel >= 256)
1610                         return ERROR_INVALID_ARGUMENTS;
1611                 break;
1612         default:
1613                 return ERROR_COMMAND_SYNTAX_ERROR;
1614         }
1615
1616         dap_ap_select(swjdp, apsel);
1617         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1618         retval = jtagdp_transaction_endcheck(swjdp);
1619         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1620                         apsel, apid);
1621
1622         return retval;
1623 }
1624
1625 DAP_COMMAND_HANDLER(dap_apid_command)
1626 {
1627         uint32_t apsel, apselsave, apid;
1628         int retval;
1629
1630         apselsave = swjdp->apsel;
1631         switch (CMD_ARGC) {
1632         case 0:
1633                 apsel = swjdp->apsel;
1634                 break;
1635         case 1:
1636                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1637                 /* AP address is in bits 31:24 of DP_SELECT */
1638                 if (apsel >= 256)
1639                         return ERROR_INVALID_ARGUMENTS;
1640                 break;
1641         default:
1642                 return ERROR_COMMAND_SYNTAX_ERROR;
1643         }
1644
1645         if (apselsave != apsel)
1646                 dap_ap_select(swjdp, apsel);
1647
1648         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1649         retval = jtagdp_transaction_endcheck(swjdp);
1650         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1651         if (apselsave != apsel)
1652                 dap_ap_select(swjdp, apselsave);
1653
1654         return retval;
1655 }