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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm.h"
  73 #include "arm_adi_v5.h"
  74 #include <helper/time_support.h>
  75
  76
  77 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  78
  79 /*
  80         uint32_t tar_block_size(uint32_t address)
  81         Return the largest block starting at address that does not cross a tar block size alignment boundary
  82 */
  83 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  84 {
  85         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  86 }
  87
  88 /***************************************************************************
  89  *                                                                         *
  90  * DP and MEM-AP  register access  through APACC and DPACC                 *
  91  *                                                                         *
  92 ***************************************************************************/
  93
  94 /**
  95  * Select one of the APs connected to the specified DAP.  The
  96  * selection is implicitly used with future AP transactions.
  97  * This is a NOP if the specified AP is already selected.
  98  *
  99  * @param dap The DAP
 100  * @param apsel Number of the AP to (implicitly) use with further
 101  *      transactions.  This normally identifies a MEM-AP.
 102  */
 103 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
 104 {
 105         uint32_t select_apsel = (apsel << 24) & 0xFF000000;
 106
 107         if (select_apsel != dap->apsel)
 108         {
 109                 dap->apsel = select_apsel;
 110                 /* Switching AP invalidates cached values.
 111                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 112                  */
 113                 dap->ap_bank_value = -1;
 114                 dap->ap_csw_value = -1;
 115                 dap->ap_tar_value = -1;
 116         }
 117 }
 118
 119 /**
 120  * Queue transactions setting up transfer parameters for the
 121  * currently selected MEM-AP.
 122  *
 123  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 124  * initiate data reads or writes using memory or peripheral addresses.
 125  * If the CSW is configured for it, the TAR may be automatically
 126  * incremented after each transfer.
 127  *
 128  * @todo Rename to reflect it being specifically a MEM-AP function.
 129  *
 130  * @param dap The DAP connected to the MEM-AP.
 131  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 132  *      matches the cached value, the register is not changed.
 133  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 134  *      matches the cached address, the register is not changed.
 135  *
 136  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 137  */
 138 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 139 {
 140         int retval;
 141
 142         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 143         if (csw != dap->ap_csw_value)
 144         {
 145                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 146                 retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 147                 if (retval != ERROR_OK)
 148                         return retval;
 149                 dap->ap_csw_value = csw;
 150         }
 151         if (tar != dap->ap_tar_value)
 152         {
 153                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 154                 retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 155                 if (retval != ERROR_OK)
 156                         return retval;
 157                 dap->ap_tar_value = tar;
 158         }
 159         /* Disable TAR cache when autoincrementing */
 160         if (csw & CSW_ADDRINC_MASK)
 161                 dap->ap_tar_value = -1;
 162         return ERROR_OK;
 163 }
 164
 165 /**
 166  * Asynchronous (queued) read of a word from memory or a system register.
 167  *
 168  * @param dap The DAP connected to the MEM-AP performing the read.
 169  * @param address Address of the 32-bit word to read; it must be
 170  *      readable by the currently selected MEM-AP.
 171  * @param value points to where the word will be stored when the
 172  *      transaction queue is flushed (assuming no errors).
 173  *
 174  * @return ERROR_OK for success.  Otherwise a fault code.
 175  */
 176 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 177                 uint32_t *value)
 178 {
 179         int retval;
 180
 181         /* Use banked addressing (REG_BDx) to avoid some link traffic
 182          * (updating TAR) when reading several consecutive addresses.
 183          */
 184         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 185                         address & 0xFFFFFFF0);
 186         if (retval != ERROR_OK)
 187                 return retval;
 188
 189         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 190 }
 191
 192 /**
 193  * Synchronous read of a word from memory or a system register.
 194  * As a side effect, this flushes any queued transactions.
 195  *
 196  * @param dap The DAP connected to the MEM-AP performing the read.
 197  * @param address Address of the 32-bit word to read; it must be
 198  *      readable by the currently selected MEM-AP.
 199  * @param value points to where the result will be stored.
 200  *
 201  * @return ERROR_OK for success; *value holds the result.
 202  * Otherwise a fault code.
 203  */
 204 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 205                 uint32_t *value)
 206 {
 207         int retval;
 208
 209         retval = mem_ap_read_u32(dap, address, value);
 210         if (retval != ERROR_OK)
 211                 return retval;
 212
 213         return dap_run(dap);
 214 }
 215
 216 /**
 217  * Asynchronous (queued) write of a word to memory or a system register.
 218  *
 219  * @param dap The DAP connected to the MEM-AP.
 220  * @param address Address to be written; it must be writable by
 221  *      the currently selected MEM-AP.
 222  * @param value Word that will be written to the address when transaction
 223  *      queue is flushed (assuming no errors).
 224  *
 225  * @return ERROR_OK for success.  Otherwise a fault code.
 226  */
 227 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 228                 uint32_t value)
 229 {
 230         int retval;
 231
 232         /* Use banked addressing (REG_BDx) to avoid some link traffic
 233          * (updating TAR) when writing several consecutive addresses.
 234          */
 235         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 236                         address & 0xFFFFFFF0);
 237         if (retval != ERROR_OK)
 238                 return retval;
 239
 240         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 241                         value);
 242 }
 243
 244 /**
 245  * Synchronous write of a word to memory or a system register.
 246  * As a side effect, this flushes any queued transactions.
 247  *
 248  * @param dap The DAP connected to the MEM-AP.
 249  * @param address Address to be written; it must be writable by
 250  *      the currently selected MEM-AP.
 251  * @param value Word that will be written.
 252  *
 253  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 254  */
 255 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 256                 uint32_t value)
 257 {
 258         int retval = mem_ap_write_u32(dap, address, value);
 259
 260         if (retval != ERROR_OK)
 261                 return retval;
 262
 263         return dap_run(dap);
 264 }
 265
 266 /*****************************************************************************
 267 *                                                                            *
 268 * mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 269 *                                                                            *
 270 * Write a buffer in target order (little endian)                             *
 271 *                                                                            *
 272 *****************************************************************************/
 273 int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 274 {
 275         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 276         uint32_t adr = address;
 277         uint8_t* pBuffer = buffer;
 278
 279         count >>= 2;
 280         wcount = count;
 281
 282         /* if we have an unaligned access - reorder data */
 283         if (adr & 0x3u)
 284         {
 285                 for (writecount = 0; writecount < count; writecount++)
 286                 {
 287                         int i;
 288                         uint32_t outvalue;
 289                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 290
 291                         for (i = 0; i < 4; i++)
 292                         {
 293                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 294                                 outvalue >>= 8;
 295                                 adr++;
 296                         }
 297                         pBuffer += sizeof(uint32_t);
 298                 }
 299         }
 300
 301         while (wcount > 0)
 302         {
 303                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 304                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 305                 if (wcount < blocksize)
 306                         blocksize = wcount;
 307
 308                 /* handle unaligned data at 4k boundary */
 309                 if (blocksize == 0)
 310                         blocksize = 1;
 311
 312                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315
 316                 for (writecount = 0; writecount < blocksize; writecount++)
 317                 {
 318                         retval = dap_queue_ap_write(dap, AP_REG_DRW,
 319                                 *(uint32_t *) (buffer + 4 * writecount));
 320                         if (retval != ERROR_OK)
 321                                 break;
 322                 }
 323
 324                 if (dap_run(dap) == ERROR_OK)
 325                 {
 326                         wcount = wcount - blocksize;
 327                         address = address + 4 * blocksize;
 328                         buffer = buffer + 4 * blocksize;
 329                 }
 330                 else
 331                 {
 332                         errorcount++;
 333                 }
 334
 335                 if (errorcount > 1)
 336                 {
 337                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 338                         /* REVISIT return the *actual* fault code */
 339                         return ERROR_JTAG_DEVICE_ERROR;
 340                 }
 341         }
 342
 343         return retval;
 344 }
 345
 346 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 347                 uint8_t *buffer, int count, uint32_t address)
 348 {
 349         int retval = ERROR_OK;
 350         int wcount, blocksize, writecount, i;
 351
 352         wcount = count >> 1;
 353
 354         while (wcount > 0)
 355         {
 356                 int nbytes;
 357
 358                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 359                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 360
 361                 if (wcount < blocksize)
 362                         blocksize = wcount;
 363
 364                 /* handle unaligned data at 4k boundary */
 365                 if (blocksize == 0)
 366                         blocksize = 1;
 367
 368                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 369                 if (retval != ERROR_OK)
 370                         return retval;
 371                 writecount = blocksize;
 372
 373                 do
 374                 {
 375                         nbytes = MIN((writecount << 1), 4);
 376
 377                         if (nbytes < 4)
 378                         {
 379                                 if (mem_ap_write_buf_u16(dap, buffer,
 380                                                 nbytes, address) != ERROR_OK)
 381                                 {
 382                                         LOG_WARNING("Block write error address "
 383                                                 "0x%" PRIx32 ", count 0x%x",
 384                                                 address, count);
 385                                         return ERROR_JTAG_DEVICE_ERROR;
 386                                 }
 387
 388                                 address += nbytes >> 1;
 389                         }
 390                         else
 391                         {
 392                                 uint32_t outvalue;
 393                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 394
 395                                 for (i = 0; i < nbytes; i++)
 396                                 {
 397                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 398                                         outvalue >>= 8;
 399                                         address++;
 400                                 }
 401
 402                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 403                                 retval = dap_queue_ap_write(dap,
 404                                                 AP_REG_DRW, outvalue);
 405                                 if (retval != ERROR_OK)
 406                                         break;
 407
 408                                 if (dap_run(dap) != ERROR_OK)
 409                                 {
 410                                         LOG_WARNING("Block write error address "
 411                                                 "0x%" PRIx32 ", count 0x%x",
 412                                                 address, count);
 413                                         /* REVISIT return *actual* fault code */
 414                                         return ERROR_JTAG_DEVICE_ERROR;
 415                                 }
 416                         }
 417
 418                         buffer += nbytes >> 1;
 419                         writecount -= nbytes >> 1;
 420
 421                 } while (writecount);
 422                 wcount -= blocksize;
 423         }
 424
 425         return retval;
 426 }
 427
 428 int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 429 {
 430         int retval = ERROR_OK;
 431
 432         if (count >= 4)
 433                 return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 434
 435         while (count > 0)
 436         {
 437                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 438                 if (retval != ERROR_OK)
 439                         return retval;
 440                 uint16_t svalue;
 441                 memcpy(&svalue, buffer, sizeof(uint16_t));
 442                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 443                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 444                 if (retval != ERROR_OK)
 445                         break;
 446
 447                 retval = dap_run(dap);
 448                 if (retval != ERROR_OK)
 449                         break;
 450
 451                 count -= 2;
 452                 address += 2;
 453                 buffer += 2;
 454         }
 455
 456         return retval;
 457 }
 458
 459 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 460                 uint8_t *buffer, int count, uint32_t address)
 461 {
 462         int retval = ERROR_OK;
 463         int wcount, blocksize, writecount, i;
 464
 465         wcount = count;
 466
 467         while (wcount > 0)
 468         {
 469                 int nbytes;
 470
 471                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 472                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 473
 474                 if (wcount < blocksize)
 475                         blocksize = wcount;
 476
 477                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 478                 if (retval != ERROR_OK)
 479                         return retval;
 480                 writecount = blocksize;
 481
 482                 do
 483                 {
 484                         nbytes = MIN(writecount, 4);
 485
 486                         if (nbytes < 4)
 487                         {
 488                                 if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
 489                                 {
 490                                         LOG_WARNING("Block write error address "
 491                                                 "0x%" PRIx32 ", count 0x%x",
 492                                                 address, count);
 493                                         return ERROR_JTAG_DEVICE_ERROR;
 494                                 }
 495
 496                                 address += nbytes;
 497                         }
 498                         else
 499                         {
 500                                 uint32_t outvalue;
 501                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 502
 503                                 for (i = 0; i < nbytes; i++)
 504                                 {
 505                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 506                                         outvalue >>= 8;
 507                                         address++;
 508                                 }
 509
 510                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 511                                 retval = dap_queue_ap_write(dap,
 512                                                 AP_REG_DRW, outvalue);
 513                                 if (retval != ERROR_OK)
 514                                         break;
 515
 516                                 if (dap_run(dap) != ERROR_OK)
 517                                 {
 518                                         LOG_WARNING("Block write error address "
 519                                                 "0x%" PRIx32 ", count 0x%x",
 520                                                 address, count);
 521                                         /* REVISIT return *actual* fault code */
 522                                         return ERROR_JTAG_DEVICE_ERROR;
 523                                 }
 524                         }
 525
 526                         buffer += nbytes;
 527                         writecount -= nbytes;
 528
 529                 } while (writecount);
 530                 wcount -= blocksize;
 531         }
 532
 533         return retval;
 534 }
 535
 536 int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 537 {
 538         int retval = ERROR_OK;
 539
 540         if (count >= 4)
 541                 return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 542
 543         while (count > 0)
 544         {
 545                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 546                 if (retval != ERROR_OK)
 547                         return retval;
 548                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 549                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 550                 if (retval != ERROR_OK)
 551                         break;
 552
 553                 retval = dap_run(dap);
 554                 if (retval != ERROR_OK)
 555                         break;
 556
 557                 count--;
 558                 address++;
 559                 buffer++;
 560         }
 561
 562         return retval;
 563 }
 564
 565 /* FIXME don't import ... this is a temporary workaround for the
 566  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
 567  */
 568 extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 569                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 570                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 571
 572 /**
 573  * Synchronously read a block of 32-bit words into a buffer
 574  * @param dap The DAP connected to the MEM-AP.
 575  * @param buffer where the words will be stored (in host byte order).
 576  * @param count How many words to read.
 577  * @param address Memory address from which to read words; all the
 578  *      words must be readable by the currently selected MEM-AP.
 579  */
 580 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 581                 int count, uint32_t address)
 582 {
 583         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 584         uint32_t adr = address;
 585         uint8_t* pBuffer = buffer;
 586
 587         count >>= 2;
 588         wcount = count;
 589
 590         while (wcount > 0)
 591         {
 592                 /* Adjust to read blocks within boundaries aligned to the
 593                  * TAR autoincrement size (at least 2^10).  Autoincrement
 594                  * mode avoids an extra per-word roundtrip to update TAR.
 595                  */
 596                 blocksize = max_tar_block_size(dap->tar_autoincr_block,
 597                                 address);
 598                 if (wcount < blocksize)
 599                         blocksize = wcount;
 600
 601                 /* handle unaligned data at 4k boundary */
 602                 if (blocksize == 0)
 603                         blocksize = 1;
 604
 605                 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 606                                 address);
 607                 if (retval != ERROR_OK)
 608                         return retval;
 609
 610                 /* FIXME remove these three calls to adi_jtag_dp_scan(),
 611                  * so this routine becomes transport-neutral.  Be careful
 612                  * not to cause performance problems with JTAG; would it
 613                  * suffice to loop over dap_queue_ap_read(), or would that
 614                  * be slower when JTAG is the chosen transport?
 615                  */
 616
 617                 /* Scan out first read */
 618                 retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 619                                 DPAP_READ, 0, NULL, NULL);
 620                 if (retval != ERROR_OK)
 621                         return retval;
 622                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 623                 {
 624                         /* Scan out next read; scan in posted value for the
 625                          * previous one.  Assumes read is acked "OK/FAULT",
 626                          * and CTRL_STAT says that meant "OK".
 627                          */
 628                         retval = adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 629                                         DPAP_READ, 0, buffer + 4 * readcount,
 630                                         &dap->ack);
 631                         if (retval != ERROR_OK)
 632                                 return retval;
 633                 }
 634
 635                 /* Scan in last posted value; RDBUFF has no other effect,
 636                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 637                  */
 638                 retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 639                                 DPAP_READ, 0, buffer + 4 * readcount,
 640                                 &dap->ack);
 641                 if (retval != ERROR_OK)
 642                         return retval;
 643
 644                 retval = dap_run(dap);
 645                 if (retval != ERROR_OK)
 646                 {
 647                         errorcount++;
 648                         if (errorcount <= 1)
 649                         {
 650                                 /* try again */
 651                                 continue;
 652                         }
 653                         LOG_WARNING("Block read error address 0x%" PRIx32, address);
 654                         return retval;
 655                 }
 656                 wcount = wcount - blocksize;
 657                 address += 4 * blocksize;
 658                 buffer += 4 * blocksize;
 659         }
 660
 661         /* if we have an unaligned access - reorder data */
 662         if (adr & 0x3u)
 663         {
 664                 for (readcount = 0; readcount < count; readcount++)
 665                 {
 666                         int i;
 667                         uint32_t data;
 668                         memcpy(&data, pBuffer, sizeof(uint32_t));
 669
 670                         for (i = 0; i < 4; i++)
 671                         {
 672                                 *((uint8_t*)pBuffer) =
 673                                                 (data >> 8 * (adr & 0x3));
 674                                 pBuffer++;
 675                                 adr++;
 676                         }
 677                 }
 678         }
 679
 680         return retval;
 681 }
 682
 683 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 684                 uint8_t *buffer, int count, uint32_t address)
 685 {
 686         uint32_t invalue;
 687         int retval = ERROR_OK;
 688         int wcount, blocksize, readcount, i;
 689
 690         wcount = count >> 1;
 691
 692         while (wcount > 0)
 693         {
 694                 int nbytes;
 695
 696                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 697                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 698                 if (wcount < blocksize)
 699                         blocksize = wcount;
 700
 701                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 702                 if (retval != ERROR_OK)
 703                         return retval;
 704
 705                 /* handle unaligned data at 4k boundary */
 706                 if (blocksize == 0)
 707                         blocksize = 1;
 708                 readcount = blocksize;
 709
 710                 do
 711                 {
 712                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 713                         if (dap_run(dap) != ERROR_OK)
 714                         {
 715                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 716                                 /* REVISIT return the *actual* fault code */
 717                                 return ERROR_JTAG_DEVICE_ERROR;
 718                         }
 719
 720                         nbytes = MIN((readcount << 1), 4);
 721
 722                         for (i = 0; i < nbytes; i++)
 723                         {
 724                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 725                                 buffer++;
 726                                 address++;
 727                         }
 728
 729                         readcount -= (nbytes >> 1);
 730                 } while (readcount);
 731                 wcount -= blocksize;
 732         }
 733
 734         return retval;
 735 }
 736
 737 /**
 738  * Synchronously read a block of 16-bit halfwords into a buffer
 739  * @param dap The DAP connected to the MEM-AP.
 740  * @param buffer where the halfwords will be stored (in host byte order).
 741  * @param count How many halfwords to read.
 742  * @param address Memory address from which to read words; all the
 743  *      words must be readable by the currently selected MEM-AP.
 744  */
 745 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 746                 int count, uint32_t address)
 747 {
 748         uint32_t invalue, i;
 749         int retval = ERROR_OK;
 750
 751         if (count >= 4)
 752                 return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 753
 754         while (count > 0)
 755         {
 756                 retval = dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 757                 if (retval != ERROR_OK)
 758                         return retval;
 759                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 760                 if (retval != ERROR_OK)
 761                         break;
 762
 763                 retval = dap_run(dap);
 764                 if (retval != ERROR_OK)
 765                         break;
 766
 767                 if (address & 0x1)
 768                 {
 769                         for (i = 0; i < 2; i++)
 770                         {
 771                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 772                                 buffer++;
 773                                 address++;
 774                         }
 775                 }
 776                 else
 777                 {
 778                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 779                         memcpy(buffer, &svalue, sizeof(uint16_t));
 780                         address += 2;
 781                         buffer += 2;
 782                 }
 783                 count -= 2;
 784         }
 785
 786         return retval;
 787 }
 788
 789 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 790  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 791  *
 792  * The solution is to arrange for a large out/in scan in this loop and
 793  * and convert data afterwards.
 794  */
 795 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 796                 uint8_t *buffer, int count, uint32_t address)
 797 {
 798         uint32_t invalue;
 799         int retval = ERROR_OK;
 800         int wcount, blocksize, readcount, i;
 801
 802         wcount = count;
 803
 804         while (wcount > 0)
 805         {
 806                 int nbytes;
 807
 808                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 809                 blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 810
 811                 if (wcount < blocksize)
 812                         blocksize = wcount;
 813
 814                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 815                 if (retval != ERROR_OK)
 816                         return retval;
 817                 readcount = blocksize;
 818
 819                 do
 820                 {
 821                         retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 822                         if (dap_run(dap) != ERROR_OK)
 823                         {
 824                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 825                                 /* REVISIT return the *actual* fault code */
 826                                 return ERROR_JTAG_DEVICE_ERROR;
 827                         }
 828
 829                         nbytes = MIN(readcount, 4);
 830
 831                         for (i = 0; i < nbytes; i++)
 832                         {
 833                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 834                                 buffer++;
 835                                 address++;
 836                         }
 837
 838                         readcount -= nbytes;
 839                 } while (readcount);
 840                 wcount -= blocksize;
 841         }
 842
 843         return retval;
 844 }
 845
 846 /**
 847  * Synchronously read a block of bytes into a buffer
 848  * @param dap The DAP connected to the MEM-AP.
 849  * @param buffer where the bytes will be stored.
 850  * @param count How many bytes to read.
 851  * @param address Memory address from which to read data; all the
 852  *      data must be readable by the currently selected MEM-AP.
 853  */
 854 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 855                 int count, uint32_t address)
 856 {
 857         uint32_t invalue;
 858         int retval = ERROR_OK;
 859
 860         if (count >= 4)
 861                 return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 862
 863         while (count > 0)
 864         {
 865                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 866                 if (retval != ERROR_OK)
 867                         return retval;
 868                 retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 869                 if (retval != ERROR_OK)
 870                         return retval;
 871                 retval = dap_run(dap);
 872                 if (retval != ERROR_OK)
 873                         break;
 874
 875                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 876                 count--;
 877                 address++;
 878                 buffer++;
 879         }
 880
 881         return retval;
 882 }
 883
 884 /*--------------------------------------------------------------------------*/
 885
 886
 887 /* FIXME don't import ... just initialize as
 888  * part of DAP transport setup
 889 */
 890 extern const struct dap_ops jtag_dp_ops;
 891
 892 /*--------------------------------------------------------------------------*/
 893
 894 /**
 895  * Initialize a DAP.  This sets up the power domains, prepares the DP
 896  * for further use, and arranges to use AP #0 for all AP operations
 897  * until dap_ap-select() changes that policy.
 898  *
 899  * @param dap The DAP being initialized.
 900  *
 901  * @todo Rename this.  We also need an initialization scheme which account
 902  * for SWD transports not just JTAG; that will need to address differences
 903  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 904  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 905  */
 906 int ahbap_debugport_init(struct adiv5_dap *dap)
 907 {
 908         uint32_t idreg, romaddr, dummy;
 909         uint32_t ctrlstat;
 910         int cnt = 0;
 911         int retval;
 912
 913         LOG_DEBUG(" ");
 914
 915         /* JTAG-DP or SWJ-DP, in JTAG mode */
 916         dap->ops = &jtag_dp_ops;
 917
 918         /* Default MEM-AP setup.
 919          *
 920          * REVISIT AP #0 may be an inappropriate default for this.
 921          * Should we probe, or take a hint from the caller?
 922          * Presumably we can ignore the possibility of multiple APs.
 923          */
 924         dap->apsel = !0;
 925         dap_ap_select(dap, 0);
 926
 927         /* DP initialization */
 928
 929         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 930         if (retval != ERROR_OK)
 931                 return retval;
 932
 933         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 934         if (retval != ERROR_OK)
 935                 return retval;
 936
 937         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 938         if (retval != ERROR_OK)
 939                 return retval;
 940
 941         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 942         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 943         if (retval != ERROR_OK)
 944                 return retval;
 945
 946         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 947         if (retval != ERROR_OK)
 948                 return retval;
 949         if ((retval = dap_run(dap)) != ERROR_OK)
 950                 return retval;
 951
 952         /* Check that we have debug power domains activated */
 953         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
 954         {
 955                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 956                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 957                 if (retval != ERROR_OK)
 958                         return retval;
 959                 if ((retval = dap_run(dap)) != ERROR_OK)
 960                         return retval;
 961                 alive_sleep(10);
 962         }
 963
 964         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
 965         {
 966                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 967                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 968                 if (retval != ERROR_OK)
 969                         return retval;
 970                 if ((retval = dap_run(dap)) != ERROR_OK)
 971                         return retval;
 972                 alive_sleep(10);
 973         }
 974
 975         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 976         if (retval != ERROR_OK)
 977                 return retval;
 978         /* With debug power on we can activate OVERRUN checking */
 979         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 980         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 981         if (retval != ERROR_OK)
 982                 return retval;
 983         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 984         if (retval != ERROR_OK)
 985                 return retval;
 986
 987         /*
 988          * REVISIT this isn't actually *initializing* anything in an AP,
 989          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
 990          * Should it?  If the ROM address is valid, is this the right
 991          * place to scan the table and do any topology detection?
 992          */
 993         retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
 994         retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
 995
 996         if ((retval = dap_run(dap)) != ERROR_OK)
 997                 return retval;
 998
 999         LOG_DEBUG("MEM-AP #%" PRId32 " ID Register 0x%" PRIx32
1000                 ", Debug ROM Address 0x%" PRIx32,
1001                 dap->apsel, idreg, romaddr);
1002
1003         return ERROR_OK;
1004 }
1005
1006 /* CID interpretation -- see ARM IHI 0029B section 3
1007  * and ARM IHI 0031A table 13-3.
1008  */
1009 static const char *class_description[16] ={
1010         "Reserved", "ROM table", "Reserved", "Reserved",
1011         "Reserved", "Reserved", "Reserved", "Reserved",
1012         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1013         "Reserved", "OptimoDE DESS",
1014                 "Generic IP component", "PrimeCell or System component"
1015 };
1016
1017 static bool
1018 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1019 {
1020         return cid3 == 0xb1 && cid2 == 0x05
1021                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1022 }
1023
1024 static int dap_info_command(struct command_context *cmd_ctx,
1025                 struct adiv5_dap *dap, int apsel)
1026 {
1027         int retval;
1028         uint32_t dbgbase, apid;
1029         int romtable_present = 0;
1030         uint8_t mem_ap;
1031         uint32_t apselold;
1032
1033         /* AP address is in bits 31:24 of DP_SELECT */
1034         if (apsel >= 256)
1035                 return ERROR_INVALID_ARGUMENTS;
1036
1037         apselold = dap->apsel;
1038         dap_ap_select(dap, apsel);
1039         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1040         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1041         retval = dap_run(dap);
1042         if (retval != ERROR_OK)
1043                 return retval;
1044
1045         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1046         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1047         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1048         if (apid)
1049         {
1050                 switch (apid&0x0F)
1051                 {
1052                         case 0:
1053                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1054                                 break;
1055                         case 1:
1056                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1057                                 break;
1058                         case 2:
1059                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1060                                 break;
1061                         default:
1062                                 command_print(cmd_ctx, "\tUnknown AP type");
1063                                 break;
1064                 }
1065
1066                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1067                  * not a ROM table ... or have no such components at all.
1068                  */
1069                 if (mem_ap)
1070                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1071                                         dbgbase);
1072         }
1073         else
1074         {
1075                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1076         }
1077
1078         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1079         if (romtable_present)
1080         {
1081                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1082                 uint16_t entry_offset;
1083
1084                 /* bit 16 of apid indicates a memory access port */
1085                 if (dbgbase & 0x02)
1086                         command_print(cmd_ctx, "\tValid ROM table present");
1087                 else
1088                         command_print(cmd_ctx, "\tROM table in legacy format");
1089
1090                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1091                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1092                 if (retval != ERROR_OK)
1093                         return retval;
1094                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1095                 if (retval != ERROR_OK)
1096                         return retval;
1097                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1098                 if (retval != ERROR_OK)
1099                         return retval;
1100                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1101                 if (retval != ERROR_OK)
1102                         return retval;
1103                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1104                 if (retval != ERROR_OK)
1105                         return retval;
1106                 retval = dap_run(dap);
1107                 if (retval != ERROR_OK)
1108                         return retval;
1109
1110                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1111                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1112                                         ", CID2 0x%2.2x"
1113                                         ", CID1 0x%2.2x"
1114                                         ", CID0 0x%2.2x",
1115                                         (unsigned) cid3, (unsigned)cid2,
1116                                         (unsigned) cid1, (unsigned) cid0);
1117                 if (memtype & 0x01)
1118                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1119                 else
1120                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1121                                         "Dedicated debug bus.");
1122
1123                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1124                 entry_offset = 0;
1125                 do
1126                 {
1127                         mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1128                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1129                         if (romentry&0x01)
1130                         {
1131                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1132                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1133                                 uint32_t component_base;
1134                                 unsigned part_num;
1135                                 char *type, *full;
1136
1137                                 component_base = (dbgbase & 0xFFFFF000)
1138                                                 + (romentry & 0xFFFFF000);
1139
1140                                 /* IDs are in last 4K section */
1141
1142
1143                                 mem_ap_read_atomic_u32(dap,
1144                                         component_base + 0xFE0, &c_pid0);
1145                                 c_pid0 &= 0xff;
1146                                 mem_ap_read_atomic_u32(dap,
1147                                         component_base + 0xFE4, &c_pid1);
1148                                 c_pid1 &= 0xff;
1149                                 mem_ap_read_atomic_u32(dap,
1150                                         component_base + 0xFE8, &c_pid2);
1151                                 c_pid2 &= 0xff;
1152                                 mem_ap_read_atomic_u32(dap,
1153                                         component_base + 0xFEC, &c_pid3);
1154                                 c_pid3 &= 0xff;
1155                                 mem_ap_read_atomic_u32(dap,
1156                                         component_base + 0xFD0, &c_pid4);
1157                                 c_pid4 &= 0xff;
1158
1159                                 mem_ap_read_atomic_u32(dap,
1160                                         component_base + 0xFF0, &c_cid0);
1161                                 c_cid0 &= 0xff;
1162                                 mem_ap_read_atomic_u32(dap,
1163                                         component_base + 0xFF4, &c_cid1);
1164                                 c_cid1 &= 0xff;
1165                                 mem_ap_read_atomic_u32(dap,
1166                                         component_base + 0xFF8, &c_cid2);
1167                                 c_cid2 &= 0xff;
1168                                 mem_ap_read_atomic_u32(dap,
1169                                         component_base + 0xFFC, &c_cid3);
1170                                 c_cid3 &= 0xff;
1171
1172
1173                                 command_print(cmd_ctx,
1174                                 "\t\tComponent base address 0x%" PRIx32
1175                                         ", start address 0x%" PRIx32,
1176                                                 component_base,
1177                                 /* component may take multiple 4K pages */
1178                                 component_base - 0x1000*(c_pid4 >> 4));
1179                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1180                                                 (int) (c_cid1 >> 4) & 0xf,
1181                                                 /* See ARM IHI 0029B Table 3-3 */
1182                                                 class_description[(c_cid1 >> 4) & 0xf]);
1183
1184                                 /* CoreSight component? */
1185                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1186                                         uint32_t devtype;
1187                                         unsigned minor;
1188                                         char *major = "Reserved", *subtype = "Reserved";
1189
1190                                         mem_ap_read_atomic_u32(dap,
1191                                                         (component_base & 0xfffff000) | 0xfcc,
1192                                                         &devtype);
1193                                         minor = (devtype >> 4) & 0x0f;
1194                                         switch (devtype & 0x0f) {
1195                                         case 0:
1196                                                 major = "Miscellaneous";
1197                                                 switch (minor) {
1198                                                 case 0:
1199                                                         subtype = "other";
1200                                                         break;
1201                                                 case 4:
1202                                                         subtype = "Validation component";
1203                                                         break;
1204                                                 }
1205                                                 break;
1206                                         case 1:
1207                                                 major = "Trace Sink";
1208                                                 switch (minor) {
1209                                                 case 0:
1210                                                         subtype = "other";
1211                                                         break;
1212                                                 case 1:
1213                                                         subtype = "Port";
1214                                                         break;
1215                                                 case 2:
1216                                                         subtype = "Buffer";
1217                                                         break;
1218                                                 }
1219                                                 break;
1220                                         case 2:
1221                                                 major = "Trace Link";
1222                                                 switch (minor) {
1223                                                 case 0:
1224                                                         subtype = "other";
1225                                                         break;
1226                                                 case 1:
1227                                                         subtype = "Funnel, router";
1228                                                         break;
1229                                                 case 2:
1230                                                         subtype = "Filter";
1231                                                         break;
1232                                                 case 3:
1233                                                         subtype = "FIFO, buffer";
1234                                                         break;
1235                                                 }
1236                                                 break;
1237                                         case 3:
1238                                                 major = "Trace Source";
1239                                                 switch (minor) {
1240                                                 case 0:
1241                                                         subtype = "other";
1242                                                         break;
1243                                                 case 1:
1244                                                         subtype = "Processor";
1245                                                         break;
1246                                                 case 2:
1247                                                         subtype = "DSP";
1248                                                         break;
1249                                                 case 3:
1250                                                         subtype = "Engine/Coprocessor";
1251                                                         break;
1252                                                 case 4:
1253                                                         subtype = "Bus";
1254                                                         break;
1255                                                 }
1256                                                 break;
1257                                         case 4:
1258                                                 major = "Debug Control";
1259                                                 switch (minor) {
1260                                                 case 0:
1261                                                         subtype = "other";
1262                                                         break;
1263                                                 case 1:
1264                                                         subtype = "Trigger Matrix";
1265                                                         break;
1266                                                 case 2:
1267                                                         subtype = "Debug Auth";
1268                                                         break;
1269                                                 }
1270                                                 break;
1271                                         case 5:
1272                                                 major = "Debug Logic";
1273                                                 switch (minor) {
1274                                                 case 0:
1275                                                         subtype = "other";
1276                                                         break;
1277                                                 case 1:
1278                                                         subtype = "Processor";
1279                                                         break;
1280                                                 case 2:
1281                                                         subtype = "DSP";
1282                                                         break;
1283                                                 case 3:
1284                                                         subtype = "Engine/Coprocessor";
1285                                                         break;
1286                                                 }
1287                                                 break;
1288                                         }
1289                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1290                                                         (unsigned) (devtype & 0xff),
1291                                                         major, subtype);
1292                                         /* REVISIT also show 0xfc8 DevId */
1293                                 }
1294
1295                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1296                                         command_print(cmd_ctx,
1297                                                       "\t\tCID3 0%2.2x"
1298                                                         ", CID2 0%2.2x"
1299                                                         ", CID1 0%2.2x"
1300                                                         ", CID0 0%2.2x",
1301                                                         (int) c_cid3,
1302                                                         (int) c_cid2,
1303                                                         (int)c_cid1,
1304                                                         (int)c_cid0);
1305                                 command_print(cmd_ctx,
1306                                 "\t\tPeripheral ID[4..0] = hex "
1307                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1308                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1309                                 (int) c_pid1, (int) c_pid0);
1310
1311                                 /* Part number interpretations are from Cortex
1312                                  * core specs, the CoreSight components TRM
1313                                  * (ARM DDI 0314H), and ETM specs; also from
1314                                  * chip observation (e.g. TI SDTI).
1315                                  */
1316                                 part_num = (c_pid0 & 0xff);
1317                                 part_num |= (c_pid1 & 0x0f) << 8;
1318                                 switch (part_num) {
1319                                 case 0x000:
1320                                         type = "Cortex-M3 NVIC";
1321                                         full = "(Interrupt Controller)";
1322                                         break;
1323                                 case 0x001:
1324                                         type = "Cortex-M3 ITM";
1325                                         full = "(Instrumentation Trace Module)";
1326                                         break;
1327                                 case 0x002:
1328                                         type = "Cortex-M3 DWT";
1329                                         full = "(Data Watchpoint and Trace)";
1330                                         break;
1331                                 case 0x003:
1332                                         type = "Cortex-M3 FBP";
1333                                         full = "(Flash Patch and Breakpoint)";
1334                                         break;
1335                                 case 0x00d:
1336                                         type = "CoreSight ETM11";
1337                                         full = "(Embedded Trace)";
1338                                         break;
1339                                 // case 0x113: what?
1340                                 case 0x120:             /* from OMAP3 memmap */
1341                                         type = "TI SDTI";
1342                                         full = "(System Debug Trace Interface)";
1343                                         break;
1344                                 case 0x343:             /* from OMAP3 memmap */
1345                                         type = "TI DAPCTL";
1346                                         full = "";
1347                                         break;
1348                                 case 0x906:
1349                                         type = "Coresight CTI";
1350                                         full = "(Cross Trigger)";
1351                                         break;
1352                                 case 0x907:
1353                                         type = "Coresight ETB";
1354                                         full = "(Trace Buffer)";
1355                                         break;
1356                                 case 0x908:
1357                                         type = "Coresight CSTF";
1358                                         full = "(Trace Funnel)";
1359                                         break;
1360                                 case 0x910:
1361                                         type = "CoreSight ETM9";
1362                                         full = "(Embedded Trace)";
1363                                         break;
1364                                 case 0x912:
1365                                         type = "Coresight TPIU";
1366                                         full = "(Trace Port Interface Unit)";
1367                                         break;
1368                                 case 0x921:
1369                                         type = "Cortex-A8 ETM";
1370                                         full = "(Embedded Trace)";
1371                                         break;
1372                                 case 0x922:
1373                                         type = "Cortex-A8 CTI";
1374                                         full = "(Cross Trigger)";
1375                                         break;
1376                                 case 0x923:
1377                                         type = "Cortex-M3 TPIU";
1378                                         full = "(Trace Port Interface Unit)";
1379                                         break;
1380                                 case 0x924:
1381                                         type = "Cortex-M3 ETM";
1382                                         full = "(Embedded Trace)";
1383                                         break;
1384                                 case 0xc08:
1385                                         type = "Cortex-A8 Debug";
1386                                         full = "(Debug Unit)";
1387                                         break;
1388                                 default:
1389                                         type = "-*- unrecognized -*-";
1390                                         full = "";
1391                                         break;
1392                                 }
1393                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1394                                                 type, full);
1395                         }
1396                         else
1397                         {
1398                                 if (romentry)
1399                                         command_print(cmd_ctx, "\t\tComponent not present");
1400                                 else
1401                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1402                         }
1403                         entry_offset += 4;
1404                 } while (romentry > 0);
1405         }
1406         else
1407         {
1408                 command_print(cmd_ctx, "\tNo ROM table present");
1409         }
1410         dap_ap_select(dap, apselold);
1411
1412         return ERROR_OK;
1413 }
1414
1415 COMMAND_HANDLER(handle_dap_info_command)
1416 {
1417         struct target *target = get_current_target(CMD_CTX);
1418         struct arm *arm = target_to_arm(target);
1419         struct adiv5_dap *dap = arm->dap;
1420         uint32_t apsel;
1421
1422         switch (CMD_ARGC) {
1423         case 0:
1424                 apsel = dap->apsel;
1425                 break;
1426         case 1:
1427                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1428                 break;
1429         default:
1430                 return ERROR_COMMAND_SYNTAX_ERROR;
1431         }
1432
1433         return dap_info_command(CMD_CTX, dap, apsel);
1434 }
1435
1436 COMMAND_HANDLER(dap_baseaddr_command)
1437 {
1438         struct target *target = get_current_target(CMD_CTX);
1439         struct arm *arm = target_to_arm(target);
1440         struct adiv5_dap *dap = arm->dap;
1441
1442         uint32_t apsel, apselsave, baseaddr;
1443         int retval;
1444
1445         apselsave = dap->apsel;
1446         switch (CMD_ARGC) {
1447         case 0:
1448                 apsel = dap->apsel;
1449                 break;
1450         case 1:
1451                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1452                 /* AP address is in bits 31:24 of DP_SELECT */
1453                 if (apsel >= 256)
1454                         return ERROR_INVALID_ARGUMENTS;
1455                 break;
1456         default:
1457                 return ERROR_COMMAND_SYNTAX_ERROR;
1458         }
1459
1460         if (apselsave != apsel)
1461                 dap_ap_select(dap, apsel);
1462
1463         /* NOTE:  assumes we're talking to a MEM-AP, which
1464          * has a base address.  There are other kinds of AP,
1465          * though they're not common for now.  This should
1466          * use the ID register to verify it's a MEM-AP.
1467          */
1468         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1469         retval = dap_run(dap);
1470         if (retval != ERROR_OK)
1471                 return retval;
1472
1473         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1474
1475         if (apselsave != apsel)
1476                 dap_ap_select(dap, apselsave);
1477
1478         return retval;
1479 }
1480
1481 COMMAND_HANDLER(dap_memaccess_command)
1482 {
1483         struct target *target = get_current_target(CMD_CTX);
1484         struct arm *arm = target_to_arm(target);
1485         struct adiv5_dap *dap = arm->dap;
1486
1487         uint32_t memaccess_tck;
1488
1489         switch (CMD_ARGC) {
1490         case 0:
1491                 memaccess_tck = dap->memaccess_tck;
1492                 break;
1493         case 1:
1494                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1495                 break;
1496         default:
1497                 return ERROR_COMMAND_SYNTAX_ERROR;
1498         }
1499         dap->memaccess_tck = memaccess_tck;
1500
1501         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1502                         dap->memaccess_tck);
1503
1504         return ERROR_OK;
1505 }
1506
1507 COMMAND_HANDLER(dap_apsel_command)
1508 {
1509         struct target *target = get_current_target(CMD_CTX);
1510         struct arm *arm = target_to_arm(target);
1511         struct adiv5_dap *dap = arm->dap;
1512
1513         uint32_t apsel, apid;
1514         int retval;
1515
1516         switch (CMD_ARGC) {
1517         case 0:
1518                 apsel = 0;
1519                 break;
1520         case 1:
1521                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1522                 /* AP address is in bits 31:24 of DP_SELECT */
1523                 if (apsel >= 256)
1524                         return ERROR_INVALID_ARGUMENTS;
1525                 break;
1526         default:
1527                 return ERROR_COMMAND_SYNTAX_ERROR;
1528         }
1529
1530         dap_ap_select(dap, apsel);
1531         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1532         retval = dap_run(dap);
1533         if (retval != ERROR_OK)
1534                 return retval;
1535
1536         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1537                         apsel, apid);
1538
1539         return retval;
1540 }
1541
1542 COMMAND_HANDLER(dap_apid_command)
1543 {
1544         struct target *target = get_current_target(CMD_CTX);
1545         struct arm *arm = target_to_arm(target);
1546         struct adiv5_dap *dap = arm->dap;
1547
1548         uint32_t apsel, apselsave, apid;
1549         int retval;
1550
1551         apselsave = dap->apsel;
1552         switch (CMD_ARGC) {
1553         case 0:
1554                 apsel = dap->apsel;
1555                 break;
1556         case 1:
1557                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1558                 /* AP address is in bits 31:24 of DP_SELECT */
1559                 if (apsel >= 256)
1560                         return ERROR_INVALID_ARGUMENTS;
1561                 break;
1562         default:
1563                 return ERROR_COMMAND_SYNTAX_ERROR;
1564         }
1565
1566         if (apselsave != apsel)
1567                 dap_ap_select(dap, apsel);
1568
1569         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1570         retval = dap_run(dap);
1571         if (retval != ERROR_OK)
1572                 return retval;
1573
1574         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1575         if (apselsave != apsel)
1576                 dap_ap_select(dap, apselsave);
1577
1578         return retval;
1579 }
1580
1581 static const struct command_registration dap_commands[] = {
1582         {
1583                 .name = "info",
1584                 .handler = handle_dap_info_command,
1585                 .mode = COMMAND_EXEC,
1586                 .help = "display ROM table for MEM-AP "
1587                         "(default currently selected AP)",
1588                 .usage = "[ap_num]",
1589         },
1590         {
1591                 .name = "apsel",
1592                 .handler = dap_apsel_command,
1593                 .mode = COMMAND_EXEC,
1594                 .help = "Set the currently selected AP (default 0) "
1595                         "and display the result",
1596                 .usage = "[ap_num]",
1597         },
1598         {
1599                 .name = "apid",
1600                 .handler = dap_apid_command,
1601                 .mode = COMMAND_EXEC,
1602                 .help = "return ID register from AP "
1603                         "(default currently selected AP)",
1604                 .usage = "[ap_num]",
1605         },
1606         {
1607                 .name = "baseaddr",
1608                 .handler = dap_baseaddr_command,
1609                 .mode = COMMAND_EXEC,
1610                 .help = "return debug base address from MEM-AP "
1611                         "(default currently selected AP)",
1612                 .usage = "[ap_num]",
1613         },
1614         {
1615                 .name = "memaccess",
1616                 .handler = dap_memaccess_command,
1617                 .mode = COMMAND_EXEC,
1618                 .help = "set/get number of extra tck for MEM-AP memory "
1619                         "bus access [0-255]",
1620                 .usage = "[cycles]",
1621         },
1622         COMMAND_REGISTRATION_DONE
1623 };
1624
1625 const struct command_registration dap_command_handlers[] = {
1626         {
1627                 .name = "dap",
1628                 .mode = COMMAND_EXEC,
1629                 .help = "DAP command group",
1630                 .chain = dap_commands,
1631         },
1632         COMMAND_REGISTRATION_DONE
1633 };
1634
1635