ADIv5 error checking for Tcl commands
[fw/openocd] / src / target / arm_adi_v5.c
1 /***************************************************************************
2  *   Copyright (C) 2006 by Magnus Lundin                                   *
3  *   lundin@mlu.mine.nu                                                    *
4  *                                                                         *
5  *   Copyright (C) 2008 by Spencer Oliver                                  *
6  *   spen@spen-soft.co.uk                                                  *
7  *                                                                         *
8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
9  *   oyvind.harboe@zylin.com                                               *
10  *                                                                         *
11  *   Copyright (C) 2009-2010 by David Brownell                             *
12  *                                                                         *
13  *   This program is free software; you can redistribute it and/or modify  *
14  *   it under the terms of the GNU General Public License as published by  *
15  *   the Free Software Foundation; either version 2 of the License, or     *
16  *   (at your option) any later version.                                   *
17  *                                                                         *
18  *   This program is distributed in the hope that it will be useful,       *
19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
21  *   GNU General Public License for more details.                          *
22  *                                                                         *
23  *   You should have received a copy of the GNU General Public License     *
24  *   along with this program; if not, write to the                         *
25  *   Free Software Foundation, Inc.,                                       *
26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
27  ***************************************************************************/
28
29 /**
30  * @file
31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32  * debugging architecture.  Compared with previous versions, this includes
33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34  * transport, and focusses on memory mapped resources as defined by the
35  * CoreSight architecture.
36  *
37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
38  * basic components:  a Debug Port (DP) transporting messages to and from a
39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
41  * One uses only SWD for communication, and is called SW-DP.  The third can
42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
45  */
46
47 /*
48  * Relevant specifications from ARM include:
49  *
50  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
51  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
52  *
53  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
54  * Cortex-M3(tm) TRM, ARM DDI 0337G
55  */
56
57 #ifdef HAVE_CONFIG_H
58 #include "config.h"
59 #endif
60
61 #include "arm_adi_v5.h"
62 #include <helper/time_support.h>
63
64 /*
65  * Transaction Mode:
66  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
67  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
68  * result checking until swjdp_end_transaction()
69  * This must be done before using or deallocating any return variables.
70  * swjdp->trans_mode == TRANS_MODE_ATOMIC
71  * All reads and writes to the AHB bus are checked for valid completion, and return values
72  * are immediatley available.
73 */
74
75
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
77
78 /*
79         uint32_t tar_block_size(uint32_t address)
80         Return the largest block starting at address that does not cross a tar block size alignment boundary
81 */
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
83 {
84         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
85 }
86
87 /***************************************************************************
88  *                                                                         *
89  * DPACC and APACC scanchain access through JTAG-DP                        *
90  *                                                                         *
91 ***************************************************************************/
92
93 /**
94  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
95  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
96  * discusses operations which access these registers.
97  *
98  * Note that only one scan is performed.  If RnW is set, a separate scan
99  * will be needed to collect the data which was read; the "invalue" collects
100  * the posted result of a preceding operation, not the current one.
101  *
102  * @param swjdp the DAP
103  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105  *      SELECT register has more addressing bits.
106  * @param RnW false iff outvalue will be written to the DP or AP
107  * @param outvalue points to a 32-bit (little-endian) integer
108  * @param invalue NULL, or points to a 32-bit (little-endian) integer
109  * @param ack points to where the three bit JTAG_ACK_* code will be stored
110  */
111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
112                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
113                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
114 {
115         struct arm_jtag *jtag_info = swjdp->jtag_info;
116         struct scan_field fields[2];
117         uint8_t out_addr_buf;
118
119         jtag_set_end_state(TAP_IDLE);
120         arm_jtag_set_instr(jtag_info, instr, NULL);
121
122         /* Add specified number of tck clocks before accessing memory bus */
123
124         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
125          * they provide more time for the (MEM) AP to complete the read ...
126          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
127          */
128         if ((instr == JTAG_DP_APACC)
129                         && ((reg_addr == AP_REG_DRW)
130                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
131                         && (swjdp->memaccess_tck != 0))
132                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
133
134         /* Scan out a read or write operation using some DP or AP register.
135          * For APACC access with any sticky error flag set, this is discarded.
136          */
137         fields[0].tap = jtag_info->tap;
138         fields[0].num_bits = 3;
139         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
140         fields[0].out_value = &out_addr_buf;
141         fields[0].in_value = ack;
142
143         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
144          * complete; data we write is discarded, data we read is unpredictable.
145          * When overrun detect is active, STICKYORUN is set.
146          */
147
148         fields[1].tap = jtag_info->tap;
149         fields[1].num_bits = 32;
150         fields[1].out_value = outvalue;
151         fields[1].in_value = invalue;
152
153         jtag_add_dr_scan(2, fields, jtag_get_end_state());
154
155         return ERROR_OK;
156 }
157
158 /* Scan out and in from host ordered uint32_t variables */
159 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
160                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
161                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
162 {
163         struct arm_jtag *jtag_info = swjdp->jtag_info;
164         struct scan_field fields[2];
165         uint8_t out_value_buf[4];
166         uint8_t out_addr_buf;
167
168         jtag_set_end_state(TAP_IDLE);
169         arm_jtag_set_instr(jtag_info, instr, NULL);
170
171         /* Add specified number of tck clocks before accessing memory bus */
172
173         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
174          * they provide more time for the (MEM) AP to complete the read ...
175          */
176         if ((instr == JTAG_DP_APACC)
177                         && ((reg_addr == AP_REG_DRW)
178                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
179                         && (swjdp->memaccess_tck != 0))
180                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
181
182         fields[0].tap = jtag_info->tap;
183         fields[0].num_bits = 3;
184         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
185         fields[0].out_value = &out_addr_buf;
186         fields[0].in_value = ack;
187
188         fields[1].tap = jtag_info->tap;
189         fields[1].num_bits = 32;
190         buf_set_u32(out_value_buf, 0, 32, outvalue);
191         fields[1].out_value = out_value_buf;
192         fields[1].in_value = NULL;
193
194         if (invalue)
195         {
196                 fields[1].in_value = (uint8_t *)invalue;
197                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
198
199                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
200         } else
201         {
202
203                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
204         }
205
206         return ERROR_OK;
207 }
208
209 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
210 static int scan_inout_check(struct swjdp_common *swjdp,
211                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
212                 uint8_t *outvalue, uint8_t *invalue)
213 {
214         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
215
216         if ((RnW == DPAP_READ) && (invalue != NULL))
217                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
218                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
219
220         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
221          * ack = OK/FAULT and the check CTRL_STAT
222          */
223         if ((instr == JTAG_DP_APACC)
224                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
225                 return jtagdp_transaction_endcheck(swjdp);
226
227         return ERROR_OK;
228 }
229
230 static int scan_inout_check_u32(struct swjdp_common *swjdp,
231                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
232                 uint32_t outvalue, uint32_t *invalue)
233 {
234         /* Issue the read or write */
235         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
236
237         /* For reads,  collect posted value; RDBUFF has no other effect.
238          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
239          */
240         if ((RnW == DPAP_READ) && (invalue != NULL))
241                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
242                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
243
244         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
245          * ack = OK/FAULT and then check CTRL_STAT
246          */
247         if ((instr == JTAG_DP_APACC)
248                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
249                 return jtagdp_transaction_endcheck(swjdp);
250
251         return ERROR_OK;
252 }
253
254 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
255 {
256         int retval;
257         uint32_t ctrlstat;
258
259         /* too expensive to call keep_alive() here */
260
261 #if 0
262         /* Danger!!!! BROKEN!!!! */
263         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
264                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
265         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
266         R956 introduced the check on return value here and now Michael Schwingen reports
267         that this code no longer works....
268
269         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
270         */
271         if ((retval = jtag_execute_queue()) != ERROR_OK)
272         {
273                 LOG_ERROR("BUG: Why does this fail the first time????");
274         }
275         /* Why??? second time it works??? */
276 #endif
277
278         /* Post CTRL/STAT read; discard any previous posted read value
279          * but collect its ACK status.
280          */
281         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
282                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
283         if ((retval = jtag_execute_queue()) != ERROR_OK)
284                 return retval;
285
286         swjdp->ack = swjdp->ack & 0x7;
287
288         /* common code path avoids calling timeval_ms() */
289         if (swjdp->ack != JTAG_ACK_OK_FAULT)
290         {
291                 long long then = timeval_ms();
292
293                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
294                 {
295                         if (swjdp->ack == JTAG_ACK_WAIT)
296                         {
297                                 if ((timeval_ms()-then) > 1000)
298                                 {
299                                         /* NOTE:  this would be a good spot
300                                          * to use JTAG_DP_ABORT.
301                                          */
302                                         LOG_WARNING("Timeout (1000ms) waiting "
303                                                 "for ACK=OK/FAULT "
304                                                 "in JTAG-DP transaction");
305                                         return ERROR_JTAG_DEVICE_ERROR;
306                                 }
307                         }
308                         else
309                         {
310                                 LOG_WARNING("Invalid ACK %#x "
311                                                 "in JTAG-DP transaction",
312                                                 swjdp->ack);
313                                 return ERROR_JTAG_DEVICE_ERROR;
314                         }
315
316                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
317                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
318                         if ((retval = jtag_execute_queue()) != ERROR_OK)
319                                 return retval;
320                         swjdp->ack = swjdp->ack & 0x7;
321                 }
322         }
323
324         /* Check for STICKYERR and STICKYORUN */
325         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
326         {
327                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
328                 /* Check power to debug regions */
329                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
330                 {
331                          ahbap_debugport_init(swjdp);
332                 }
333                 else
334                 {
335                         uint32_t mem_ap_csw, mem_ap_tar;
336
337                         /* Print information about last AHBAP access */
338                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
339                                 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
340                                 swjdp->dp_select_value, swjdp->ap_csw_value,
341                                 swjdp->ap_tar_value);
342                         if (ctrlstat & SSTICKYORUN)
343                                 LOG_ERROR("JTAG-DP OVERRUN - "
344                                         "check clock or reduce jtag speed");
345
346                         if (ctrlstat & SSTICKYERR)
347                                 LOG_ERROR("JTAG-DP STICKY ERROR");
348
349                         /* Clear Sticky Error Bits */
350                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
351                                         DP_CTRL_STAT, DPAP_WRITE,
352                                         swjdp->dp_ctrl_stat | SSTICKYORUN
353                                                 | SSTICKYERR, NULL);
354                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
355                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
356                         if ((retval = jtag_execute_queue()) != ERROR_OK)
357                                 return retval;
358
359                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
360
361                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
362                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
363                         if ((retval = jtag_execute_queue()) != ERROR_OK)
364                                 return retval;
365                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
366                                         PRIx32, mem_ap_csw, mem_ap_tar);
367
368                 }
369                 if ((retval = jtag_execute_queue()) != ERROR_OK)
370                         return retval;
371                 return ERROR_JTAG_DEVICE_ERROR;
372         }
373
374         return ERROR_OK;
375 }
376
377 /***************************************************************************
378  *                                                                         *
379  * DP and MEM-AP  register access  through APACC and DPACC                 *
380  *                                                                         *
381 ***************************************************************************/
382
383 static int dap_dp_write_reg(struct swjdp_common *swjdp,
384                 uint32_t value, uint8_t reg_addr)
385 {
386         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
387                         reg_addr, DPAP_WRITE, value, NULL);
388 }
389
390 static int dap_dp_read_reg(struct swjdp_common *swjdp,
391                 uint32_t *value, uint8_t reg_addr)
392 {
393         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
394                         reg_addr, DPAP_READ, 0, value);
395 }
396
397 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
398 {
399         uint32_t select;
400         select = (apsel << 24) & 0xFF000000;
401
402         if (select != swjdp->apsel)
403         {
404                 swjdp->apsel = select;
405                 /* Switching AP invalidates cached values */
406                 swjdp->dp_select_value = -1;
407                 swjdp->ap_csw_value = -1;
408                 swjdp->ap_tar_value = -1;
409         }
410
411         return ERROR_OK;
412 }
413
414 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
415 {
416         uint32_t select;
417         select = (ap_reg & 0x000000F0);
418
419         if (select != swjdp->dp_select_value)
420         {
421                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
422                 swjdp->dp_select_value = select;
423         }
424
425         return ERROR_OK;
426 }
427
428 static int dap_ap_write_reg(struct swjdp_common *swjdp,
429                 uint32_t reg_addr, uint8_t *out_value_buf)
430 {
431         dap_dp_bankselect(swjdp, reg_addr);
432         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
433                         DPAP_WRITE, out_value_buf, NULL);
434
435         return ERROR_OK;
436 }
437
438 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
439 {
440         uint8_t out_value_buf[4];
441
442         buf_set_u32(out_value_buf, 0, 32, value);
443         dap_dp_bankselect(swjdp, reg_addr);
444         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
445                         DPAP_WRITE, out_value_buf, NULL);
446
447         return ERROR_OK;
448 }
449
450 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
451 {
452         dap_dp_bankselect(swjdp, reg_addr);
453         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
454                         DPAP_READ, 0, value);
455
456         return ERROR_OK;
457 }
458
459 /***************************************************************************
460  *                                                                         *
461  * AHB-AP access to memory and system registers on AHB bus                 *
462  *                                                                         *
463 ***************************************************************************/
464
465 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
466 {
467         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
468         if (csw != swjdp->ap_csw_value)
469         {
470                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
471                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
472                 swjdp->ap_csw_value = csw;
473         }
474         if (tar != swjdp->ap_tar_value)
475         {
476                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
477                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
478                 swjdp->ap_tar_value = tar;
479         }
480         if (csw & CSW_ADDRINC_MASK)
481         {
482                 /* Do not cache TAR value when autoincrementing */
483                 swjdp->ap_tar_value = -1;
484         }
485         return ERROR_OK;
486 }
487
488 /*****************************************************************************
489 *                                                                            *
490 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
491 *                                                                            *
492 * Read a uint32_t value from memory or system register                            *
493 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
494 * but with less overhead                                                     *
495 *****************************************************************************/
496 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
497 {
498         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
499
500         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
501         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
502
503         return ERROR_OK;
504 }
505
506 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
507 {
508         mem_ap_read_u32(swjdp, address, value);
509
510         return jtagdp_transaction_endcheck(swjdp);
511 }
512
513 /*****************************************************************************
514 *                                                                            *
515 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
516 *                                                                            *
517 * Write a uint32_t value to memory or memory mapped register                              *
518 *                                                                            *
519 *****************************************************************************/
520 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
521 {
522         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
523
524         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
525         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
526
527         return ERROR_OK;
528 }
529
530 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
531 {
532         mem_ap_write_u32(swjdp, address, value);
533
534         return jtagdp_transaction_endcheck(swjdp);
535 }
536
537 /*****************************************************************************
538 *                                                                            *
539 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
540 *                                                                            *
541 * Write a buffer in target order (little endian)                             *
542 *                                                                            *
543 *****************************************************************************/
544 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
545 {
546         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
547         uint32_t adr = address;
548         uint8_t* pBuffer = buffer;
549
550         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
551
552         count >>= 2;
553         wcount = count;
554
555         /* if we have an unaligned access - reorder data */
556         if (adr & 0x3u)
557         {
558                 for (writecount = 0; writecount < count; writecount++)
559                 {
560                         int i;
561                         uint32_t outvalue;
562                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
563
564                         for (i = 0; i < 4; i++)
565                         {
566                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
567                                 outvalue >>= 8;
568                                 adr++;
569                         }
570                         pBuffer += sizeof(uint32_t);
571                 }
572         }
573
574         while (wcount > 0)
575         {
576                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
577                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
578                 if (wcount < blocksize)
579                         blocksize = wcount;
580
581                 /* handle unaligned data at 4k boundary */
582                 if (blocksize == 0)
583                         blocksize = 1;
584
585                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
586
587                 for (writecount = 0; writecount < blocksize; writecount++)
588                 {
589                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
590                 }
591
592                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
593                 {
594                         wcount = wcount - blocksize;
595                         address = address + 4 * blocksize;
596                         buffer = buffer + 4 * blocksize;
597                 }
598                 else
599                 {
600                         errorcount++;
601                 }
602
603                 if (errorcount > 1)
604                 {
605                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
606                         return ERROR_JTAG_DEVICE_ERROR;
607                 }
608         }
609
610         return retval;
611 }
612
613 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
614                 uint8_t *buffer, int count, uint32_t address)
615 {
616         int retval = ERROR_OK;
617         int wcount, blocksize, writecount, i;
618
619         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
620
621         wcount = count >> 1;
622
623         while (wcount > 0)
624         {
625                 int nbytes;
626
627                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
628                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
629
630                 if (wcount < blocksize)
631                         blocksize = wcount;
632
633                 /* handle unaligned data at 4k boundary */
634                 if (blocksize == 0)
635                         blocksize = 1;
636
637                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
638                 writecount = blocksize;
639
640                 do
641                 {
642                         nbytes = MIN((writecount << 1), 4);
643
644                         if (nbytes < 4)
645                         {
646                                 if (mem_ap_write_buf_u16(swjdp, buffer,
647                                                 nbytes, address) != ERROR_OK)
648                                 {
649                                         LOG_WARNING("Block write error address "
650                                                 "0x%" PRIx32 ", count 0x%x",
651                                                 address, count);
652                                         return ERROR_JTAG_DEVICE_ERROR;
653                                 }
654
655                                 address += nbytes >> 1;
656                         }
657                         else
658                         {
659                                 uint32_t outvalue;
660                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
661
662                                 for (i = 0; i < nbytes; i++)
663                                 {
664                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
665                                         outvalue >>= 8;
666                                         address++;
667                                 }
668
669                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
670                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
671                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
672                                 {
673                                         LOG_WARNING("Block write error address "
674                                                 "0x%" PRIx32 ", count 0x%x",
675                                                 address, count);
676                                         return ERROR_JTAG_DEVICE_ERROR;
677                                 }
678                         }
679
680                         buffer += nbytes >> 1;
681                         writecount -= nbytes >> 1;
682
683                 } while (writecount);
684                 wcount -= blocksize;
685         }
686
687         return retval;
688 }
689
690 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
691 {
692         int retval = ERROR_OK;
693
694         if (count >= 4)
695                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
696
697         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
698
699         while (count > 0)
700         {
701                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
702                 uint16_t svalue;
703                 memcpy(&svalue, buffer, sizeof(uint16_t));
704                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
705                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
706                 retval = jtagdp_transaction_endcheck(swjdp);
707                 count -= 2;
708                 address += 2;
709                 buffer += 2;
710         }
711
712         return retval;
713 }
714
715 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
716                 uint8_t *buffer, int count, uint32_t address)
717 {
718         int retval = ERROR_OK;
719         int wcount, blocksize, writecount, i;
720
721         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
722
723         wcount = count;
724
725         while (wcount > 0)
726         {
727                 int nbytes;
728
729                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
730                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
731
732                 if (wcount < blocksize)
733                         blocksize = wcount;
734
735                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
736                 writecount = blocksize;
737
738                 do
739                 {
740                         nbytes = MIN(writecount, 4);
741
742                         if (nbytes < 4)
743                         {
744                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
745                                 {
746                                         LOG_WARNING("Block write error address "
747                                                 "0x%" PRIx32 ", count 0x%x",
748                                                 address, count);
749                                         return ERROR_JTAG_DEVICE_ERROR;
750                                 }
751
752                                 address += nbytes;
753                         }
754                         else
755                         {
756                                 uint32_t outvalue;
757                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
758
759                                 for (i = 0; i < nbytes; i++)
760                                 {
761                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
762                                         outvalue >>= 8;
763                                         address++;
764                                 }
765
766                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
767                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
768                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
769                                 {
770                                         LOG_WARNING("Block write error address "
771                                                 "0x%" PRIx32 ", count 0x%x",
772                                                 address, count);
773                                         return ERROR_JTAG_DEVICE_ERROR;
774                                 }
775                         }
776
777                         buffer += nbytes;
778                         writecount -= nbytes;
779
780                 } while (writecount);
781                 wcount -= blocksize;
782         }
783
784         return retval;
785 }
786
787 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
788 {
789         int retval = ERROR_OK;
790
791         if (count >= 4)
792                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
793
794         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
795
796         while (count > 0)
797         {
798                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
799                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
800                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
801                 retval = jtagdp_transaction_endcheck(swjdp);
802                 count--;
803                 address++;
804                 buffer++;
805         }
806
807         return retval;
808 }
809
810 /*********************************************************************************
811 *                                                                                *
812 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
813 *                                                                                *
814 * Read block fast in target order (little endian) into a buffer                  *
815 *                                                                                *
816 **********************************************************************************/
817 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
818 {
819         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
820         uint32_t adr = address;
821         uint8_t* pBuffer = buffer;
822
823         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
824
825         count >>= 2;
826         wcount = count;
827
828         while (wcount > 0)
829         {
830                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
831                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
832                 if (wcount < blocksize)
833                         blocksize = wcount;
834
835                 /* handle unaligned data at 4k boundary */
836                 if (blocksize == 0)
837                         blocksize = 1;
838
839                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
840
841                 /* Scan out first read */
842                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
843                                 DPAP_READ, 0, NULL, NULL);
844                 for (readcount = 0; readcount < blocksize - 1; readcount++)
845                 {
846                         /* Scan out next read; scan in posted value for the
847                          * previous one.  Assumes read is acked "OK/FAULT",
848                          * and CTRL_STAT says that meant "OK".
849                          */
850                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
851                                         DPAP_READ, 0, buffer + 4 * readcount,
852                                         &swjdp->ack);
853                 }
854
855                 /* Scan in last posted value; RDBUFF has no other effect,
856                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
857                  */
858                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
859                                 DPAP_READ, 0, buffer + 4 * readcount,
860                                 &swjdp->ack);
861                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
862                 {
863                         wcount = wcount - blocksize;
864                         address += 4 * blocksize;
865                         buffer += 4 * blocksize;
866                 }
867                 else
868                 {
869                         errorcount++;
870                 }
871
872                 if (errorcount > 1)
873                 {
874                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
875                         return ERROR_JTAG_DEVICE_ERROR;
876                 }
877         }
878
879         /* if we have an unaligned access - reorder data */
880         if (adr & 0x3u)
881         {
882                 for (readcount = 0; readcount < count; readcount++)
883                 {
884                         int i;
885                         uint32_t data;
886                         memcpy(&data, pBuffer, sizeof(uint32_t));
887
888                         for (i = 0; i < 4; i++)
889                         {
890                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
891                                 pBuffer++;
892                                 adr++;
893                         }
894                 }
895         }
896
897         return retval;
898 }
899
900 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
901                 uint8_t *buffer, int count, uint32_t address)
902 {
903         uint32_t invalue;
904         int retval = ERROR_OK;
905         int wcount, blocksize, readcount, i;
906
907         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
908
909         wcount = count >> 1;
910
911         while (wcount > 0)
912         {
913                 int nbytes;
914
915                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
916                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
917                 if (wcount < blocksize)
918                         blocksize = wcount;
919
920                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
921
922                 /* handle unaligned data at 4k boundary */
923                 if (blocksize == 0)
924                         blocksize = 1;
925                 readcount = blocksize;
926
927                 do
928                 {
929                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
930                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
931                         {
932                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
933                                 return ERROR_JTAG_DEVICE_ERROR;
934                         }
935
936                         nbytes = MIN((readcount << 1), 4);
937
938                         for (i = 0; i < nbytes; i++)
939                         {
940                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
941                                 buffer++;
942                                 address++;
943                         }
944
945                         readcount -= (nbytes >> 1);
946                 } while (readcount);
947                 wcount -= blocksize;
948         }
949
950         return retval;
951 }
952
953 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
954 {
955         uint32_t invalue, i;
956         int retval = ERROR_OK;
957
958         if (count >= 4)
959                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
960
961         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
962
963         while (count > 0)
964         {
965                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
966                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
967                 retval = jtagdp_transaction_endcheck(swjdp);
968                 if (address & 0x1)
969                 {
970                         for (i = 0; i < 2; i++)
971                         {
972                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
973                                 buffer++;
974                                 address++;
975                         }
976                 }
977                 else
978                 {
979                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
980                         memcpy(buffer, &svalue, sizeof(uint16_t));
981                         address += 2;
982                         buffer += 2;
983                 }
984                 count -= 2;
985         }
986
987         return retval;
988 }
989
990 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
991  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
992  *
993  * The solution is to arrange for a large out/in scan in this loop and
994  * and convert data afterwards.
995  */
996 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
997                 uint8_t *buffer, int count, uint32_t address)
998 {
999         uint32_t invalue;
1000         int retval = ERROR_OK;
1001         int wcount, blocksize, readcount, i;
1002
1003         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1004
1005         wcount = count;
1006
1007         while (wcount > 0)
1008         {
1009                 int nbytes;
1010
1011                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1012                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1013
1014                 if (wcount < blocksize)
1015                         blocksize = wcount;
1016
1017                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1018                 readcount = blocksize;
1019
1020                 do
1021                 {
1022                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1023                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1024                         {
1025                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1026                                 return ERROR_JTAG_DEVICE_ERROR;
1027                         }
1028
1029                         nbytes = MIN(readcount, 4);
1030
1031                         for (i = 0; i < nbytes; i++)
1032                         {
1033                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1034                                 buffer++;
1035                                 address++;
1036                         }
1037
1038                         readcount -= nbytes;
1039                 } while (readcount);
1040                 wcount -= blocksize;
1041         }
1042
1043         return retval;
1044 }
1045
1046 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1047 {
1048         uint32_t invalue;
1049         int retval = ERROR_OK;
1050
1051         if (count >= 4)
1052                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1053
1054         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1055
1056         while (count > 0)
1057         {
1058                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1059                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1060                 retval = jtagdp_transaction_endcheck(swjdp);
1061                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1062                 count--;
1063                 address++;
1064                 buffer++;
1065         }
1066
1067         return retval;
1068 }
1069
1070 /**
1071  * Initialize a DAP.
1072  *
1073  * @todo Rename this.  We also need an initialization scheme which account
1074  * for SWD transports not just JTAG; that will need to address differences
1075  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1076  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1077  */
1078 int ahbap_debugport_init(struct swjdp_common *swjdp)
1079 {
1080         uint32_t idreg, romaddr, dummy;
1081         uint32_t ctrlstat;
1082         int cnt = 0;
1083         int retval;
1084
1085         LOG_DEBUG(" ");
1086
1087         /* Default MEM-AP setup.
1088          *
1089          * REVISIT AP #0 may be an inappropriate default for this.
1090          * Should we probe, or receve a hint from the caller?
1091          * Presumably we can ignore the possibility of multiple APs.
1092          */
1093         swjdp->apsel = 0;
1094         swjdp->ap_csw_value = -1;
1095         swjdp->ap_tar_value = -1;
1096
1097         /* DP initialization */
1098         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1099         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1100         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1101         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1102
1103         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1104
1105         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1106         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1107         if ((retval = jtag_execute_queue()) != ERROR_OK)
1108                 return retval;
1109
1110         /* Check that we have debug power domains activated */
1111         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1112         {
1113                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1114                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1115                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1116                         return retval;
1117                 alive_sleep(10);
1118         }
1119
1120         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1121         {
1122                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1123                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1124                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1125                         return retval;
1126                 alive_sleep(10);
1127         }
1128
1129         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1130         /* With debug power on we can activate OVERRUN checking */
1131         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1132         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1133         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1134
1135         /*
1136          * REVISIT this isn't actually *initializing* anything in an AP,
1137          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1138          * Should it?  If the ROM address is valid, is this the right
1139          * place to scan the table and do any topology detection?
1140          */
1141         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1142         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1143
1144         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1145                 ", Debug ROM Address 0x%" PRIx32,
1146                 swjdp->apsel, idreg, romaddr);
1147
1148         return ERROR_OK;
1149 }
1150
1151 /* CID interpretation -- see ARM IHI 0029B section 3
1152  * and ARM IHI 0031A table 13-3.
1153  */
1154 static const char *class_description[16] ={
1155         "Reserved", "ROM table", "Reserved", "Reserved",
1156         "Reserved", "Reserved", "Reserved", "Reserved",
1157         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1158         "Reserved", "OptimoDE DESS",
1159                 "Generic IP component", "PrimeCell or System component"
1160 };
1161
1162 static bool
1163 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1164 {
1165         return cid3 == 0xb1 && cid2 == 0x05
1166                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1167 }
1168
1169 int dap_info_command(struct command_context *cmd_ctx,
1170                 struct swjdp_common *swjdp, int apsel)
1171 {
1172
1173         uint32_t dbgbase, apid;
1174         int romtable_present = 0;
1175         uint8_t mem_ap;
1176         uint32_t apselold;
1177
1178         /* AP address is in bits 31:24 of DP_SELECT */
1179         if (apsel >= 256)
1180                 return ERROR_INVALID_ARGUMENTS;
1181
1182         apselold = swjdp->apsel;
1183         dap_ap_select(swjdp, apsel);
1184         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1185         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1186         jtagdp_transaction_endcheck(swjdp);
1187         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1188         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1189         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1190         if (apid)
1191         {
1192                 switch (apid&0x0F)
1193                 {
1194                         case 0:
1195                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1196                                 break;
1197                         case 1:
1198                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1199                                 break;
1200                         case 2:
1201                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1202                                 break;
1203                         default:
1204                                 command_print(cmd_ctx, "\tUnknown AP type");
1205                                 break;
1206                 }
1207
1208                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1209                  * not a ROM table ... or have no such components at all.
1210                  */
1211                 if (mem_ap)
1212                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1213                                         dbgbase);
1214         }
1215         else
1216         {
1217                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1218         }
1219
1220         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1221         if (romtable_present)
1222         {
1223                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1224                 uint16_t entry_offset;
1225
1226                 /* bit 16 of apid indicates a memory access port */
1227                 if (dbgbase & 0x02)
1228                         command_print(cmd_ctx, "\tValid ROM table present");
1229                 else
1230                         command_print(cmd_ctx, "\tROM table in legacy format");
1231
1232                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1233                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1234                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1235                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1236                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1237                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1238                 jtagdp_transaction_endcheck(swjdp);
1239                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1240                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1241                                         ", CID2 0x%2.2" PRIx32
1242                                         ", CID1 0x%2.2" PRIx32
1243                                         ", CID0 0x%2.2" PRIx32,
1244                                         cid3, cid2, cid1, cid0);
1245                 if (memtype & 0x01)
1246                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1247                 else
1248                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1249                                         "Dedicated debug bus.");
1250
1251                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1252                 entry_offset = 0;
1253                 do
1254                 {
1255                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1256                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1257                         if (romentry&0x01)
1258                         {
1259                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1260                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1261                                 uint32_t component_start, component_base;
1262                                 unsigned part_num;
1263                                 char *type, *full;
1264
1265                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1266                                                 + (int)(romentry & 0xFFFFF000));
1267                                 mem_ap_read_atomic_u32(swjdp,
1268                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1269                                 mem_ap_read_atomic_u32(swjdp,
1270                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1271                                 mem_ap_read_atomic_u32(swjdp,
1272                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1273                                 mem_ap_read_atomic_u32(swjdp,
1274                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1275                                 mem_ap_read_atomic_u32(swjdp,
1276                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1277                                 mem_ap_read_atomic_u32(swjdp,
1278                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1279                                 mem_ap_read_atomic_u32(swjdp,
1280                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1281                                 mem_ap_read_atomic_u32(swjdp,
1282                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1283                                 mem_ap_read_atomic_u32(swjdp,
1284                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1285                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1286
1287                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1288                                                 ", start address 0x%" PRIx32,
1289                                                 component_base, component_start);
1290                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1291                                                 (int) (c_cid1 >> 4) & 0xf,
1292                                                 /* See ARM IHI 0029B Table 3-3 */
1293                                                 class_description[(c_cid1 >> 4) & 0xf]);
1294
1295                                 /* CoreSight component? */
1296                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1297                                         uint32_t devtype;
1298                                         unsigned minor;
1299                                         char *major = "Reserved", *subtype = "Reserved";
1300
1301                                         mem_ap_read_atomic_u32(swjdp,
1302                                                         (component_base & 0xfffff000) | 0xfcc,
1303                                                         &devtype);
1304                                         minor = (devtype >> 4) & 0x0f;
1305                                         switch (devtype & 0x0f) {
1306                                         case 0:
1307                                                 major = "Miscellaneous";
1308                                                 switch (minor) {
1309                                                 case 0:
1310                                                         subtype = "other";
1311                                                         break;
1312                                                 case 4:
1313                                                         subtype = "Validation component";
1314                                                         break;
1315                                                 }
1316                                                 break;
1317                                         case 1:
1318                                                 major = "Trace Sink";
1319                                                 switch (minor) {
1320                                                 case 0:
1321                                                         subtype = "other";
1322                                                         break;
1323                                                 case 1:
1324                                                         subtype = "Port";
1325                                                         break;
1326                                                 case 2:
1327                                                         subtype = "Buffer";
1328                                                         break;
1329                                                 }
1330                                                 break;
1331                                         case 2:
1332                                                 major = "Trace Link";
1333                                                 switch (minor) {
1334                                                 case 0:
1335                                                         subtype = "other";
1336                                                         break;
1337                                                 case 1:
1338                                                         subtype = "Funnel, router";
1339                                                         break;
1340                                                 case 2:
1341                                                         subtype = "Filter";
1342                                                         break;
1343                                                 case 3:
1344                                                         subtype = "FIFO, buffer";
1345                                                         break;
1346                                                 }
1347                                                 break;
1348                                         case 3:
1349                                                 major = "Trace Source";
1350                                                 switch (minor) {
1351                                                 case 0:
1352                                                         subtype = "other";
1353                                                         break;
1354                                                 case 1:
1355                                                         subtype = "Processor";
1356                                                         break;
1357                                                 case 2:
1358                                                         subtype = "DSP";
1359                                                         break;
1360                                                 case 3:
1361                                                         subtype = "Engine/Coprocessor";
1362                                                         break;
1363                                                 case 4:
1364                                                         subtype = "Bus";
1365                                                         break;
1366                                                 }
1367                                                 break;
1368                                         case 4:
1369                                                 major = "Debug Control";
1370                                                 switch (minor) {
1371                                                 case 0:
1372                                                         subtype = "other";
1373                                                         break;
1374                                                 case 1:
1375                                                         subtype = "Trigger Matrix";
1376                                                         break;
1377                                                 case 2:
1378                                                         subtype = "Debug Auth";
1379                                                         break;
1380                                                 }
1381                                                 break;
1382                                         case 5:
1383                                                 major = "Debug Logic";
1384                                                 switch (minor) {
1385                                                 case 0:
1386                                                         subtype = "other";
1387                                                         break;
1388                                                 case 1:
1389                                                         subtype = "Processor";
1390                                                         break;
1391                                                 case 2:
1392                                                         subtype = "DSP";
1393                                                         break;
1394                                                 case 3:
1395                                                         subtype = "Engine/Coprocessor";
1396                                                         break;
1397                                                 }
1398                                                 break;
1399                                         }
1400                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1401                                                         (unsigned) (devtype & 0xff),
1402                                                         major, subtype);
1403                                         /* REVISIT also show 0xfc8 DevId */
1404                                 }
1405
1406                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1407                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1408                                                         ", CID2 0x%2.2" PRIx32
1409                                                         ", CID1 0x%2.2" PRIx32
1410                                                         ", CID0 0x%2.2" PRIx32,
1411                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1412                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1413                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1414                                                 (int) c_pid4,
1415                                                 (int) c_pid3, (int) c_pid2,
1416                                                 (int) c_pid1, (int) c_pid0);
1417
1418                                 /* Part number interpretations are from Cortex
1419                                  * core specs, the CoreSight components TRM
1420                                  * (ARM DDI 0314H), and ETM specs; also from
1421                                  * chip observation (e.g. TI SDTI).
1422                                  */
1423                                 part_num = c_pid0 & 0xff;
1424                                 part_num |= (c_pid1 & 0x0f) << 8;
1425                                 switch (part_num) {
1426                                 case 0x000:
1427                                         type = "Cortex-M3 NVIC";
1428                                         full = "(Interrupt Controller)";
1429                                         break;
1430                                 case 0x001:
1431                                         type = "Cortex-M3 ITM";
1432                                         full = "(Instrumentation Trace Module)";
1433                                         break;
1434                                 case 0x002:
1435                                         type = "Cortex-M3 DWT";
1436                                         full = "(Data Watchpoint and Trace)";
1437                                         break;
1438                                 case 0x003:
1439                                         type = "Cortex-M3 FBP";
1440                                         full = "(Flash Patch and Breakpoint)";
1441                                         break;
1442                                 case 0x00d:
1443                                         type = "CoreSight ETM11";
1444                                         full = "(Embedded Trace)";
1445                                         break;
1446                                 // case 0x113: what?
1447                                 case 0x120:             /* from OMAP3 memmap */
1448                                         type = "TI SDTI";
1449                                         full = "(System Debug Trace Interface)";
1450                                         break;
1451                                 case 0x343:             /* from OMAP3 memmap */
1452                                         type = "TI DAPCTL";
1453                                         full = "";
1454                                         break;
1455                                 case 0x4e0:
1456                                         type = "Cortex-M3 ETM";
1457                                         full = "(Embedded Trace)";
1458                                         break;
1459                                 case 0x906:
1460                                         type = "Coresight CTI";
1461                                         full = "(Cross Trigger)";
1462                                         break;
1463                                 case 0x907:
1464                                         type = "Coresight ETB";
1465                                         full = "(Trace Buffer)";
1466                                         break;
1467                                 case 0x908:
1468                                         type = "Coresight CSTF";
1469                                         full = "(Trace Funnel)";
1470                                         break;
1471                                 case 0x910:
1472                                         type = "CoreSight ETM9";
1473                                         full = "(Embedded Trace)";
1474                                         break;
1475                                 case 0x912:
1476                                         type = "Coresight TPIU";
1477                                         full = "(Trace Port Interface Unit)";
1478                                         break;
1479                                 case 0x921:
1480                                         type = "Cortex-A8 ETM";
1481                                         full = "(Embedded Trace)";
1482                                         break;
1483                                 case 0x922:
1484                                         type = "Cortex-A8 CTI";
1485                                         full = "(Cross Trigger)";
1486                                         break;
1487                                 case 0x923:
1488                                         type = "Cortex-M3 TPIU";
1489                                         full = "(Trace Port Interface Unit)";
1490                                         break;
1491                                 case 0xc08:
1492                                         type = "Cortex-A8 Debug";
1493                                         full = "(Debug Unit)";
1494                                         break;
1495                                 default:
1496                                         type = "-*- unrecognized -*-";
1497                                         full = "";
1498                                         break;
1499                                 }
1500                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1501                                                 type, full);
1502                         }
1503                         else
1504                         {
1505                                 if (romentry)
1506                                         command_print(cmd_ctx, "\t\tComponent not present");
1507                                 else
1508                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1509                         }
1510                         entry_offset += 4;
1511                 } while (romentry > 0);
1512         }
1513         else
1514         {
1515                 command_print(cmd_ctx, "\tNo ROM table present");
1516         }
1517         dap_ap_select(swjdp, apselold);
1518
1519         return ERROR_OK;
1520 }
1521
1522 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1523 {
1524         uint32_t apsel, apselsave, baseaddr;
1525         int retval;
1526
1527         apselsave = swjdp->apsel;
1528         switch (CMD_ARGC) {
1529         case 0:
1530                 apsel = swjdp->apsel;
1531                 break;
1532         case 1:
1533                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1534                 /* AP address is in bits 31:24 of DP_SELECT */
1535                 if (apsel >= 256)
1536                         return ERROR_INVALID_ARGUMENTS;
1537                 break;
1538         default:
1539                 return ERROR_COMMAND_SYNTAX_ERROR;
1540         }
1541
1542         if (apselsave != apsel)
1543                 dap_ap_select(swjdp, apsel);
1544
1545         /* NOTE:  assumes we're talking to a MEM-AP, which
1546          * has a base address.  There are other kinds of AP,
1547          * though they're not common for now.  This should
1548          * use the ID register to verify it's a MEM-AP.
1549          */
1550         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1551         retval = jtagdp_transaction_endcheck(swjdp);
1552         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1553
1554         if (apselsave != apsel)
1555                 dap_ap_select(swjdp, apselsave);
1556
1557         return retval;
1558 }
1559
1560 DAP_COMMAND_HANDLER(dap_memaccess_command)
1561 {
1562         uint32_t memaccess_tck;
1563
1564         switch (CMD_ARGC) {
1565         case 0:
1566                 memaccess_tck = swjdp->memaccess_tck;
1567                 break;
1568         case 1:
1569                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1570                 break;
1571         default:
1572                 return ERROR_COMMAND_SYNTAX_ERROR;
1573         }
1574         swjdp->memaccess_tck = memaccess_tck;
1575
1576         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1577                         swjdp->memaccess_tck);
1578
1579         return ERROR_OK;
1580 }
1581
1582 DAP_COMMAND_HANDLER(dap_apsel_command)
1583 {
1584         uint32_t apsel, apid;
1585         int retval;
1586
1587         switch (CMD_ARGC) {
1588         case 0:
1589                 apsel = 0;
1590                 break;
1591         case 1:
1592                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1593                 /* AP address is in bits 31:24 of DP_SELECT */
1594                 if (apsel >= 256)
1595                         return ERROR_INVALID_ARGUMENTS;
1596                 break;
1597         default:
1598                 return ERROR_COMMAND_SYNTAX_ERROR;
1599         }
1600
1601         dap_ap_select(swjdp, apsel);
1602         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1603         retval = jtagdp_transaction_endcheck(swjdp);
1604         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1605                         apsel, apid);
1606
1607         return retval;
1608 }
1609
1610 DAP_COMMAND_HANDLER(dap_apid_command)
1611 {
1612         uint32_t apsel, apselsave, apid;
1613         int retval;
1614
1615         apselsave = swjdp->apsel;
1616         switch (CMD_ARGC) {
1617         case 0:
1618                 apsel = swjdp->apsel;
1619                 break;
1620         case 1:
1621                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1622                 /* AP address is in bits 31:24 of DP_SELECT */
1623                 if (apsel >= 256)
1624                         return ERROR_INVALID_ARGUMENTS;
1625                 break;
1626         default:
1627                 return ERROR_COMMAND_SYNTAX_ERROR;
1628         }
1629
1630         if (apselsave != apsel)
1631                 dap_ap_select(swjdp, apsel);
1632
1633         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1634         retval = jtagdp_transaction_endcheck(swjdp);
1635         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1636         if (apselsave != apsel)
1637                 dap_ap_select(swjdp, apselsave);
1638
1639         return retval;
1640 }