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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm_adi_v5.h"
  73 #include <helper/time_support.h>
  74
  75
  76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  77
  78 /*
  79         uint32_t tar_block_size(uint32_t address)
  80         Return the largest block starting at address that does not cross a tar block size alignment boundary
  81 */
  82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  83 {
  84         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  85 }
  86
  87 /***************************************************************************
  88  *                                                                         *
  89  * DPACC and APACC scanchain access through JTAG-DP                        *
  90  *                                                                         *
  91 ***************************************************************************/
  92
  93 /**
  94  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  95  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  96  * discusses operations which access these registers.
  97  *
  98  * Note that only one scan is performed.  If RnW is set, a separate scan
  99  * will be needed to collect the data which was read; the "invalue" collects
 100  * the posted result of a preceding operation, not the current one.
 101  *
 102  * @param swjdp the DAP
 103  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 104  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 105  *      SELECT register has more addressing bits.
 106  * @param RnW false iff outvalue will be written to the DP or AP
 107  * @param outvalue points to a 32-bit (little-endian) integer
 108  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 109  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 110  */
 111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 112                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 113                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 114 {
 115         struct arm_jtag *jtag_info = swjdp->jtag_info;
 116         struct scan_field fields[2];
 117         uint8_t out_addr_buf;
 118
 119         jtag_set_end_state(TAP_IDLE);
 120         arm_jtag_set_instr(jtag_info, instr, NULL);
 121
 122         /* Scan out a read or write operation using some DP or AP register.
 123          * For APACC access with any sticky error flag set, this is discarded.
 124          */
 125         fields[0].tap = jtag_info->tap;
 126         fields[0].num_bits = 3;
 127         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 128         fields[0].out_value = &out_addr_buf;
 129         fields[0].in_value = ack;
 130
 131         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 132          * complete; data we write is discarded, data we read is unpredictable.
 133          * When overrun detect is active, STICKYORUN is set.
 134          */
 135
 136         fields[1].tap = jtag_info->tap;
 137         fields[1].num_bits = 32;
 138         fields[1].out_value = outvalue;
 139         fields[1].in_value = invalue;
 140
 141         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 142
 143         /* Add specified number of tck clocks after starting memory bus
 144          * access, giving the hardware time to complete the access.
 145          * They provide more time for the (MEM) AP to complete the read ...
 146          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 147          */
 148         if ((instr == JTAG_DP_APACC)
 149                         && ((reg_addr == AP_REG_DRW)
 150                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 151                         && (swjdp->memaccess_tck != 0))
 152                 jtag_add_runtest(swjdp->memaccess_tck,
 153                                 jtag_set_end_state(TAP_IDLE));
 154
 155         return jtag_get_error();
 156 }
 157
 158 /**
 159  * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
 160  * This is exactly like adi_jtag_dp_scan(), except that endianness
 161  * conversions are performed (so the types of invalue and outvalue
 162  * must be different).
 163  */
 164 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 165                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 166                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 167 {
 168         uint8_t out_value_buf[4];
 169         int retval;
 170
 171         buf_set_u32(out_value_buf, 0, 32, outvalue);
 172
 173         retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
 174                         out_value_buf, (uint8_t *)invalue, ack);
 175         if (retval != ERROR_OK)
 176                 return retval;
 177
 178         if (invalue)
 179                 jtag_add_callback(arm_le_to_h_u32,
 180                                 (jtag_callback_data_t) invalue);
 181
 182         return retval;
 183 }
 184
 185 /**
 186  * Utility to write AP registers.
 187  */
 188 static inline int adi_jtag_ap_write_check(struct swjdp_common *dap,
 189                 uint8_t reg_addr, uint8_t *outvalue)
 190 {
 191         return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
 192                         outvalue, NULL, NULL);
 193 }
 194
 195 static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
 196                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 197                 uint32_t outvalue, uint32_t *invalue)
 198 {
 199         int retval;
 200
 201         /* Issue the read or write */
 202         retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
 203                         RnW, outvalue, NULL, NULL);
 204         if (retval != ERROR_OK)
 205                 return retval;
 206
 207         /* For reads,  collect posted value; RDBUFF has no other effect.
 208          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 209          */
 210         if ((RnW == DPAP_READ) && (invalue != NULL))
 211                 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 212                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 213         return retval;
 214 }
 215
 216 static int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 217 {
 218         int retval;
 219         uint32_t ctrlstat;
 220
 221         /* too expensive to call keep_alive() here */
 222
 223 #if 0
 224         /* Danger!!!! BROKEN!!!! */
 225         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 226                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 227         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 228         R956 introduced the check on return value here and now Michael Schwingen reports
 229         that this code no longer works....
 230
 231         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 232         */
 233         if ((retval = jtag_execute_queue()) != ERROR_OK)
 234         {
 235                 LOG_ERROR("BUG: Why does this fail the first time????");
 236         }
 237         /* Why??? second time it works??? */
 238 #endif
 239
 240         /* Post CTRL/STAT read; discard any previous posted read value
 241          * but collect its ACK status.
 242          */
 243         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 244                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 245         if ((retval = jtag_execute_queue()) != ERROR_OK)
 246                 return retval;
 247
 248         swjdp->ack = swjdp->ack & 0x7;
 249
 250         /* common code path avoids calling timeval_ms() */
 251         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 252         {
 253                 long long then = timeval_ms();
 254
 255                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 256                 {
 257                         if (swjdp->ack == JTAG_ACK_WAIT)
 258                         {
 259                                 if ((timeval_ms()-then) > 1000)
 260                                 {
 261                                         /* NOTE:  this would be a good spot
 262                                          * to use JTAG_DP_ABORT.
 263                                          */
 264                                         LOG_WARNING("Timeout (1000ms) waiting "
 265                                                 "for ACK=OK/FAULT "
 266                                                 "in JTAG-DP transaction");
 267                                         return ERROR_JTAG_DEVICE_ERROR;
 268                                 }
 269                         }
 270                         else
 271                         {
 272                                 LOG_WARNING("Invalid ACK %#x "
 273                                                 "in JTAG-DP transaction",
 274                                                 swjdp->ack);
 275                                 return ERROR_JTAG_DEVICE_ERROR;
 276                         }
 277
 278                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 279                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 280                         if ((retval = dap_run(swjdp)) != ERROR_OK)
 281                                 return retval;
 282                         swjdp->ack = swjdp->ack & 0x7;
 283                 }
 284         }
 285
 286         /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 287
 288         /* Check for STICKYERR and STICKYORUN */
 289         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 290         {
 291                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 292                 /* Check power to debug regions */
 293                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 294                          ahbap_debugport_init(swjdp);
 295                 else
 296                 {
 297                         uint32_t mem_ap_csw, mem_ap_tar;
 298
 299                         /* Maybe print information about last intended
 300                          * MEM-AP access; but not if autoincrementing.
 301                          * *Real* CSW and TAR values are always shown.
 302                          */
 303                         if (swjdp->ap_tar_value != (uint32_t) -1)
 304                                 LOG_DEBUG("MEM-AP Cached values: "
 305                                         "ap_bank 0x%" PRIx32
 306                                         ", ap_csw 0x%" PRIx32
 307                                         ", ap_tar 0x%" PRIx32,
 308                                         swjdp->ap_bank_value,
 309                                         swjdp->ap_csw_value,
 310                                         swjdp->ap_tar_value);
 311
 312                         if (ctrlstat & SSTICKYORUN)
 313                                 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 314                                         "memaccess, or reduce jtag speed");
 315
 316                         if (ctrlstat & SSTICKYERR)
 317                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 318
 319                         /* Clear Sticky Error Bits */
 320                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 321                                         DP_CTRL_STAT, DPAP_WRITE,
 322                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 323                                                 | SSTICKYERR, NULL);
 324                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 325                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 326                         if ((retval = dap_run(swjdp)) != ERROR_OK)
 327                                 return retval;
 328
 329                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 330
 331                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 332                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 333                         if ((retval = dap_run(swjdp)) != ERROR_OK)
 334                                 return retval;
 335                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 336                                         PRIx32, mem_ap_csw, mem_ap_tar);
 337
 338                 }
 339                 if ((retval = dap_run(swjdp)) != ERROR_OK)
 340                         return retval;
 341                 return ERROR_JTAG_DEVICE_ERROR;
 342         }
 343
 344         return ERROR_OK;
 345 }
 346
 347 /***************************************************************************
 348  *                                                                         *
 349  * DP and MEM-AP  register access  through APACC and DPACC                 *
 350  *                                                                         *
 351 ***************************************************************************/
 352
 353 /**
 354  * Select one of the APs connected to the specified DAP.  The
 355  * selection is implicitly used with future AP transactions.
 356  * This is a NOP if the specified AP is already selected.
 357  *
 358  * @param swjdp The DAP
 359  * @param apsel Number of the AP to (implicitly) use with further
 360  *      transactions.  This normally identifies a MEM-AP.
 361  */
 362 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 363 {
 364         uint32_t select = (apsel << 24) & 0xFF000000;
 365
 366         if (select != swjdp->apsel)
 367         {
 368                 swjdp->apsel = select;
 369                 /* Switching AP invalidates cached values.
 370                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 371                  */
 372                 swjdp->ap_bank_value = -1;
 373                 swjdp->ap_csw_value = -1;
 374                 swjdp->ap_tar_value = -1;
 375         }
 376 }
 377
 378 /** Select the AP register bank matching bits 7:4 of ap_reg. */
 379 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 380 {
 381         uint32_t select = (ap_reg & 0x000000F0);
 382
 383         if (select != swjdp->ap_bank_value)
 384         {
 385                 swjdp->ap_bank_value = select;
 386                 select |= swjdp->apsel;
 387                 return dap_queue_dp_write(swjdp, DP_SELECT, select);
 388         } else
 389                 return ERROR_OK;
 390 }
 391
 392 /* FIXME remove dap_ap_{read,write}_reg() and dap_ap_write_reg_u32()
 393  * ... these should become the bodies of the JTAG implementations of
 394  * dap_queue_ap_{read,write}(), then all their current callers should
 395  * switch over to the transport-neutral calls.
 396  */
 397
 398 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 399                 uint32_t reg_addr, uint8_t *out_value_buf)
 400 {
 401         int retval;
 402
 403         retval = dap_ap_bankselect(swjdp, reg_addr);
 404         if (retval != ERROR_OK)
 405                 return retval;
 406
 407         return adi_jtag_ap_write_check(swjdp, reg_addr, out_value_buf);
 408 }
 409
 410 /**
 411  * Asynchronous (queued) AP register write.
 412  *
 413  * @param swjdp The DAP whose currently selected AP will be written.
 414  * @param reg_addr Eight bit AP register address.
 415  * @param value Word to be written at reg_addr
 416  *
 417  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 418  */
 419 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 420                 uint32_t reg_addr, uint32_t value)
 421 {
 422         uint8_t out_value_buf[4];
 423
 424         buf_set_u32(out_value_buf, 0, 32, value);
 425         return dap_ap_write_reg(swjdp,
 426                         reg_addr, out_value_buf);
 427 }
 428
 429 /**
 430  * Asynchronous (queued) AP register eread.
 431  *
 432  * @param swjdp The DAP whose currently selected AP will be read.
 433  * @param reg_addr Eight bit AP register address.
 434  * @param value Points to where the 32-bit (little-endian) word will be stored.
 435  *
 436  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 437  */
 438 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 439                 uint32_t reg_addr, uint32_t *value)
 440 {
 441         int retval;
 442
 443         retval = dap_ap_bankselect(swjdp, reg_addr);
 444         if (retval != ERROR_OK)
 445                 return retval;
 446
 447         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 448                         DPAP_READ, 0, value);
 449 }
 450
 451 /**
 452  * Queue transactions setting up transfer parameters for the
 453  * currently selected MEM-AP.
 454  *
 455  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 456  * initiate data reads or writes using memory or peripheral addresses.
 457  * If the CSW is configured for it, the TAR may be automatically
 458  * incremented after each transfer.
 459  *
 460  * @todo Rename to reflect it being specifically a MEM-AP function.
 461  *
 462  * @param swjdp The DAP connected to the MEM-AP.
 463  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 464  *      matches the cached value, the register is not changed.
 465  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 466  *      matches the cached address, the register is not changed.
 467  *
 468  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 469  */
 470 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 471 {
 472         int retval;
 473
 474         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 475         if (csw != swjdp->ap_csw_value)
 476         {
 477                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 478                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 479                 if (retval != ERROR_OK)
 480                         return retval;
 481                 swjdp->ap_csw_value = csw;
 482         }
 483         if (tar != swjdp->ap_tar_value)
 484         {
 485                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 486                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 487                 if (retval != ERROR_OK)
 488                         return retval;
 489                 swjdp->ap_tar_value = tar;
 490         }
 491         /* Disable TAR cache when autoincrementing */
 492         if (csw & CSW_ADDRINC_MASK)
 493                 swjdp->ap_tar_value = -1;
 494         return ERROR_OK;
 495 }
 496
 497 /**
 498  * Asynchronous (queued) read of a word from memory or a system register.
 499  *
 500  * @param swjdp The DAP connected to the MEM-AP performing the read.
 501  * @param address Address of the 32-bit word to read; it must be
 502  *      readable by the currently selected MEM-AP.
 503  * @param value points to where the word will be stored when the
 504  *      transaction queue is flushed (assuming no errors).
 505  *
 506  * @return ERROR_OK for success.  Otherwise a fault code.
 507  */
 508 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
 509                 uint32_t *value)
 510 {
 511         int retval;
 512
 513         /* Use banked addressing (REG_BDx) to avoid some link traffic
 514          * (updating TAR) when reading several consecutive addresses.
 515          */
 516         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 517                         address & 0xFFFFFFF0);
 518         if (retval != ERROR_OK)
 519                 return retval;
 520
 521         return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 522 }
 523
 524 /**
 525  * Synchronous read of a word from memory or a system register.
 526  * As a side effect, this flushes any queued transactions.
 527  *
 528  * @param swjdp The DAP connected to the MEM-AP performing the read.
 529  * @param address Address of the 32-bit word to read; it must be
 530  *      readable by the currently selected MEM-AP.
 531  * @param value points to where the result will be stored.
 532  *
 533  * @return ERROR_OK for success; *value holds the result.
 534  * Otherwise a fault code.
 535  */
 536 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 537                 uint32_t *value)
 538 {
 539         int retval;
 540
 541         retval = mem_ap_read_u32(swjdp, address, value);
 542         if (retval != ERROR_OK)
 543                 return retval;
 544
 545         return dap_run(swjdp);
 546 }
 547
 548 /**
 549  * Asynchronous (queued) write of a word to memory or a system register.
 550  *
 551  * @param swjdp The DAP connected to the MEM-AP.
 552  * @param address Address to be written; it must be writable by
 553  *      the currently selected MEM-AP.
 554  * @param value Word that will be written to the address when transaction
 555  *      queue is flushed (assuming no errors).
 556  *
 557  * @return ERROR_OK for success.  Otherwise a fault code.
 558  */
 559 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
 560                 uint32_t value)
 561 {
 562         int retval;
 563
 564         /* Use banked addressing (REG_BDx) to avoid some link traffic
 565          * (updating TAR) when writing several consecutive addresses.
 566          */
 567         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 568                         address & 0xFFFFFFF0);
 569         if (retval != ERROR_OK)
 570                 return retval;
 571
 572         return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
 573                         value);
 574 }
 575
 576 /**
 577  * Synchronous write of a word to memory or a system register.
 578  * As a side effect, this flushes any queued transactions.
 579  *
 580  * @param swjdp The DAP connected to the MEM-AP.
 581  * @param address Address to be written; it must be writable by
 582  *      the currently selected MEM-AP.
 583  * @param value Word that will be written.
 584  *
 585  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 586  */
 587 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 588                 uint32_t value)
 589 {
 590         int retval = mem_ap_write_u32(swjdp, address, value);
 591
 592         if (retval != ERROR_OK)
 593                 return retval;
 594
 595         return dap_run(swjdp);
 596 }
 597
 598 /*****************************************************************************
 599 *                                                                            *
 600 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 601 *                                                                            *
 602 * Write a buffer in target order (little endian)                             *
 603 *                                                                            *
 604 *****************************************************************************/
 605 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 606 {
 607         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 608         uint32_t adr = address;
 609         uint8_t* pBuffer = buffer;
 610
 611         count >>= 2;
 612         wcount = count;
 613
 614         /* if we have an unaligned access - reorder data */
 615         if (adr & 0x3u)
 616         {
 617                 for (writecount = 0; writecount < count; writecount++)
 618                 {
 619                         int i;
 620                         uint32_t outvalue;
 621                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 622
 623                         for (i = 0; i < 4; i++)
 624                         {
 625                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 626                                 outvalue >>= 8;
 627                                 adr++;
 628                         }
 629                         pBuffer += sizeof(uint32_t);
 630                 }
 631         }
 632
 633         while (wcount > 0)
 634         {
 635                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 636                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 637                 if (wcount < blocksize)
 638                         blocksize = wcount;
 639
 640                 /* handle unaligned data at 4k boundary */
 641                 if (blocksize == 0)
 642                         blocksize = 1;
 643
 644                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 645
 646                 for (writecount = 0; writecount < blocksize; writecount++)
 647                 {
 648                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 649                 }
 650
 651                 if (dap_run(swjdp) == ERROR_OK)
 652                 {
 653                         wcount = wcount - blocksize;
 654                         address = address + 4 * blocksize;
 655                         buffer = buffer + 4 * blocksize;
 656                 }
 657                 else
 658                 {
 659                         errorcount++;
 660                 }
 661
 662                 if (errorcount > 1)
 663                 {
 664                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 665                         /* REVISIT return the *actual* fault code */
 666                         return ERROR_JTAG_DEVICE_ERROR;
 667                 }
 668         }
 669
 670         return retval;
 671 }
 672
 673 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 674                 uint8_t *buffer, int count, uint32_t address)
 675 {
 676         int retval = ERROR_OK;
 677         int wcount, blocksize, writecount, i;
 678
 679         wcount = count >> 1;
 680
 681         while (wcount > 0)
 682         {
 683                 int nbytes;
 684
 685                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 686                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 687
 688                 if (wcount < blocksize)
 689                         blocksize = wcount;
 690
 691                 /* handle unaligned data at 4k boundary */
 692                 if (blocksize == 0)
 693                         blocksize = 1;
 694
 695                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 696                 writecount = blocksize;
 697
 698                 do
 699                 {
 700                         nbytes = MIN((writecount << 1), 4);
 701
 702                         if (nbytes < 4)
 703                         {
 704                                 if (mem_ap_write_buf_u16(swjdp, buffer,
 705                                                 nbytes, address) != ERROR_OK)
 706                                 {
 707                                         LOG_WARNING("Block write error address "
 708                                                 "0x%" PRIx32 ", count 0x%x",
 709                                                 address, count);
 710                                         return ERROR_JTAG_DEVICE_ERROR;
 711                                 }
 712
 713                                 address += nbytes >> 1;
 714                         }
 715                         else
 716                         {
 717                                 uint32_t outvalue;
 718                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 719
 720                                 for (i = 0; i < nbytes; i++)
 721                                 {
 722                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 723                                         outvalue >>= 8;
 724                                         address++;
 725                                 }
 726
 727                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 728                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 729                                 if (dap_run(swjdp) != ERROR_OK)
 730                                 {
 731                                         LOG_WARNING("Block write error address "
 732                                                 "0x%" PRIx32 ", count 0x%x",
 733                                                 address, count);
 734                                         /* REVISIT return *actual* fault code */
 735                                         return ERROR_JTAG_DEVICE_ERROR;
 736                                 }
 737                         }
 738
 739                         buffer += nbytes >> 1;
 740                         writecount -= nbytes >> 1;
 741
 742                 } while (writecount);
 743                 wcount -= blocksize;
 744         }
 745
 746         return retval;
 747 }
 748
 749 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 750 {
 751         int retval = ERROR_OK;
 752
 753         if (count >= 4)
 754                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 755
 756         while (count > 0)
 757         {
 758                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 759                 uint16_t svalue;
 760                 memcpy(&svalue, buffer, sizeof(uint16_t));
 761                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 762                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 763                 retval = dap_run(swjdp);
 764                 if (retval != ERROR_OK)
 765                         break;
 766
 767                 count -= 2;
 768                 address += 2;
 769                 buffer += 2;
 770         }
 771
 772         return retval;
 773 }
 774
 775 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 776                 uint8_t *buffer, int count, uint32_t address)
 777 {
 778         int retval = ERROR_OK;
 779         int wcount, blocksize, writecount, i;
 780
 781         wcount = count;
 782
 783         while (wcount > 0)
 784         {
 785                 int nbytes;
 786
 787                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 788                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 789
 790                 if (wcount < blocksize)
 791                         blocksize = wcount;
 792
 793                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 794                 writecount = blocksize;
 795
 796                 do
 797                 {
 798                         nbytes = MIN(writecount, 4);
 799
 800                         if (nbytes < 4)
 801                         {
 802                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 803                                 {
 804                                         LOG_WARNING("Block write error address "
 805                                                 "0x%" PRIx32 ", count 0x%x",
 806                                                 address, count);
 807                                         return ERROR_JTAG_DEVICE_ERROR;
 808                                 }
 809
 810                                 address += nbytes;
 811                         }
 812                         else
 813                         {
 814                                 uint32_t outvalue;
 815                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 816
 817                                 for (i = 0; i < nbytes; i++)
 818                                 {
 819                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 820                                         outvalue >>= 8;
 821                                         address++;
 822                                 }
 823
 824                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 825                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 826                                 if (dap_run(swjdp) != ERROR_OK)
 827                                 {
 828                                         LOG_WARNING("Block write error address "
 829                                                 "0x%" PRIx32 ", count 0x%x",
 830                                                 address, count);
 831                                         /* REVISIT return *actual* fault code */
 832                                         return ERROR_JTAG_DEVICE_ERROR;
 833                                 }
 834                         }
 835
 836                         buffer += nbytes;
 837                         writecount -= nbytes;
 838
 839                 } while (writecount);
 840                 wcount -= blocksize;
 841         }
 842
 843         return retval;
 844 }
 845
 846 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 847 {
 848         int retval = ERROR_OK;
 849
 850         if (count >= 4)
 851                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 852
 853         while (count > 0)
 854         {
 855                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 856                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 857                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 858                 retval = dap_run(swjdp);
 859                 if (retval != ERROR_OK)
 860                         break;
 861
 862                 count--;
 863                 address++;
 864                 buffer++;
 865         }
 866
 867         return retval;
 868 }
 869
 870 /**
 871  * Synchronously read a block of 32-bit words into a buffer
 872  * @param swjdp The DAP connected to the MEM-AP.
 873  * @param buffer where the words will be stored (in host byte order).
 874  * @param count How many words to read.
 875  * @param address Memory address from which to read words; all the
 876  *      words must be readable by the currently selected MEM-AP.
 877  */
 878 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
 879                 int count, uint32_t address)
 880 {
 881         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 882         uint32_t adr = address;
 883         uint8_t* pBuffer = buffer;
 884
 885         count >>= 2;
 886         wcount = count;
 887
 888         while (wcount > 0)
 889         {
 890                 /* Adjust to read blocks within boundaries aligned to the
 891                  * TAR autoincrement size (at least 2^10).  Autoincrement
 892                  * mode avoids an extra per-word roundtrip to update TAR.
 893                  */
 894                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
 895                                 address);
 896                 if (wcount < blocksize)
 897                         blocksize = wcount;
 898
 899                 /* handle unaligned data at 4k boundary */
 900                 if (blocksize == 0)
 901                         blocksize = 1;
 902
 903                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
 904                                 address);
 905
 906                 /* Scan out first read */
 907                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 908                                 DPAP_READ, 0, NULL, NULL);
 909                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 910                 {
 911                         /* Scan out next read; scan in posted value for the
 912                          * previous one.  Assumes read is acked "OK/FAULT",
 913                          * and CTRL_STAT says that meant "OK".
 914                          */
 915                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 916                                         DPAP_READ, 0, buffer + 4 * readcount,
 917                                         &swjdp->ack);
 918                 }
 919
 920                 /* Scan in last posted value; RDBUFF has no other effect,
 921                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 922                  */
 923                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 924                                 DPAP_READ, 0, buffer + 4 * readcount,
 925                                 &swjdp->ack);
 926                 if (dap_run(swjdp) == ERROR_OK)
 927                 {
 928                         wcount = wcount - blocksize;
 929                         address += 4 * blocksize;
 930                         buffer += 4 * blocksize;
 931                 }
 932                 else
 933                 {
 934                         errorcount++;
 935                 }
 936
 937                 if (errorcount > 1)
 938                 {
 939                         LOG_WARNING("Block read error address 0x%" PRIx32
 940                                 ", count 0x%x", address, count);
 941                         /* REVISIT return the *actual* fault code */
 942                         return ERROR_JTAG_DEVICE_ERROR;
 943                 }
 944         }
 945
 946         /* if we have an unaligned access - reorder data */
 947         if (adr & 0x3u)
 948         {
 949                 for (readcount = 0; readcount < count; readcount++)
 950                 {
 951                         int i;
 952                         uint32_t data;
 953                         memcpy(&data, pBuffer, sizeof(uint32_t));
 954
 955                         for (i = 0; i < 4; i++)
 956                         {
 957                                 *((uint8_t*)pBuffer) =
 958                                                 (data >> 8 * (adr & 0x3));
 959                                 pBuffer++;
 960                                 adr++;
 961                         }
 962                 }
 963         }
 964
 965         return retval;
 966 }
 967
 968 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 969                 uint8_t *buffer, int count, uint32_t address)
 970 {
 971         uint32_t invalue;
 972         int retval = ERROR_OK;
 973         int wcount, blocksize, readcount, i;
 974
 975         wcount = count >> 1;
 976
 977         while (wcount > 0)
 978         {
 979                 int nbytes;
 980
 981                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 982                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 983                 if (wcount < blocksize)
 984                         blocksize = wcount;
 985
 986                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 987
 988                 /* handle unaligned data at 4k boundary */
 989                 if (blocksize == 0)
 990                         blocksize = 1;
 991                 readcount = blocksize;
 992
 993                 do
 994                 {
 995                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 996                         if (dap_run(swjdp) != ERROR_OK)
 997                         {
 998                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 999                                 /* REVISIT return the *actual* fault code */
1000                                 return ERROR_JTAG_DEVICE_ERROR;
1001                         }
1002
1003                         nbytes = MIN((readcount << 1), 4);
1004
1005                         for (i = 0; i < nbytes; i++)
1006                         {
1007                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1008                                 buffer++;
1009                                 address++;
1010                         }
1011
1012                         readcount -= (nbytes >> 1);
1013                 } while (readcount);
1014                 wcount -= blocksize;
1015         }
1016
1017         return retval;
1018 }
1019
1020 /**
1021  * Synchronously read a block of 16-bit halfwords into a buffer
1022  * @param swjdp The DAP connected to the MEM-AP.
1023  * @param buffer where the halfwords will be stored (in host byte order).
1024  * @param count How many halfwords to read.
1025  * @param address Memory address from which to read words; all the
1026  *      words must be readable by the currently selected MEM-AP.
1027  */
1028 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
1029                 int count, uint32_t address)
1030 {
1031         uint32_t invalue, i;
1032         int retval = ERROR_OK;
1033
1034         if (count >= 4)
1035                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1036
1037         while (count > 0)
1038         {
1039                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1040                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1041                 retval = dap_run(swjdp);
1042                 if (retval != ERROR_OK)
1043                         break;
1044
1045                 if (address & 0x1)
1046                 {
1047                         for (i = 0; i < 2; i++)
1048                         {
1049                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1050                                 buffer++;
1051                                 address++;
1052                         }
1053                 }
1054                 else
1055                 {
1056                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
1057                         memcpy(buffer, &svalue, sizeof(uint16_t));
1058                         address += 2;
1059                         buffer += 2;
1060                 }
1061                 count -= 2;
1062         }
1063
1064         return retval;
1065 }
1066
1067 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1068  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1069  *
1070  * The solution is to arrange for a large out/in scan in this loop and
1071  * and convert data afterwards.
1072  */
1073 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1074                 uint8_t *buffer, int count, uint32_t address)
1075 {
1076         uint32_t invalue;
1077         int retval = ERROR_OK;
1078         int wcount, blocksize, readcount, i;
1079
1080         wcount = count;
1081
1082         while (wcount > 0)
1083         {
1084                 int nbytes;
1085
1086                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1087                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1088
1089                 if (wcount < blocksize)
1090                         blocksize = wcount;
1091
1092                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1093                 readcount = blocksize;
1094
1095                 do
1096                 {
1097                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1098                         if (dap_run(swjdp) != ERROR_OK)
1099                         {
1100                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1101                                 /* REVISIT return the *actual* fault code */
1102                                 return ERROR_JTAG_DEVICE_ERROR;
1103                         }
1104
1105                         nbytes = MIN(readcount, 4);
1106
1107                         for (i = 0; i < nbytes; i++)
1108                         {
1109                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1110                                 buffer++;
1111                                 address++;
1112                         }
1113
1114                         readcount -= nbytes;
1115                 } while (readcount);
1116                 wcount -= blocksize;
1117         }
1118
1119         return retval;
1120 }
1121
1122 /**
1123  * Synchronously read a block of bytes into a buffer
1124  * @param swjdp The DAP connected to the MEM-AP.
1125  * @param buffer where the bytes will be stored.
1126  * @param count How many bytes to read.
1127  * @param address Memory address from which to read data; all the
1128  *      data must be readable by the currently selected MEM-AP.
1129  */
1130 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
1131                 int count, uint32_t address)
1132 {
1133         uint32_t invalue;
1134         int retval = ERROR_OK;
1135
1136         if (count >= 4)
1137                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1138
1139         while (count > 0)
1140         {
1141                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1142                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1143                 retval = dap_run(swjdp);
1144                 if (retval != ERROR_OK)
1145                         break;
1146
1147                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1148                 count--;
1149                 address++;
1150                 buffer++;
1151         }
1152
1153         return retval;
1154 }
1155
1156 /*--------------------------------------------------------------------------*/
1157
1158 static int jtag_idcode_q_read(struct swjdp_common *dap,
1159                 uint8_t *ack, uint32_t *data)
1160 {
1161         struct arm_jtag *jtag_info = dap->jtag_info;
1162         int retval;
1163         struct scan_field fields[1];
1164
1165         jtag_set_end_state(TAP_IDLE);
1166
1167         /* This is a standard JTAG operation -- no DAP tweakage */
1168         retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
1169         if (retval != ERROR_OK)
1170                 return retval;
1171
1172         fields[0].tap = jtag_info->tap;
1173         fields[0].num_bits = 32;
1174         fields[0].out_value = NULL;
1175         fields[0].in_value = (void *) data;
1176
1177         jtag_add_dr_scan(1, fields, jtag_get_end_state());
1178         retval = jtag_get_error();
1179         if (retval != ERROR_OK)
1180                 return retval;
1181
1182         jtag_add_callback(arm_le_to_h_u32,
1183                         (jtag_callback_data_t) data);
1184
1185         return retval;
1186 }
1187
1188 static int jtag_dp_q_read(struct swjdp_common *dap, unsigned reg,
1189                 uint32_t *data)
1190 {
1191         return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
1192                         reg, DPAP_READ, 0, data);
1193 }
1194
1195 static int jtag_dp_q_write(struct swjdp_common *dap, unsigned reg,
1196                 uint32_t data)
1197 {
1198         return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
1199                         reg, DPAP_WRITE, data, NULL);
1200 }
1201
1202 static int jtag_ap_q_bankselect(struct swjdp_common *dap, unsigned reg)
1203 {
1204         uint32_t select = reg & 0x000000F0;
1205
1206         if (select == dap->ap_bank_value)
1207                 return ERROR_OK;
1208         dap->ap_bank_value = select;
1209
1210         select |= dap->apsel;
1211
1212         return jtag_dp_q_write(dap, DP_SELECT, select);
1213 }
1214
1215 static int jtag_ap_q_read(struct swjdp_common *dap, unsigned reg,
1216                 uint32_t *data)
1217 {
1218         int retval = jtag_ap_q_bankselect(dap, reg);
1219
1220         if (retval != ERROR_OK)
1221                 return retval;
1222         return dap_ap_read_reg_u32(dap, reg, data);
1223 }
1224
1225 static int jtag_ap_q_write(struct swjdp_common *dap, unsigned reg,
1226                 uint32_t data)
1227 {
1228         int retval = jtag_ap_q_bankselect(dap, reg);
1229
1230         if (retval != ERROR_OK)
1231                 return retval;
1232         return dap_ap_write_reg_u32(dap, reg, data);
1233 }
1234
1235 static int jtag_ap_q_abort(struct swjdp_common *dap, uint8_t *ack)
1236 {
1237         /* for JTAG, this is the only valid ABORT register operation */
1238         return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
1239                         0, DPAP_WRITE, 1, NULL, ack);
1240 }
1241
1242 static int jtag_dp_run(struct swjdp_common *dap)
1243 {
1244         return jtagdp_transaction_endcheck(dap);
1245 }
1246
1247 static const struct dap_ops jtag_dp_ops = {
1248         .queue_idcode_read =    jtag_idcode_q_read,
1249         .queue_dp_read =        jtag_dp_q_read,
1250         .queue_dp_write =       jtag_dp_q_write,
1251         .queue_ap_read =        jtag_ap_q_read,
1252         .queue_ap_write =       jtag_ap_q_write,
1253         .queue_ap_abort =       jtag_ap_q_abort,
1254         .run =                  jtag_dp_run,
1255 };
1256
1257 /*--------------------------------------------------------------------------*/
1258
1259 /**
1260  * Initialize a DAP.  This sets up the power domains, prepares the DP
1261  * for further use, and arranges to use AP #0 for all AP operations
1262  * until dap_ap-select() changes that policy.
1263  *
1264  * @param swjdp The DAP being initialized.
1265  *
1266  * @todo Rename this.  We also need an initialization scheme which account
1267  * for SWD transports not just JTAG; that will need to address differences
1268  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1269  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1270  */
1271 int ahbap_debugport_init(struct swjdp_common *swjdp)
1272 {
1273         uint32_t idreg, romaddr, dummy;
1274         uint32_t ctrlstat;
1275         int cnt = 0;
1276         int retval;
1277
1278         LOG_DEBUG(" ");
1279
1280         /* JTAG-DP or SWJ-DP, in JTAG mode */
1281         swjdp->ops = &jtag_dp_ops;
1282
1283         /* Default MEM-AP setup.
1284          *
1285          * REVISIT AP #0 may be an inappropriate default for this.
1286          * Should we probe, or take a hint from the caller?
1287          * Presumably we can ignore the possibility of multiple APs.
1288          */
1289         swjdp->apsel = !0;
1290         dap_ap_select(swjdp, 0);
1291
1292         /* DP initialization */
1293
1294         retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1295         if (retval != ERROR_OK)
1296                 return retval;
1297
1298         retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
1299         if (retval != ERROR_OK)
1300                 return retval;
1301
1302         retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1303         if (retval != ERROR_OK)
1304                 return retval;
1305
1306         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1307         retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
1308         if (retval != ERROR_OK)
1309                 return retval;
1310
1311         retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1312         if (retval != ERROR_OK)
1313                 return retval;
1314         if ((retval = dap_run(swjdp)) != ERROR_OK)
1315                 return retval;
1316
1317         /* Check that we have debug power domains activated */
1318         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1319         {
1320                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1321                 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1322                 if (retval != ERROR_OK)
1323                         return retval;
1324                 if ((retval = dap_run(swjdp)) != ERROR_OK)
1325                         return retval;
1326                 alive_sleep(10);
1327         }
1328
1329         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1330         {
1331                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1332                 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1333                 if (retval != ERROR_OK)
1334                         return retval;
1335                 if ((retval = dap_run(swjdp)) != ERROR_OK)
1336                         return retval;
1337                 alive_sleep(10);
1338         }
1339
1340         retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1341         if (retval != ERROR_OK)
1342                 return retval;
1343         /* With debug power on we can activate OVERRUN checking */
1344         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1345         retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
1346         if (retval != ERROR_OK)
1347                 return retval;
1348         retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1349         if (retval != ERROR_OK)
1350                 return retval;
1351
1352         /*
1353          * REVISIT this isn't actually *initializing* anything in an AP,
1354          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1355          * Should it?  If the ROM address is valid, is this the right
1356          * place to scan the table and do any topology detection?
1357          */
1358         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1359         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1360
1361         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1362                 ", Debug ROM Address 0x%" PRIx32,
1363                 swjdp->apsel, idreg, romaddr);
1364
1365         return ERROR_OK;
1366 }
1367
1368 /* CID interpretation -- see ARM IHI 0029B section 3
1369  * and ARM IHI 0031A table 13-3.
1370  */
1371 static const char *class_description[16] ={
1372         "Reserved", "ROM table", "Reserved", "Reserved",
1373         "Reserved", "Reserved", "Reserved", "Reserved",
1374         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1375         "Reserved", "OptimoDE DESS",
1376                 "Generic IP component", "PrimeCell or System component"
1377 };
1378
1379 static bool
1380 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1381 {
1382         return cid3 == 0xb1 && cid2 == 0x05
1383                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1384 }
1385
1386 int dap_info_command(struct command_context *cmd_ctx,
1387                 struct swjdp_common *swjdp, int apsel)
1388 {
1389         int retval;
1390         uint32_t dbgbase, apid;
1391         int romtable_present = 0;
1392         uint8_t mem_ap;
1393         uint32_t apselold;
1394
1395         /* AP address is in bits 31:24 of DP_SELECT */
1396         if (apsel >= 256)
1397                 return ERROR_INVALID_ARGUMENTS;
1398
1399         apselold = swjdp->apsel;
1400         dap_ap_select(swjdp, apsel);
1401         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1402         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1403         retval = dap_run(swjdp);
1404         if (retval != ERROR_OK)
1405                 return retval;
1406
1407         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1408         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1409         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1410         if (apid)
1411         {
1412                 switch (apid&0x0F)
1413                 {
1414                         case 0:
1415                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1416                                 break;
1417                         case 1:
1418                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1419                                 break;
1420                         case 2:
1421                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1422                                 break;
1423                         default:
1424                                 command_print(cmd_ctx, "\tUnknown AP type");
1425                                 break;
1426                 }
1427
1428                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1429                  * not a ROM table ... or have no such components at all.
1430                  */
1431                 if (mem_ap)
1432                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1433                                         dbgbase);
1434         }
1435         else
1436         {
1437                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1438         }
1439
1440         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1441         if (romtable_present)
1442         {
1443                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1444                 uint16_t entry_offset;
1445
1446                 /* bit 16 of apid indicates a memory access port */
1447                 if (dbgbase & 0x02)
1448                         command_print(cmd_ctx, "\tValid ROM table present");
1449                 else
1450                         command_print(cmd_ctx, "\tROM table in legacy format");
1451
1452                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1453                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1454                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1455                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1456                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1457                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1458                 retval = dap_run(swjdp);
1459                 if (retval != ERROR_OK)
1460                         return retval;
1461
1462                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1463                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1464                                         ", CID2 0x%2.2" PRIx32
1465                                         ", CID1 0x%2.2" PRIx32
1466                                         ", CID0 0x%2.2" PRIx32,
1467                                         cid3, cid2, cid1, cid0);
1468                 if (memtype & 0x01)
1469                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1470                 else
1471                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1472                                         "Dedicated debug bus.");
1473
1474                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1475                 entry_offset = 0;
1476                 do
1477                 {
1478                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1479                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1480                         if (romentry&0x01)
1481                         {
1482                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1483                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1484                                 uint32_t component_start, component_base;
1485                                 unsigned part_num;
1486                                 char *type, *full;
1487
1488                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1489                                                 + (int)(romentry & 0xFFFFF000));
1490                                 mem_ap_read_atomic_u32(swjdp,
1491                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1492                                 mem_ap_read_atomic_u32(swjdp,
1493                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1494                                 mem_ap_read_atomic_u32(swjdp,
1495                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1496                                 mem_ap_read_atomic_u32(swjdp,
1497                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1498                                 mem_ap_read_atomic_u32(swjdp,
1499                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1500                                 mem_ap_read_atomic_u32(swjdp,
1501                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1502                                 mem_ap_read_atomic_u32(swjdp,
1503                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1504                                 mem_ap_read_atomic_u32(swjdp,
1505                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1506                                 mem_ap_read_atomic_u32(swjdp,
1507                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1508                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1509
1510                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1511                                                 ", start address 0x%" PRIx32,
1512                                                 component_base, component_start);
1513                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1514                                                 (int) (c_cid1 >> 4) & 0xf,
1515                                                 /* See ARM IHI 0029B Table 3-3 */
1516                                                 class_description[(c_cid1 >> 4) & 0xf]);
1517
1518                                 /* CoreSight component? */
1519                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1520                                         uint32_t devtype;
1521                                         unsigned minor;
1522                                         char *major = "Reserved", *subtype = "Reserved";
1523
1524                                         mem_ap_read_atomic_u32(swjdp,
1525                                                         (component_base & 0xfffff000) | 0xfcc,
1526                                                         &devtype);
1527                                         minor = (devtype >> 4) & 0x0f;
1528                                         switch (devtype & 0x0f) {
1529                                         case 0:
1530                                                 major = "Miscellaneous";
1531                                                 switch (minor) {
1532                                                 case 0:
1533                                                         subtype = "other";
1534                                                         break;
1535                                                 case 4:
1536                                                         subtype = "Validation component";
1537                                                         break;
1538                                                 }
1539                                                 break;
1540                                         case 1:
1541                                                 major = "Trace Sink";
1542                                                 switch (minor) {
1543                                                 case 0:
1544                                                         subtype = "other";
1545                                                         break;
1546                                                 case 1:
1547                                                         subtype = "Port";
1548                                                         break;
1549                                                 case 2:
1550                                                         subtype = "Buffer";
1551                                                         break;
1552                                                 }
1553                                                 break;
1554                                         case 2:
1555                                                 major = "Trace Link";
1556                                                 switch (minor) {
1557                                                 case 0:
1558                                                         subtype = "other";
1559                                                         break;
1560                                                 case 1:
1561                                                         subtype = "Funnel, router";
1562                                                         break;
1563                                                 case 2:
1564                                                         subtype = "Filter";
1565                                                         break;
1566                                                 case 3:
1567                                                         subtype = "FIFO, buffer";
1568                                                         break;
1569                                                 }
1570                                                 break;
1571                                         case 3:
1572                                                 major = "Trace Source";
1573                                                 switch (minor) {
1574                                                 case 0:
1575                                                         subtype = "other";
1576                                                         break;
1577                                                 case 1:
1578                                                         subtype = "Processor";
1579                                                         break;
1580                                                 case 2:
1581                                                         subtype = "DSP";
1582                                                         break;
1583                                                 case 3:
1584                                                         subtype = "Engine/Coprocessor";
1585                                                         break;
1586                                                 case 4:
1587                                                         subtype = "Bus";
1588                                                         break;
1589                                                 }
1590                                                 break;
1591                                         case 4:
1592                                                 major = "Debug Control";
1593                                                 switch (minor) {
1594                                                 case 0:
1595                                                         subtype = "other";
1596                                                         break;
1597                                                 case 1:
1598                                                         subtype = "Trigger Matrix";
1599                                                         break;
1600                                                 case 2:
1601                                                         subtype = "Debug Auth";
1602                                                         break;
1603                                                 }
1604                                                 break;
1605                                         case 5:
1606                                                 major = "Debug Logic";
1607                                                 switch (minor) {
1608                                                 case 0:
1609                                                         subtype = "other";
1610                                                         break;
1611                                                 case 1:
1612                                                         subtype = "Processor";
1613                                                         break;
1614                                                 case 2:
1615                                                         subtype = "DSP";
1616                                                         break;
1617                                                 case 3:
1618                                                         subtype = "Engine/Coprocessor";
1619                                                         break;
1620                                                 }
1621                                                 break;
1622                                         }
1623                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1624                                                         (unsigned) (devtype & 0xff),
1625                                                         major, subtype);
1626                                         /* REVISIT also show 0xfc8 DevId */
1627                                 }
1628
1629                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1630                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1631                                                         ", CID2 0x%2.2" PRIx32
1632                                                         ", CID1 0x%2.2" PRIx32
1633                                                         ", CID0 0x%2.2" PRIx32,
1634                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1635                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1636                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1637                                                 (int) c_pid4,
1638                                                 (int) c_pid3, (int) c_pid2,
1639                                                 (int) c_pid1, (int) c_pid0);
1640
1641                                 /* Part number interpretations are from Cortex
1642                                  * core specs, the CoreSight components TRM
1643                                  * (ARM DDI 0314H), and ETM specs; also from
1644                                  * chip observation (e.g. TI SDTI).
1645                                  */
1646                                 part_num = c_pid0 & 0xff;
1647                                 part_num |= (c_pid1 & 0x0f) << 8;
1648                                 switch (part_num) {
1649                                 case 0x000:
1650                                         type = "Cortex-M3 NVIC";
1651                                         full = "(Interrupt Controller)";
1652                                         break;
1653                                 case 0x001:
1654                                         type = "Cortex-M3 ITM";
1655                                         full = "(Instrumentation Trace Module)";
1656                                         break;
1657                                 case 0x002:
1658                                         type = "Cortex-M3 DWT";
1659                                         full = "(Data Watchpoint and Trace)";
1660                                         break;
1661                                 case 0x003:
1662                                         type = "Cortex-M3 FBP";
1663                                         full = "(Flash Patch and Breakpoint)";
1664                                         break;
1665                                 case 0x00d:
1666                                         type = "CoreSight ETM11";
1667                                         full = "(Embedded Trace)";
1668                                         break;
1669                                 // case 0x113: what?
1670                                 case 0x120:             /* from OMAP3 memmap */
1671                                         type = "TI SDTI";
1672                                         full = "(System Debug Trace Interface)";
1673                                         break;
1674                                 case 0x343:             /* from OMAP3 memmap */
1675                                         type = "TI DAPCTL";
1676                                         full = "";
1677                                         break;
1678                                 case 0x906:
1679                                         type = "Coresight CTI";
1680                                         full = "(Cross Trigger)";
1681                                         break;
1682                                 case 0x907:
1683                                         type = "Coresight ETB";
1684                                         full = "(Trace Buffer)";
1685                                         break;
1686                                 case 0x908:
1687                                         type = "Coresight CSTF";
1688                                         full = "(Trace Funnel)";
1689                                         break;
1690                                 case 0x910:
1691                                         type = "CoreSight ETM9";
1692                                         full = "(Embedded Trace)";
1693                                         break;
1694                                 case 0x912:
1695                                         type = "Coresight TPIU";
1696                                         full = "(Trace Port Interface Unit)";
1697                                         break;
1698                                 case 0x921:
1699                                         type = "Cortex-A8 ETM";
1700                                         full = "(Embedded Trace)";
1701                                         break;
1702                                 case 0x922:
1703                                         type = "Cortex-A8 CTI";
1704                                         full = "(Cross Trigger)";
1705                                         break;
1706                                 case 0x923:
1707                                         type = "Cortex-M3 TPIU";
1708                                         full = "(Trace Port Interface Unit)";
1709                                         break;
1710                                 case 0x924:
1711                                         type = "Cortex-M3 ETM";
1712                                         full = "(Embedded Trace)";
1713                                         break;
1714                                 case 0xc08:
1715                                         type = "Cortex-A8 Debug";
1716                                         full = "(Debug Unit)";
1717                                         break;
1718                                 default:
1719                                         type = "-*- unrecognized -*-";
1720                                         full = "";
1721                                         break;
1722                                 }
1723                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1724                                                 type, full);
1725                         }
1726                         else
1727                         {
1728                                 if (romentry)
1729                                         command_print(cmd_ctx, "\t\tComponent not present");
1730                                 else
1731                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1732                         }
1733                         entry_offset += 4;
1734                 } while (romentry > 0);
1735         }
1736         else
1737         {
1738                 command_print(cmd_ctx, "\tNo ROM table present");
1739         }
1740         dap_ap_select(swjdp, apselold);
1741
1742         return ERROR_OK;
1743 }
1744
1745 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1746 {
1747         uint32_t apsel, apselsave, baseaddr;
1748         int retval;
1749
1750         apselsave = swjdp->apsel;
1751         switch (CMD_ARGC) {
1752         case 0:
1753                 apsel = swjdp->apsel;
1754                 break;
1755         case 1:
1756                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1757                 /* AP address is in bits 31:24 of DP_SELECT */
1758                 if (apsel >= 256)
1759                         return ERROR_INVALID_ARGUMENTS;
1760                 break;
1761         default:
1762                 return ERROR_COMMAND_SYNTAX_ERROR;
1763         }
1764
1765         if (apselsave != apsel)
1766                 dap_ap_select(swjdp, apsel);
1767
1768         /* NOTE:  assumes we're talking to a MEM-AP, which
1769          * has a base address.  There are other kinds of AP,
1770          * though they're not common for now.  This should
1771          * use the ID register to verify it's a MEM-AP.
1772          */
1773         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1774         retval = dap_run(swjdp);
1775         if (retval != ERROR_OK)
1776                 return retval;
1777
1778         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1779
1780         if (apselsave != apsel)
1781                 dap_ap_select(swjdp, apselsave);
1782
1783         return retval;
1784 }
1785
1786 DAP_COMMAND_HANDLER(dap_memaccess_command)
1787 {
1788         uint32_t memaccess_tck;
1789
1790         switch (CMD_ARGC) {
1791         case 0:
1792                 memaccess_tck = swjdp->memaccess_tck;
1793                 break;
1794         case 1:
1795                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1796                 break;
1797         default:
1798                 return ERROR_COMMAND_SYNTAX_ERROR;
1799         }
1800         swjdp->memaccess_tck = memaccess_tck;
1801
1802         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1803                         swjdp->memaccess_tck);
1804
1805         return ERROR_OK;
1806 }
1807
1808 DAP_COMMAND_HANDLER(dap_apsel_command)
1809 {
1810         uint32_t apsel, apid;
1811         int retval;
1812
1813         switch (CMD_ARGC) {
1814         case 0:
1815                 apsel = 0;
1816                 break;
1817         case 1:
1818                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1819                 /* AP address is in bits 31:24 of DP_SELECT */
1820                 if (apsel >= 256)
1821                         return ERROR_INVALID_ARGUMENTS;
1822                 break;
1823         default:
1824                 return ERROR_COMMAND_SYNTAX_ERROR;
1825         }
1826
1827         dap_ap_select(swjdp, apsel);
1828         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1829         retval = dap_run(swjdp);
1830         if (retval != ERROR_OK)
1831                 return retval;
1832
1833         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1834                         apsel, apid);
1835
1836         return retval;
1837 }
1838
1839 DAP_COMMAND_HANDLER(dap_apid_command)
1840 {
1841         uint32_t apsel, apselsave, apid;
1842         int retval;
1843
1844         apselsave = swjdp->apsel;
1845         switch (CMD_ARGC) {
1846         case 0:
1847                 apsel = swjdp->apsel;
1848                 break;
1849         case 1:
1850                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1851                 /* AP address is in bits 31:24 of DP_SELECT */
1852                 if (apsel >= 256)
1853                         return ERROR_INVALID_ARGUMENTS;
1854                 break;
1855         default:
1856                 return ERROR_COMMAND_SYNTAX_ERROR;
1857         }
1858
1859         if (apselsave != apsel)
1860                 dap_ap_select(swjdp, apsel);
1861
1862         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1863         retval = dap_run(swjdp);
1864         if (retval != ERROR_OK)
1865                 return retval;
1866
1867         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1868         if (apselsave != apsel)
1869                 dap_ap_select(swjdp, apselsave);
1870
1871         return retval;
1872 }
1873
1874 /*
1875  * This represents the bits which must be sent out on TMS/SWDIO to
1876  * switch a DAP implemented using an SWJ-DP module into SWD mode.
1877  * These bits are stored (and transmitted) LSB-first.
1878  *
1879  * See the DAP-Lite specification, section 2.2.5 for information
1880  * about making the debug link select SWD or JTAG.  (Similar info
1881  * is in a few other ARM documents.)
1882  */
1883 static const uint8_t jtag2swd_bitseq[] = {
1884         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1885          * putting both JTAG and SWD logic into reset state.
1886          */
1887         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1888         /* Switching sequence enables SWD and disables JTAG
1889          * NOTE: bits in the DP's IDCODE may expose the need for
1890          * an old/deprecated sequence (0xb6 0xed).
1891          */
1892         0x9e, 0xe7,
1893         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1894          * putting both JTAG and SWD logic into reset state.
1895          */
1896         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1897 };
1898
1899 /**
1900  * Put the debug link into SWD mode, if the target supports it.
1901  * The link's initial mode may be either JTAG (for example,
1902  * with SWJ-DP after reset) or SWD.
1903  *
1904  * @param target Enters SWD mode (if possible).
1905  *
1906  * Note that targets using the JTAG-DP do not support SWD, and that
1907  * some targets which could otherwise support it may have have been
1908  * configured to disable SWD signaling
1909  *
1910  * @return ERROR_OK or else a fault code.
1911  */
1912 int dap_to_swd(struct target *target)
1913 {
1914         int retval;
1915
1916         LOG_DEBUG("Enter SWD mode");
1917
1918         /* REVISIT it's nasty to need to make calls to a "jtag"
1919          * subsystem if the link isn't in JTAG mode...
1920          */
1921
1922         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
1923                         jtag2swd_bitseq, TAP_INVALID);
1924         if (retval == ERROR_OK)
1925                 retval = jtag_execute_queue();
1926
1927         /* REVISIT set up the DAP's ops vector for SWD mode. */
1928
1929         return retval;
1930 }
1931
1932 /**
1933  * This represents the bits which must be sent out on TMS/SWDIO to
1934  * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1935  * These bits are stored (and transmitted) LSB-first.
1936  *
1937  * These bits are stored (and transmitted) LSB-first.
1938  */
1939 static const uint8_t swd2jtag_bitseq[] = {
1940         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1941          * putting both JTAG and SWD logic into reset state.
1942          */
1943         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1944         /* Switching equence disables SWD and enables JTAG
1945          * NOTE: bits in the DP's IDCODE can expose the need for
1946          * the old/deprecated sequence (0xae 0xde).
1947          */
1948         0x3c, 0xe7,
1949         /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1950          * putting both JTAG and SWD logic into reset state.
1951          * NOTE:  some docs say "at least 5".
1952          */
1953         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1954 };
1955
1956 /** Put the debug link into JTAG mode, if the target supports it.
1957  * The link's initial mode may be either SWD or JTAG.
1958  *
1959  * @param target Enters JTAG mode (if possible).
1960  *
1961  * Note that targets implemented with SW-DP do not support JTAG, and
1962  * that some targets which could otherwise support it may have been
1963  * configured to disable JTAG signaling
1964  *
1965  * @return ERROR_OK or else a fault code.
1966  */
1967 int dap_to_jtag(struct target *target)
1968 {
1969         int retval;
1970
1971         LOG_DEBUG("Enter JTAG mode");
1972
1973         /* REVISIT it's nasty to need to make calls to a "jtag"
1974          * subsystem if the link isn't in JTAG mode...
1975          */
1976
1977         retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
1978                         swd2jtag_bitseq, TAP_RESET);
1979         if (retval == ERROR_OK)
1980                 retval = jtag_execute_queue();
1981
1982         /* REVISIT set up the DAP's ops vector for JTAG mode. */
1983
1984         return retval;
1985 }