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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 /**
  28  * @file
  29  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  30  * debugging architecture.  Compared with previous versions, this includes
  31  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  32  * transport, and focusses on memory mapped resources as defined by the
  33  * CoreSight architecture.
  34  *
  35  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  36  * basic components:  a Debug Port (DP) transporting messages to and from a
  37  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  38  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  39  * One uses only SWD for communication, and is called SW-DP.  The third can
  40  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  41  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  42  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  43  */
  44
  45 /*
  46  * Relevant specifications from ARM include:
  47  *
  48  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  49  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  50  *
  51  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  52  * Cortex-M3(tm) TRM, ARM DDI 0337G
  53  */
  54
  55 #ifdef HAVE_CONFIG_H
  56 #include "config.h"
  57 #endif
  58
  59 #include "arm_adi_v5.h"
  60 #include <helper/time_support.h>
  61
  62 /*
  63  * Transaction Mode:
  64  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  66  * result checking until swjdp_end_transaction()
  67  * This must be done before using or deallocating any return variables.
  68  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  69  * All reads and writes to the AHB bus are checked for valid completion, and return values
  70  * are immediatley available.
  71 */
  72
  73
  74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  75
  76 /*
  77         uint32_t tar_block_size(uint32_t address)
  78         Return the largest block starting at address that does not cross a tar block size alignment boundary
  79 */
  80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  81 {
  82         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  83 }
  84
  85 /***************************************************************************
  86  *                                                                         *
  87  * DPACC and APACC scanchain access through JTAG-DP                        *
  88  *                                                                         *
  89 ***************************************************************************/
  90
  91 /**
  92  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  93  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  94  * discusses operations which access these registers.
  95  *
  96  * Note that only one scan is performed.  If RnW is set, a separate scan
  97  * will be needed to collect the data which was read; the "invalue" collects
  98  * the posted result of a preceding operation, not the current one.
  99  *
 100  * @param swjdp the DAP
 101  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 102  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 103  *      SELECT register has more addressing bits.
 104  * @param RnW false iff outvalue will be written to the DP or AP
 105  * @param outvalue points to a 32-bit (little-endian) integer
 106  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 107  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 108  */
 109 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 110                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 111                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 112 {
 113         struct arm_jtag *jtag_info = swjdp->jtag_info;
 114         struct scan_field fields[2];
 115         uint8_t out_addr_buf;
 116
 117         jtag_set_end_state(TAP_IDLE);
 118         arm_jtag_set_instr(jtag_info, instr, NULL);
 119
 120         /* Add specified number of tck clocks before accessing memory bus */
 121
 122         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 123          * they provide more time for the (MEM) AP to complete the read ...
 124          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 125          */
 126         if ((instr == JTAG_DP_APACC)
 127                         && ((reg_addr == AP_REG_DRW)
 128                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 129                         && (swjdp->memaccess_tck != 0))
 130                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 131
 132         /* Scan out a read or write operation using some DP or AP register.
 133          * For APACC access with any sticky error flag set, this is discarded.
 134          */
 135         fields[0].tap = jtag_info->tap;
 136         fields[0].num_bits = 3;
 137         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 138         fields[0].out_value = &out_addr_buf;
 139         fields[0].in_value = ack;
 140
 141         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 142          * complete; data we write is discarded, data we read is unpredictable.
 143          * When overrun detect is active, STICKYORUN is set.
 144          */
 145
 146         fields[1].tap = jtag_info->tap;
 147         fields[1].num_bits = 32;
 148         fields[1].out_value = outvalue;
 149         fields[1].in_value = invalue;
 150
 151         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 152
 153         return ERROR_OK;
 154 }
 155
 156 /* Scan out and in from host ordered uint32_t variables */
 157 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 158                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 159                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 160 {
 161         struct arm_jtag *jtag_info = swjdp->jtag_info;
 162         struct scan_field fields[2];
 163         uint8_t out_value_buf[4];
 164         uint8_t out_addr_buf;
 165
 166         jtag_set_end_state(TAP_IDLE);
 167         arm_jtag_set_instr(jtag_info, instr, NULL);
 168
 169         /* Add specified number of tck clocks before accessing memory bus */
 170
 171         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 172          * they provide more time for the (MEM) AP to complete the read ...
 173          */
 174         if ((instr == JTAG_DP_APACC)
 175                         && ((reg_addr == AP_REG_DRW)
 176                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 177                         && (swjdp->memaccess_tck != 0))
 178                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 179
 180         fields[0].tap = jtag_info->tap;
 181         fields[0].num_bits = 3;
 182         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 183         fields[0].out_value = &out_addr_buf;
 184         fields[0].in_value = ack;
 185
 186         fields[1].tap = jtag_info->tap;
 187         fields[1].num_bits = 32;
 188         buf_set_u32(out_value_buf, 0, 32, outvalue);
 189         fields[1].out_value = out_value_buf;
 190         fields[1].in_value = NULL;
 191
 192         if (invalue)
 193         {
 194                 fields[1].in_value = (uint8_t *)invalue;
 195                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 196
 197                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 198         } else
 199         {
 200
 201                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 202         }
 203
 204         return ERROR_OK;
 205 }
 206
 207 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 208 static int scan_inout_check(struct swjdp_common *swjdp,
 209                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 210                 uint8_t *outvalue, uint8_t *invalue)
 211 {
 212         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 213
 214         if ((RnW == DPAP_READ) && (invalue != NULL))
 215                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 216                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 217
 218         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 219          * ack = OK/FAULT and the check CTRL_STAT
 220          */
 221         if ((instr == JTAG_DP_APACC)
 222                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 223                 return jtagdp_transaction_endcheck(swjdp);
 224
 225         return ERROR_OK;
 226 }
 227
 228 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 229                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 230                 uint32_t outvalue, uint32_t *invalue)
 231 {
 232         /* Issue the read or write */
 233         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 234
 235         /* For reads,  collect posted value; RDBUFF has no other effect.
 236          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 237          */
 238         if ((RnW == DPAP_READ) && (invalue != NULL))
 239                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 240                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 241
 242         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 243          * ack = OK/FAULT and then check CTRL_STAT
 244          */
 245         if ((instr == JTAG_DP_APACC)
 246                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 247                 return jtagdp_transaction_endcheck(swjdp);
 248
 249         return ERROR_OK;
 250 }
 251
 252 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 253 {
 254         int retval;
 255         uint32_t ctrlstat;
 256
 257         /* too expensive to call keep_alive() here */
 258
 259 #if 0
 260         /* Danger!!!! BROKEN!!!! */
 261         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 262                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 263         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 264         R956 introduced the check on return value here and now Michael Schwingen reports
 265         that this code no longer works....
 266
 267         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 268         */
 269         if ((retval = jtag_execute_queue()) != ERROR_OK)
 270         {
 271                 LOG_ERROR("BUG: Why does this fail the first time????");
 272         }
 273         /* Why??? second time it works??? */
 274 #endif
 275
 276         /* Post CTRL/STAT read; discard any previous posted read value
 277          * but collect its ACK status.
 278          */
 279         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 280                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 281         if ((retval = jtag_execute_queue()) != ERROR_OK)
 282                 return retval;
 283
 284         swjdp->ack = swjdp->ack & 0x7;
 285
 286         /* common code path avoids calling timeval_ms() */
 287         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 288         {
 289                 long long then = timeval_ms();
 290
 291                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 292                 {
 293                         if (swjdp->ack == JTAG_ACK_WAIT)
 294                         {
 295                                 if ((timeval_ms()-then) > 1000)
 296                                 {
 297                                         /* NOTE:  this would be a good spot
 298                                          * to use JTAG_DP_ABORT.
 299                                          */
 300                                         LOG_WARNING("Timeout (1000ms) waiting "
 301                                                 "for ACK=OK/FAULT "
 302                                                 "in JTAG-DP transaction");
 303                                         return ERROR_JTAG_DEVICE_ERROR;
 304                                 }
 305                         }
 306                         else
 307                         {
 308                                 LOG_WARNING("Invalid ACK %#x "
 309                                                 "in JTAG-DP transaction",
 310                                                 swjdp->ack);
 311                                 return ERROR_JTAG_DEVICE_ERROR;
 312                         }
 313
 314                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 315                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 316                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 317                                 return retval;
 318                         swjdp->ack = swjdp->ack & 0x7;
 319                 }
 320         }
 321
 322         /* Check for STICKYERR and STICKYORUN */
 323         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 324         {
 325                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 326                 /* Check power to debug regions */
 327                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 328                 {
 329                          ahbap_debugport_init(swjdp);
 330                 }
 331                 else
 332                 {
 333                         uint32_t mem_ap_csw, mem_ap_tar;
 334
 335                         /* Print information about last AHBAP access */
 336                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
 337                                 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
 338                                 swjdp->dp_select_value, swjdp->ap_csw_value,
 339                                 swjdp->ap_tar_value);
 340                         if (ctrlstat & SSTICKYORUN)
 341                                 LOG_ERROR("JTAG-DP OVERRUN - "
 342                                         "check clock or reduce jtag speed");
 343
 344                         if (ctrlstat & SSTICKYERR)
 345                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 346
 347                         /* Clear Sticky Error Bits */
 348                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 349                                         DP_CTRL_STAT, DPAP_WRITE,
 350                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 351                                                 | SSTICKYERR, NULL);
 352                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 353                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 354                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 355                                 return retval;
 356
 357                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 358
 359                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 360                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 361                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 362                                 return retval;
 363                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 364                                         PRIx32, mem_ap_csw, mem_ap_tar);
 365
 366                 }
 367                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 368                         return retval;
 369                 return ERROR_JTAG_DEVICE_ERROR;
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 /***************************************************************************
 376  *                                                                         *
 377  * DP and MEM-AP  register access  through APACC and DPACC                 *
 378  *                                                                         *
 379 ***************************************************************************/
 380
 381 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 382                 uint32_t value, uint8_t reg_addr)
 383 {
 384         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 385                         reg_addr, DPAP_WRITE, value, NULL);
 386 }
 387
 388 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 389                 uint32_t *value, uint8_t reg_addr)
 390 {
 391         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 392                         reg_addr, DPAP_READ, 0, value);
 393 }
 394
 395 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 396 {
 397         uint32_t select;
 398         select = (apsel << 24) & 0xFF000000;
 399
 400         if (select != swjdp->apsel)
 401         {
 402                 swjdp->apsel = select;
 403                 /* Switching AP invalidates cached values */
 404                 swjdp->dp_select_value = -1;
 405                 swjdp->ap_csw_value = -1;
 406                 swjdp->ap_tar_value = -1;
 407         }
 408
 409         return ERROR_OK;
 410 }
 411
 412 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 413 {
 414         uint32_t select;
 415         select = (ap_reg & 0x000000F0);
 416
 417         if (select != swjdp->dp_select_value)
 418         {
 419                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 420                 swjdp->dp_select_value = select;
 421         }
 422
 423         return ERROR_OK;
 424 }
 425
 426 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 427                 uint32_t reg_addr, uint8_t *out_value_buf)
 428 {
 429         dap_dp_bankselect(swjdp, reg_addr);
 430         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 431                         DPAP_WRITE, out_value_buf, NULL);
 432
 433         return ERROR_OK;
 434 }
 435
 436 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 437 {
 438         uint8_t out_value_buf[4];
 439
 440         buf_set_u32(out_value_buf, 0, 32, value);
 441         dap_dp_bankselect(swjdp, reg_addr);
 442         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 443                         DPAP_WRITE, out_value_buf, NULL);
 444
 445         return ERROR_OK;
 446 }
 447
 448 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 449 {
 450         dap_dp_bankselect(swjdp, reg_addr);
 451         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 452                         DPAP_READ, 0, value);
 453
 454         return ERROR_OK;
 455 }
 456
 457 /***************************************************************************
 458  *                                                                         *
 459  * AHB-AP access to memory and system registers on AHB bus                 *
 460  *                                                                         *
 461 ***************************************************************************/
 462
 463 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 464 {
 465         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 466         if (csw != swjdp->ap_csw_value)
 467         {
 468                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 469                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 470                 swjdp->ap_csw_value = csw;
 471         }
 472         if (tar != swjdp->ap_tar_value)
 473         {
 474                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 475                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 476                 swjdp->ap_tar_value = tar;
 477         }
 478         if (csw & CSW_ADDRINC_MASK)
 479         {
 480                 /* Do not cache TAR value when autoincrementing */
 481                 swjdp->ap_tar_value = -1;
 482         }
 483         return ERROR_OK;
 484 }
 485
 486 /*****************************************************************************
 487 *                                                                            *
 488 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 489 *                                                                            *
 490 * Read a uint32_t value from memory or system register                            *
 491 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 492 * but with less overhead                                                     *
 493 *****************************************************************************/
 494 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 495 {
 496         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 497
 498         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 499         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 500
 501         return ERROR_OK;
 502 }
 503
 504 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 505 {
 506         mem_ap_read_u32(swjdp, address, value);
 507
 508         return jtagdp_transaction_endcheck(swjdp);
 509 }
 510
 511 /*****************************************************************************
 512 *                                                                            *
 513 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 514 *                                                                            *
 515 * Write a uint32_t value to memory or memory mapped register                              *
 516 *                                                                            *
 517 *****************************************************************************/
 518 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 519 {
 520         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 521
 522         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 523         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 524
 525         return ERROR_OK;
 526 }
 527
 528 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 529 {
 530         mem_ap_write_u32(swjdp, address, value);
 531
 532         return jtagdp_transaction_endcheck(swjdp);
 533 }
 534
 535 /*****************************************************************************
 536 *                                                                            *
 537 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 538 *                                                                            *
 539 * Write a buffer in target order (little endian)                             *
 540 *                                                                            *
 541 *****************************************************************************/
 542 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 543 {
 544         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 545         uint32_t adr = address;
 546         uint8_t* pBuffer = buffer;
 547
 548         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 549
 550         count >>= 2;
 551         wcount = count;
 552
 553         /* if we have an unaligned access - reorder data */
 554         if (adr & 0x3u)
 555         {
 556                 for (writecount = 0; writecount < count; writecount++)
 557                 {
 558                         int i;
 559                         uint32_t outvalue;
 560                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 561
 562                         for (i = 0; i < 4; i++)
 563                         {
 564                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 565                                 outvalue >>= 8;
 566                                 adr++;
 567                         }
 568                         pBuffer += sizeof(uint32_t);
 569                 }
 570         }
 571
 572         while (wcount > 0)
 573         {
 574                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 575                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 576                 if (wcount < blocksize)
 577                         blocksize = wcount;
 578
 579                 /* handle unaligned data at 4k boundary */
 580                 if (blocksize == 0)
 581                         blocksize = 1;
 582
 583                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 584
 585                 for (writecount = 0; writecount < blocksize; writecount++)
 586                 {
 587                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 588                 }
 589
 590                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 591                 {
 592                         wcount = wcount - blocksize;
 593                         address = address + 4 * blocksize;
 594                         buffer = buffer + 4 * blocksize;
 595                 }
 596                 else
 597                 {
 598                         errorcount++;
 599                 }
 600
 601                 if (errorcount > 1)
 602                 {
 603                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 604                         return ERROR_JTAG_DEVICE_ERROR;
 605                 }
 606         }
 607
 608         return retval;
 609 }
 610
 611 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 612                 uint8_t *buffer, int count, uint32_t address)
 613 {
 614         int retval = ERROR_OK;
 615         int wcount, blocksize, writecount, i;
 616
 617         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 618
 619         wcount = count >> 1;
 620
 621         while (wcount > 0)
 622         {
 623                 int nbytes;
 624
 625                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 626                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 627
 628                 if (wcount < blocksize)
 629                         blocksize = wcount;
 630
 631                 /* handle unaligned data at 4k boundary */
 632                 if (blocksize == 0)
 633                         blocksize = 1;
 634
 635                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 636                 writecount = blocksize;
 637
 638                 do
 639                 {
 640                         nbytes = MIN((writecount << 1), 4);
 641
 642                         if (nbytes < 4)
 643                         {
 644                                 if (mem_ap_write_buf_u16(swjdp, buffer,
 645                                                 nbytes, address) != ERROR_OK)
 646                                 {
 647                                         LOG_WARNING("Block write error address "
 648                                                 "0x%" PRIx32 ", count 0x%x",
 649                                                 address, count);
 650                                         return ERROR_JTAG_DEVICE_ERROR;
 651                                 }
 652
 653                                 address += nbytes >> 1;
 654                         }
 655                         else
 656                         {
 657                                 uint32_t outvalue;
 658                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 659
 660                                 for (i = 0; i < nbytes; i++)
 661                                 {
 662                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 663                                         outvalue >>= 8;
 664                                         address++;
 665                                 }
 666
 667                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 668                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 669                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 670                                 {
 671                                         LOG_WARNING("Block write error address "
 672                                                 "0x%" PRIx32 ", count 0x%x",
 673                                                 address, count);
 674                                         return ERROR_JTAG_DEVICE_ERROR;
 675                                 }
 676                         }
 677
 678                         buffer += nbytes >> 1;
 679                         writecount -= nbytes >> 1;
 680
 681                 } while (writecount);
 682                 wcount -= blocksize;
 683         }
 684
 685         return retval;
 686 }
 687
 688 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 689 {
 690         int retval = ERROR_OK;
 691
 692         if (count >= 4)
 693                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 694
 695         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 696
 697         while (count > 0)
 698         {
 699                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 700                 uint16_t svalue;
 701                 memcpy(&svalue, buffer, sizeof(uint16_t));
 702                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 703                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 704                 retval = jtagdp_transaction_endcheck(swjdp);
 705                 count -= 2;
 706                 address += 2;
 707                 buffer += 2;
 708         }
 709
 710         return retval;
 711 }
 712
 713 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 714                 uint8_t *buffer, int count, uint32_t address)
 715 {
 716         int retval = ERROR_OK;
 717         int wcount, blocksize, writecount, i;
 718
 719         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 720
 721         wcount = count;
 722
 723         while (wcount > 0)
 724         {
 725                 int nbytes;
 726
 727                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 728                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 729
 730                 if (wcount < blocksize)
 731                         blocksize = wcount;
 732
 733                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 734                 writecount = blocksize;
 735
 736                 do
 737                 {
 738                         nbytes = MIN(writecount, 4);
 739
 740                         if (nbytes < 4)
 741                         {
 742                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 743                                 {
 744                                         LOG_WARNING("Block write error address "
 745                                                 "0x%" PRIx32 ", count 0x%x",
 746                                                 address, count);
 747                                         return ERROR_JTAG_DEVICE_ERROR;
 748                                 }
 749
 750                                 address += nbytes;
 751                         }
 752                         else
 753                         {
 754                                 uint32_t outvalue;
 755                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 756
 757                                 for (i = 0; i < nbytes; i++)
 758                                 {
 759                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 760                                         outvalue >>= 8;
 761                                         address++;
 762                                 }
 763
 764                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 765                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 766                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 767                                 {
 768                                         LOG_WARNING("Block write error address "
 769                                                 "0x%" PRIx32 ", count 0x%x",
 770                                                 address, count);
 771                                         return ERROR_JTAG_DEVICE_ERROR;
 772                                 }
 773                         }
 774
 775                         buffer += nbytes;
 776                         writecount -= nbytes;
 777
 778                 } while (writecount);
 779                 wcount -= blocksize;
 780         }
 781
 782         return retval;
 783 }
 784
 785 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 786 {
 787         int retval = ERROR_OK;
 788
 789         if (count >= 4)
 790                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 791
 792         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 793
 794         while (count > 0)
 795         {
 796                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 797                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 798                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 799                 retval = jtagdp_transaction_endcheck(swjdp);
 800                 count--;
 801                 address++;
 802                 buffer++;
 803         }
 804
 805         return retval;
 806 }
 807
 808 /*********************************************************************************
 809 *                                                                                *
 810 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 811 *                                                                                *
 812 * Read block fast in target order (little endian) into a buffer                  *
 813 *                                                                                *
 814 **********************************************************************************/
 815 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 816 {
 817         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 818         uint32_t adr = address;
 819         uint8_t* pBuffer = buffer;
 820
 821         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 822
 823         count >>= 2;
 824         wcount = count;
 825
 826         while (wcount > 0)
 827         {
 828                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 829                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 830                 if (wcount < blocksize)
 831                         blocksize = wcount;
 832
 833                 /* handle unaligned data at 4k boundary */
 834                 if (blocksize == 0)
 835                         blocksize = 1;
 836
 837                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 838
 839                 /* Scan out first read */
 840                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 841                                 DPAP_READ, 0, NULL, NULL);
 842                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 843                 {
 844                         /* Scan out next read; scan in posted value for the
 845                          * previous one.  Assumes read is acked "OK/FAULT",
 846                          * and CTRL_STAT says that meant "OK".
 847                          */
 848                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 849                                         DPAP_READ, 0, buffer + 4 * readcount,
 850                                         &swjdp->ack);
 851                 }
 852
 853                 /* Scan in last posted value; RDBUFF has no other effect,
 854                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 855                  */
 856                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 857                                 DPAP_READ, 0, buffer + 4 * readcount,
 858                                 &swjdp->ack);
 859                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 860                 {
 861                         wcount = wcount - blocksize;
 862                         address += 4 * blocksize;
 863                         buffer += 4 * blocksize;
 864                 }
 865                 else
 866                 {
 867                         errorcount++;
 868                 }
 869
 870                 if (errorcount > 1)
 871                 {
 872                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 873                         return ERROR_JTAG_DEVICE_ERROR;
 874                 }
 875         }
 876
 877         /* if we have an unaligned access - reorder data */
 878         if (adr & 0x3u)
 879         {
 880                 for (readcount = 0; readcount < count; readcount++)
 881                 {
 882                         int i;
 883                         uint32_t data;
 884                         memcpy(&data, pBuffer, sizeof(uint32_t));
 885
 886                         for (i = 0; i < 4; i++)
 887                         {
 888                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 889                                 pBuffer++;
 890                                 adr++;
 891                         }
 892                 }
 893         }
 894
 895         return retval;
 896 }
 897
 898 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 899                 uint8_t *buffer, int count, uint32_t address)
 900 {
 901         uint32_t invalue;
 902         int retval = ERROR_OK;
 903         int wcount, blocksize, readcount, i;
 904
 905         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 906
 907         wcount = count >> 1;
 908
 909         while (wcount > 0)
 910         {
 911                 int nbytes;
 912
 913                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 914                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 915                 if (wcount < blocksize)
 916                         blocksize = wcount;
 917
 918                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 919
 920                 /* handle unaligned data at 4k boundary */
 921                 if (blocksize == 0)
 922                         blocksize = 1;
 923                 readcount = blocksize;
 924
 925                 do
 926                 {
 927                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 928                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 929                         {
 930                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 931                                 return ERROR_JTAG_DEVICE_ERROR;
 932                         }
 933
 934                         nbytes = MIN((readcount << 1), 4);
 935
 936                         for (i = 0; i < nbytes; i++)
 937                         {
 938                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 939                                 buffer++;
 940                                 address++;
 941                         }
 942
 943                         readcount -= (nbytes >> 1);
 944                 } while (readcount);
 945                 wcount -= blocksize;
 946         }
 947
 948         return retval;
 949 }
 950
 951 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 952 {
 953         uint32_t invalue, i;
 954         int retval = ERROR_OK;
 955
 956         if (count >= 4)
 957                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 958
 959         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 960
 961         while (count > 0)
 962         {
 963                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 964                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 965                 retval = jtagdp_transaction_endcheck(swjdp);
 966                 if (address & 0x1)
 967                 {
 968                         for (i = 0; i < 2; i++)
 969                         {
 970                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 971                                 buffer++;
 972                                 address++;
 973                         }
 974                 }
 975                 else
 976                 {
 977                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 978                         memcpy(buffer, &svalue, sizeof(uint16_t));
 979                         address += 2;
 980                         buffer += 2;
 981                 }
 982                 count -= 2;
 983         }
 984
 985         return retval;
 986 }
 987
 988 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 989  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 990  *
 991  * The solution is to arrange for a large out/in scan in this loop and
 992  * and convert data afterwards.
 993  */
 994 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 995                 uint8_t *buffer, int count, uint32_t address)
 996 {
 997         uint32_t invalue;
 998         int retval = ERROR_OK;
 999         int wcount, blocksize, readcount, i;
1000
1001         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1002
1003         wcount = count;
1004
1005         while (wcount > 0)
1006         {
1007                 int nbytes;
1008
1009                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1010                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1011
1012                 if (wcount < blocksize)
1013                         blocksize = wcount;
1014
1015                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1016                 readcount = blocksize;
1017
1018                 do
1019                 {
1020                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1021                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1022                         {
1023                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1024                                 return ERROR_JTAG_DEVICE_ERROR;
1025                         }
1026
1027                         nbytes = MIN(readcount, 4);
1028
1029                         for (i = 0; i < nbytes; i++)
1030                         {
1031                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1032                                 buffer++;
1033                                 address++;
1034                         }
1035
1036                         readcount -= nbytes;
1037                 } while (readcount);
1038                 wcount -= blocksize;
1039         }
1040
1041         return retval;
1042 }
1043
1044 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1045 {
1046         uint32_t invalue;
1047         int retval = ERROR_OK;
1048
1049         if (count >= 4)
1050                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1051
1052         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1053
1054         while (count > 0)
1055         {
1056                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1057                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1058                 retval = jtagdp_transaction_endcheck(swjdp);
1059                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1060                 count--;
1061                 address++;
1062                 buffer++;
1063         }
1064
1065         return retval;
1066 }
1067
1068 /**
1069  * Initialize a DAP.
1070  *
1071  * @todo Rename this.  We also need an initialization scheme which account
1072  * for SWD transports not just JTAG; that will need to address differences
1073  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1074  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1075  */
1076 int ahbap_debugport_init(struct swjdp_common *swjdp)
1077 {
1078         uint32_t idreg, romaddr, dummy;
1079         uint32_t ctrlstat;
1080         int cnt = 0;
1081         int retval;
1082
1083         LOG_DEBUG(" ");
1084
1085         /* Default MEM-AP setup.
1086          *
1087          * REVISIT AP #0 may be an inappropriate default for this.
1088          * Should we probe, or receve a hint from the caller?
1089          * Presumably we can ignore the possibility of multiple APs.
1090          */
1091         swjdp->apsel = 0;
1092         swjdp->ap_csw_value = -1;
1093         swjdp->ap_tar_value = -1;
1094
1095         /* DP initialization */
1096         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1097         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1098         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1099         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1100
1101         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1102
1103         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1104         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1105         if ((retval = jtag_execute_queue()) != ERROR_OK)
1106                 return retval;
1107
1108         /* Check that we have debug power domains activated */
1109         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1110         {
1111                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1112                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1113                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1114                         return retval;
1115                 alive_sleep(10);
1116         }
1117
1118         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1119         {
1120                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1121                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1122                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1123                         return retval;
1124                 alive_sleep(10);
1125         }
1126
1127         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1128         /* With debug power on we can activate OVERRUN checking */
1129         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1130         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1131         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1132
1133         /*
1134          * REVISIT this isn't actually *initializing* anything in an AP,
1135          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1136          * Should it?  If the ROM address is valid, is this the right
1137          * place to scan the table and do any topology detection?
1138          */
1139         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1140         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1141
1142         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1143                 ", Debug ROM Address 0x%" PRIx32,
1144                 swjdp->apsel, idreg, romaddr);
1145
1146         return ERROR_OK;
1147 }
1148
1149 /* CID interpretation -- see ARM IHI 0029B section 3
1150  * and ARM IHI 0031A table 13-3.
1151  */
1152 static const char *class_description[16] ={
1153         "Reserved", "ROM table", "Reserved", "Reserved",
1154         "Reserved", "Reserved", "Reserved", "Reserved",
1155         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1156         "Reserved", "OptimoDE DESS",
1157                 "Generic IP component", "PrimeCell or System component"
1158 };
1159
1160 static bool
1161 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1162 {
1163         return cid3 == 0xb1 && cid2 == 0x05
1164                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1165 }
1166
1167 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1168 {
1169
1170         uint32_t dbgbase, apid;
1171         int romtable_present = 0;
1172         uint8_t mem_ap;
1173         uint32_t apselold;
1174
1175         apselold = swjdp->apsel;
1176         dap_ap_select(swjdp, apsel);
1177         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1178         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1179         jtagdp_transaction_endcheck(swjdp);
1180         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1181         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1182         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1183         if (apid)
1184         {
1185                 switch (apid&0x0F)
1186                 {
1187                         case 0:
1188                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1189                                 break;
1190                         case 1:
1191                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1192                                 break;
1193                         case 2:
1194                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1195                                 break;
1196                         default:
1197                                 command_print(cmd_ctx, "\tUnknown AP type");
1198                                 break;
1199                 }
1200
1201                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1202                  * not a ROM table ... or have no such components at all.
1203                  */
1204                 if (mem_ap)
1205                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1206                                         dbgbase);
1207         }
1208         else
1209         {
1210                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1211         }
1212
1213         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1214         if (romtable_present)
1215         {
1216                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1217                 uint16_t entry_offset;
1218
1219                 /* bit 16 of apid indicates a memory access port */
1220                 if (dbgbase & 0x02)
1221                         command_print(cmd_ctx, "\tValid ROM table present");
1222                 else
1223                         command_print(cmd_ctx, "\tROM table in legacy format");
1224
1225                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1226                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1227                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1228                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1229                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1230                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1231                 jtagdp_transaction_endcheck(swjdp);
1232                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1233                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1234                                         ", CID2 0x%2.2" PRIx32
1235                                         ", CID1 0x%2.2" PRIx32
1236                                         ", CID0 0x%2.2" PRIx32,
1237                                         cid3, cid2, cid1, cid0);
1238                 if (memtype & 0x01)
1239                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1240                 else
1241                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1242                                         "Dedicated debug bus.");
1243
1244                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1245                 entry_offset = 0;
1246                 do
1247                 {
1248                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1249                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1250                         if (romentry&0x01)
1251                         {
1252                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1253                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1254                                 uint32_t component_start, component_base;
1255                                 unsigned part_num;
1256                                 char *type, *full;
1257
1258                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1259                                                 + (int)(romentry & 0xFFFFF000));
1260                                 mem_ap_read_atomic_u32(swjdp,
1261                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1262                                 mem_ap_read_atomic_u32(swjdp,
1263                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1264                                 mem_ap_read_atomic_u32(swjdp,
1265                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1266                                 mem_ap_read_atomic_u32(swjdp,
1267                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1268                                 mem_ap_read_atomic_u32(swjdp,
1269                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1270                                 mem_ap_read_atomic_u32(swjdp,
1271                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1272                                 mem_ap_read_atomic_u32(swjdp,
1273                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1274                                 mem_ap_read_atomic_u32(swjdp,
1275                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1276                                 mem_ap_read_atomic_u32(swjdp,
1277                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1278                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1279
1280                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1281                                                 ", start address 0x%" PRIx32,
1282                                                 component_base, component_start);
1283                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1284                                                 (int) (c_cid1 >> 4) & 0xf,
1285                                                 /* See ARM IHI 0029B Table 3-3 */
1286                                                 class_description[(c_cid1 >> 4) & 0xf]);
1287
1288                                 /* CoreSight component? */
1289                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1290                                         uint32_t devtype;
1291                                         unsigned minor;
1292                                         char *major = "Reserved", *subtype = "Reserved";
1293
1294                                         mem_ap_read_atomic_u32(swjdp,
1295                                                         (component_base & 0xfffff000) | 0xfcc,
1296                                                         &devtype);
1297                                         minor = (devtype >> 4) & 0x0f;
1298                                         switch (devtype & 0x0f) {
1299                                         case 0:
1300                                                 major = "Miscellaneous";
1301                                                 switch (minor) {
1302                                                 case 0:
1303                                                         subtype = "other";
1304                                                         break;
1305                                                 case 4:
1306                                                         subtype = "Validation component";
1307                                                         break;
1308                                                 }
1309                                                 break;
1310                                         case 1:
1311                                                 major = "Trace Sink";
1312                                                 switch (minor) {
1313                                                 case 0:
1314                                                         subtype = "other";
1315                                                         break;
1316                                                 case 1:
1317                                                         subtype = "Port";
1318                                                         break;
1319                                                 case 2:
1320                                                         subtype = "Buffer";
1321                                                         break;
1322                                                 }
1323                                                 break;
1324                                         case 2:
1325                                                 major = "Trace Link";
1326                                                 switch (minor) {
1327                                                 case 0:
1328                                                         subtype = "other";
1329                                                         break;
1330                                                 case 1:
1331                                                         subtype = "Funnel, router";
1332                                                         break;
1333                                                 case 2:
1334                                                         subtype = "Filter";
1335                                                         break;
1336                                                 case 3:
1337                                                         subtype = "FIFO, buffer";
1338                                                         break;
1339                                                 }
1340                                                 break;
1341                                         case 3:
1342                                                 major = "Trace Source";
1343                                                 switch (minor) {
1344                                                 case 0:
1345                                                         subtype = "other";
1346                                                         break;
1347                                                 case 1:
1348                                                         subtype = "Processor";
1349                                                         break;
1350                                                 case 2:
1351                                                         subtype = "DSP";
1352                                                         break;
1353                                                 case 3:
1354                                                         subtype = "Engine/Coprocessor";
1355                                                         break;
1356                                                 case 4:
1357                                                         subtype = "Bus";
1358                                                         break;
1359                                                 }
1360                                                 break;
1361                                         case 4:
1362                                                 major = "Debug Control";
1363                                                 switch (minor) {
1364                                                 case 0:
1365                                                         subtype = "other";
1366                                                         break;
1367                                                 case 1:
1368                                                         subtype = "Trigger Matrix";
1369                                                         break;
1370                                                 case 2:
1371                                                         subtype = "Debug Auth";
1372                                                         break;
1373                                                 }
1374                                                 break;
1375                                         case 5:
1376                                                 major = "Debug Logic";
1377                                                 switch (minor) {
1378                                                 case 0:
1379                                                         subtype = "other";
1380                                                         break;
1381                                                 case 1:
1382                                                         subtype = "Processor";
1383                                                         break;
1384                                                 case 2:
1385                                                         subtype = "DSP";
1386                                                         break;
1387                                                 case 3:
1388                                                         subtype = "Engine/Coprocessor";
1389                                                         break;
1390                                                 }
1391                                                 break;
1392                                         }
1393                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1394                                                         (unsigned) (devtype & 0xff),
1395                                                         major, subtype);
1396                                         /* REVISIT also show 0xfc8 DevId */
1397                                 }
1398
1399                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1400                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1401                                                         ", CID2 0x%2.2" PRIx32
1402                                                         ", CID1 0x%2.2" PRIx32
1403                                                         ", CID0 0x%2.2" PRIx32,
1404                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1405                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1406                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1407                                                 (int) c_pid4,
1408                                                 (int) c_pid3, (int) c_pid2,
1409                                                 (int) c_pid1, (int) c_pid0);
1410
1411                                 /* Part number interpretations are from Cortex
1412                                  * core specs, the CoreSight components TRM
1413                                  * (ARM DDI 0314H), and ETM specs; also from
1414                                  * chip observation (e.g. TI SDTI).
1415                                  */
1416                                 part_num = c_pid0 & 0xff;
1417                                 part_num |= (c_pid1 & 0x0f) << 8;
1418                                 switch (part_num) {
1419                                 case 0x000:
1420                                         type = "Cortex-M3 NVIC";
1421                                         full = "(Interrupt Controller)";
1422                                         break;
1423                                 case 0x001:
1424                                         type = "Cortex-M3 ITM";
1425                                         full = "(Instrumentation Trace Module)";
1426                                         break;
1427                                 case 0x002:
1428                                         type = "Cortex-M3 DWT";
1429                                         full = "(Data Watchpoint and Trace)";
1430                                         break;
1431                                 case 0x003:
1432                                         type = "Cortex-M3 FBP";
1433                                         full = "(Flash Patch and Breakpoint)";
1434                                         break;
1435                                 case 0x00d:
1436                                         type = "CoreSight ETM11";
1437                                         full = "(Embedded Trace)";
1438                                         break;
1439                                 // case 0x113: what?
1440                                 case 0x120:             /* from OMAP3 memmap */
1441                                         type = "TI SDTI";
1442                                         full = "(System Debug Trace Interface)";
1443                                         break;
1444                                 case 0x343:             /* from OMAP3 memmap */
1445                                         type = "TI DAPCTL";
1446                                         full = "";
1447                                         break;
1448                                 case 0x4e0:
1449                                         type = "Cortex-M3 ETM";
1450                                         full = "(Embedded Trace)";
1451                                         break;
1452                                 case 0x906:
1453                                         type = "Coresight CTI";
1454                                         full = "(Cross Trigger)";
1455                                         break;
1456                                 case 0x907:
1457                                         type = "Coresight ETB";
1458                                         full = "(Trace Buffer)";
1459                                         break;
1460                                 case 0x908:
1461                                         type = "Coresight CSTF";
1462                                         full = "(Trace Funnel)";
1463                                         break;
1464                                 case 0x910:
1465                                         type = "CoreSight ETM9";
1466                                         full = "(Embedded Trace)";
1467                                         break;
1468                                 case 0x912:
1469                                         type = "Coresight TPIU";
1470                                         full = "(Trace Port Interface Unit)";
1471                                         break;
1472                                 case 0x921:
1473                                         type = "Cortex-A8 ETM";
1474                                         full = "(Embedded Trace)";
1475                                         break;
1476                                 case 0x922:
1477                                         type = "Cortex-A8 CTI";
1478                                         full = "(Cross Trigger)";
1479                                         break;
1480                                 case 0x923:
1481                                         type = "Cortex-M3 TPIU";
1482                                         full = "(Trace Port Interface Unit)";
1483                                         break;
1484                                 case 0xc08:
1485                                         type = "Cortex-A8 Debug";
1486                                         full = "(Debug Unit)";
1487                                         break;
1488                                 default:
1489                                         type = "-*- unrecognized -*-";
1490                                         full = "";
1491                                         break;
1492                                 }
1493                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1494                                                 type, full);
1495                         }
1496                         else
1497                         {
1498                                 if (romentry)
1499                                         command_print(cmd_ctx, "\t\tComponent not present");
1500                                 else
1501                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1502                         }
1503                         entry_offset += 4;
1504                 } while (romentry > 0);
1505         }
1506         else
1507         {
1508                 command_print(cmd_ctx, "\tNo ROM table present");
1509         }
1510         dap_ap_select(swjdp, apselold);
1511
1512         return ERROR_OK;
1513 }
1514
1515 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1516 {
1517         uint32_t apsel, apselsave, baseaddr;
1518         int retval;
1519
1520         apselsave = swjdp->apsel;
1521         switch (CMD_ARGC) {
1522         case 0:
1523                 apsel = swjdp->apsel;
1524                 break;
1525         case 1:
1526                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1527                 break;
1528         default:
1529                 return ERROR_COMMAND_SYNTAX_ERROR;
1530         }
1531
1532         if (apselsave != apsel)
1533                 dap_ap_select(swjdp, apsel);
1534
1535         /* NOTE:  assumes we're talking to a MEM-AP, which
1536          * has a base address.  There are other kinds of AP,
1537          * though they're not common for now.  This should
1538          * use the ID register to verify it's a MEM-AP.
1539          */
1540         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1541         retval = jtagdp_transaction_endcheck(swjdp);
1542         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1543
1544         if (apselsave != apsel)
1545                 dap_ap_select(swjdp, apselsave);
1546
1547         return retval;
1548 }
1549
1550 DAP_COMMAND_HANDLER(dap_memaccess_command)
1551 {
1552         uint32_t memaccess_tck;
1553
1554         switch (CMD_ARGC) {
1555         case 0:
1556                 memaccess_tck = swjdp->memaccess_tck;
1557                 break;
1558         case 1:
1559                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1560                 break;
1561         default:
1562                 return ERROR_COMMAND_SYNTAX_ERROR;
1563         }
1564         swjdp->memaccess_tck = memaccess_tck;
1565
1566         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1567                         swjdp->memaccess_tck);
1568
1569         return ERROR_OK;
1570 }
1571
1572 DAP_COMMAND_HANDLER(dap_apsel_command)
1573 {
1574         uint32_t apsel, apid;
1575         int retval;
1576
1577         switch (CMD_ARGC) {
1578         case 0:
1579                 apsel = 0;
1580                 break;
1581         case 1:
1582                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1583                 break;
1584         default:
1585                 return ERROR_COMMAND_SYNTAX_ERROR;
1586         }
1587
1588         dap_ap_select(swjdp, apsel);
1589         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1590         retval = jtagdp_transaction_endcheck(swjdp);
1591         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1592                         apsel, apid);
1593
1594         return retval;
1595 }
1596
1597 DAP_COMMAND_HANDLER(dap_apid_command)
1598 {
1599         uint32_t apsel, apselsave, apid;
1600         int retval;
1601
1602         apselsave = swjdp->apsel;
1603         switch (CMD_ARGC) {
1604         case 0:
1605                 apsel = swjdp->apsel;
1606                 break;
1607         case 1:
1608                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1609                 break;
1610         default:
1611                 return ERROR_COMMAND_SYNTAX_ERROR;
1612         }
1613
1614         if (apselsave != apsel)
1615                 dap_ap_select(swjdp, apsel);
1616
1617         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1618         retval = jtagdp_transaction_endcheck(swjdp);
1619         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1620         if (apselsave != apsel)
1621                 dap_ap_select(swjdp, apselsave);
1622
1623         return retval;
1624 }