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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   This program is free software; you can redistribute it and/or modify  *
  14  *   it under the terms of the GNU General Public License as published by  *
  15  *   the Free Software Foundation; either version 2 of the License, or     *
  16  *   (at your option) any later version.                                   *
  17  *                                                                         *
  18  *   This program is distributed in the hope that it will be useful,       *
  19  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  20  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  21  *   GNU General Public License for more details.                          *
  22  *                                                                         *
  23  *   You should have received a copy of the GNU General Public License     *
  24  *   along with this program; if not, write to the                         *
  25  *   Free Software Foundation, Inc.,                                       *
  26  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  27  ***************************************************************************/
  28
  29 /**
  30  * @file
  31  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  32  * debugging architecture.  Compared with previous versions, this includes
  33  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  34  * transport, and focusses on memory mapped resources as defined by the
  35  * CoreSight architecture.
  36  *
  37  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  38  * basic components:  a Debug Port (DP) transporting messages to and from a
  39  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  40  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  41  * One uses only SWD for communication, and is called SW-DP.  The third can
  42  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  43  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  44  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  45  *
  46  * This programming interface allows DAP pipelined operations through a
  47  * transaction queue.  This primarily affects AP operations (such as using
  48  * a MEM-AP to access memory or registers).  If the current transaction has
  49  * not finished by the time the next one must begin, and the ORUNDETECT bit
  50  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  51  * further AP operations will fail.  There are two basic methods to avoid
  52  * such overrun errors.  One involves polling for status instead of using
  53  * transaction piplining.  The other involves adding delays to ensure the
  54  * AP has enough time to complete one operation before starting the next
  55  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  56  */
  57
  58 /*
  59  * Relevant specifications from ARM include:
  60  *
  61  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  62  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  63  *
  64  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  65  * Cortex-M3(tm) TRM, ARM DDI 0337G
  66  */
  67
  68 #ifdef HAVE_CONFIG_H
  69 #include "config.h"
  70 #endif
  71
  72 #include "arm_adi_v5.h"
  73 #include <helper/time_support.h>
  74
  75
  76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  77
  78 /*
  79         uint32_t tar_block_size(uint32_t address)
  80         Return the largest block starting at address that does not cross a tar block size alignment boundary
  81 */
  82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  83 {
  84         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  85 }
  86
  87 /***************************************************************************
  88  *                                                                         *
  89  * DPACC and APACC scanchain access through JTAG-DP                        *
  90  *                                                                         *
  91 ***************************************************************************/
  92
  93 /**
  94  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  95  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  96  * discusses operations which access these registers.
  97  *
  98  * Note that only one scan is performed.  If RnW is set, a separate scan
  99  * will be needed to collect the data which was read; the "invalue" collects
 100  * the posted result of a preceding operation, not the current one.
 101  *
 102  * @param swjdp the DAP
 103  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 104  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 105  *      SELECT register has more addressing bits.
 106  * @param RnW false iff outvalue will be written to the DP or AP
 107  * @param outvalue points to a 32-bit (little-endian) integer
 108  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 109  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 110  */
 111 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 112                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 113                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 114 {
 115         struct arm_jtag *jtag_info = swjdp->jtag_info;
 116         struct scan_field fields[2];
 117         uint8_t out_addr_buf;
 118
 119         jtag_set_end_state(TAP_IDLE);
 120         arm_jtag_set_instr(jtag_info, instr, NULL);
 121
 122         /* Scan out a read or write operation using some DP or AP register.
 123          * For APACC access with any sticky error flag set, this is discarded.
 124          */
 125         fields[0].tap = jtag_info->tap;
 126         fields[0].num_bits = 3;
 127         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 128         fields[0].out_value = &out_addr_buf;
 129         fields[0].in_value = ack;
 130
 131         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 132          * complete; data we write is discarded, data we read is unpredictable.
 133          * When overrun detect is active, STICKYORUN is set.
 134          */
 135
 136         fields[1].tap = jtag_info->tap;
 137         fields[1].num_bits = 32;
 138         fields[1].out_value = outvalue;
 139         fields[1].in_value = invalue;
 140
 141         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 142
 143         /* Add specified number of tck clocks after starting memory bus
 144          * access, giving the hardware time to complete the access.
 145          * They provide more time for the (MEM) AP to complete the read ...
 146          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 147          */
 148         if ((instr == JTAG_DP_APACC)
 149                         && ((reg_addr == AP_REG_DRW)
 150                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 151                         && (swjdp->memaccess_tck != 0))
 152                 jtag_add_runtest(swjdp->memaccess_tck,
 153                                 jtag_set_end_state(TAP_IDLE));
 154
 155         return jtag_get_error();
 156 }
 157
 158 /**
 159  * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
 160  * This is exactly like adi_jtag_dp_scan(), except that endianness
 161  * conversions are performed (so the types of invalue and outvalue
 162  * must be different).
 163  */
 164 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 165                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 166                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 167 {
 168         uint8_t out_value_buf[4];
 169         int retval;
 170
 171         buf_set_u32(out_value_buf, 0, 32, outvalue);
 172
 173         retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
 174                         out_value_buf, (uint8_t *)invalue, ack);
 175         if (retval != ERROR_OK)
 176                 return retval;
 177
 178         if (invalue)
 179                 jtag_add_callback(arm_le_to_h_u32,
 180                                 (jtag_callback_data_t) invalue);
 181
 182         return retval;
 183 }
 184
 185 /**
 186  * Utility to write AP registers.
 187  */
 188 static inline int adi_jtag_ap_write_check(struct swjdp_common *dap,
 189                 uint8_t reg_addr, uint8_t *outvalue)
 190 {
 191         return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
 192                         outvalue, NULL, NULL);
 193 }
 194
 195 static int adi_jtag_scan_inout_check_u32(struct swjdp_common *swjdp,
 196                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 197                 uint32_t outvalue, uint32_t *invalue)
 198 {
 199         int retval;
 200
 201         /* Issue the read or write */
 202         retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
 203                         RnW, outvalue, NULL, NULL);
 204         if (retval != ERROR_OK)
 205                 return retval;
 206
 207         /* For reads,  collect posted value; RDBUFF has no other effect.
 208          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 209          */
 210         if ((RnW == DPAP_READ) && (invalue != NULL))
 211                 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 212                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 213         return retval;
 214 }
 215
 216 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 217 {
 218         int retval;
 219         uint32_t ctrlstat;
 220
 221         /* too expensive to call keep_alive() here */
 222
 223 #if 0
 224         /* Danger!!!! BROKEN!!!! */
 225         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 226                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 227         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 228         R956 introduced the check on return value here and now Michael Schwingen reports
 229         that this code no longer works....
 230
 231         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 232         */
 233         if ((retval = jtag_execute_queue()) != ERROR_OK)
 234         {
 235                 LOG_ERROR("BUG: Why does this fail the first time????");
 236         }
 237         /* Why??? second time it works??? */
 238 #endif
 239
 240         /* Post CTRL/STAT read; discard any previous posted read value
 241          * but collect its ACK status.
 242          */
 243         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 244                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 245         if ((retval = jtag_execute_queue()) != ERROR_OK)
 246                 return retval;
 247
 248         swjdp->ack = swjdp->ack & 0x7;
 249
 250         /* common code path avoids calling timeval_ms() */
 251         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 252         {
 253                 long long then = timeval_ms();
 254
 255                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 256                 {
 257                         if (swjdp->ack == JTAG_ACK_WAIT)
 258                         {
 259                                 if ((timeval_ms()-then) > 1000)
 260                                 {
 261                                         /* NOTE:  this would be a good spot
 262                                          * to use JTAG_DP_ABORT.
 263                                          */
 264                                         LOG_WARNING("Timeout (1000ms) waiting "
 265                                                 "for ACK=OK/FAULT "
 266                                                 "in JTAG-DP transaction");
 267                                         return ERROR_JTAG_DEVICE_ERROR;
 268                                 }
 269                         }
 270                         else
 271                         {
 272                                 LOG_WARNING("Invalid ACK %#x "
 273                                                 "in JTAG-DP transaction",
 274                                                 swjdp->ack);
 275                                 return ERROR_JTAG_DEVICE_ERROR;
 276                         }
 277
 278                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 279                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 280                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 281                                 return retval;
 282                         swjdp->ack = swjdp->ack & 0x7;
 283                 }
 284         }
 285
 286         /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 287
 288         /* Check for STICKYERR and STICKYORUN */
 289         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 290         {
 291                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 292                 /* Check power to debug regions */
 293                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 294                          ahbap_debugport_init(swjdp);
 295                 else
 296                 {
 297                         uint32_t mem_ap_csw, mem_ap_tar;
 298
 299                         /* Maybe print information about last intended
 300                          * MEM-AP access; but not if autoincrementing.
 301                          * *Real* CSW and TAR values are always shown.
 302                          */
 303                         if (swjdp->ap_tar_value != (uint32_t) -1)
 304                                 LOG_DEBUG("MEM-AP Cached values: "
 305                                         "ap_bank 0x%" PRIx32
 306                                         ", ap_csw 0x%" PRIx32
 307                                         ", ap_tar 0x%" PRIx32,
 308                                         swjdp->ap_bank_value,
 309                                         swjdp->ap_csw_value,
 310                                         swjdp->ap_tar_value);
 311
 312                         if (ctrlstat & SSTICKYORUN)
 313                                 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
 314                                         "memaccess, or reduce jtag speed");
 315
 316                         if (ctrlstat & SSTICKYERR)
 317                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 318
 319                         /* Clear Sticky Error Bits */
 320                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 321                                         DP_CTRL_STAT, DPAP_WRITE,
 322                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 323                                                 | SSTICKYERR, NULL);
 324                         adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 325                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 326                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 327                                 return retval;
 328
 329                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 330
 331                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 332                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 333                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 334                                 return retval;
 335                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 336                                         PRIx32, mem_ap_csw, mem_ap_tar);
 337
 338                 }
 339                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 340                         return retval;
 341                 return ERROR_JTAG_DEVICE_ERROR;
 342         }
 343
 344         return ERROR_OK;
 345 }
 346
 347 /***************************************************************************
 348  *                                                                         *
 349  * DP and MEM-AP  register access  through APACC and DPACC                 *
 350  *                                                                         *
 351 ***************************************************************************/
 352
 353 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 354                 uint32_t value, uint8_t reg_addr)
 355 {
 356         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 357                         reg_addr, DPAP_WRITE, value, NULL);
 358 }
 359
 360 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 361                 uint32_t *value, uint8_t reg_addr)
 362 {
 363         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 364                         reg_addr, DPAP_READ, 0, value);
 365 }
 366
 367 /**
 368  * Select one of the APs connected to the specified DAP.  The
 369  * selection is implicitly used with future AP transactions.
 370  * This is a NOP if the specified AP is already selected.
 371  *
 372  * @param swjdp The DAP
 373  * @param apsel Number of the AP to (implicitly) use with further
 374  *      transactions.  This normally identifies a MEM-AP.
 375  */
 376 void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 377 {
 378         uint32_t select = (apsel << 24) & 0xFF000000;
 379
 380         if (select != swjdp->apsel)
 381         {
 382                 swjdp->apsel = select;
 383                 /* Switching AP invalidates cached values.
 384                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 385                  */
 386                 swjdp->ap_bank_value = -1;
 387                 swjdp->ap_csw_value = -1;
 388                 swjdp->ap_tar_value = -1;
 389         }
 390 }
 391
 392 /** Select the AP register bank matching bits 7:4 of ap_reg. */
 393 static int dap_ap_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 394 {
 395         uint32_t select = (ap_reg & 0x000000F0);
 396
 397         if (select != swjdp->ap_bank_value)
 398         {
 399                 swjdp->ap_bank_value = select;
 400                 select |= swjdp->apsel;
 401                 return dap_dp_write_reg(swjdp, select, DP_SELECT);
 402         } else
 403                 return ERROR_OK;
 404 }
 405
 406 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 407                 uint32_t reg_addr, uint8_t *out_value_buf)
 408 {
 409         int retval;
 410
 411         retval = dap_ap_bankselect(swjdp, reg_addr);
 412         if (retval != ERROR_OK)
 413                 return retval;
 414
 415         return adi_jtag_ap_write_check(swjdp, reg_addr, out_value_buf);
 416 }
 417
 418 /**
 419  * Asynchronous (queued) AP register write.
 420  *
 421  * @param swjdp The DAP whose currently selected AP will be written.
 422  * @param reg_addr Eight bit AP register address.
 423  * @param value Word to be written at reg_addr
 424  *
 425  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 426  */
 427 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 428                 uint32_t reg_addr, uint32_t value)
 429 {
 430         uint8_t out_value_buf[4];
 431
 432         buf_set_u32(out_value_buf, 0, 32, value);
 433         return dap_ap_write_reg(swjdp,
 434                         reg_addr, out_value_buf);
 435 }
 436
 437 /**
 438  * Asynchronous (queued) AP register eread.
 439  *
 440  * @param swjdp The DAP whose currently selected AP will be read.
 441  * @param reg_addr Eight bit AP register address.
 442  * @param value Points to where the 32-bit (little-endian) word will be stored.
 443  *
 444  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 445  */
 446 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 447                 uint32_t reg_addr, uint32_t *value)
 448 {
 449         int retval;
 450
 451         retval = dap_ap_bankselect(swjdp, reg_addr);
 452         if (retval != ERROR_OK)
 453                 return retval;
 454
 455         return adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 456                         DPAP_READ, 0, value);
 457 }
 458
 459 /**
 460  * Queue transactions setting up transfer parameters for the
 461  * currently selected MEM-AP.
 462  *
 463  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 464  * initiate data reads or writes using memory or peripheral addresses.
 465  * If the CSW is configured for it, the TAR may be automatically
 466  * incremented after each transfer.
 467  *
 468  * @todo Rename to reflect it being specifically a MEM-AP function.
 469  *
 470  * @param swjdp The DAP connected to the MEM-AP.
 471  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 472  *      matches the cached value, the register is not changed.
 473  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 474  *      matches the cached address, the register is not changed.
 475  *
 476  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 477  */
 478 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 479 {
 480         int retval;
 481
 482         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 483         if (csw != swjdp->ap_csw_value)
 484         {
 485                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 486                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 487                 if (retval != ERROR_OK)
 488                         return retval;
 489                 swjdp->ap_csw_value = csw;
 490         }
 491         if (tar != swjdp->ap_tar_value)
 492         {
 493                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 494                 retval = dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 495                 if (retval != ERROR_OK)
 496                         return retval;
 497                 swjdp->ap_tar_value = tar;
 498         }
 499         /* Disable TAR cache when autoincrementing */
 500         if (csw & CSW_ADDRINC_MASK)
 501                 swjdp->ap_tar_value = -1;
 502         return ERROR_OK;
 503 }
 504
 505 /**
 506  * Asynchronous (queued) read of a word from memory or a system register.
 507  *
 508  * @param swjdp The DAP connected to the MEM-AP performing the read.
 509  * @param address Address of the 32-bit word to read; it must be
 510  *      readable by the currently selected MEM-AP.
 511  * @param value points to where the word will be stored when the
 512  *      transaction queue is flushed (assuming no errors).
 513  *
 514  * @return ERROR_OK for success.  Otherwise a fault code.
 515  */
 516 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
 517                 uint32_t *value)
 518 {
 519         int retval;
 520
 521         /* Use banked addressing (REG_BDx) to avoid some link traffic
 522          * (updating TAR) when reading several consecutive addresses.
 523          */
 524         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 525                         address & 0xFFFFFFF0);
 526         if (retval != ERROR_OK)
 527                 return retval;
 528
 529         return dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 530 }
 531
 532 /**
 533  * Synchronous read of a word from memory or a system register.
 534  * As a side effect, this flushes any queued transactions.
 535  *
 536  * @param swjdp The DAP connected to the MEM-AP performing the read.
 537  * @param address Address of the 32-bit word to read; it must be
 538  *      readable by the currently selected MEM-AP.
 539  * @param value points to where the result will be stored.
 540  *
 541  * @return ERROR_OK for success; *value holds the result.
 542  * Otherwise a fault code.
 543  */
 544 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 545                 uint32_t *value)
 546 {
 547         int retval;
 548
 549         retval = mem_ap_read_u32(swjdp, address, value);
 550         if (retval != ERROR_OK)
 551                 return retval;
 552
 553         return jtagdp_transaction_endcheck(swjdp);
 554 }
 555
 556 /**
 557  * Asynchronous (queued) write of a word to memory or a system register.
 558  *
 559  * @param swjdp The DAP connected to the MEM-AP.
 560  * @param address Address to be written; it must be writable by
 561  *      the currently selected MEM-AP.
 562  * @param value Word that will be written to the address when transaction
 563  *      queue is flushed (assuming no errors).
 564  *
 565  * @return ERROR_OK for success.  Otherwise a fault code.
 566  */
 567 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
 568                 uint32_t value)
 569 {
 570         int retval;
 571
 572         /* Use banked addressing (REG_BDx) to avoid some link traffic
 573          * (updating TAR) when writing several consecutive addresses.
 574          */
 575         retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
 576                         address & 0xFFFFFFF0);
 577         if (retval != ERROR_OK)
 578                 return retval;
 579
 580         return dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC),
 581                         value);
 582 }
 583
 584 /**
 585  * Synchronous write of a word to memory or a system register.
 586  * As a side effect, this flushes any queued transactions.
 587  *
 588  * @param swjdp The DAP connected to the MEM-AP.
 589  * @param address Address to be written; it must be writable by
 590  *      the currently selected MEM-AP.
 591  * @param value Word that will be written.
 592  *
 593  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 594  */
 595 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
 596                 uint32_t value)
 597 {
 598         int retval = mem_ap_write_u32(swjdp, address, value);
 599
 600         if (retval != ERROR_OK)
 601                 return retval;
 602
 603         return jtagdp_transaction_endcheck(swjdp);
 604 }
 605
 606 /*****************************************************************************
 607 *                                                                            *
 608 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 609 *                                                                            *
 610 * Write a buffer in target order (little endian)                             *
 611 *                                                                            *
 612 *****************************************************************************/
 613 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 614 {
 615         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 616         uint32_t adr = address;
 617         uint8_t* pBuffer = buffer;
 618
 619         count >>= 2;
 620         wcount = count;
 621
 622         /* if we have an unaligned access - reorder data */
 623         if (adr & 0x3u)
 624         {
 625                 for (writecount = 0; writecount < count; writecount++)
 626                 {
 627                         int i;
 628                         uint32_t outvalue;
 629                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 630
 631                         for (i = 0; i < 4; i++)
 632                         {
 633                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 634                                 outvalue >>= 8;
 635                                 adr++;
 636                         }
 637                         pBuffer += sizeof(uint32_t);
 638                 }
 639         }
 640
 641         while (wcount > 0)
 642         {
 643                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 644                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 645                 if (wcount < blocksize)
 646                         blocksize = wcount;
 647
 648                 /* handle unaligned data at 4k boundary */
 649                 if (blocksize == 0)
 650                         blocksize = 1;
 651
 652                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 653
 654                 for (writecount = 0; writecount < blocksize; writecount++)
 655                 {
 656                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 657                 }
 658
 659                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 660                 {
 661                         wcount = wcount - blocksize;
 662                         address = address + 4 * blocksize;
 663                         buffer = buffer + 4 * blocksize;
 664                 }
 665                 else
 666                 {
 667                         errorcount++;
 668                 }
 669
 670                 if (errorcount > 1)
 671                 {
 672                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 673                         return ERROR_JTAG_DEVICE_ERROR;
 674                 }
 675         }
 676
 677         return retval;
 678 }
 679
 680 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 681                 uint8_t *buffer, int count, uint32_t address)
 682 {
 683         int retval = ERROR_OK;
 684         int wcount, blocksize, writecount, i;
 685
 686         wcount = count >> 1;
 687
 688         while (wcount > 0)
 689         {
 690                 int nbytes;
 691
 692                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 693                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 694
 695                 if (wcount < blocksize)
 696                         blocksize = wcount;
 697
 698                 /* handle unaligned data at 4k boundary */
 699                 if (blocksize == 0)
 700                         blocksize = 1;
 701
 702                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 703                 writecount = blocksize;
 704
 705                 do
 706                 {
 707                         nbytes = MIN((writecount << 1), 4);
 708
 709                         if (nbytes < 4)
 710                         {
 711                                 if (mem_ap_write_buf_u16(swjdp, buffer,
 712                                                 nbytes, address) != ERROR_OK)
 713                                 {
 714                                         LOG_WARNING("Block write error address "
 715                                                 "0x%" PRIx32 ", count 0x%x",
 716                                                 address, count);
 717                                         return ERROR_JTAG_DEVICE_ERROR;
 718                                 }
 719
 720                                 address += nbytes >> 1;
 721                         }
 722                         else
 723                         {
 724                                 uint32_t outvalue;
 725                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 726
 727                                 for (i = 0; i < nbytes; i++)
 728                                 {
 729                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 730                                         outvalue >>= 8;
 731                                         address++;
 732                                 }
 733
 734                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 735                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 736                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 737                                 {
 738                                         LOG_WARNING("Block write error address "
 739                                                 "0x%" PRIx32 ", count 0x%x",
 740                                                 address, count);
 741                                         return ERROR_JTAG_DEVICE_ERROR;
 742                                 }
 743                         }
 744
 745                         buffer += nbytes >> 1;
 746                         writecount -= nbytes >> 1;
 747
 748                 } while (writecount);
 749                 wcount -= blocksize;
 750         }
 751
 752         return retval;
 753 }
 754
 755 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 756 {
 757         int retval = ERROR_OK;
 758
 759         if (count >= 4)
 760                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 761
 762         while (count > 0)
 763         {
 764                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 765                 uint16_t svalue;
 766                 memcpy(&svalue, buffer, sizeof(uint16_t));
 767                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 768                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 769                 retval = jtagdp_transaction_endcheck(swjdp);
 770                 count -= 2;
 771                 address += 2;
 772                 buffer += 2;
 773         }
 774
 775         return retval;
 776 }
 777
 778 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 779                 uint8_t *buffer, int count, uint32_t address)
 780 {
 781         int retval = ERROR_OK;
 782         int wcount, blocksize, writecount, i;
 783
 784         wcount = count;
 785
 786         while (wcount > 0)
 787         {
 788                 int nbytes;
 789
 790                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 791                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 792
 793                 if (wcount < blocksize)
 794                         blocksize = wcount;
 795
 796                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 797                 writecount = blocksize;
 798
 799                 do
 800                 {
 801                         nbytes = MIN(writecount, 4);
 802
 803                         if (nbytes < 4)
 804                         {
 805                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 806                                 {
 807                                         LOG_WARNING("Block write error address "
 808                                                 "0x%" PRIx32 ", count 0x%x",
 809                                                 address, count);
 810                                         return ERROR_JTAG_DEVICE_ERROR;
 811                                 }
 812
 813                                 address += nbytes;
 814                         }
 815                         else
 816                         {
 817                                 uint32_t outvalue;
 818                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 819
 820                                 for (i = 0; i < nbytes; i++)
 821                                 {
 822                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 823                                         outvalue >>= 8;
 824                                         address++;
 825                                 }
 826
 827                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 828                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 829                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 830                                 {
 831                                         LOG_WARNING("Block write error address "
 832                                                 "0x%" PRIx32 ", count 0x%x",
 833                                                 address, count);
 834                                         return ERROR_JTAG_DEVICE_ERROR;
 835                                 }
 836                         }
 837
 838                         buffer += nbytes;
 839                         writecount -= nbytes;
 840
 841                 } while (writecount);
 842                 wcount -= blocksize;
 843         }
 844
 845         return retval;
 846 }
 847
 848 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 849 {
 850         int retval = ERROR_OK;
 851
 852         if (count >= 4)
 853                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 854
 855         while (count > 0)
 856         {
 857                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 858                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 859                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 860                 retval = jtagdp_transaction_endcheck(swjdp);
 861                 count--;
 862                 address++;
 863                 buffer++;
 864         }
 865
 866         return retval;
 867 }
 868
 869 /**
 870  * Synchronously read a block of 32-bit words into a buffer
 871  * @param swjdp The DAP connected to the MEM-AP.
 872  * @param buffer where the words will be stored (in host byte order).
 873  * @param count How many words to read.
 874  * @param address Memory address from which to read words; all the
 875  *      words must be readable by the currently selected MEM-AP.
 876  */
 877 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer,
 878                 int count, uint32_t address)
 879 {
 880         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 881         uint32_t adr = address;
 882         uint8_t* pBuffer = buffer;
 883
 884         count >>= 2;
 885         wcount = count;
 886
 887         while (wcount > 0)
 888         {
 889                 /* Adjust to read blocks within boundaries aligned to the
 890                  * TAR autoincrement size (at least 2^10).  Autoincrement
 891                  * mode avoids an extra per-word roundtrip to update TAR.
 892                  */
 893                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
 894                                 address);
 895                 if (wcount < blocksize)
 896                         blocksize = wcount;
 897
 898                 /* handle unaligned data at 4k boundary */
 899                 if (blocksize == 0)
 900                         blocksize = 1;
 901
 902                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
 903                                 address);
 904
 905                 /* Scan out first read */
 906                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 907                                 DPAP_READ, 0, NULL, NULL);
 908                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 909                 {
 910                         /* Scan out next read; scan in posted value for the
 911                          * previous one.  Assumes read is acked "OK/FAULT",
 912                          * and CTRL_STAT says that meant "OK".
 913                          */
 914                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 915                                         DPAP_READ, 0, buffer + 4 * readcount,
 916                                         &swjdp->ack);
 917                 }
 918
 919                 /* Scan in last posted value; RDBUFF has no other effect,
 920                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 921                  */
 922                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 923                                 DPAP_READ, 0, buffer + 4 * readcount,
 924                                 &swjdp->ack);
 925                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 926                 {
 927                         wcount = wcount - blocksize;
 928                         address += 4 * blocksize;
 929                         buffer += 4 * blocksize;
 930                 }
 931                 else
 932                 {
 933                         errorcount++;
 934                 }
 935
 936                 if (errorcount > 1)
 937                 {
 938                         LOG_WARNING("Block read error address 0x%" PRIx32
 939                                 ", count 0x%x", address, count);
 940                         return ERROR_JTAG_DEVICE_ERROR;
 941                 }
 942         }
 943
 944         /* if we have an unaligned access - reorder data */
 945         if (adr & 0x3u)
 946         {
 947                 for (readcount = 0; readcount < count; readcount++)
 948                 {
 949                         int i;
 950                         uint32_t data;
 951                         memcpy(&data, pBuffer, sizeof(uint32_t));
 952
 953                         for (i = 0; i < 4; i++)
 954                         {
 955                                 *((uint8_t*)pBuffer) =
 956                                                 (data >> 8 * (adr & 0x3));
 957                                 pBuffer++;
 958                                 adr++;
 959                         }
 960                 }
 961         }
 962
 963         return retval;
 964 }
 965
 966 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 967                 uint8_t *buffer, int count, uint32_t address)
 968 {
 969         uint32_t invalue;
 970         int retval = ERROR_OK;
 971         int wcount, blocksize, readcount, i;
 972
 973         wcount = count >> 1;
 974
 975         while (wcount > 0)
 976         {
 977                 int nbytes;
 978
 979                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 980                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 981                 if (wcount < blocksize)
 982                         blocksize = wcount;
 983
 984                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 985
 986                 /* handle unaligned data at 4k boundary */
 987                 if (blocksize == 0)
 988                         blocksize = 1;
 989                 readcount = blocksize;
 990
 991                 do
 992                 {
 993                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 994                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 995                         {
 996                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 997                                 return ERROR_JTAG_DEVICE_ERROR;
 998                         }
 999
1000                         nbytes = MIN((readcount << 1), 4);
1001
1002                         for (i = 0; i < nbytes; i++)
1003                         {
1004                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1005                                 buffer++;
1006                                 address++;
1007                         }
1008
1009                         readcount -= (nbytes >> 1);
1010                 } while (readcount);
1011                 wcount -= blocksize;
1012         }
1013
1014         return retval;
1015 }
1016
1017 /**
1018  * Synchronously read a block of 16-bit halfwords into a buffer
1019  * @param swjdp The DAP connected to the MEM-AP.
1020  * @param buffer where the halfwords will be stored (in host byte order).
1021  * @param count How many halfwords to read.
1022  * @param address Memory address from which to read words; all the
1023  *      words must be readable by the currently selected MEM-AP.
1024  */
1025 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer,
1026                 int count, uint32_t address)
1027 {
1028         uint32_t invalue, i;
1029         int retval = ERROR_OK;
1030
1031         if (count >= 4)
1032                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
1033
1034         while (count > 0)
1035         {
1036                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
1037                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1038                 retval = jtagdp_transaction_endcheck(swjdp);
1039                 if (address & 0x1)
1040                 {
1041                         for (i = 0; i < 2; i++)
1042                         {
1043                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1044                                 buffer++;
1045                                 address++;
1046                         }
1047                 }
1048                 else
1049                 {
1050                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
1051                         memcpy(buffer, &svalue, sizeof(uint16_t));
1052                         address += 2;
1053                         buffer += 2;
1054                 }
1055                 count -= 2;
1056         }
1057
1058         return retval;
1059 }
1060
1061 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1062  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1063  *
1064  * The solution is to arrange for a large out/in scan in this loop and
1065  * and convert data afterwards.
1066  */
1067 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
1068                 uint8_t *buffer, int count, uint32_t address)
1069 {
1070         uint32_t invalue;
1071         int retval = ERROR_OK;
1072         int wcount, blocksize, readcount, i;
1073
1074         wcount = count;
1075
1076         while (wcount > 0)
1077         {
1078                 int nbytes;
1079
1080                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1081                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1082
1083                 if (wcount < blocksize)
1084                         blocksize = wcount;
1085
1086                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1087                 readcount = blocksize;
1088
1089                 do
1090                 {
1091                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1092                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1093                         {
1094                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1095                                 return ERROR_JTAG_DEVICE_ERROR;
1096                         }
1097
1098                         nbytes = MIN(readcount, 4);
1099
1100                         for (i = 0; i < nbytes; i++)
1101                         {
1102                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1103                                 buffer++;
1104                                 address++;
1105                         }
1106
1107                         readcount -= nbytes;
1108                 } while (readcount);
1109                 wcount -= blocksize;
1110         }
1111
1112         return retval;
1113 }
1114
1115 /**
1116  * Synchronously read a block of bytes into a buffer
1117  * @param swjdp The DAP connected to the MEM-AP.
1118  * @param buffer where the bytes will be stored.
1119  * @param count How many bytes to read.
1120  * @param address Memory address from which to read data; all the
1121  *      data must be readable by the currently selected MEM-AP.
1122  */
1123 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer,
1124                 int count, uint32_t address)
1125 {
1126         uint32_t invalue;
1127         int retval = ERROR_OK;
1128
1129         if (count >= 4)
1130                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1131
1132         while (count > 0)
1133         {
1134                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1135                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1136                 retval = jtagdp_transaction_endcheck(swjdp);
1137                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1138                 count--;
1139                 address++;
1140                 buffer++;
1141         }
1142
1143         return retval;
1144 }
1145
1146 /**
1147  * Initialize a DAP.  This sets up the power domains, prepares the DP
1148  * for further use, and arranges to use AP #0 for all AP operations
1149  * until dap_ap-select() changes that policy.
1150  *
1151  * @param swjdp The DAP being initialized.
1152  *
1153  * @todo Rename this.  We also need an initialization scheme which account
1154  * for SWD transports not just JTAG; that will need to address differences
1155  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1156  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1157  */
1158 int ahbap_debugport_init(struct swjdp_common *swjdp)
1159 {
1160         uint32_t idreg, romaddr, dummy;
1161         uint32_t ctrlstat;
1162         int cnt = 0;
1163         int retval;
1164
1165         LOG_DEBUG(" ");
1166
1167         /* Default MEM-AP setup.
1168          *
1169          * REVISIT AP #0 may be an inappropriate default for this.
1170          * Should we probe, or take a hint from the caller?
1171          * Presumably we can ignore the possibility of multiple APs.
1172          */
1173         swjdp->apsel = !0;
1174         dap_ap_select(swjdp, 0);
1175
1176         /* DP initialization */
1177         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1178         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1179         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1180
1181         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1182
1183         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1184         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1185         if ((retval = jtag_execute_queue()) != ERROR_OK)
1186                 return retval;
1187
1188         /* Check that we have debug power domains activated */
1189         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1190         {
1191                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1192                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1193                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1194                         return retval;
1195                 alive_sleep(10);
1196         }
1197
1198         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1199         {
1200                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1201                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1202                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1203                         return retval;
1204                 alive_sleep(10);
1205         }
1206
1207         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1208         /* With debug power on we can activate OVERRUN checking */
1209         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1210         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1211         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1212
1213         /*
1214          * REVISIT this isn't actually *initializing* anything in an AP,
1215          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1216          * Should it?  If the ROM address is valid, is this the right
1217          * place to scan the table and do any topology detection?
1218          */
1219         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1220         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1221
1222         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1223                 ", Debug ROM Address 0x%" PRIx32,
1224                 swjdp->apsel, idreg, romaddr);
1225
1226         return ERROR_OK;
1227 }
1228
1229 /* CID interpretation -- see ARM IHI 0029B section 3
1230  * and ARM IHI 0031A table 13-3.
1231  */
1232 static const char *class_description[16] ={
1233         "Reserved", "ROM table", "Reserved", "Reserved",
1234         "Reserved", "Reserved", "Reserved", "Reserved",
1235         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1236         "Reserved", "OptimoDE DESS",
1237                 "Generic IP component", "PrimeCell or System component"
1238 };
1239
1240 static bool
1241 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1242 {
1243         return cid3 == 0xb1 && cid2 == 0x05
1244                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1245 }
1246
1247 int dap_info_command(struct command_context *cmd_ctx,
1248                 struct swjdp_common *swjdp, int apsel)
1249 {
1250
1251         uint32_t dbgbase, apid;
1252         int romtable_present = 0;
1253         uint8_t mem_ap;
1254         uint32_t apselold;
1255
1256         /* AP address is in bits 31:24 of DP_SELECT */
1257         if (apsel >= 256)
1258                 return ERROR_INVALID_ARGUMENTS;
1259
1260         apselold = swjdp->apsel;
1261         dap_ap_select(swjdp, apsel);
1262         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1263         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1264         jtagdp_transaction_endcheck(swjdp);
1265         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1266         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1267         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1268         if (apid)
1269         {
1270                 switch (apid&0x0F)
1271                 {
1272                         case 0:
1273                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1274                                 break;
1275                         case 1:
1276                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1277                                 break;
1278                         case 2:
1279                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1280                                 break;
1281                         default:
1282                                 command_print(cmd_ctx, "\tUnknown AP type");
1283                                 break;
1284                 }
1285
1286                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1287                  * not a ROM table ... or have no such components at all.
1288                  */
1289                 if (mem_ap)
1290                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1291                                         dbgbase);
1292         }
1293         else
1294         {
1295                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1296         }
1297
1298         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1299         if (romtable_present)
1300         {
1301                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1302                 uint16_t entry_offset;
1303
1304                 /* bit 16 of apid indicates a memory access port */
1305                 if (dbgbase & 0x02)
1306                         command_print(cmd_ctx, "\tValid ROM table present");
1307                 else
1308                         command_print(cmd_ctx, "\tROM table in legacy format");
1309
1310                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1311                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1312                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1313                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1314                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1315                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1316                 jtagdp_transaction_endcheck(swjdp);
1317                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1318                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1319                                         ", CID2 0x%2.2" PRIx32
1320                                         ", CID1 0x%2.2" PRIx32
1321                                         ", CID0 0x%2.2" PRIx32,
1322                                         cid3, cid2, cid1, cid0);
1323                 if (memtype & 0x01)
1324                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1325                 else
1326                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1327                                         "Dedicated debug bus.");
1328
1329                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1330                 entry_offset = 0;
1331                 do
1332                 {
1333                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1334                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1335                         if (romentry&0x01)
1336                         {
1337                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1338                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1339                                 uint32_t component_start, component_base;
1340                                 unsigned part_num;
1341                                 char *type, *full;
1342
1343                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1344                                                 + (int)(romentry & 0xFFFFF000));
1345                                 mem_ap_read_atomic_u32(swjdp,
1346                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1347                                 mem_ap_read_atomic_u32(swjdp,
1348                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1349                                 mem_ap_read_atomic_u32(swjdp,
1350                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1351                                 mem_ap_read_atomic_u32(swjdp,
1352                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1353                                 mem_ap_read_atomic_u32(swjdp,
1354                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1355                                 mem_ap_read_atomic_u32(swjdp,
1356                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1357                                 mem_ap_read_atomic_u32(swjdp,
1358                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1359                                 mem_ap_read_atomic_u32(swjdp,
1360                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1361                                 mem_ap_read_atomic_u32(swjdp,
1362                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1363                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1364
1365                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1366                                                 ", start address 0x%" PRIx32,
1367                                                 component_base, component_start);
1368                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1369                                                 (int) (c_cid1 >> 4) & 0xf,
1370                                                 /* See ARM IHI 0029B Table 3-3 */
1371                                                 class_description[(c_cid1 >> 4) & 0xf]);
1372
1373                                 /* CoreSight component? */
1374                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1375                                         uint32_t devtype;
1376                                         unsigned minor;
1377                                         char *major = "Reserved", *subtype = "Reserved";
1378
1379                                         mem_ap_read_atomic_u32(swjdp,
1380                                                         (component_base & 0xfffff000) | 0xfcc,
1381                                                         &devtype);
1382                                         minor = (devtype >> 4) & 0x0f;
1383                                         switch (devtype & 0x0f) {
1384                                         case 0:
1385                                                 major = "Miscellaneous";
1386                                                 switch (minor) {
1387                                                 case 0:
1388                                                         subtype = "other";
1389                                                         break;
1390                                                 case 4:
1391                                                         subtype = "Validation component";
1392                                                         break;
1393                                                 }
1394                                                 break;
1395                                         case 1:
1396                                                 major = "Trace Sink";
1397                                                 switch (minor) {
1398                                                 case 0:
1399                                                         subtype = "other";
1400                                                         break;
1401                                                 case 1:
1402                                                         subtype = "Port";
1403                                                         break;
1404                                                 case 2:
1405                                                         subtype = "Buffer";
1406                                                         break;
1407                                                 }
1408                                                 break;
1409                                         case 2:
1410                                                 major = "Trace Link";
1411                                                 switch (minor) {
1412                                                 case 0:
1413                                                         subtype = "other";
1414                                                         break;
1415                                                 case 1:
1416                                                         subtype = "Funnel, router";
1417                                                         break;
1418                                                 case 2:
1419                                                         subtype = "Filter";
1420                                                         break;
1421                                                 case 3:
1422                                                         subtype = "FIFO, buffer";
1423                                                         break;
1424                                                 }
1425                                                 break;
1426                                         case 3:
1427                                                 major = "Trace Source";
1428                                                 switch (minor) {
1429                                                 case 0:
1430                                                         subtype = "other";
1431                                                         break;
1432                                                 case 1:
1433                                                         subtype = "Processor";
1434                                                         break;
1435                                                 case 2:
1436                                                         subtype = "DSP";
1437                                                         break;
1438                                                 case 3:
1439                                                         subtype = "Engine/Coprocessor";
1440                                                         break;
1441                                                 case 4:
1442                                                         subtype = "Bus";
1443                                                         break;
1444                                                 }
1445                                                 break;
1446                                         case 4:
1447                                                 major = "Debug Control";
1448                                                 switch (minor) {
1449                                                 case 0:
1450                                                         subtype = "other";
1451                                                         break;
1452                                                 case 1:
1453                                                         subtype = "Trigger Matrix";
1454                                                         break;
1455                                                 case 2:
1456                                                         subtype = "Debug Auth";
1457                                                         break;
1458                                                 }
1459                                                 break;
1460                                         case 5:
1461                                                 major = "Debug Logic";
1462                                                 switch (minor) {
1463                                                 case 0:
1464                                                         subtype = "other";
1465                                                         break;
1466                                                 case 1:
1467                                                         subtype = "Processor";
1468                                                         break;
1469                                                 case 2:
1470                                                         subtype = "DSP";
1471                                                         break;
1472                                                 case 3:
1473                                                         subtype = "Engine/Coprocessor";
1474                                                         break;
1475                                                 }
1476                                                 break;
1477                                         }
1478                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1479                                                         (unsigned) (devtype & 0xff),
1480                                                         major, subtype);
1481                                         /* REVISIT also show 0xfc8 DevId */
1482                                 }
1483
1484                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1485                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1486                                                         ", CID2 0x%2.2" PRIx32
1487                                                         ", CID1 0x%2.2" PRIx32
1488                                                         ", CID0 0x%2.2" PRIx32,
1489                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1490                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1491                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1492                                                 (int) c_pid4,
1493                                                 (int) c_pid3, (int) c_pid2,
1494                                                 (int) c_pid1, (int) c_pid0);
1495
1496                                 /* Part number interpretations are from Cortex
1497                                  * core specs, the CoreSight components TRM
1498                                  * (ARM DDI 0314H), and ETM specs; also from
1499                                  * chip observation (e.g. TI SDTI).
1500                                  */
1501                                 part_num = c_pid0 & 0xff;
1502                                 part_num |= (c_pid1 & 0x0f) << 8;
1503                                 switch (part_num) {
1504                                 case 0x000:
1505                                         type = "Cortex-M3 NVIC";
1506                                         full = "(Interrupt Controller)";
1507                                         break;
1508                                 case 0x001:
1509                                         type = "Cortex-M3 ITM";
1510                                         full = "(Instrumentation Trace Module)";
1511                                         break;
1512                                 case 0x002:
1513                                         type = "Cortex-M3 DWT";
1514                                         full = "(Data Watchpoint and Trace)";
1515                                         break;
1516                                 case 0x003:
1517                                         type = "Cortex-M3 FBP";
1518                                         full = "(Flash Patch and Breakpoint)";
1519                                         break;
1520                                 case 0x00d:
1521                                         type = "CoreSight ETM11";
1522                                         full = "(Embedded Trace)";
1523                                         break;
1524                                 // case 0x113: what?
1525                                 case 0x120:             /* from OMAP3 memmap */
1526                                         type = "TI SDTI";
1527                                         full = "(System Debug Trace Interface)";
1528                                         break;
1529                                 case 0x343:             /* from OMAP3 memmap */
1530                                         type = "TI DAPCTL";
1531                                         full = "";
1532                                         break;
1533                                 case 0x4e0:
1534                                         type = "Cortex-M3 ETM";
1535                                         full = "(Embedded Trace)";
1536                                         break;
1537                                 case 0x906:
1538                                         type = "Coresight CTI";
1539                                         full = "(Cross Trigger)";
1540                                         break;
1541                                 case 0x907:
1542                                         type = "Coresight ETB";
1543                                         full = "(Trace Buffer)";
1544                                         break;
1545                                 case 0x908:
1546                                         type = "Coresight CSTF";
1547                                         full = "(Trace Funnel)";
1548                                         break;
1549                                 case 0x910:
1550                                         type = "CoreSight ETM9";
1551                                         full = "(Embedded Trace)";
1552                                         break;
1553                                 case 0x912:
1554                                         type = "Coresight TPIU";
1555                                         full = "(Trace Port Interface Unit)";
1556                                         break;
1557                                 case 0x921:
1558                                         type = "Cortex-A8 ETM";
1559                                         full = "(Embedded Trace)";
1560                                         break;
1561                                 case 0x922:
1562                                         type = "Cortex-A8 CTI";
1563                                         full = "(Cross Trigger)";
1564                                         break;
1565                                 case 0x923:
1566                                         type = "Cortex-M3 TPIU";
1567                                         full = "(Trace Port Interface Unit)";
1568                                         break;
1569                                 case 0xc08:
1570                                         type = "Cortex-A8 Debug";
1571                                         full = "(Debug Unit)";
1572                                         break;
1573                                 default:
1574                                         type = "-*- unrecognized -*-";
1575                                         full = "";
1576                                         break;
1577                                 }
1578                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1579                                                 type, full);
1580                         }
1581                         else
1582                         {
1583                                 if (romentry)
1584                                         command_print(cmd_ctx, "\t\tComponent not present");
1585                                 else
1586                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1587                         }
1588                         entry_offset += 4;
1589                 } while (romentry > 0);
1590         }
1591         else
1592         {
1593                 command_print(cmd_ctx, "\tNo ROM table present");
1594         }
1595         dap_ap_select(swjdp, apselold);
1596
1597         return ERROR_OK;
1598 }
1599
1600 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1601 {
1602         uint32_t apsel, apselsave, baseaddr;
1603         int retval;
1604
1605         apselsave = swjdp->apsel;
1606         switch (CMD_ARGC) {
1607         case 0:
1608                 apsel = swjdp->apsel;
1609                 break;
1610         case 1:
1611                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1612                 /* AP address is in bits 31:24 of DP_SELECT */
1613                 if (apsel >= 256)
1614                         return ERROR_INVALID_ARGUMENTS;
1615                 break;
1616         default:
1617                 return ERROR_COMMAND_SYNTAX_ERROR;
1618         }
1619
1620         if (apselsave != apsel)
1621                 dap_ap_select(swjdp, apsel);
1622
1623         /* NOTE:  assumes we're talking to a MEM-AP, which
1624          * has a base address.  There are other kinds of AP,
1625          * though they're not common for now.  This should
1626          * use the ID register to verify it's a MEM-AP.
1627          */
1628         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1629         retval = jtagdp_transaction_endcheck(swjdp);
1630         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1631
1632         if (apselsave != apsel)
1633                 dap_ap_select(swjdp, apselsave);
1634
1635         return retval;
1636 }
1637
1638 DAP_COMMAND_HANDLER(dap_memaccess_command)
1639 {
1640         uint32_t memaccess_tck;
1641
1642         switch (CMD_ARGC) {
1643         case 0:
1644                 memaccess_tck = swjdp->memaccess_tck;
1645                 break;
1646         case 1:
1647                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1648                 break;
1649         default:
1650                 return ERROR_COMMAND_SYNTAX_ERROR;
1651         }
1652         swjdp->memaccess_tck = memaccess_tck;
1653
1654         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1655                         swjdp->memaccess_tck);
1656
1657         return ERROR_OK;
1658 }
1659
1660 DAP_COMMAND_HANDLER(dap_apsel_command)
1661 {
1662         uint32_t apsel, apid;
1663         int retval;
1664
1665         switch (CMD_ARGC) {
1666         case 0:
1667                 apsel = 0;
1668                 break;
1669         case 1:
1670                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1671                 /* AP address is in bits 31:24 of DP_SELECT */
1672                 if (apsel >= 256)
1673                         return ERROR_INVALID_ARGUMENTS;
1674                 break;
1675         default:
1676                 return ERROR_COMMAND_SYNTAX_ERROR;
1677         }
1678
1679         dap_ap_select(swjdp, apsel);
1680         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1681         retval = jtagdp_transaction_endcheck(swjdp);
1682         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1683                         apsel, apid);
1684
1685         return retval;
1686 }
1687
1688 DAP_COMMAND_HANDLER(dap_apid_command)
1689 {
1690         uint32_t apsel, apselsave, apid;
1691         int retval;
1692
1693         apselsave = swjdp->apsel;
1694         switch (CMD_ARGC) {
1695         case 0:
1696                 apsel = swjdp->apsel;
1697                 break;
1698         case 1:
1699                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1700                 /* AP address is in bits 31:24 of DP_SELECT */
1701                 if (apsel >= 256)
1702                         return ERROR_INVALID_ARGUMENTS;
1703                 break;
1704         default:
1705                 return ERROR_COMMAND_SYNTAX_ERROR;
1706         }
1707
1708         if (apselsave != apsel)
1709                 dap_ap_select(swjdp, apsel);
1710
1711         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1712         retval = jtagdp_transaction_endcheck(swjdp);
1713         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1714         if (apselsave != apsel)
1715                 dap_ap_select(swjdp, apselsave);
1716
1717         return retval;
1718 }
1719
1720 /*
1721  * This represents the bits which must be sent out on TMS/SWDIO to
1722  * switch a DAP implemented using an SWJ-DP module into SWD mode.
1723  * These bits are stored (and transmitted) LSB-first.
1724  *
1725  * See the DAP-Lite specification, section 2.2.5 for information
1726  * about making the debug link select SWD or JTAG.  (Similar info
1727  * is in a few other ARM documents.)
1728  */
1729 static const uint8_t jtag2swd_bitseq[] = {
1730         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1731          * putting both JTAG and SWD logic into reset state.
1732          */
1733         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1734         /* Switching sequence enables SWD and disables JTAG
1735          * NOTE: bits in the DP's IDCODE may expose the need for
1736          * an old/deprecated sequence (0xb6 0xed).
1737          */
1738         0x9e, 0xe7,
1739         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1740          * putting both JTAG and SWD logic into reset state.
1741          */
1742         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1743 };
1744
1745 /**
1746  * Put the debug link into SWD mode, if the target supports it.
1747  * The link's initial mode may be either JTAG (for example,
1748  * with SWJ-DP after reset) or SWD.
1749  *
1750  * @param target Enters SWD mode (if possible).
1751  *
1752  * Note that targets using the JTAG-DP do not support SWD, and that
1753  * some targets which could otherwise support it may have have been
1754  * configured to disable SWD signaling
1755  *
1756  * @return ERROR_OK or else a fault code.
1757  */
1758 int dap_to_swd(struct target *target)
1759 {
1760         int retval;
1761
1762         LOG_DEBUG("Enter SWD mode");
1763
1764         /* REVISIT it's nasty to need to make calls to a "jtag"
1765          * subsystem if the link isn't in JTAG mode...
1766          */
1767
1768         retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
1769                         jtag2swd_bitseq, TAP_INVALID);
1770         if (retval == ERROR_OK)
1771                 retval = jtag_execute_queue();
1772
1773         /* REVISIT set up the DAP's ops vector for SWD mode. */
1774
1775         return retval;
1776 }
1777
1778 /**
1779  * This represents the bits which must be sent out on TMS/SWDIO to
1780  * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1781  * These bits are stored (and transmitted) LSB-first.
1782  *
1783  * These bits are stored (and transmitted) LSB-first.
1784  */
1785 static const uint8_t swd2jtag_bitseq[] = {
1786         /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1787          * putting both JTAG and SWD logic into reset state.
1788          */
1789         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1790         /* Switching equence disables SWD and enables JTAG
1791          * NOTE: bits in the DP's IDCODE can expose the need for
1792          * the old/deprecated sequence (0xae 0xde).
1793          */
1794         0x3c, 0xe7,
1795         /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1796          * putting both JTAG and SWD logic into reset state.
1797          * NOTE:  some docs say "at least 5".
1798          */
1799         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1800 };
1801
1802 /** Put the debug link into JTAG mode, if the target supports it.
1803  * The link's initial mode may be either SWD or JTAG.
1804  *
1805  * @param target Enters JTAG mode (if possible).
1806  *
1807  * Note that targets implemented with SW-DP do not support JTAG, and
1808  * that some targets which could otherwise support it may have been
1809  * configured to disable JTAG signaling
1810  *
1811  * @return ERROR_OK or else a fault code.
1812  */
1813 int dap_to_jtag(struct target *target)
1814 {
1815         int retval;
1816
1817         LOG_DEBUG("Enter JTAG mode");
1818
1819         /* REVISIT it's nasty to need to make calls to a "jtag"
1820          * subsystem if the link isn't in JTAG mode...
1821          */
1822
1823         retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
1824                         swd2jtag_bitseq, TAP_RESET);
1825         if (retval == ERROR_OK)
1826                 retval = jtag_execute_queue();
1827
1828         /* REVISIT set up the DAP's ops vector for JTAG mode. */
1829
1830         return retval;
1831 }