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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 /**
  28  * @file
  29  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  30  * debugging architecture.  Compared with previous versions, this includes
  31  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  32  * transport, and focusses on memory mapped resources as defined by the
  33  * CoreSight architecture.
  34  *
  35  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  36  * basic components:  a Debug Port (DP) transporting messages to and from a
  37  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  38  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  39  * One uses only SWD for communication, and is called SW-DP.  The third can
  40  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  41  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  42  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  43  */
  44
  45 /*
  46  * Relevant specifications from ARM include:
  47  *
  48  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  49  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  50  *
  51  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  52  * Cortex-M3(tm) TRM, ARM DDI 0337G
  53  */
  54
  55 #ifdef HAVE_CONFIG_H
  56 #include "config.h"
  57 #endif
  58
  59 #include "arm_adi_v5.h"
  60 #include <helper/time_support.h>
  61
  62 /*
  63  * Transaction Mode:
  64  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  66  * result checking until swjdp_end_transaction()
  67  * This must be done before using or deallocating any return variables.
  68  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  69  * All reads and writes to the AHB bus are checked for valid completion, and return values
  70  * are immediatley available.
  71 */
  72
  73
  74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  75
  76 /*
  77         uint32_t tar_block_size(uint32_t address)
  78         Return the largest block starting at address that does not cross a tar block size alignment boundary
  79 */
  80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  81 {
  82         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  83 }
  84
  85 /***************************************************************************
  86  *                                                                         *
  87  * DPACC and APACC scanchain access through JTAG-DP                        *
  88  *                                                                         *
  89 ***************************************************************************/
  90
  91 /**
  92  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  93  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  94  * discusses operations which access these registers.
  95  *
  96  * Note that only one scan is performed.  If RnW is set, a separate scan
  97  * will be needed to collect the data which was read; the "invalue" collects
  98  * the posted result of a preceding operation, not the current one.
  99  *
 100  * @param swjdp the DAP
 101  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 102  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 103  *      SELECT register has more addressing bits.
 104  * @param RnW false iff outvalue will be written to the DP or AP
 105  * @param outvalue points to a 32-bit (little-endian) integer
 106  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 107  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 108  */
 109 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 110                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 111                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 112 {
 113         struct arm_jtag *jtag_info = swjdp->jtag_info;
 114         struct scan_field fields[2];
 115         uint8_t out_addr_buf;
 116
 117         jtag_set_end_state(TAP_IDLE);
 118         arm_jtag_set_instr(jtag_info, instr, NULL);
 119
 120         /* Add specified number of tck clocks before accessing memory bus */
 121
 122         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 123          * they provide more time for the (MEM) AP to complete the read ...
 124          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 125          */
 126         if ((instr == JTAG_DP_APACC)
 127                         && ((reg_addr == AP_REG_DRW)
 128                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 129                         && (swjdp->memaccess_tck != 0))
 130                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 131
 132         /* Scan out a read or write operation using some DP or AP register.
 133          * For APACC access with any sticky error flag set, this is discarded.
 134          */
 135         fields[0].tap = jtag_info->tap;
 136         fields[0].num_bits = 3;
 137         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 138         fields[0].out_value = &out_addr_buf;
 139         fields[0].in_value = ack;
 140
 141         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 142          * complete; data we write is discarded, data we read is unpredictable.
 143          * When overrun detect is active, STICKYORUN is set.
 144          */
 145
 146         fields[1].tap = jtag_info->tap;
 147         fields[1].num_bits = 32;
 148         fields[1].out_value = outvalue;
 149         fields[1].in_value = invalue;
 150
 151         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 152
 153         return ERROR_OK;
 154 }
 155
 156 /* Scan out and in from host ordered uint32_t variables */
 157 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 158                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 159                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 160 {
 161         struct arm_jtag *jtag_info = swjdp->jtag_info;
 162         struct scan_field fields[2];
 163         uint8_t out_value_buf[4];
 164         uint8_t out_addr_buf;
 165
 166         jtag_set_end_state(TAP_IDLE);
 167         arm_jtag_set_instr(jtag_info, instr, NULL);
 168
 169         /* Add specified number of tck clocks before accessing memory bus */
 170
 171         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 172          * they provide more time for the (MEM) AP to complete the read ...
 173          */
 174         if ((instr == JTAG_DP_APACC)
 175                         && ((reg_addr == AP_REG_DRW)
 176                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 177                         && (swjdp->memaccess_tck != 0))
 178                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 179
 180         fields[0].tap = jtag_info->tap;
 181         fields[0].num_bits = 3;
 182         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 183         fields[0].out_value = &out_addr_buf;
 184         fields[0].in_value = ack;
 185
 186         fields[1].tap = jtag_info->tap;
 187         fields[1].num_bits = 32;
 188         buf_set_u32(out_value_buf, 0, 32, outvalue);
 189         fields[1].out_value = out_value_buf;
 190         fields[1].in_value = NULL;
 191
 192         if (invalue)
 193         {
 194                 fields[1].in_value = (uint8_t *)invalue;
 195                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 196
 197                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 198         } else
 199         {
 200
 201                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 202         }
 203
 204         return ERROR_OK;
 205 }
 206
 207 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 208 static int scan_inout_check(struct swjdp_common *swjdp,
 209                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 210                 uint8_t *outvalue, uint8_t *invalue)
 211 {
 212         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 213
 214         if ((RnW == DPAP_READ) && (invalue != NULL))
 215                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 216                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 217
 218         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 219          * ack = OK/FAULT and the check CTRL_STAT
 220          */
 221         if ((instr == JTAG_DP_APACC)
 222                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 223                 return jtagdp_transaction_endcheck(swjdp);
 224
 225         return ERROR_OK;
 226 }
 227
 228 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 229                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 230                 uint32_t outvalue, uint32_t *invalue)
 231 {
 232         /* Issue the read or write */
 233         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 234
 235         /* For reads,  collect posted value; RDBUFF has no other effect.
 236          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 237          */
 238         if ((RnW == DPAP_READ) && (invalue != NULL))
 239                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 240                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 241
 242         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 243          * ack = OK/FAULT and then check CTRL_STAT
 244          */
 245         if ((instr == JTAG_DP_APACC)
 246                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 247                 return jtagdp_transaction_endcheck(swjdp);
 248
 249         return ERROR_OK;
 250 }
 251
 252 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 253 {
 254         int retval;
 255         uint32_t ctrlstat;
 256
 257         /* too expensive to call keep_alive() here */
 258
 259 #if 0
 260         /* Danger!!!! BROKEN!!!! */
 261         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 262                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 263         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 264         R956 introduced the check on return value here and now Michael Schwingen reports
 265         that this code no longer works....
 266
 267         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 268         */
 269         if ((retval = jtag_execute_queue()) != ERROR_OK)
 270         {
 271                 LOG_ERROR("BUG: Why does this fail the first time????");
 272         }
 273         /* Why??? second time it works??? */
 274 #endif
 275
 276         /* Post CTRL/STAT read; discard any previous posted read value
 277          * but collect its ACK status.
 278          */
 279         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 280                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 281         if ((retval = jtag_execute_queue()) != ERROR_OK)
 282                 return retval;
 283
 284         swjdp->ack = swjdp->ack & 0x7;
 285
 286         /* common code path avoids calling timeval_ms() */
 287         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 288         {
 289                 long long then = timeval_ms();
 290
 291                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 292                 {
 293                         if (swjdp->ack == JTAG_ACK_WAIT)
 294                         {
 295                                 if ((timeval_ms()-then) > 1000)
 296                                 {
 297                                         /* NOTE:  this would be a good spot
 298                                          * to use JTAG_DP_ABORT.
 299                                          */
 300                                         LOG_WARNING("Timeout (1000ms) waiting "
 301                                                 "for ACK=OK/FAULT "
 302                                                 "in JTAG-DP transaction");
 303                                         return ERROR_JTAG_DEVICE_ERROR;
 304                                 }
 305                         }
 306                         else
 307                         {
 308                                 LOG_WARNING("Invalid ACK %#x "
 309                                                 "in JTAG-DP transaction",
 310                                                 swjdp->ack);
 311                                 return ERROR_JTAG_DEVICE_ERROR;
 312                         }
 313
 314                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 315                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 316                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 317                                 return retval;
 318                         swjdp->ack = swjdp->ack & 0x7;
 319                 }
 320         }
 321
 322         /* Check for STICKYERR and STICKYORUN */
 323         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 324         {
 325                 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 326                 /* Check power to debug regions */
 327                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 328                 {
 329                          ahbap_debugport_init(swjdp);
 330                 }
 331                 else
 332                 {
 333                         uint32_t mem_ap_csw, mem_ap_tar;
 334
 335                         /* Print information about last AHBAP access */
 336                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
 337                                 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
 338                                 swjdp->dp_select_value, swjdp->ap_csw_value,
 339                                 swjdp->ap_tar_value);
 340                         if (ctrlstat & SSTICKYORUN)
 341                                 LOG_ERROR("JTAG-DP OVERRUN - "
 342                                         "check clock or reduce jtag speed");
 343
 344                         if (ctrlstat & SSTICKYERR)
 345                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 346
 347                         /* Clear Sticky Error Bits */
 348                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 349                                         DP_CTRL_STAT, DPAP_WRITE,
 350                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 351                                                 | SSTICKYERR, NULL);
 352                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 353                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 354                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 355                                 return retval;
 356
 357                         LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 358
 359                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 360                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 361                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 362                                 return retval;
 363                         LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 364                                         PRIx32, mem_ap_csw, mem_ap_tar);
 365
 366                 }
 367                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 368                         return retval;
 369                 return ERROR_JTAG_DEVICE_ERROR;
 370         }
 371
 372         return ERROR_OK;
 373 }
 374
 375 /***************************************************************************
 376  *                                                                         *
 377  * DP and MEM-AP  register access  through APACC and DPACC                 *
 378  *                                                                         *
 379 ***************************************************************************/
 380
 381 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 382                 uint32_t value, uint8_t reg_addr)
 383 {
 384         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 385                         reg_addr, DPAP_WRITE, value, NULL);
 386 }
 387
 388 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 389                 uint32_t *value, uint8_t reg_addr)
 390 {
 391         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 392                         reg_addr, DPAP_READ, 0, value);
 393 }
 394
 395 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 396 {
 397         uint32_t select;
 398         select = (apsel << 24) & 0xFF000000;
 399
 400         if (select != swjdp->apsel)
 401         {
 402                 swjdp->apsel = select;
 403                 /* Switching AP invalidates cached values */
 404                 swjdp->dp_select_value = -1;
 405                 swjdp->ap_csw_value = -1;
 406                 swjdp->ap_tar_value = -1;
 407         }
 408
 409         return ERROR_OK;
 410 }
 411
 412 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 413 {
 414         uint32_t select;
 415         select = (ap_reg & 0x000000F0);
 416
 417         if (select != swjdp->dp_select_value)
 418         {
 419                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 420                 swjdp->dp_select_value = select;
 421         }
 422
 423         return ERROR_OK;
 424 }
 425
 426 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 427                 uint32_t reg_addr, uint8_t *out_value_buf)
 428 {
 429         dap_dp_bankselect(swjdp, reg_addr);
 430         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 431                         DPAP_WRITE, out_value_buf, NULL);
 432
 433         return ERROR_OK;
 434 }
 435
 436 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 437 {
 438         uint8_t out_value_buf[4];
 439
 440         buf_set_u32(out_value_buf, 0, 32, value);
 441         dap_dp_bankselect(swjdp, reg_addr);
 442         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 443                         DPAP_WRITE, out_value_buf, NULL);
 444
 445         return ERROR_OK;
 446 }
 447
 448 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 449 {
 450         dap_dp_bankselect(swjdp, reg_addr);
 451         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 452                         DPAP_READ, 0, value);
 453
 454         return ERROR_OK;
 455 }
 456
 457 /***************************************************************************
 458  *                                                                         *
 459  * AHB-AP access to memory and system registers on AHB bus                 *
 460  *                                                                         *
 461 ***************************************************************************/
 462
 463 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 464 {
 465         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 466         if (csw != swjdp->ap_csw_value)
 467         {
 468                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 469                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 470                 swjdp->ap_csw_value = csw;
 471         }
 472         if (tar != swjdp->ap_tar_value)
 473         {
 474                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 475                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 476                 swjdp->ap_tar_value = tar;
 477         }
 478         if (csw & CSW_ADDRINC_MASK)
 479         {
 480                 /* Do not cache TAR value when autoincrementing */
 481                 swjdp->ap_tar_value = -1;
 482         }
 483         return ERROR_OK;
 484 }
 485
 486 /*****************************************************************************
 487 *                                                                            *
 488 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 489 *                                                                            *
 490 * Read a uint32_t value from memory or system register                            *
 491 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 492 * but with less overhead                                                     *
 493 *****************************************************************************/
 494 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 495 {
 496         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 497
 498         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 499         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 500
 501         return ERROR_OK;
 502 }
 503
 504 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 505 {
 506         mem_ap_read_u32(swjdp, address, value);
 507
 508         return jtagdp_transaction_endcheck(swjdp);
 509 }
 510
 511 /*****************************************************************************
 512 *                                                                            *
 513 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 514 *                                                                            *
 515 * Write a uint32_t value to memory or memory mapped register                              *
 516 *                                                                            *
 517 *****************************************************************************/
 518 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 519 {
 520         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 521
 522         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 523         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 524
 525         return ERROR_OK;
 526 }
 527
 528 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 529 {
 530         mem_ap_write_u32(swjdp, address, value);
 531
 532         return jtagdp_transaction_endcheck(swjdp);
 533 }
 534
 535 /*****************************************************************************
 536 *                                                                            *
 537 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 538 *                                                                            *
 539 * Write a buffer in target order (little endian)                             *
 540 *                                                                            *
 541 *****************************************************************************/
 542 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 543 {
 544         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 545         uint32_t adr = address;
 546         uint8_t* pBuffer = buffer;
 547
 548         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 549
 550         count >>= 2;
 551         wcount = count;
 552
 553         /* if we have an unaligned access - reorder data */
 554         if (adr & 0x3u)
 555         {
 556                 for (writecount = 0; writecount < count; writecount++)
 557                 {
 558                         int i;
 559                         uint32_t outvalue;
 560                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 561
 562                         for (i = 0; i < 4; i++)
 563                         {
 564                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 565                                 outvalue >>= 8;
 566                                 adr++;
 567                         }
 568                         pBuffer += sizeof(uint32_t);
 569                 }
 570         }
 571
 572         while (wcount > 0)
 573         {
 574                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 575                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 576                 if (wcount < blocksize)
 577                         blocksize = wcount;
 578
 579                 /* handle unaligned data at 4k boundary */
 580                 if (blocksize == 0)
 581                         blocksize = 1;
 582
 583                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 584
 585                 for (writecount = 0; writecount < blocksize; writecount++)
 586                 {
 587                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 588                 }
 589
 590                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 591                 {
 592                         wcount = wcount - blocksize;
 593                         address = address + 4 * blocksize;
 594                         buffer = buffer + 4 * blocksize;
 595                 }
 596                 else
 597                 {
 598                         errorcount++;
 599                 }
 600
 601                 if (errorcount > 1)
 602                 {
 603                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 604                         return ERROR_JTAG_DEVICE_ERROR;
 605                 }
 606         }
 607
 608         return retval;
 609 }
 610
 611 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 612                 uint8_t *buffer, int count, uint32_t address)
 613 {
 614         int retval = ERROR_OK;
 615         int wcount, blocksize, writecount, i;
 616
 617         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 618
 619         wcount = count >> 1;
 620
 621         while (wcount > 0)
 622         {
 623                 int nbytes;
 624
 625                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 626                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 627
 628                 if (wcount < blocksize)
 629                         blocksize = wcount;
 630
 631                 /* handle unaligned data at 4k boundary */
 632                 if (blocksize == 0)
 633                         blocksize = 1;
 634
 635                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 636                 writecount = blocksize;
 637
 638                 do
 639                 {
 640                         nbytes = MIN((writecount << 1), 4);
 641
 642                         if (nbytes < 4)
 643                         {
 644                                 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
 645                                 {
 646                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 647                                         return ERROR_JTAG_DEVICE_ERROR;
 648                                 }
 649
 650                                 address += nbytes >> 1;
 651                         }
 652                         else
 653                         {
 654                                 uint32_t outvalue;
 655                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 656
 657                                 for (i = 0; i < nbytes; i++)
 658                                 {
 659                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 660                                         outvalue >>= 8;
 661                                         address++;
 662                                 }
 663
 664                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 665                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 666                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 667                                 {
 668                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 669                                         return ERROR_JTAG_DEVICE_ERROR;
 670                                 }
 671                         }
 672
 673                         buffer += nbytes >> 1;
 674                         writecount -= nbytes >> 1;
 675
 676                 } while (writecount);
 677                 wcount -= blocksize;
 678         }
 679
 680         return retval;
 681 }
 682
 683 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 684 {
 685         int retval = ERROR_OK;
 686
 687         if (count >= 4)
 688                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 689
 690         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 691
 692         while (count > 0)
 693         {
 694                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 695                 uint16_t svalue;
 696                 memcpy(&svalue, buffer, sizeof(uint16_t));
 697                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 698                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 699                 retval = jtagdp_transaction_endcheck(swjdp);
 700                 count -= 2;
 701                 address += 2;
 702                 buffer += 2;
 703         }
 704
 705         return retval;
 706 }
 707
 708 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 709                 uint8_t *buffer, int count, uint32_t address)
 710 {
 711         int retval = ERROR_OK;
 712         int wcount, blocksize, writecount, i;
 713
 714         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 715
 716         wcount = count;
 717
 718         while (wcount > 0)
 719         {
 720                 int nbytes;
 721
 722                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 723                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 724
 725                 if (wcount < blocksize)
 726                         blocksize = wcount;
 727
 728                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 729                 writecount = blocksize;
 730
 731                 do
 732                 {
 733                         nbytes = MIN(writecount, 4);
 734
 735                         if (nbytes < 4)
 736                         {
 737                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 738                                 {
 739                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 740                                         return ERROR_JTAG_DEVICE_ERROR;
 741                                 }
 742
 743                                 address += nbytes;
 744                         }
 745                         else
 746                         {
 747                                 uint32_t outvalue;
 748                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 749
 750                                 for (i = 0; i < nbytes; i++)
 751                                 {
 752                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 753                                         outvalue >>= 8;
 754                                         address++;
 755                                 }
 756
 757                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 758                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 759                                 if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 760                                 {
 761                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 762                                         return ERROR_JTAG_DEVICE_ERROR;
 763                                 }
 764                         }
 765
 766                         buffer += nbytes;
 767                         writecount -= nbytes;
 768
 769                 } while (writecount);
 770                 wcount -= blocksize;
 771         }
 772
 773         return retval;
 774 }
 775
 776 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 777 {
 778         int retval = ERROR_OK;
 779
 780         if (count >= 4)
 781                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 782
 783         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 784
 785         while (count > 0)
 786         {
 787                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 788                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 789                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 790                 retval = jtagdp_transaction_endcheck(swjdp);
 791                 count--;
 792                 address++;
 793                 buffer++;
 794         }
 795
 796         return retval;
 797 }
 798
 799 /*********************************************************************************
 800 *                                                                                *
 801 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 802 *                                                                                *
 803 * Read block fast in target order (little endian) into a buffer                  *
 804 *                                                                                *
 805 **********************************************************************************/
 806 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 807 {
 808         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 809         uint32_t adr = address;
 810         uint8_t* pBuffer = buffer;
 811
 812         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 813
 814         count >>= 2;
 815         wcount = count;
 816
 817         while (wcount > 0)
 818         {
 819                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 820                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 821                 if (wcount < blocksize)
 822                         blocksize = wcount;
 823
 824                 /* handle unaligned data at 4k boundary */
 825                 if (blocksize == 0)
 826                         blocksize = 1;
 827
 828                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 829
 830                 /* Scan out first read */
 831                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 832                                 DPAP_READ, 0, NULL, NULL);
 833                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 834                 {
 835                         /* Scan out next read; scan in posted value for the
 836                          * previous one.  Assumes read is acked "OK/FAULT",
 837                          * and CTRL_STAT says that meant "OK".
 838                          */
 839                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 840                                         DPAP_READ, 0, buffer + 4 * readcount,
 841                                         &swjdp->ack);
 842                 }
 843
 844                 /* Scan in last posted value; RDBUFF has no other effect,
 845                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 846                  */
 847                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 848                                 DPAP_READ, 0, buffer + 4 * readcount,
 849                                 &swjdp->ack);
 850                 if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 851                 {
 852                         wcount = wcount - blocksize;
 853                         address += 4 * blocksize;
 854                         buffer += 4 * blocksize;
 855                 }
 856                 else
 857                 {
 858                         errorcount++;
 859                 }
 860
 861                 if (errorcount > 1)
 862                 {
 863                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 864                         return ERROR_JTAG_DEVICE_ERROR;
 865                 }
 866         }
 867
 868         /* if we have an unaligned access - reorder data */
 869         if (adr & 0x3u)
 870         {
 871                 for (readcount = 0; readcount < count; readcount++)
 872                 {
 873                         int i;
 874                         uint32_t data;
 875                         memcpy(&data, pBuffer, sizeof(uint32_t));
 876
 877                         for (i = 0; i < 4; i++)
 878                         {
 879                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 880                                 pBuffer++;
 881                                 adr++;
 882                         }
 883                 }
 884         }
 885
 886         return retval;
 887 }
 888
 889 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 890                 uint8_t *buffer, int count, uint32_t address)
 891 {
 892         uint32_t invalue;
 893         int retval = ERROR_OK;
 894         int wcount, blocksize, readcount, i;
 895
 896         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 897
 898         wcount = count >> 1;
 899
 900         while (wcount > 0)
 901         {
 902                 int nbytes;
 903
 904                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 905                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 906                 if (wcount < blocksize)
 907                         blocksize = wcount;
 908
 909                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 910
 911                 /* handle unaligned data at 4k boundary */
 912                 if (blocksize == 0)
 913                         blocksize = 1;
 914                 readcount = blocksize;
 915
 916                 do
 917                 {
 918                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 919                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 920                         {
 921                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 922                                 return ERROR_JTAG_DEVICE_ERROR;
 923                         }
 924
 925                         nbytes = MIN((readcount << 1), 4);
 926
 927                         for (i = 0; i < nbytes; i++)
 928                         {
 929                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 930                                 buffer++;
 931                                 address++;
 932                         }
 933
 934                         readcount -= (nbytes >> 1);
 935                 } while (readcount);
 936                 wcount -= blocksize;
 937         }
 938
 939         return retval;
 940 }
 941
 942 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 943 {
 944         uint32_t invalue, i;
 945         int retval = ERROR_OK;
 946
 947         if (count >= 4)
 948                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 949
 950         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 951
 952         while (count > 0)
 953         {
 954                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 955                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 956                 retval = jtagdp_transaction_endcheck(swjdp);
 957                 if (address & 0x1)
 958                 {
 959                         for (i = 0; i < 2; i++)
 960                         {
 961                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 962                                 buffer++;
 963                                 address++;
 964                         }
 965                 }
 966                 else
 967                 {
 968                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 969                         memcpy(buffer, &svalue, sizeof(uint16_t));
 970                         address += 2;
 971                         buffer += 2;
 972                 }
 973                 count -= 2;
 974         }
 975
 976         return retval;
 977 }
 978
 979 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 980  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 981  *
 982  * The solution is to arrange for a large out/in scan in this loop and
 983  * and convert data afterwards.
 984  */
 985 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 986                 uint8_t *buffer, int count, uint32_t address)
 987 {
 988         uint32_t invalue;
 989         int retval = ERROR_OK;
 990         int wcount, blocksize, readcount, i;
 991
 992         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 993
 994         wcount = count;
 995
 996         while (wcount > 0)
 997         {
 998                 int nbytes;
 999
1000                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1001                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1002
1003                 if (wcount < blocksize)
1004                         blocksize = wcount;
1005
1006                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1007                 readcount = blocksize;
1008
1009                 do
1010                 {
1011                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1012                         if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
1013                         {
1014                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1015                                 return ERROR_JTAG_DEVICE_ERROR;
1016                         }
1017
1018                         nbytes = MIN(readcount, 4);
1019
1020                         for (i = 0; i < nbytes; i++)
1021                         {
1022                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1023                                 buffer++;
1024                                 address++;
1025                         }
1026
1027                         readcount -= nbytes;
1028                 } while (readcount);
1029                 wcount -= blocksize;
1030         }
1031
1032         return retval;
1033 }
1034
1035 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1036 {
1037         uint32_t invalue;
1038         int retval = ERROR_OK;
1039
1040         if (count >= 4)
1041                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1042
1043         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1044
1045         while (count > 0)
1046         {
1047                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1048                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1049                 retval = jtagdp_transaction_endcheck(swjdp);
1050                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1051                 count--;
1052                 address++;
1053                 buffer++;
1054         }
1055
1056         return retval;
1057 }
1058
1059 /**
1060  * Initialize a DAP.
1061  *
1062  * @todo Rename this.  We also need an initialization scheme which account
1063  * for SWD transports not just JTAG; that will need to address differences
1064  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1065  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1066  */
1067 int ahbap_debugport_init(struct swjdp_common *swjdp)
1068 {
1069         uint32_t idreg, romaddr, dummy;
1070         uint32_t ctrlstat;
1071         int cnt = 0;
1072         int retval;
1073
1074         LOG_DEBUG(" ");
1075
1076         /* Default MEM-AP setup.
1077          *
1078          * REVISIT AP #0 may be an inappropriate default for this.
1079          * Should we probe, or receve a hint from the caller?
1080          * Presumably we can ignore the possibility of multiple APs.
1081          */
1082         swjdp->apsel = 0;
1083         swjdp->ap_csw_value = -1;
1084         swjdp->ap_tar_value = -1;
1085
1086         /* DP initialization */
1087         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1088         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1089         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1090         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1091
1092         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1093
1094         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1095         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1096         if ((retval = jtag_execute_queue()) != ERROR_OK)
1097                 return retval;
1098
1099         /* Check that we have debug power domains activated */
1100         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1101         {
1102                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1103                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1104                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1105                         return retval;
1106                 alive_sleep(10);
1107         }
1108
1109         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1110         {
1111                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1112                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1113                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1114                         return retval;
1115                 alive_sleep(10);
1116         }
1117
1118         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1119         /* With debug power on we can activate OVERRUN checking */
1120         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1121         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1122         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1123
1124         /*
1125          * REVISIT this isn't actually *initializing* anything in an AP,
1126          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1127          * Should it?  If the ROM address is valid, is this the right
1128          * place to scan the table and do any topology detection?
1129          */
1130         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1131         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1132
1133         LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1134                 ", Debug ROM Address 0x%" PRIx32,
1135                 swjdp->apsel, idreg, romaddr);
1136
1137         return ERROR_OK;
1138 }
1139
1140 /* CID interpretation -- see ARM IHI 0029B section 3
1141  * and ARM IHI 0031A table 13-3.
1142  */
1143 static const char *class_description[16] ={
1144         "Reserved", "ROM table", "Reserved", "Reserved",
1145         "Reserved", "Reserved", "Reserved", "Reserved",
1146         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1147         "Reserved", "OptimoDE DESS",
1148                 "Generic IP component", "PrimeCell or System component"
1149 };
1150
1151 static bool
1152 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1153 {
1154         return cid3 == 0xb1 && cid2 == 0x05
1155                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1156 }
1157
1158 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1159 {
1160
1161         uint32_t dbgbase, apid;
1162         int romtable_present = 0;
1163         uint8_t mem_ap;
1164         uint32_t apselold;
1165
1166         apselold = swjdp->apsel;
1167         dap_ap_select(swjdp, apsel);
1168         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1169         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1170         jtagdp_transaction_endcheck(swjdp);
1171         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1172         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1173         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1174         if (apid)
1175         {
1176                 switch (apid&0x0F)
1177                 {
1178                         case 0:
1179                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1180                                 break;
1181                         case 1:
1182                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1183                                 break;
1184                         case 2:
1185                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1186                                 break;
1187                         default:
1188                                 command_print(cmd_ctx, "\tUnknown AP type");
1189                                 break;
1190                 }
1191
1192                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1193                  * not a ROM table ... or have no such components at all.
1194                  */
1195                 if (mem_ap)
1196                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1197                                         dbgbase);
1198         }
1199         else
1200         {
1201                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1202         }
1203
1204         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1205         if (romtable_present)
1206         {
1207                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1208                 uint16_t entry_offset;
1209
1210                 /* bit 16 of apid indicates a memory access port */
1211                 if (dbgbase & 0x02)
1212                         command_print(cmd_ctx, "\tValid ROM table present");
1213                 else
1214                         command_print(cmd_ctx, "\tROM table in legacy format");
1215
1216                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1217                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1218                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1219                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1220                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1221                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1222                 jtagdp_transaction_endcheck(swjdp);
1223                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1224                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1225                                         ", CID2 0x%2.2" PRIx32
1226                                         ", CID1 0x%2.2" PRIx32
1227                                         ", CID0 0x%2.2" PRIx32,
1228                                         cid3, cid2, cid1, cid0);
1229                 if (memtype & 0x01)
1230                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1231                 else
1232                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1233                                         "Dedicated debug bus.");
1234
1235                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1236                 entry_offset = 0;
1237                 do
1238                 {
1239                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1240                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1241                         if (romentry&0x01)
1242                         {
1243                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1244                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1245                                 uint32_t component_start, component_base;
1246                                 unsigned part_num;
1247                                 char *type, *full;
1248
1249                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1250                                                 + (int)(romentry & 0xFFFFF000));
1251                                 mem_ap_read_atomic_u32(swjdp,
1252                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1253                                 mem_ap_read_atomic_u32(swjdp,
1254                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1255                                 mem_ap_read_atomic_u32(swjdp,
1256                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1257                                 mem_ap_read_atomic_u32(swjdp,
1258                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1259                                 mem_ap_read_atomic_u32(swjdp,
1260                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1261                                 mem_ap_read_atomic_u32(swjdp,
1262                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1263                                 mem_ap_read_atomic_u32(swjdp,
1264                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1265                                 mem_ap_read_atomic_u32(swjdp,
1266                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1267                                 mem_ap_read_atomic_u32(swjdp,
1268                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1269                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1270
1271                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1272                                                 ", start address 0x%" PRIx32,
1273                                                 component_base, component_start);
1274                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1275                                                 (int) (c_cid1 >> 4) & 0xf,
1276                                                 /* See ARM IHI 0029B Table 3-3 */
1277                                                 class_description[(c_cid1 >> 4) & 0xf]);
1278
1279                                 /* CoreSight component? */
1280                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1281                                         uint32_t devtype;
1282                                         unsigned minor;
1283                                         char *major = "Reserved", *subtype = "Reserved";
1284
1285                                         mem_ap_read_atomic_u32(swjdp,
1286                                                         (component_base & 0xfffff000) | 0xfcc,
1287                                                         &devtype);
1288                                         minor = (devtype >> 4) & 0x0f;
1289                                         switch (devtype & 0x0f) {
1290                                         case 0:
1291                                                 major = "Miscellaneous";
1292                                                 switch (minor) {
1293                                                 case 0:
1294                                                         subtype = "other";
1295                                                         break;
1296                                                 case 4:
1297                                                         subtype = "Validation component";
1298                                                         break;
1299                                                 }
1300                                                 break;
1301                                         case 1:
1302                                                 major = "Trace Sink";
1303                                                 switch (minor) {
1304                                                 case 0:
1305                                                         subtype = "other";
1306                                                         break;
1307                                                 case 1:
1308                                                         subtype = "Port";
1309                                                         break;
1310                                                 case 2:
1311                                                         subtype = "Buffer";
1312                                                         break;
1313                                                 }
1314                                                 break;
1315                                         case 2:
1316                                                 major = "Trace Link";
1317                                                 switch (minor) {
1318                                                 case 0:
1319                                                         subtype = "other";
1320                                                         break;
1321                                                 case 1:
1322                                                         subtype = "Funnel, router";
1323                                                         break;
1324                                                 case 2:
1325                                                         subtype = "Filter";
1326                                                         break;
1327                                                 case 3:
1328                                                         subtype = "FIFO, buffer";
1329                                                         break;
1330                                                 }
1331                                                 break;
1332                                         case 3:
1333                                                 major = "Trace Source";
1334                                                 switch (minor) {
1335                                                 case 0:
1336                                                         subtype = "other";
1337                                                         break;
1338                                                 case 1:
1339                                                         subtype = "Processor";
1340                                                         break;
1341                                                 case 2:
1342                                                         subtype = "DSP";
1343                                                         break;
1344                                                 case 3:
1345                                                         subtype = "Engine/Coprocessor";
1346                                                         break;
1347                                                 case 4:
1348                                                         subtype = "Bus";
1349                                                         break;
1350                                                 }
1351                                                 break;
1352                                         case 4:
1353                                                 major = "Debug Control";
1354                                                 switch (minor) {
1355                                                 case 0:
1356                                                         subtype = "other";
1357                                                         break;
1358                                                 case 1:
1359                                                         subtype = "Trigger Matrix";
1360                                                         break;
1361                                                 case 2:
1362                                                         subtype = "Debug Auth";
1363                                                         break;
1364                                                 }
1365                                                 break;
1366                                         case 5:
1367                                                 major = "Debug Logic";
1368                                                 switch (minor) {
1369                                                 case 0:
1370                                                         subtype = "other";
1371                                                         break;
1372                                                 case 1:
1373                                                         subtype = "Processor";
1374                                                         break;
1375                                                 case 2:
1376                                                         subtype = "DSP";
1377                                                         break;
1378                                                 case 3:
1379                                                         subtype = "Engine/Coprocessor";
1380                                                         break;
1381                                                 }
1382                                                 break;
1383                                         }
1384                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1385                                                         (unsigned) (devtype & 0xff),
1386                                                         major, subtype);
1387                                         /* REVISIT also show 0xfc8 DevId */
1388                                 }
1389
1390                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1391                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1392                                                         ", CID2 0x%2.2" PRIx32
1393                                                         ", CID1 0x%2.2" PRIx32
1394                                                         ", CID0 0x%2.2" PRIx32,
1395                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1396                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1397                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1398                                                 (int) c_pid4,
1399                                                 (int) c_pid3, (int) c_pid2,
1400                                                 (int) c_pid1, (int) c_pid0);
1401
1402                                 /* Part number interpretations are from Cortex
1403                                  * core specs, the CoreSight components TRM
1404                                  * (ARM DDI 0314H), and ETM specs; also from
1405                                  * chip observation (e.g. TI SDTI).
1406                                  */
1407                                 part_num = c_pid0 & 0xff;
1408                                 part_num |= (c_pid1 & 0x0f) << 8;
1409                                 switch (part_num) {
1410                                 case 0x000:
1411                                         type = "Cortex-M3 NVIC";
1412                                         full = "(Interrupt Controller)";
1413                                         break;
1414                                 case 0x001:
1415                                         type = "Cortex-M3 ITM";
1416                                         full = "(Instrumentation Trace Module)";
1417                                         break;
1418                                 case 0x002:
1419                                         type = "Cortex-M3 DWT";
1420                                         full = "(Data Watchpoint and Trace)";
1421                                         break;
1422                                 case 0x003:
1423                                         type = "Cortex-M3 FBP";
1424                                         full = "(Flash Patch and Breakpoint)";
1425                                         break;
1426                                 case 0x00d:
1427                                         type = "CoreSight ETM11";
1428                                         full = "(Embedded Trace)";
1429                                         break;
1430                                 // case 0x113: what?
1431                                 case 0x120:             /* from OMAP3 memmap */
1432                                         type = "TI SDTI";
1433                                         full = "(System Debug Trace Interface)";
1434                                         break;
1435                                 case 0x343:             /* from OMAP3 memmap */
1436                                         type = "TI DAPCTL";
1437                                         full = "";
1438                                         break;
1439                                 case 0x4e0:
1440                                         type = "Cortex-M3 ETM";
1441                                         full = "(Embedded Trace)";
1442                                         break;
1443                                 case 0x906:
1444                                         type = "Coresight CTI";
1445                                         full = "(Cross Trigger)";
1446                                         break;
1447                                 case 0x907:
1448                                         type = "Coresight ETB";
1449                                         full = "(Trace Buffer)";
1450                                         break;
1451                                 case 0x908:
1452                                         type = "Coresight CSTF";
1453                                         full = "(Trace Funnel)";
1454                                         break;
1455                                 case 0x910:
1456                                         type = "CoreSight ETM9";
1457                                         full = "(Embedded Trace)";
1458                                         break;
1459                                 case 0x912:
1460                                         type = "Coresight TPIU";
1461                                         full = "(Trace Port Interface Unit)";
1462                                         break;
1463                                 case 0x921:
1464                                         type = "Cortex-A8 ETM";
1465                                         full = "(Embedded Trace)";
1466                                         break;
1467                                 case 0x922:
1468                                         type = "Cortex-A8 CTI";
1469                                         full = "(Cross Trigger)";
1470                                         break;
1471                                 case 0x923:
1472                                         type = "Cortex-M3 TPIU";
1473                                         full = "(Trace Port Interface Unit)";
1474                                         break;
1475                                 case 0xc08:
1476                                         type = "Cortex-A8 Debug";
1477                                         full = "(Debug Unit)";
1478                                         break;
1479                                 default:
1480                                         type = "-*- unrecognized -*-";
1481                                         full = "";
1482                                         break;
1483                                 }
1484                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1485                                                 type, full);
1486                         }
1487                         else
1488                         {
1489                                 if (romentry)
1490                                         command_print(cmd_ctx, "\t\tComponent not present");
1491                                 else
1492                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1493                         }
1494                         entry_offset += 4;
1495                 } while (romentry > 0);
1496         }
1497         else
1498         {
1499                 command_print(cmd_ctx, "\tNo ROM table present");
1500         }
1501         dap_ap_select(swjdp, apselold);
1502
1503         return ERROR_OK;
1504 }
1505
1506 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1507 {
1508         uint32_t apsel, apselsave, baseaddr;
1509         int retval;
1510
1511         apselsave = swjdp->apsel;
1512         switch (CMD_ARGC) {
1513         case 0:
1514                 apsel = swjdp->apsel;
1515                 break;
1516         case 1:
1517                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1518                 break;
1519         default:
1520                 return ERROR_COMMAND_SYNTAX_ERROR;
1521         }
1522
1523         if (apselsave != apsel)
1524                 dap_ap_select(swjdp, apsel);
1525
1526         /* NOTE:  assumes we're talking to a MEM-AP, which
1527          * has a base address.  There are other kinds of AP,
1528          * though they're not common for now.  This should
1529          * use the ID register to verify it's a MEM-AP.
1530          */
1531         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1532         retval = jtagdp_transaction_endcheck(swjdp);
1533         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1534
1535         if (apselsave != apsel)
1536                 dap_ap_select(swjdp, apselsave);
1537
1538         return retval;
1539 }
1540
1541 DAP_COMMAND_HANDLER(dap_memaccess_command)
1542 {
1543         uint32_t memaccess_tck;
1544
1545         switch (CMD_ARGC) {
1546         case 0:
1547                 memaccess_tck = swjdp->memaccess_tck;
1548                 break;
1549         case 1:
1550                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1551                 break;
1552         default:
1553                 return ERROR_COMMAND_SYNTAX_ERROR;
1554         }
1555         swjdp->memaccess_tck = memaccess_tck;
1556
1557         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1558                         swjdp->memaccess_tck);
1559
1560         return ERROR_OK;
1561 }
1562
1563 DAP_COMMAND_HANDLER(dap_apsel_command)
1564 {
1565         uint32_t apsel, apid;
1566         int retval;
1567
1568         switch (CMD_ARGC) {
1569         case 0:
1570                 apsel = 0;
1571                 break;
1572         case 1:
1573                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1574                 break;
1575         default:
1576                 return ERROR_COMMAND_SYNTAX_ERROR;
1577         }
1578
1579         dap_ap_select(swjdp, apsel);
1580         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1581         retval = jtagdp_transaction_endcheck(swjdp);
1582         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1583                         apsel, apid);
1584
1585         return retval;
1586 }
1587
1588 DAP_COMMAND_HANDLER(dap_apid_command)
1589 {
1590         uint32_t apsel, apselsave, apid;
1591         int retval;
1592
1593         apselsave = swjdp->apsel;
1594         switch (CMD_ARGC) {
1595         case 0:
1596                 apsel = swjdp->apsel;
1597                 break;
1598         case 1:
1599                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1600                 break;
1601         default:
1602                 return ERROR_COMMAND_SYNTAX_ERROR;
1603         }
1604
1605         if (apselsave != apsel)
1606                 dap_ap_select(swjdp, apsel);
1607
1608         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1609         retval = jtagdp_transaction_endcheck(swjdp);
1610         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1611         if (apselsave != apsel)
1612                 dap_ap_select(swjdp, apselsave);
1613
1614         return retval;
1615 }