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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Oyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26
  27 /**
  28  * @file
  29  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  30  * debugging architecture.  Compared with previous versions, this includes
  31  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  32  * transport, and focusses on memory mapped resources as defined by the
  33  * CoreSight architecture.
  34  *
  35  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  36  * basic components:  a Debug Port (DP) transporting messages to and from a
  37  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  38  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  39  * One uses only SWD for communication, and is called SW-DP.  The third can
  40  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  41  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  42  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  43  */
  44
  45 /*
  46  * Relevant specifications from ARM include:
  47  *
  48  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  49  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  50  *
  51  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  52  * Cortex-M3(tm) TRM, ARM DDI 0337G
  53  */
  54
  55 #ifdef HAVE_CONFIG_H
  56 #include "config.h"
  57 #endif
  58
  59 #include "arm_adi_v5.h"
  60 #include <helper/time_support.h>
  61
  62 /*
  63  * Transaction Mode:
  64  * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
  65  * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
  66  * result checking until swjdp_end_transaction()
  67  * This must be done before using or deallocating any return variables.
  68  * swjdp->trans_mode == TRANS_MODE_ATOMIC
  69  * All reads and writes to the AHB bus are checked for valid completion, and return values
  70  * are immediatley available.
  71 */
  72
  73
  74 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  75
  76 /*
  77         uint32_t tar_block_size(uint32_t address)
  78         Return the largest block starting at address that does not cross a tar block size alignment boundary
  79 */
  80 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  81 {
  82         return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
  83 }
  84
  85 /***************************************************************************
  86  *                                                                         *
  87  * DPACC and APACC scanchain access through JTAG-DP                        *
  88  *                                                                         *
  89 ***************************************************************************/
  90
  91 /**
  92  * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
  93  * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
  94  * discusses operations which access these registers.
  95  *
  96  * Note that only one scan is performed.  If RnW is set, a separate scan
  97  * will be needed to collect the data which was read; the "invalue" collects
  98  * the posted result of a preceding operation, not the current one.
  99  *
 100  * @param swjdp the DAP
 101  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
 102  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
 103  *      SELECT register has more addressing bits.
 104  * @param RnW false iff outvalue will be written to the DP or AP
 105  * @param outvalue points to a 32-bit (little-endian) integer
 106  * @param invalue NULL, or points to a 32-bit (little-endian) integer
 107  * @param ack points to where the three bit JTAG_ACK_* code will be stored
 108  */
 109 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 110                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 111                 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 112 {
 113         struct arm_jtag *jtag_info = swjdp->jtag_info;
 114         struct scan_field fields[2];
 115         uint8_t out_addr_buf;
 116
 117         jtag_set_end_state(TAP_IDLE);
 118         arm_jtag_set_instr(jtag_info, instr, NULL);
 119
 120         /* Add specified number of tck clocks before accessing memory bus */
 121
 122         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 123          * they provide more time for the (MEM) AP to complete the read ...
 124          * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 125          */
 126         if ((instr == JTAG_DP_APACC)
 127                         && ((reg_addr == AP_REG_DRW)
 128                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 129                         && (swjdp->memaccess_tck != 0))
 130                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 131
 132         /* Scan out a read or write operation using some DP or AP register.
 133          * For APACC access with any sticky error flag set, this is discarded.
 134          */
 135         fields[0].tap = jtag_info->tap;
 136         fields[0].num_bits = 3;
 137         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 138         fields[0].out_value = &out_addr_buf;
 139         fields[0].in_value = ack;
 140
 141         /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
 142          * complete; data we write is discarded, data we read is unpredictable.
 143          * When overrun detect is active, STICKYORUN is set.
 144          */
 145
 146         fields[1].tap = jtag_info->tap;
 147         fields[1].num_bits = 32;
 148         fields[1].out_value = outvalue;
 149         fields[1].in_value = invalue;
 150
 151         jtag_add_dr_scan(2, fields, jtag_get_end_state());
 152
 153         return ERROR_OK;
 154 }
 155
 156 /* Scan out and in from host ordered uint32_t variables */
 157 static int adi_jtag_dp_scan_u32(struct swjdp_common *swjdp,
 158                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 159                 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 160 {
 161         struct arm_jtag *jtag_info = swjdp->jtag_info;
 162         struct scan_field fields[2];
 163         uint8_t out_value_buf[4];
 164         uint8_t out_addr_buf;
 165
 166         jtag_set_end_state(TAP_IDLE);
 167         arm_jtag_set_instr(jtag_info, instr, NULL);
 168
 169         /* Add specified number of tck clocks before accessing memory bus */
 170
 171         /* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 172          * they provide more time for the (MEM) AP to complete the read ...
 173          */
 174         if ((instr == JTAG_DP_APACC)
 175                         && ((reg_addr == AP_REG_DRW)
 176                                 || ((reg_addr & 0xF0) == AP_REG_BD0))
 177                         && (swjdp->memaccess_tck != 0))
 178                 jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 179
 180         fields[0].tap = jtag_info->tap;
 181         fields[0].num_bits = 3;
 182         buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 183         fields[0].out_value = &out_addr_buf;
 184         fields[0].in_value = ack;
 185
 186         fields[1].tap = jtag_info->tap;
 187         fields[1].num_bits = 32;
 188         buf_set_u32(out_value_buf, 0, 32, outvalue);
 189         fields[1].out_value = out_value_buf;
 190         fields[1].in_value = NULL;
 191
 192         if (invalue)
 193         {
 194                 fields[1].in_value = (uint8_t *)invalue;
 195                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 196
 197                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t) invalue);
 198         } else
 199         {
 200
 201                 jtag_add_dr_scan(2, fields, jtag_get_end_state());
 202         }
 203
 204         return ERROR_OK;
 205 }
 206
 207 /* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
 208 static int scan_inout_check(struct swjdp_common *swjdp,
 209                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 210                 uint8_t *outvalue, uint8_t *invalue)
 211 {
 212         adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 213
 214         if ((RnW == DPAP_READ) && (invalue != NULL))
 215                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC,
 216                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 217
 218         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 219          * ack = OK/FAULT and the check CTRL_STAT
 220          */
 221         if ((instr == JTAG_DP_APACC)
 222                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 223                 return swjdp_transaction_endcheck(swjdp);
 224
 225         return ERROR_OK;
 226 }
 227
 228 static int scan_inout_check_u32(struct swjdp_common *swjdp,
 229                 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 230                 uint32_t outvalue, uint32_t *invalue)
 231 {
 232         /* Issue the read or write */
 233         adi_jtag_dp_scan_u32(swjdp, instr, reg_addr, RnW, outvalue, NULL, NULL);
 234
 235         /* For reads,  collect posted value; RDBUFF has no other effect.
 236          * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 237          */
 238         if ((RnW == DPAP_READ) && (invalue != NULL))
 239                 adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
 240                                 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
 241
 242         /* In TRANS_MODE_ATOMIC all JTAG_DP_APACC transactions wait for
 243          * ack = OK/FAULT and then check CTRL_STAT
 244          */
 245         if ((instr == JTAG_DP_APACC)
 246                         && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
 247                 return swjdp_transaction_endcheck(swjdp);
 248
 249         return ERROR_OK;
 250 }
 251
 252 int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 253 {
 254         int retval;
 255         uint32_t ctrlstat;
 256
 257         /* too expensive to call keep_alive() here */
 258
 259 #if 0
 260         /* Danger!!!! BROKEN!!!! */
 261         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 262                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 263         /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 264         R956 introduced the check on return value here and now Michael Schwingen reports
 265         that this code no longer works....
 266
 267         https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
 268         */
 269         if ((retval = jtag_execute_queue()) != ERROR_OK)
 270         {
 271                 LOG_ERROR("BUG: Why does this fail the first time????");
 272         }
 273         /* Why??? second time it works??? */
 274 #endif
 275
 276         /* Post CTRL/STAT read; discard any previous posted read value
 277          * but collect its ACK status.
 278          */
 279         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 280                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 281         if ((retval = jtag_execute_queue()) != ERROR_OK)
 282                 return retval;
 283
 284         swjdp->ack = swjdp->ack & 0x7;
 285
 286         /* common code path avoids calling timeval_ms() */
 287         if (swjdp->ack != JTAG_ACK_OK_FAULT)
 288         {
 289                 long long then = timeval_ms();
 290
 291                 while (swjdp->ack != JTAG_ACK_OK_FAULT)
 292                 {
 293                         if (swjdp->ack == JTAG_ACK_WAIT)
 294                         {
 295                                 if ((timeval_ms()-then) > 1000)
 296                                 {
 297                                         /* NOTE:  this would be a good spot
 298                                          * to use JTAG_DP_ABORT.
 299                                          */
 300                                         LOG_WARNING("Timeout (1000ms) waiting "
 301                                                 "for ACK=OK/FAULT "
 302                                                 "in JTAG-DP transaction");
 303                                         return ERROR_JTAG_DEVICE_ERROR;
 304                                 }
 305                         }
 306                         else
 307                         {
 308                                 LOG_WARNING("Invalid ACK %#x"
 309                                                 "in JTAG-DP transaction",
 310                                                 swjdp->ack);
 311                                 return ERROR_JTAG_DEVICE_ERROR;
 312                         }
 313
 314                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 315                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 316                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 317                                 return retval;
 318                         swjdp->ack = swjdp->ack & 0x7;
 319                 }
 320         }
 321
 322         /* Check for STICKYERR and STICKYORUN */
 323         if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 324         {
 325                 LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
 326                 /* Check power to debug regions */
 327                 if ((ctrlstat & 0xf0000000) != 0xf0000000)
 328                 {
 329                          ahbap_debugport_init(swjdp);
 330                 }
 331                 else
 332                 {
 333                         uint32_t mem_ap_csw, mem_ap_tar;
 334
 335                         /* Print information about last AHBAP access */
 336                         LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
 337                         if (ctrlstat & SSTICKYORUN)
 338                                 LOG_ERROR("JTAG-DP OVERRUN - "
 339                                         "check clock or reduce jtag speed");
 340
 341                         if (ctrlstat & SSTICKYERR)
 342                                 LOG_ERROR("JTAG-DP STICKY ERROR");
 343
 344                         /* Clear Sticky Error Bits */
 345                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 346                                         DP_CTRL_STAT, DPAP_WRITE,
 347                                         swjdp->dp_ctrl_stat | SSTICKYORUN
 348                                                 | SSTICKYERR, NULL);
 349                         scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 350                                         DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 351                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 352                                 return retval;
 353
 354                         LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
 355
 356                         dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 357                         dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 358                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 359                                 return retval;
 360                         LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
 361
 362                 }
 363                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 364                         return retval;
 365                 return ERROR_JTAG_DEVICE_ERROR;
 366         }
 367
 368         return ERROR_OK;
 369 }
 370
 371 /***************************************************************************
 372  *                                                                         *
 373  * DP and MEM-AP  register access  through APACC and DPACC                 *
 374  *                                                                         *
 375 ***************************************************************************/
 376
 377 static int dap_dp_write_reg(struct swjdp_common *swjdp,
 378                 uint32_t value, uint8_t reg_addr)
 379 {
 380         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 381                         reg_addr, DPAP_WRITE, value, NULL);
 382 }
 383
 384 static int dap_dp_read_reg(struct swjdp_common *swjdp,
 385                 uint32_t *value, uint8_t reg_addr)
 386 {
 387         return scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
 388                         reg_addr, DPAP_READ, 0, value);
 389 }
 390
 391 int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 392 {
 393         uint32_t select;
 394         select = (apsel << 24) & 0xFF000000;
 395
 396         if (select != swjdp->apsel)
 397         {
 398                 swjdp->apsel = select;
 399                 /* Switching AP invalidates cached values */
 400                 swjdp->dp_select_value = -1;
 401                 swjdp->ap_csw_value = -1;
 402                 swjdp->ap_tar_value = -1;
 403         }
 404
 405         return ERROR_OK;
 406 }
 407
 408 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 409 {
 410         uint32_t select;
 411         select = (ap_reg & 0x000000F0);
 412
 413         if (select != swjdp->dp_select_value)
 414         {
 415                 dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
 416                 swjdp->dp_select_value = select;
 417         }
 418
 419         return ERROR_OK;
 420 }
 421
 422 static int dap_ap_write_reg(struct swjdp_common *swjdp,
 423                 uint32_t reg_addr, uint8_t *out_value_buf)
 424 {
 425         dap_dp_bankselect(swjdp, reg_addr);
 426         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 427                         DPAP_WRITE, out_value_buf, NULL);
 428
 429         return ERROR_OK;
 430 }
 431
 432 int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
 433 {
 434         uint8_t out_value_buf[4];
 435
 436         buf_set_u32(out_value_buf, 0, 32, value);
 437         dap_dp_bankselect(swjdp, reg_addr);
 438         scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 439                         DPAP_WRITE, out_value_buf, NULL);
 440
 441         return ERROR_OK;
 442 }
 443
 444 int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
 445 {
 446         dap_dp_bankselect(swjdp, reg_addr);
 447         scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 448                         DPAP_READ, 0, value);
 449
 450         return ERROR_OK;
 451 }
 452
 453 /***************************************************************************
 454  *                                                                         *
 455  * AHB-AP access to memory and system registers on AHB bus                 *
 456  *                                                                         *
 457 ***************************************************************************/
 458
 459 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 460 {
 461         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 462         if (csw != swjdp->ap_csw_value)
 463         {
 464                 /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
 465                 dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 466                 swjdp->ap_csw_value = csw;
 467         }
 468         if (tar != swjdp->ap_tar_value)
 469         {
 470                 /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
 471                 dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 472                 swjdp->ap_tar_value = tar;
 473         }
 474         if (csw & CSW_ADDRINC_MASK)
 475         {
 476                 /* Do not cache TAR value when autoincrementing */
 477                 swjdp->ap_tar_value = -1;
 478         }
 479         return ERROR_OK;
 480 }
 481
 482 /*****************************************************************************
 483 *                                                                            *
 484 * mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
 485 *                                                                            *
 486 * Read a uint32_t value from memory or system register                            *
 487 * Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
 488 * but with less overhead                                                     *
 489 *****************************************************************************/
 490 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 491 {
 492         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 493
 494         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 495         dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 496
 497         return ERROR_OK;
 498 }
 499
 500 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
 501 {
 502         mem_ap_read_u32(swjdp, address, value);
 503
 504         return swjdp_transaction_endcheck(swjdp);
 505 }
 506
 507 /*****************************************************************************
 508 *                                                                            *
 509 * mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
 510 *                                                                            *
 511 * Write a uint32_t value to memory or memory mapped register                              *
 512 *                                                                            *
 513 *****************************************************************************/
 514 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 515 {
 516         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 517
 518         dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
 519         dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 520
 521         return ERROR_OK;
 522 }
 523
 524 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
 525 {
 526         mem_ap_write_u32(swjdp, address, value);
 527
 528         return swjdp_transaction_endcheck(swjdp);
 529 }
 530
 531 /*****************************************************************************
 532 *                                                                            *
 533 * mem_ap_write_buf(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address) *
 534 *                                                                            *
 535 * Write a buffer in target order (little endian)                             *
 536 *                                                                            *
 537 *****************************************************************************/
 538 int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 539 {
 540         int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 541         uint32_t adr = address;
 542         uint8_t* pBuffer = buffer;
 543
 544         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 545
 546         count >>= 2;
 547         wcount = count;
 548
 549         /* if we have an unaligned access - reorder data */
 550         if (adr & 0x3u)
 551         {
 552                 for (writecount = 0; writecount < count; writecount++)
 553                 {
 554                         int i;
 555                         uint32_t outvalue;
 556                         memcpy(&outvalue, pBuffer, sizeof(uint32_t));
 557
 558                         for (i = 0; i < 4; i++)
 559                         {
 560                                 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
 561                                 outvalue >>= 8;
 562                                 adr++;
 563                         }
 564                         pBuffer += sizeof(uint32_t);
 565                 }
 566         }
 567
 568         while (wcount > 0)
 569         {
 570                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 571                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 572                 if (wcount < blocksize)
 573                         blocksize = wcount;
 574
 575                 /* handle unaligned data at 4k boundary */
 576                 if (blocksize == 0)
 577                         blocksize = 1;
 578
 579                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 580
 581                 for (writecount = 0; writecount < blocksize; writecount++)
 582                 {
 583                         dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 584                 }
 585
 586                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 587                 {
 588                         wcount = wcount - blocksize;
 589                         address = address + 4 * blocksize;
 590                         buffer = buffer + 4 * blocksize;
 591                 }
 592                 else
 593                 {
 594                         errorcount++;
 595                 }
 596
 597                 if (errorcount > 1)
 598                 {
 599                         LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 600                         return ERROR_JTAG_DEVICE_ERROR;
 601                 }
 602         }
 603
 604         return retval;
 605 }
 606
 607 static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 608                 uint8_t *buffer, int count, uint32_t address)
 609 {
 610         int retval = ERROR_OK;
 611         int wcount, blocksize, writecount, i;
 612
 613         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 614
 615         wcount = count >> 1;
 616
 617         while (wcount > 0)
 618         {
 619                 int nbytes;
 620
 621                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 622                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 623
 624                 if (wcount < blocksize)
 625                         blocksize = wcount;
 626
 627                 /* handle unaligned data at 4k boundary */
 628                 if (blocksize == 0)
 629                         blocksize = 1;
 630
 631                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 632                 writecount = blocksize;
 633
 634                 do
 635                 {
 636                         nbytes = MIN((writecount << 1), 4);
 637
 638                         if (nbytes < 4)
 639                         {
 640                                 if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
 641                                 {
 642                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 643                                         return ERROR_JTAG_DEVICE_ERROR;
 644                                 }
 645
 646                                 address += nbytes >> 1;
 647                         }
 648                         else
 649                         {
 650                                 uint32_t outvalue;
 651                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 652
 653                                 for (i = 0; i < nbytes; i++)
 654                                 {
 655                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 656                                         outvalue >>= 8;
 657                                         address++;
 658                                 }
 659
 660                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 661                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 662                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 663                                 {
 664                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 665                                         return ERROR_JTAG_DEVICE_ERROR;
 666                                 }
 667                         }
 668
 669                         buffer += nbytes >> 1;
 670                         writecount -= nbytes >> 1;
 671
 672                 } while (writecount);
 673                 wcount -= blocksize;
 674         }
 675
 676         return retval;
 677 }
 678
 679 int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 680 {
 681         int retval = ERROR_OK;
 682
 683         if (count >= 4)
 684                 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
 685
 686         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 687
 688         while (count > 0)
 689         {
 690                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 691                 uint16_t svalue;
 692                 memcpy(&svalue, buffer, sizeof(uint16_t));
 693                 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 694                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 695                 retval = swjdp_transaction_endcheck(swjdp);
 696                 count -= 2;
 697                 address += 2;
 698                 buffer += 2;
 699         }
 700
 701         return retval;
 702 }
 703
 704 static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 705                 uint8_t *buffer, int count, uint32_t address)
 706 {
 707         int retval = ERROR_OK;
 708         int wcount, blocksize, writecount, i;
 709
 710         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 711
 712         wcount = count;
 713
 714         while (wcount > 0)
 715         {
 716                 int nbytes;
 717
 718                 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
 719                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 720
 721                 if (wcount < blocksize)
 722                         blocksize = wcount;
 723
 724                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 725                 writecount = blocksize;
 726
 727                 do
 728                 {
 729                         nbytes = MIN(writecount, 4);
 730
 731                         if (nbytes < 4)
 732                         {
 733                                 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 734                                 {
 735                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 736                                         return ERROR_JTAG_DEVICE_ERROR;
 737                                 }
 738
 739                                 address += nbytes;
 740                         }
 741                         else
 742                         {
 743                                 uint32_t outvalue;
 744                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 745
 746                                 for (i = 0; i < nbytes; i++)
 747                                 {
 748                                         *((uint8_t*)buffer + (address & 0x3)) = outvalue;
 749                                         outvalue >>= 8;
 750                                         address++;
 751                                 }
 752
 753                                 memcpy(&outvalue, buffer, sizeof(uint32_t));
 754                                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 755                                 if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 756                                 {
 757                                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 758                                         return ERROR_JTAG_DEVICE_ERROR;
 759                                 }
 760                         }
 761
 762                         buffer += nbytes;
 763                         writecount -= nbytes;
 764
 765                 } while (writecount);
 766                 wcount -= blocksize;
 767         }
 768
 769         return retval;
 770 }
 771
 772 int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 773 {
 774         int retval = ERROR_OK;
 775
 776         if (count >= 4)
 777                 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
 778
 779         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 780
 781         while (count > 0)
 782         {
 783                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 784                 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 785                 dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 786                 retval = swjdp_transaction_endcheck(swjdp);
 787                 count--;
 788                 address++;
 789                 buffer++;
 790         }
 791
 792         return retval;
 793 }
 794
 795 /*********************************************************************************
 796 *                                                                                *
 797 * mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)  *
 798 *                                                                                *
 799 * Read block fast in target order (little endian) into a buffer                  *
 800 *                                                                                *
 801 **********************************************************************************/
 802 int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 803 {
 804         int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
 805         uint32_t adr = address;
 806         uint8_t* pBuffer = buffer;
 807
 808         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 809
 810         count >>= 2;
 811         wcount = count;
 812
 813         while (wcount > 0)
 814         {
 815                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 816                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 817                 if (wcount < blocksize)
 818                         blocksize = wcount;
 819
 820                 /* handle unaligned data at 4k boundary */
 821                 if (blocksize == 0)
 822                         blocksize = 1;
 823
 824                 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 825
 826                 /* Scan out first read */
 827                 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 828                                 DPAP_READ, 0, NULL, NULL);
 829                 for (readcount = 0; readcount < blocksize - 1; readcount++)
 830                 {
 831                         /* Scan out next read; scan in posted value for the
 832                          * previous one.  Assumes read is acked "OK/FAULT",
 833                          * and CTRL_STAT says that meant "OK".
 834                          */
 835                         adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
 836                                         DPAP_READ, 0, buffer + 4 * readcount,
 837                                         &swjdp->ack);
 838                 }
 839
 840                 /* Scan in last posted value; RDBUFF has no other effect,
 841                  * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 842                  */
 843                 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 844                                 DPAP_READ, 0, buffer + 4 * readcount,
 845                                 &swjdp->ack);
 846                 if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
 847                 {
 848                         wcount = wcount - blocksize;
 849                         address += 4 * blocksize;
 850                         buffer += 4 * blocksize;
 851                 }
 852                 else
 853                 {
 854                         errorcount++;
 855                 }
 856
 857                 if (errorcount > 1)
 858                 {
 859                         LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 860                         return ERROR_JTAG_DEVICE_ERROR;
 861                 }
 862         }
 863
 864         /* if we have an unaligned access - reorder data */
 865         if (adr & 0x3u)
 866         {
 867                 for (readcount = 0; readcount < count; readcount++)
 868                 {
 869                         int i;
 870                         uint32_t data;
 871                         memcpy(&data, pBuffer, sizeof(uint32_t));
 872
 873                         for (i = 0; i < 4; i++)
 874                         {
 875                                 *((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
 876                                 pBuffer++;
 877                                 adr++;
 878                         }
 879                 }
 880         }
 881
 882         return retval;
 883 }
 884
 885 static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 886                 uint8_t *buffer, int count, uint32_t address)
 887 {
 888         uint32_t invalue;
 889         int retval = ERROR_OK;
 890         int wcount, blocksize, readcount, i;
 891
 892         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 893
 894         wcount = count >> 1;
 895
 896         while (wcount > 0)
 897         {
 898                 int nbytes;
 899
 900                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 901                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 902                 if (wcount < blocksize)
 903                         blocksize = wcount;
 904
 905                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 906
 907                 /* handle unaligned data at 4k boundary */
 908                 if (blocksize == 0)
 909                         blocksize = 1;
 910                 readcount = blocksize;
 911
 912                 do
 913                 {
 914                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 915                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 916                         {
 917                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 918                                 return ERROR_JTAG_DEVICE_ERROR;
 919                         }
 920
 921                         nbytes = MIN((readcount << 1), 4);
 922
 923                         for (i = 0; i < nbytes; i++)
 924                         {
 925                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 926                                 buffer++;
 927                                 address++;
 928                         }
 929
 930                         readcount -= (nbytes >> 1);
 931                 } while (readcount);
 932                 wcount -= blocksize;
 933         }
 934
 935         return retval;
 936 }
 937
 938 int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
 939 {
 940         uint32_t invalue, i;
 941         int retval = ERROR_OK;
 942
 943         if (count >= 4)
 944                 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
 945
 946         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 947
 948         while (count > 0)
 949         {
 950                 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 951                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
 952                 retval = swjdp_transaction_endcheck(swjdp);
 953                 if (address & 0x1)
 954                 {
 955                         for (i = 0; i < 2; i++)
 956                         {
 957                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 958                                 buffer++;
 959                                 address++;
 960                         }
 961                 }
 962                 else
 963                 {
 964                         uint16_t svalue = (invalue >> 8 * (address & 0x3));
 965                         memcpy(buffer, &svalue, sizeof(uint16_t));
 966                         address += 2;
 967                         buffer += 2;
 968                 }
 969                 count -= 2;
 970         }
 971
 972         return retval;
 973 }
 974
 975 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
 976  * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
 977  *
 978  * The solution is to arrange for a large out/in scan in this loop and
 979  * and convert data afterwards.
 980  */
 981 static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 982                 uint8_t *buffer, int count, uint32_t address)
 983 {
 984         uint32_t invalue;
 985         int retval = ERROR_OK;
 986         int wcount, blocksize, readcount, i;
 987
 988         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 989
 990         wcount = count;
 991
 992         while (wcount > 0)
 993         {
 994                 int nbytes;
 995
 996                 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
 997                 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
 998
 999                 if (wcount < blocksize)
1000                         blocksize = wcount;
1001
1002                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1003                 readcount = blocksize;
1004
1005                 do
1006                 {
1007                         dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1008                         if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
1009                         {
1010                                 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1011                                 return ERROR_JTAG_DEVICE_ERROR;
1012                         }
1013
1014                         nbytes = MIN(readcount, 4);
1015
1016                         for (i = 0; i < nbytes; i++)
1017                         {
1018                                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1019                                 buffer++;
1020                                 address++;
1021                         }
1022
1023                         readcount -= nbytes;
1024                 } while (readcount);
1025                 wcount -= blocksize;
1026         }
1027
1028         return retval;
1029 }
1030
1031 int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, uint32_t address)
1032 {
1033         uint32_t invalue;
1034         int retval = ERROR_OK;
1035
1036         if (count >= 4)
1037                 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1038
1039         swjdp->trans_mode = TRANS_MODE_COMPOSITE;
1040
1041         while (count > 0)
1042         {
1043                 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1044                 dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
1045                 retval = swjdp_transaction_endcheck(swjdp);
1046                 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1047                 count--;
1048                 address++;
1049                 buffer++;
1050         }
1051
1052         return retval;
1053 }
1054
1055 /**
1056  * Initialize a DAP.
1057  *
1058  * @todo Rename this.  We also need an initialization scheme which account
1059  * for SWD transports not just JTAG; that will need to address differences
1060  * in layering.  (JTAG is useful without any debug target; but not SWD.)
1061  */
1062 int ahbap_debugport_init(struct swjdp_common *swjdp)
1063 {
1064         uint32_t idreg, romaddr, dummy;
1065         uint32_t ctrlstat;
1066         int cnt = 0;
1067         int retval;
1068
1069         LOG_DEBUG(" ");
1070
1071         /* Default MEM-AP setup.
1072          *
1073          * REVISIT AP #0 may be an inappropriate default for this.
1074          * Should we probe, or receve a hint from the caller?
1075          * Presumably we can ignore the possibility of multiple APs.
1076          */
1077         swjdp->apsel = 0;
1078         swjdp->ap_csw_value = -1;
1079         swjdp->ap_tar_value = -1;
1080
1081         /* DP initialization */
1082         swjdp->trans_mode = TRANS_MODE_ATOMIC;
1083         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1084         dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
1085         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1086
1087         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1088
1089         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1090         dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1091         if ((retval = jtag_execute_queue()) != ERROR_OK)
1092                 return retval;
1093
1094         /* Check that we have debug power domains activated */
1095         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1096         {
1097                 LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
1098                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1099                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1100                         return retval;
1101                 alive_sleep(10);
1102         }
1103
1104         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1105         {
1106                 LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
1107                 dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
1108                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1109                         return retval;
1110                 alive_sleep(10);
1111         }
1112
1113         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1114         /* With debug power on we can activate OVERRUN checking */
1115         swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1116         dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
1117         dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
1118
1119         /*
1120          * REVISIT this isn't actually *initializing* anything in an AP,
1121          * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1122          * Should it?  If the ROM address is valid, is this the right
1123          * place to scan the table and do any topology detection?
1124          */
1125         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
1126         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
1127
1128         LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
1129
1130         return ERROR_OK;
1131 }
1132
1133 /* CID interpretation -- see ARM IHI 0029B section 3
1134  * and ARM IHI 0031A table 13-3.
1135  */
1136 static const char *class_description[16] ={
1137         "Reserved", "ROM table", "Reserved", "Reserved",
1138         "Reserved", "Reserved", "Reserved", "Reserved",
1139         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1140         "Reserved", "OptimoDE DESS",
1141                 "Generic IP component", "PrimeCell or System component"
1142 };
1143
1144 static bool
1145 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1146 {
1147         return cid3 == 0xb1 && cid2 == 0x05
1148                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1149 }
1150
1151 int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
1152 {
1153
1154         uint32_t dbgbase, apid;
1155         int romtable_present = 0;
1156         uint8_t mem_ap;
1157         uint32_t apselold;
1158
1159         apselold = swjdp->apsel;
1160         dap_ap_select(swjdp, apsel);
1161         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
1162         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1163         swjdp_transaction_endcheck(swjdp);
1164         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1165         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1166         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1167         if (apid)
1168         {
1169                 switch (apid&0x0F)
1170                 {
1171                         case 0:
1172                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1173                                 break;
1174                         case 1:
1175                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1176                                 break;
1177                         case 2:
1178                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1179                                 break;
1180                         default:
1181                                 command_print(cmd_ctx, "\tUnknown AP type");
1182                                 break;
1183                 }
1184
1185                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1186                  * not a ROM table ... or have no such components at all.
1187                  */
1188                 if (mem_ap)
1189                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1190                                         dbgbase);
1191         }
1192         else
1193         {
1194                 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1195         }
1196
1197         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1198         if (romtable_present)
1199         {
1200                 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1201                 uint16_t entry_offset;
1202
1203                 /* bit 16 of apid indicates a memory access port */
1204                 if (dbgbase & 0x02)
1205                         command_print(cmd_ctx, "\tValid ROM table present");
1206                 else
1207                         command_print(cmd_ctx, "\tROM table in legacy format");
1208
1209                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1210                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1211                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1212                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1213                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1214                 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1215                 swjdp_transaction_endcheck(swjdp);
1216                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1217                         command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1218                                         ", CID2 0x%2.2" PRIx32
1219                                         ", CID1 0x%2.2" PRIx32
1220                                         ", CID0 0x%2.2" PRIx32,
1221                                         cid3, cid2, cid1, cid0);
1222                 if (memtype & 0x01)
1223                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1224                 else
1225                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1226                                         "Dedicated debug bus.");
1227
1228                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1229                 entry_offset = 0;
1230                 do
1231                 {
1232                         mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1233                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1234                         if (romentry&0x01)
1235                         {
1236                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1237                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1238                                 uint32_t component_start, component_base;
1239                                 unsigned part_num;
1240                                 char *type, *full;
1241
1242                                 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1243                                                 + (int)(romentry & 0xFFFFF000));
1244                                 mem_ap_read_atomic_u32(swjdp,
1245                                                 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1246                                 mem_ap_read_atomic_u32(swjdp,
1247                                                 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1248                                 mem_ap_read_atomic_u32(swjdp,
1249                                                 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1250                                 mem_ap_read_atomic_u32(swjdp,
1251                                                 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1252                                 mem_ap_read_atomic_u32(swjdp,
1253                                                 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1254                                 mem_ap_read_atomic_u32(swjdp,
1255                                                 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1256                                 mem_ap_read_atomic_u32(swjdp,
1257                                                 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1258                                 mem_ap_read_atomic_u32(swjdp,
1259                                                 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1260                                 mem_ap_read_atomic_u32(swjdp,
1261                                                 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1262                                 component_start = component_base - 0x1000*(c_pid4 >> 4);
1263
1264                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1265                                                 ", start address 0x%" PRIx32,
1266                                                 component_base, component_start);
1267                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1268                                                 (int) (c_cid1 >> 4) & 0xf,
1269                                                 /* See ARM IHI 0029B Table 3-3 */
1270                                                 class_description[(c_cid1 >> 4) & 0xf]);
1271
1272                                 /* CoreSight component? */
1273                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1274                                         uint32_t devtype;
1275                                         unsigned minor;
1276                                         char *major = "Reserved", *subtype = "Reserved";
1277
1278                                         mem_ap_read_atomic_u32(swjdp,
1279                                                         (component_base & 0xfffff000) | 0xfcc,
1280                                                         &devtype);
1281                                         minor = (devtype >> 4) & 0x0f;
1282                                         switch (devtype & 0x0f) {
1283                                         case 0:
1284                                                 major = "Miscellaneous";
1285                                                 switch (minor) {
1286                                                 case 0:
1287                                                         subtype = "other";
1288                                                         break;
1289                                                 case 4:
1290                                                         subtype = "Validation component";
1291                                                         break;
1292                                                 }
1293                                                 break;
1294                                         case 1:
1295                                                 major = "Trace Sink";
1296                                                 switch (minor) {
1297                                                 case 0:
1298                                                         subtype = "other";
1299                                                         break;
1300                                                 case 1:
1301                                                         subtype = "Port";
1302                                                         break;
1303                                                 case 2:
1304                                                         subtype = "Buffer";
1305                                                         break;
1306                                                 }
1307                                                 break;
1308                                         case 2:
1309                                                 major = "Trace Link";
1310                                                 switch (minor) {
1311                                                 case 0:
1312                                                         subtype = "other";
1313                                                         break;
1314                                                 case 1:
1315                                                         subtype = "Funnel, router";
1316                                                         break;
1317                                                 case 2:
1318                                                         subtype = "Filter";
1319                                                         break;
1320                                                 case 3:
1321                                                         subtype = "FIFO, buffer";
1322                                                         break;
1323                                                 }
1324                                                 break;
1325                                         case 3:
1326                                                 major = "Trace Source";
1327                                                 switch (minor) {
1328                                                 case 0:
1329                                                         subtype = "other";
1330                                                         break;
1331                                                 case 1:
1332                                                         subtype = "Processor";
1333                                                         break;
1334                                                 case 2:
1335                                                         subtype = "DSP";
1336                                                         break;
1337                                                 case 3:
1338                                                         subtype = "Engine/Coprocessor";
1339                                                         break;
1340                                                 case 4:
1341                                                         subtype = "Bus";
1342                                                         break;
1343                                                 }
1344                                                 break;
1345                                         case 4:
1346                                                 major = "Debug Control";
1347                                                 switch (minor) {
1348                                                 case 0:
1349                                                         subtype = "other";
1350                                                         break;
1351                                                 case 1:
1352                                                         subtype = "Trigger Matrix";
1353                                                         break;
1354                                                 case 2:
1355                                                         subtype = "Debug Auth";
1356                                                         break;
1357                                                 }
1358                                                 break;
1359                                         case 5:
1360                                                 major = "Debug Logic";
1361                                                 switch (minor) {
1362                                                 case 0:
1363                                                         subtype = "other";
1364                                                         break;
1365                                                 case 1:
1366                                                         subtype = "Processor";
1367                                                         break;
1368                                                 case 2:
1369                                                         subtype = "DSP";
1370                                                         break;
1371                                                 case 3:
1372                                                         subtype = "Engine/Coprocessor";
1373                                                         break;
1374                                                 }
1375                                                 break;
1376                                         }
1377                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1378                                                         (unsigned) (devtype & 0xff),
1379                                                         major, subtype);
1380                                         /* REVISIT also show 0xfc8 DevId */
1381                                 }
1382
1383                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1384                                         command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1385                                                         ", CID2 0x%2.2" PRIx32
1386                                                         ", CID1 0x%2.2" PRIx32
1387                                                         ", CID0 0x%2.2" PRIx32,
1388                                                         c_cid3, c_cid2, c_cid1, c_cid0);
1389                                 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1390                                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1391                                                 (int) c_pid4,
1392                                                 (int) c_pid3, (int) c_pid2,
1393                                                 (int) c_pid1, (int) c_pid0);
1394
1395                                 /* Part number interpretations are from Cortex
1396                                  * core specs, the CoreSight components TRM
1397                                  * (ARM DDI 0314H), and ETM specs; also from
1398                                  * chip observation (e.g. TI SDTI).
1399                                  */
1400                                 part_num = c_pid0 & 0xff;
1401                                 part_num |= (c_pid1 & 0x0f) << 8;
1402                                 switch (part_num) {
1403                                 case 0x000:
1404                                         type = "Cortex-M3 NVIC";
1405                                         full = "(Interrupt Controller)";
1406                                         break;
1407                                 case 0x001:
1408                                         type = "Cortex-M3 ITM";
1409                                         full = "(Instrumentation Trace Module)";
1410                                         break;
1411                                 case 0x002:
1412                                         type = "Cortex-M3 DWT";
1413                                         full = "(Data Watchpoint and Trace)";
1414                                         break;
1415                                 case 0x003:
1416                                         type = "Cortex-M3 FBP";
1417                                         full = "(Flash Patch and Breakpoint)";
1418                                         break;
1419                                 case 0x00d:
1420                                         type = "CoreSight ETM11";
1421                                         full = "(Embedded Trace)";
1422                                         break;
1423                                 // case 0x113: what?
1424                                 case 0x120:             /* from OMAP3 memmap */
1425                                         type = "TI SDTI";
1426                                         full = "(System Debug Trace Interface)";
1427                                         break;
1428                                 case 0x343:             /* from OMAP3 memmap */
1429                                         type = "TI DAPCTL";
1430                                         full = "";
1431                                         break;
1432                                 case 0x4e0:
1433                                         type = "Cortex-M3 ETM";
1434                                         full = "(Embedded Trace)";
1435                                         break;
1436                                 case 0x906:
1437                                         type = "Coresight CTI";
1438                                         full = "(Cross Trigger)";
1439                                         break;
1440                                 case 0x907:
1441                                         type = "Coresight ETB";
1442                                         full = "(Trace Buffer)";
1443                                         break;
1444                                 case 0x908:
1445                                         type = "Coresight CSTF";
1446                                         full = "(Trace Funnel)";
1447                                         break;
1448                                 case 0x910:
1449                                         type = "CoreSight ETM9";
1450                                         full = "(Embedded Trace)";
1451                                         break;
1452                                 case 0x912:
1453                                         type = "Coresight TPIU";
1454                                         full = "(Trace Port Interface Unit)";
1455                                         break;
1456                                 case 0x921:
1457                                         type = "Cortex-A8 ETM";
1458                                         full = "(Embedded Trace)";
1459                                         break;
1460                                 case 0x922:
1461                                         type = "Cortex-A8 CTI";
1462                                         full = "(Cross Trigger)";
1463                                         break;
1464                                 case 0x923:
1465                                         type = "Cortex-M3 TPIU";
1466                                         full = "(Trace Port Interface Unit)";
1467                                         break;
1468                                 case 0xc08:
1469                                         type = "Cortex-A8 Debug";
1470                                         full = "(Debug Unit)";
1471                                         break;
1472                                 default:
1473                                         type = "-*- unrecognized -*-";
1474                                         full = "";
1475                                         break;
1476                                 }
1477                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1478                                                 type, full);
1479                         }
1480                         else
1481                         {
1482                                 if (romentry)
1483                                         command_print(cmd_ctx, "\t\tComponent not present");
1484                                 else
1485                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1486                         }
1487                         entry_offset += 4;
1488                 } while (romentry > 0);
1489         }
1490         else
1491         {
1492                 command_print(cmd_ctx, "\tNo ROM table present");
1493         }
1494         dap_ap_select(swjdp, apselold);
1495
1496         return ERROR_OK;
1497 }
1498
1499 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1500 {
1501         uint32_t apsel, apselsave, baseaddr;
1502         int retval;
1503
1504         apselsave = swjdp->apsel;
1505         switch (CMD_ARGC) {
1506         case 0:
1507                 apsel = swjdp->apsel;
1508                 break;
1509         case 1:
1510                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1511                 break;
1512         default:
1513                 return ERROR_COMMAND_SYNTAX_ERROR;
1514         }
1515
1516         if (apselsave != apsel)
1517                 dap_ap_select(swjdp, apsel);
1518
1519         dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
1520         retval = swjdp_transaction_endcheck(swjdp);
1521         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1522
1523         if (apselsave != apsel)
1524                 dap_ap_select(swjdp, apselsave);
1525
1526         return retval;
1527 }
1528
1529 DAP_COMMAND_HANDLER(dap_memaccess_command)
1530 {
1531         uint32_t memaccess_tck;
1532
1533         switch (CMD_ARGC) {
1534         case 0:
1535                 memaccess_tck = swjdp->memaccess_tck;
1536                 break;
1537         case 1:
1538                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1539                 break;
1540         default:
1541                 return ERROR_COMMAND_SYNTAX_ERROR;
1542         }
1543         swjdp->memaccess_tck = memaccess_tck;
1544
1545         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1546                         swjdp->memaccess_tck);
1547
1548         return ERROR_OK;
1549 }
1550
1551 DAP_COMMAND_HANDLER(dap_apsel_command)
1552 {
1553         uint32_t apsel, apid;
1554         int retval;
1555
1556         switch (CMD_ARGC) {
1557         case 0:
1558                 apsel = 0;
1559                 break;
1560         case 1:
1561                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1562                 break;
1563         default:
1564                 return ERROR_COMMAND_SYNTAX_ERROR;
1565         }
1566
1567         dap_ap_select(swjdp, apsel);
1568         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1569         retval = swjdp_transaction_endcheck(swjdp);
1570         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1571                         apsel, apid);
1572
1573         return retval;
1574 }
1575
1576 DAP_COMMAND_HANDLER(dap_apid_command)
1577 {
1578         uint32_t apsel, apselsave, apid;
1579         int retval;
1580
1581         apselsave = swjdp->apsel;
1582         switch (CMD_ARGC) {
1583         case 0:
1584                 apsel = swjdp->apsel;
1585                 break;
1586         case 1:
1587                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1588                 break;
1589         default:
1590                 return ERROR_COMMAND_SYNTAX_ERROR;
1591         }
1592
1593         if (apselsave != apsel)
1594                 dap_ap_select(swjdp, apsel);
1595
1596         dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
1597         retval = swjdp_transaction_endcheck(swjdp);
1598         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1599         if (apselsave != apsel)
1600                 dap_ap_select(swjdp, apselsave);
1601
1602         return retval;
1603 }