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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         int retval;
 299
 300         if (size == 4)
 301                 csw_size = CSW_32BIT;
 302         else if (size == 2)
 303                 csw_size = CSW_16BIT;
 304         else if (size == 1)
 305                 csw_size = CSW_8BIT;
 306         else
 307                 return ERROR_TARGET_UNALIGNED_ACCESS;
 308
 309         retval = dap_setup_accessport_tar(dap, address);
 310         if (retval != ERROR_OK)
 311                 return retval;
 312
 313         while (nbytes > 0) {
 314                 uint32_t this_size = size;
 315
 316                 /* Select packed transfer if possible */
 317                 if (addrinc && dap->packed_transfers && nbytes >= 4
 318                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 319                         this_size = 4;
 320                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 321                 } else {
 322                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 323                 }
 324
 325                 if (retval != ERROR_OK)
 326                         break;
 327
 328                 /* How many source bytes each transfer will consume, and their location in the DRW,
 329                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 330                 uint32_t outvalue = 0;
 331                 switch (this_size) {
 332                 case 4:
 333                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 334                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 335                 case 2:
 336                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 337                 case 1:
 338                         outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 339                 }
 340
 341                 nbytes -= this_size;
 342
 343                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 344                 if (retval != ERROR_OK)
 345                         break;
 346
 347                 /* Rewrite TAR if it wrapped */
 348                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 349                         retval = dap_setup_accessport_tar(dap, address);
 350                         if (retval != ERROR_OK)
 351                                 break;
 352                 }
 353         }
 354
 355         /* REVISIT: Might want to have a queued version of this function that does not run. */
 356         if (retval == ERROR_OK)
 357                 retval = dap_run(dap);
 358
 359         if (retval != ERROR_OK) {
 360                 uint32_t tar;
 361                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 362                                 && dap_run(dap) == ERROR_OK)
 363                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 364                 else
 365                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 366         }
 367
 368         return retval;
 369 }
 370
 371 /* Compatibility wrappers around mem_ap_write(). Note that the count is in bytes for these. */
 372 int mem_ap_write_buf_u32(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address, bool addr_incr)
 373 {
 374         return mem_ap_write(dap, buffer, 4, count / 4, address, true);
 375 }
 376
 377 int mem_ap_write_buf_u16(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 378 {
 379         return mem_ap_write(dap, buffer, 2, count / 2, address, true);
 380 }
 381
 382 int mem_ap_write_buf_u8(struct adiv5_dap *dap, const uint8_t *buffer, int count, uint32_t address)
 383 {
 384         return mem_ap_write(dap, buffer, 1, count, address, true);
 385 }
 386
 387 /**
 388  * Synchronous read of a block of memory, using a specific access size.
 389  *
 390  * @param dap The DAP connected to the MEM-AP.
 391  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 392  * @param size Which access size to use, in bytes. 1, 2 or 4.
 393  * @param count The number of reads to do (in size units, not bytes).
 394  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 395  * @param addrinc Whether the target address should be increased after each read or not. This
 396  *  should normally be true, except when reading from e.g. a FIFO.
 397  * @return ERROR_OK on success, otherwise an error code.
 398  */
 399 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 400                 uint32_t adr, bool addrinc)
 401 {
 402         size_t nbytes = size * count;
 403         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 404         uint32_t csw_size;
 405         uint32_t address = adr;
 406         int retval;
 407
 408         if (size == 4)
 409                 csw_size = CSW_32BIT;
 410         else if (size == 2)
 411                 csw_size = CSW_16BIT;
 412         else if (size == 1)
 413                 csw_size = CSW_8BIT;
 414         else
 415                 return ERROR_TARGET_UNALIGNED_ACCESS;
 416
 417         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 418          * over-allocation if packed transfers are going to be used, but determining the real need at
 419          * this point would be messy. */
 420         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 421         uint32_t *read_ptr = read_buf;
 422         if (read_buf == NULL) {
 423                 LOG_ERROR("Failed to allocate read buffer");
 424                 return ERROR_FAIL;
 425         }
 426
 427         retval = dap_setup_accessport_tar(dap, address);
 428         if (retval != ERROR_OK)
 429                 return retval;
 430
 431         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 432          * useful bytes it contains, and their location in the word, depends on the type of transfer
 433          * and alignment. */
 434         while (nbytes > 0) {
 435                 uint32_t this_size = size;
 436
 437                 /* Select packed transfer if possible */
 438                 if (addrinc && dap->packed_transfers && nbytes >= 4
 439                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 440                         this_size = 4;
 441                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 442                 } else {
 443                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 444                 }
 445                 if (retval != ERROR_OK)
 446                         break;
 447
 448                 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
 449                 if (retval != ERROR_OK)
 450                         break;
 451
 452                 nbytes -= this_size;
 453                 address += this_size;
 454
 455                 /* Rewrite TAR if it wrapped */
 456                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 457                         retval = dap_setup_accessport_tar(dap, address);
 458                         if (retval != ERROR_OK)
 459                                 break;
 460                 }
 461         }
 462
 463         if (retval == ERROR_OK)
 464                 retval = dap_run(dap);
 465
 466         /* Restore state */
 467         address = adr;
 468         nbytes = size * count;
 469         read_ptr = read_buf;
 470
 471         /* If something failed, read TAR to find out how much data was successfully read, so we can
 472          * at least give the caller what we have. */
 473         if (retval != ERROR_OK) {
 474                 uint32_t tar;
 475                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 476                                 && dap_run(dap) == ERROR_OK) {
 477                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 478                         if (nbytes > tar - address)
 479                                 nbytes = tar - address;
 480                 } else {
 481                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 482                         nbytes = 0;
 483                 }
 484         }
 485
 486         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 487         while (nbytes > 0) {
 488                 uint32_t this_size = size;
 489
 490                 if (addrinc && dap->packed_transfers && nbytes >= 4
 491                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 492                         this_size = 4;
 493                 }
 494
 495                 switch (this_size) {
 496                 case 4:
 497                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 498                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 499                 case 2:
 500                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 501                 case 1:
 502                         *buffer++ = *read_ptr >> 8 * (address++ & 3);
 503                 }
 504
 505                 read_ptr++;
 506                 nbytes -= this_size;
 507         }
 508
 509         free(read_buf);
 510         return retval;
 511 }
 512
 513 /* Compatibility wrappers around mem_ap_read(). Note that the count is in bytes for these (despite
 514  * what their doxygen documentation said). */
 515 int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 516                 int count, uint32_t address, bool addr_incr)
 517 {
 518         return mem_ap_read(dap, buffer, 4, count / 4, address, addr_incr);
 519 }
 520
 521 int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 522                 int count, uint32_t address)
 523 {
 524         return mem_ap_read(dap, buffer, 2, count / 2, address, true);
 525 }
 526
 527 int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 528                 int count, uint32_t address)
 529 {
 530         return mem_ap_read(dap, buffer, 1, count, address, true);
 531 }
 532
 533 /*--------------------------------------------------------------------*/
 534 /*          Wrapping function with selection of AP                    */
 535 /*--------------------------------------------------------------------*/
 536 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 537                 uint32_t address, uint32_t *value)
 538 {
 539         dap_ap_select(swjdp, ap);
 540         return mem_ap_read_u32(swjdp, address, value);
 541 }
 542
 543 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 544                 uint32_t address, uint32_t value)
 545 {
 546         dap_ap_select(swjdp, ap);
 547         return mem_ap_write_u32(swjdp, address, value);
 548 }
 549
 550 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 551                 uint32_t address, uint32_t *value)
 552 {
 553         dap_ap_select(swjdp, ap);
 554         return mem_ap_read_atomic_u32(swjdp, address, value);
 555 }
 556
 557 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 558                 uint32_t address, uint32_t value)
 559 {
 560         dap_ap_select(swjdp, ap);
 561         return mem_ap_write_atomic_u32(swjdp, address, value);
 562 }
 563
 564 int mem_ap_sel_read_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 565                 uint8_t *buffer, int count, uint32_t address)
 566 {
 567         dap_ap_select(swjdp, ap);
 568         return mem_ap_read_buf_u8(swjdp, buffer, count, address);
 569 }
 570
 571 int mem_ap_sel_read_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 572                 uint8_t *buffer, int count, uint32_t address)
 573 {
 574         dap_ap_select(swjdp, ap);
 575         return mem_ap_read_buf_u16(swjdp, buffer, count, address);
 576 }
 577
 578 int mem_ap_sel_read_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 579                 uint8_t *buffer, int count, uint32_t address)
 580 {
 581         dap_ap_select(swjdp, ap);
 582         return mem_ap_read_buf_u32(swjdp, buffer, count, address, false);
 583 }
 584
 585 int mem_ap_sel_read_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 586                 uint8_t *buffer, int count, uint32_t address)
 587 {
 588         dap_ap_select(swjdp, ap);
 589         return mem_ap_read_buf_u32(swjdp, buffer, count, address, true);
 590 }
 591
 592 int mem_ap_sel_write_buf_u8(struct adiv5_dap *swjdp, uint8_t ap,
 593                 const uint8_t *buffer, int count, uint32_t address)
 594 {
 595         dap_ap_select(swjdp, ap);
 596         return mem_ap_write_buf_u8(swjdp, buffer, count, address);
 597 }
 598
 599 int mem_ap_sel_write_buf_u16(struct adiv5_dap *swjdp, uint8_t ap,
 600                 const uint8_t *buffer, int count, uint32_t address)
 601 {
 602         dap_ap_select(swjdp, ap);
 603         return mem_ap_write_buf_u16(swjdp, buffer, count, address);
 604 }
 605
 606 int mem_ap_sel_write_buf_u32(struct adiv5_dap *swjdp, uint8_t ap,
 607                 const uint8_t *buffer, int count, uint32_t address)
 608 {
 609         dap_ap_select(swjdp, ap);
 610         return mem_ap_write_buf_u32(swjdp, buffer, count, address, true);
 611 }
 612
 613 int mem_ap_sel_write_buf_u32_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 614                 const uint8_t *buffer, int count, uint32_t address)
 615 {
 616         dap_ap_select(swjdp, ap);
 617         return mem_ap_write_buf_u32(swjdp, buffer, count, address, false);
 618 }
 619
 620 #define MDM_REG_STAT            0x00
 621 #define MDM_REG_CTRL            0x04
 622 #define MDM_REG_ID              0xfc
 623
 624 #define MDM_STAT_FMEACK         (1<<0)
 625 #define MDM_STAT_FREADY         (1<<1)
 626 #define MDM_STAT_SYSSEC         (1<<2)
 627 #define MDM_STAT_SYSRES         (1<<3)
 628 #define MDM_STAT_FMEEN          (1<<5)
 629 #define MDM_STAT_BACKDOOREN     (1<<6)
 630 #define MDM_STAT_LPEN           (1<<7)
 631 #define MDM_STAT_VLPEN          (1<<8)
 632 #define MDM_STAT_LLSMODEXIT     (1<<9)
 633 #define MDM_STAT_VLLSXMODEXIT   (1<<10)
 634 #define MDM_STAT_CORE_HALTED    (1<<16)
 635 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
 636 #define MDM_STAT_CORESLEEPING   (1<<18)
 637
 638 #define MEM_CTRL_FMEIP          (1<<0)
 639 #define MEM_CTRL_DBG_DIS        (1<<1)
 640 #define MEM_CTRL_DBG_REQ        (1<<2)
 641 #define MEM_CTRL_SYS_RES_REQ    (1<<3)
 642 #define MEM_CTRL_CORE_HOLD_RES  (1<<4)
 643 #define MEM_CTRL_VLLSX_DBG_REQ  (1<<5)
 644 #define MEM_CTRL_VLLSX_DBG_ACK  (1<<6)
 645 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
 646
 647 #define MDM_ACCESS_TIMEOUT      3000 /* ms */
 648
 649 /**
 650  *
 651  */
 652 int dap_syssec_kinetis_mdmap(struct adiv5_dap *dap)
 653 {
 654         uint32_t val;
 655         int retval;
 656         int timeout = 0;
 657         enum reset_types jtag_reset_config = jtag_get_reset_config();
 658
 659         dap_ap_select(dap, 1);
 660
 661         /* first check mdm-ap id register */
 662         retval = dap_queue_ap_read(dap, MDM_REG_ID, &val);
 663         if (retval != ERROR_OK)
 664                 return retval;
 665         dap_run(dap);
 666
 667         if (val != 0x001C0000) {
 668                 LOG_DEBUG("id doesn't match %08" PRIX32 " != 0x001C0000", val);
 669                 dap_ap_select(dap, 0);
 670                 return ERROR_FAIL;
 671         }
 672
 673         /* read and parse status register
 674          * it's important that the device is out of
 675          * reset here
 676          */
 677         while (1) {
 678                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 679                         LOG_DEBUG("MDMAP : flash ready timeout");
 680                         return ERROR_FAIL;
 681                 }
 682                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 683                 if (retval != ERROR_OK)
 684                         return retval;
 685                 dap_run(dap);
 686
 687                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 688                 if (val & MDM_STAT_FREADY)
 689                         break;
 690                 alive_sleep(1);
 691         }
 692
 693         if ((val & MDM_STAT_SYSSEC)) {
 694                 LOG_DEBUG("MDMAP: system is secured, masserase needed");
 695
 696                 if (!(val & MDM_STAT_FMEEN))
 697                         LOG_DEBUG("MDMAP: masserase is disabled");
 698                 else {
 699                         /* we need to assert reset */
 700                         if (jtag_reset_config & RESET_HAS_SRST) {
 701                                 /* default to asserting srst */
 702                                 adapter_assert_reset();
 703                         } else {
 704                                 LOG_DEBUG("SRST not configured");
 705                                 dap_ap_select(dap, 0);
 706                                 return ERROR_FAIL;
 707                         }
 708                         timeout = 0;
 709                         while (1) {
 710                                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 711                                         LOG_DEBUG("MDMAP : flash ready timeout");
 712                                         return ERROR_FAIL;
 713                                 }
 714                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, MEM_CTRL_FMEIP);
 715                                 if (retval != ERROR_OK)
 716                                         return retval;
 717                                 dap_run(dap);
 718                                 /* read status register and wait for ready */
 719                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 720                                 if (retval != ERROR_OK)
 721                                         return retval;
 722                                 dap_run(dap);
 723                                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 724
 725                                 if ((val & 1))
 726                                         break;
 727                                 alive_sleep(1);
 728                         }
 729                         timeout = 0;
 730                         while (1) {
 731                                 if (timeout++ > MDM_ACCESS_TIMEOUT) {
 732                                         LOG_DEBUG("MDMAP : flash ready timeout");
 733                                         return ERROR_FAIL;
 734                                 }
 735                                 retval = dap_queue_ap_write(dap, MDM_REG_CTRL, 0);
 736                                 if (retval != ERROR_OK)
 737                                         return retval;
 738                                 dap_run(dap);
 739                                 /* read status register */
 740                                 retval = dap_queue_ap_read(dap, MDM_REG_STAT, &val);
 741                                 if (retval != ERROR_OK)
 742                                         return retval;
 743                                 dap_run(dap);
 744                                 LOG_DEBUG("MDM_REG_STAT %08" PRIX32, val);
 745                                 /* read control register and wait for ready */
 746                                 retval = dap_queue_ap_read(dap, MDM_REG_CTRL, &val);
 747                                 if (retval != ERROR_OK)
 748                                         return retval;
 749                                 dap_run(dap);
 750                                 LOG_DEBUG("MDM_REG_CTRL %08" PRIX32, val);
 751
 752                                 if (val == 0x00)
 753                                         break;
 754                                 alive_sleep(1);
 755                         }
 756                 }
 757         }
 758
 759         dap_ap_select(dap, 0);
 760
 761         return ERROR_OK;
 762 }
 763
 764 /** */
 765 struct dap_syssec_filter {
 766         /** */
 767         uint32_t idcode;
 768         /** */
 769         int (*dap_init)(struct adiv5_dap *dap);
 770 };
 771
 772 /** */
 773 static struct dap_syssec_filter dap_syssec_filter_data[] = {
 774         { 0x4BA00477, dap_syssec_kinetis_mdmap }
 775 };
 776
 777 /**
 778  *
 779  */
 780 int dap_syssec(struct adiv5_dap *dap)
 781 {
 782         unsigned int i;
 783         struct jtag_tap *tap;
 784
 785         for (i = 0; i < sizeof(dap_syssec_filter_data); i++) {
 786                 tap = dap->jtag_info->tap;
 787
 788                 while (tap != NULL) {
 789                         if (tap->hasidcode && (dap_syssec_filter_data[i].idcode == tap->idcode)) {
 790                                 LOG_DEBUG("DAP: mdmap_init for idcode: %08" PRIx32, tap->idcode);
 791                                 dap_syssec_filter_data[i].dap_init(dap);
 792                         }
 793                         tap = tap->next_tap;
 794                 }
 795         }
 796
 797         return ERROR_OK;
 798 }
 799
 800 /*--------------------------------------------------------------------------*/
 801
 802
 803 /* FIXME don't import ... just initialize as
 804  * part of DAP transport setup
 805 */
 806 extern const struct dap_ops jtag_dp_ops;
 807
 808 /*--------------------------------------------------------------------------*/
 809
 810 /**
 811  * Initialize a DAP.  This sets up the power domains, prepares the DP
 812  * for further use, and arranges to use AP #0 for all AP operations
 813  * until dap_ap-select() changes that policy.
 814  *
 815  * @param dap The DAP being initialized.
 816  *
 817  * @todo Rename this.  We also need an initialization scheme which account
 818  * for SWD transports not just JTAG; that will need to address differences
 819  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 820  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 821  */
 822 int ahbap_debugport_init(struct adiv5_dap *dap)
 823 {
 824         uint32_t ctrlstat;
 825         int cnt = 0;
 826         int retval;
 827
 828         LOG_DEBUG(" ");
 829
 830         /* JTAG-DP or SWJ-DP, in JTAG mode
 831          * ... for SWD mode this is patched as part
 832          * of link switchover
 833          */
 834         if (!dap->ops)
 835                 dap->ops = &jtag_dp_ops;
 836
 837         /* Default MEM-AP setup.
 838          *
 839          * REVISIT AP #0 may be an inappropriate default for this.
 840          * Should we probe, or take a hint from the caller?
 841          * Presumably we can ignore the possibility of multiple APs.
 842          */
 843         dap->ap_current = !0;
 844         dap_ap_select(dap, 0);
 845
 846         /* DP initialization */
 847
 848         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 849         if (retval != ERROR_OK)
 850                 return retval;
 851
 852         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 853         if (retval != ERROR_OK)
 854                 return retval;
 855
 856         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 857         if (retval != ERROR_OK)
 858                 return retval;
 859
 860         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 861         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 862         if (retval != ERROR_OK)
 863                 return retval;
 864
 865         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 866         if (retval != ERROR_OK)
 867                 return retval;
 868         retval = dap_run(dap);
 869         if (retval != ERROR_OK)
 870                 return retval;
 871
 872         /* Check that we have debug power domains activated */
 873         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
 874                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 875                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 876                 if (retval != ERROR_OK)
 877                         return retval;
 878                 retval = dap_run(dap);
 879                 if (retval != ERROR_OK)
 880                         return retval;
 881                 alive_sleep(10);
 882         }
 883
 884         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
 885                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 886                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 887                 if (retval != ERROR_OK)
 888                         return retval;
 889                 retval = dap_run(dap);
 890                 if (retval != ERROR_OK)
 891                         return retval;
 892                 alive_sleep(10);
 893         }
 894
 895         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 896         if (retval != ERROR_OK)
 897                 return retval;
 898         /* With debug power on we can activate OVERRUN checking */
 899         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 900         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 901         if (retval != ERROR_OK)
 902                 return retval;
 903         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 904         if (retval != ERROR_OK)
 905                 return retval;
 906
 907         dap_syssec(dap);
 908
 909         /* check that we support packed transfers */
 910         uint32_t csw;
 911
 912         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 913         if (retval != ERROR_OK)
 914                 return retval;
 915
 916         retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
 917         if (retval != ERROR_OK)
 918                 return retval;
 919
 920         retval = dap_run(dap);
 921         if (retval != ERROR_OK)
 922                 return retval;
 923
 924         if (csw & CSW_ADDRINC_PACKED)
 925                 dap->packed_transfers = true;
 926         else
 927                 dap->packed_transfers = false;
 928
 929         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 930                         dap->packed_transfers ? "enabled" : "disabled");
 931
 932         return ERROR_OK;
 933 }
 934
 935 /* CID interpretation -- see ARM IHI 0029B section 3
 936  * and ARM IHI 0031A table 13-3.
 937  */
 938 static const char *class_description[16] = {
 939         "Reserved", "ROM table", "Reserved", "Reserved",
 940         "Reserved", "Reserved", "Reserved", "Reserved",
 941         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 942         "Reserved", "OptimoDE DESS",
 943         "Generic IP component", "PrimeCell or System component"
 944 };
 945
 946 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 947 {
 948         return cid3 == 0xb1 && cid2 == 0x05
 949                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 950 }
 951
 952 /*
 953  * This function checks the ID for each access port to find the requested Access Port type
 954  */
 955 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 956 {
 957         int ap;
 958
 959         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 960         for (ap = 0; ap <= 255; ap++) {
 961
 962                 /* read the IDR register of the Access Port */
 963                 uint32_t id_val = 0;
 964                 dap_ap_select(dap, ap);
 965
 966                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 967                 if (retval != ERROR_OK)
 968                         return retval;
 969
 970                 retval = dap_run(dap);
 971
 972                 /* IDR bits:
 973                  * 31-28 : Revision
 974                  * 27-24 : JEDEC bank (0x4 for ARM)
 975                  * 23-17 : JEDEC code (0x3B for ARM)
 976                  * 16    : Mem-AP
 977                  * 15-8  : Reserved
 978                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 979                  */
 980
 981                 /* Reading register for a non-existant AP should not cause an error,
 982                  * but just to be sure, try to continue searching if an error does happen.
 983                  */
 984                 if ((retval == ERROR_OK) &&                  /* Register read success */
 985                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 986                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 987
 988                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 989                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 990                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 991                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 992                                                 ap, id_val);
 993
 994                         *ap_num_out = ap;
 995                         return ERROR_OK;
 996                 }
 997         }
 998
 999         LOG_DEBUG("No %s found",
1000                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
1001                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
1002                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
1003         return ERROR_FAIL;
1004 }
1005
1006 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
1007                         uint32_t *out_dbgbase, uint32_t *out_apid)
1008 {
1009         uint32_t ap_old;
1010         int retval;
1011         uint32_t dbgbase, apid;
1012
1013         /* AP address is in bits 31:24 of DP_SELECT */
1014         if (ap >= 256)
1015                 return ERROR_COMMAND_SYNTAX_ERROR;
1016
1017         ap_old = dap->ap_current;
1018         dap_ap_select(dap, ap);
1019
1020         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
1021         if (retval != ERROR_OK)
1022                 return retval;
1023         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1024         if (retval != ERROR_OK)
1025                 return retval;
1026         retval = dap_run(dap);
1027         if (retval != ERROR_OK)
1028                 return retval;
1029
1030         /* Excavate the device ID code */
1031         struct jtag_tap *tap = dap->jtag_info->tap;
1032         while (tap != NULL) {
1033                 if (tap->hasidcode)
1034                         break;
1035                 tap = tap->next_tap;
1036         }
1037         if (tap == NULL || !tap->hasidcode)
1038                 return ERROR_OK;
1039
1040         dap_ap_select(dap, ap_old);
1041
1042         /* The asignment happens only here to prevent modification of these
1043          * values before they are certain. */
1044         *out_dbgbase = dbgbase;
1045         *out_apid = apid;
1046
1047         return ERROR_OK;
1048 }
1049
1050 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
1051                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
1052 {
1053         uint32_t ap_old;
1054         uint32_t romentry, entry_offset = 0, component_base, devtype;
1055         int retval = ERROR_FAIL;
1056
1057         if (ap >= 256)
1058                 return ERROR_COMMAND_SYNTAX_ERROR;
1059
1060         ap_old = dap->ap_current;
1061         dap_ap_select(dap, ap);
1062
1063         do {
1064                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
1065                                                 entry_offset, &romentry);
1066                 if (retval != ERROR_OK)
1067                         return retval;
1068
1069                 component_base = (dbgbase & 0xFFFFF000)
1070                         + (romentry & 0xFFFFF000);
1071
1072                 if (romentry & 0x1) {
1073                         retval = mem_ap_read_atomic_u32(dap,
1074                                         (component_base & 0xfffff000) | 0xfcc,
1075                                         &devtype);
1076                         if (retval != ERROR_OK)
1077                                 return retval;
1078                         if ((devtype & 0xff) == type) {
1079                                 *addr = component_base;
1080                                 retval = ERROR_OK;
1081                                 break;
1082                         }
1083                 }
1084                 entry_offset += 4;
1085         } while (romentry > 0);
1086
1087         dap_ap_select(dap, ap_old);
1088
1089         return retval;
1090 }
1091
1092 static int dap_info_command(struct command_context *cmd_ctx,
1093                 struct adiv5_dap *dap, int ap)
1094 {
1095         int retval;
1096         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1097         int romtable_present = 0;
1098         uint8_t mem_ap;
1099         uint32_t ap_old;
1100
1101         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1102         if (retval != ERROR_OK)
1103                 return retval;
1104
1105         ap_old = dap->ap_current;
1106         dap_ap_select(dap, ap);
1107
1108         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1109         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1110         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1111         if (apid) {
1112                 switch (apid&0x0F) {
1113                         case 0:
1114                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1115                                 break;
1116                         case 1:
1117                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1118                                 break;
1119                         case 2:
1120                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1121                                 break;
1122                         default:
1123                                 command_print(cmd_ctx, "\tUnknown AP type");
1124                                 break;
1125                 }
1126
1127                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1128                  * not a ROM table ... or have no such components at all.
1129                  */
1130                 if (mem_ap)
1131                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1132         } else
1133                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1134
1135         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1136         if (romtable_present) {
1137                 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
1138                 uint16_t entry_offset;
1139
1140                 /* bit 16 of apid indicates a memory access port */
1141                 if (dbgbase & 0x02)
1142                         command_print(cmd_ctx, "\tValid ROM table present");
1143                 else
1144                         command_print(cmd_ctx, "\tROM table in legacy format");
1145
1146                 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1147                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1148                 if (retval != ERROR_OK)
1149                         return retval;
1150                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1151                 if (retval != ERROR_OK)
1152                         return retval;
1153                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1154                 if (retval != ERROR_OK)
1155                         return retval;
1156                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1157                 if (retval != ERROR_OK)
1158                         return retval;
1159                 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1160                 if (retval != ERROR_OK)
1161                         return retval;
1162                 retval = dap_run(dap);
1163                 if (retval != ERROR_OK)
1164                         return retval;
1165
1166                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1167                         command_print(cmd_ctx, "\tCID3 0x%2.2x"
1168                                         ", CID2 0x%2.2x"
1169                                         ", CID1 0x%2.2x"
1170                                         ", CID0 0x%2.2x",
1171                                         (unsigned) cid3, (unsigned)cid2,
1172                                         (unsigned) cid1, (unsigned) cid0);
1173                 if (memtype & 0x01)
1174                         command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1175                 else
1176                         command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1177                                         "Dedicated debug bus.");
1178
1179                 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1180                 entry_offset = 0;
1181                 do {
1182                         retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1183                         if (retval != ERROR_OK)
1184                                 return retval;
1185                         command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "", entry_offset, romentry);
1186                         if (romentry & 0x01) {
1187                                 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1188                                 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1189                                 uint32_t component_base;
1190                                 unsigned part_num;
1191                                 char *type, *full;
1192
1193                                 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1194
1195                                 /* IDs are in last 4K section */
1196                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1197                                 if (retval != ERROR_OK)
1198                                         return retval;
1199                                 c_pid0 &= 0xff;
1200                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1201                                 if (retval != ERROR_OK)
1202                                         return retval;
1203                                 c_pid1 &= 0xff;
1204                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1205                                 if (retval != ERROR_OK)
1206                                         return retval;
1207                                 c_pid2 &= 0xff;
1208                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1209                                 if (retval != ERROR_OK)
1210                                         return retval;
1211                                 c_pid3 &= 0xff;
1212                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1213                                 if (retval != ERROR_OK)
1214                                         return retval;
1215                                 c_pid4 &= 0xff;
1216
1217                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1218                                 if (retval != ERROR_OK)
1219                                         return retval;
1220                                 c_cid0 &= 0xff;
1221                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1222                                 if (retval != ERROR_OK)
1223                                         return retval;
1224                                 c_cid1 &= 0xff;
1225                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1226                                 if (retval != ERROR_OK)
1227                                         return retval;
1228                                 c_cid2 &= 0xff;
1229                                 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1230                                 if (retval != ERROR_OK)
1231                                         return retval;
1232                                 c_cid3 &= 0xff;
1233
1234                                 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ","
1235                                                 "start address 0x%" PRIx32, component_base,
1236                                 /* component may take multiple 4K pages */
1237                                 component_base - 0x1000*(c_pid4 >> 4));
1238                                 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1239                                                 (int) (c_cid1 >> 4) & 0xf,
1240                                                 /* See ARM IHI 0029B Table 3-3 */
1241                                                 class_description[(c_cid1 >> 4) & 0xf]);
1242
1243                                 /* CoreSight component? */
1244                                 if (((c_cid1 >> 4) & 0x0f) == 9) {
1245                                         uint32_t devtype;
1246                                         unsigned minor;
1247                                         char *major = "Reserved", *subtype = "Reserved";
1248
1249                                         retval = mem_ap_read_atomic_u32(dap,
1250                                                         (component_base & 0xfffff000) | 0xfcc,
1251                                                         &devtype);
1252                                         if (retval != ERROR_OK)
1253                                                 return retval;
1254                                         minor = (devtype >> 4) & 0x0f;
1255                                         switch (devtype & 0x0f) {
1256                                         case 0:
1257                                                 major = "Miscellaneous";
1258                                                 switch (minor) {
1259                                                 case 0:
1260                                                         subtype = "other";
1261                                                         break;
1262                                                 case 4:
1263                                                         subtype = "Validation component";
1264                                                         break;
1265                                                 }
1266                                                 break;
1267                                         case 1:
1268                                                 major = "Trace Sink";
1269                                                 switch (minor) {
1270                                                 case 0:
1271                                                         subtype = "other";
1272                                                         break;
1273                                                 case 1:
1274                                                         subtype = "Port";
1275                                                         break;
1276                                                 case 2:
1277                                                         subtype = "Buffer";
1278                                                         break;
1279                                                 }
1280                                                 break;
1281                                         case 2:
1282                                                 major = "Trace Link";
1283                                                 switch (minor) {
1284                                                 case 0:
1285                                                         subtype = "other";
1286                                                         break;
1287                                                 case 1:
1288                                                         subtype = "Funnel, router";
1289                                                         break;
1290                                                 case 2:
1291                                                         subtype = "Filter";
1292                                                         break;
1293                                                 case 3:
1294                                                         subtype = "FIFO, buffer";
1295                                                         break;
1296                                                 }
1297                                                 break;
1298                                         case 3:
1299                                                 major = "Trace Source";
1300                                                 switch (minor) {
1301                                                 case 0:
1302                                                         subtype = "other";
1303                                                         break;
1304                                                 case 1:
1305                                                         subtype = "Processor";
1306                                                         break;
1307                                                 case 2:
1308                                                         subtype = "DSP";
1309                                                         break;
1310                                                 case 3:
1311                                                         subtype = "Engine/Coprocessor";
1312                                                         break;
1313                                                 case 4:
1314                                                         subtype = "Bus";
1315                                                         break;
1316                                                 }
1317                                                 break;
1318                                         case 4:
1319                                                 major = "Debug Control";
1320                                                 switch (minor) {
1321                                                 case 0:
1322                                                         subtype = "other";
1323                                                         break;
1324                                                 case 1:
1325                                                         subtype = "Trigger Matrix";
1326                                                         break;
1327                                                 case 2:
1328                                                         subtype = "Debug Auth";
1329                                                         break;
1330                                                 }
1331                                                 break;
1332                                         case 5:
1333                                                 major = "Debug Logic";
1334                                                 switch (minor) {
1335                                                 case 0:
1336                                                         subtype = "other";
1337                                                         break;
1338                                                 case 1:
1339                                                         subtype = "Processor";
1340                                                         break;
1341                                                 case 2:
1342                                                         subtype = "DSP";
1343                                                         break;
1344                                                 case 3:
1345                                                         subtype = "Engine/Coprocessor";
1346                                                         break;
1347                                                 }
1348                                                 break;
1349                                         }
1350                                         command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1351                                                         (unsigned) (devtype & 0xff),
1352                                                         major, subtype);
1353                                         /* REVISIT also show 0xfc8 DevId */
1354                                 }
1355
1356                                 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1357                                         command_print(cmd_ctx,
1358                                                         "\t\tCID3 0%2.2x"
1359                                                         ", CID2 0%2.2x"
1360                                                         ", CID1 0%2.2x"
1361                                                         ", CID0 0%2.2x",
1362                                                         (int) c_cid3,
1363                                                         (int) c_cid2,
1364                                                         (int)c_cid1,
1365                                                         (int)c_cid0);
1366                                 command_print(cmd_ctx,
1367                                 "\t\tPeripheral ID[4..0] = hex "
1368                                 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1369                                 (int) c_pid4, (int) c_pid3, (int) c_pid2,
1370                                 (int) c_pid1, (int) c_pid0);
1371
1372                                 /* Part number interpretations are from Cortex
1373                                  * core specs, the CoreSight components TRM
1374                                  * (ARM DDI 0314H), CoreSight System Design
1375                                  * Guide (ARM DGI 0012D) and ETM specs; also
1376                                  * from chip observation (e.g. TI SDTI).
1377                                  */
1378                                 part_num = (c_pid0 & 0xff);
1379                                 part_num |= (c_pid1 & 0x0f) << 8;
1380                                 switch (part_num) {
1381                                 case 0x000:
1382                                         type = "Cortex-M3 NVIC";
1383                                         full = "(Interrupt Controller)";
1384                                         break;
1385                                 case 0x001:
1386                                         type = "Cortex-M3 ITM";
1387                                         full = "(Instrumentation Trace Module)";
1388                                         break;
1389                                 case 0x002:
1390                                         type = "Cortex-M3 DWT";
1391                                         full = "(Data Watchpoint and Trace)";
1392                                         break;
1393                                 case 0x003:
1394                                         type = "Cortex-M3 FBP";
1395                                         full = "(Flash Patch and Breakpoint)";
1396                                         break;
1397                                 case 0x00c:
1398                                         type = "Cortex-M4 SCS";
1399                                         full = "(System Control Space)";
1400                                         break;
1401                                 case 0x00d:
1402                                         type = "CoreSight ETM11";
1403                                         full = "(Embedded Trace)";
1404                                         break;
1405                                 /* case 0x113: what? */
1406                                 case 0x120:             /* from OMAP3 memmap */
1407                                         type = "TI SDTI";
1408                                         full = "(System Debug Trace Interface)";
1409                                         break;
1410                                 case 0x343:             /* from OMAP3 memmap */
1411                                         type = "TI DAPCTL";
1412                                         full = "";
1413                                         break;
1414                                 case 0x906:
1415                                         type = "Coresight CTI";
1416                                         full = "(Cross Trigger)";
1417                                         break;
1418                                 case 0x907:
1419                                         type = "Coresight ETB";
1420                                         full = "(Trace Buffer)";
1421                                         break;
1422                                 case 0x908:
1423                                         type = "Coresight CSTF";
1424                                         full = "(Trace Funnel)";
1425                                         break;
1426                                 case 0x910:
1427                                         type = "CoreSight ETM9";
1428                                         full = "(Embedded Trace)";
1429                                         break;
1430                                 case 0x912:
1431                                         type = "Coresight TPIU";
1432                                         full = "(Trace Port Interface Unit)";
1433                                         break;
1434                                 case 0x921:
1435                                         type = "Cortex-A8 ETM";
1436                                         full = "(Embedded Trace)";
1437                                         break;
1438                                 case 0x922:
1439                                         type = "Cortex-A8 CTI";
1440                                         full = "(Cross Trigger)";
1441                                         break;
1442                                 case 0x923:
1443                                         type = "Cortex-M3 TPIU";
1444                                         full = "(Trace Port Interface Unit)";
1445                                         break;
1446                                 case 0x924:
1447                                         type = "Cortex-M3 ETM";
1448                                         full = "(Embedded Trace)";
1449                                         break;
1450                                 case 0x925:
1451                                         type = "Cortex-M4 ETM";
1452                                         full = "(Embedded Trace)";
1453                                         break;
1454                                 case 0x930:
1455                                         type = "Cortex-R4 ETM";
1456                                         full = "(Embedded Trace)";
1457                                         break;
1458                                 case 0x9a1:
1459                                         type = "Cortex-M4 TPUI";
1460                                         full = "(Trace Port Interface Unit)";
1461                                         break;
1462                                 case 0xc08:
1463                                         type = "Cortex-A8 Debug";
1464                                         full = "(Debug Unit)";
1465                                         break;
1466                                 default:
1467                                         type = "-*- unrecognized -*-";
1468                                         full = "";
1469                                         break;
1470                                 }
1471                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1472                                                 type, full);
1473                         } else {
1474                                 if (romentry)
1475                                         command_print(cmd_ctx, "\t\tComponent not present");
1476                                 else
1477                                         command_print(cmd_ctx, "\t\tEnd of ROM table");
1478                         }
1479                         entry_offset += 4;
1480                 } while (romentry > 0);
1481         } else
1482                 command_print(cmd_ctx, "\tNo ROM table present");
1483         dap_ap_select(dap, ap_old);
1484
1485         return ERROR_OK;
1486 }
1487
1488 COMMAND_HANDLER(handle_dap_info_command)
1489 {
1490         struct target *target = get_current_target(CMD_CTX);
1491         struct arm *arm = target_to_arm(target);
1492         struct adiv5_dap *dap = arm->dap;
1493         uint32_t apsel;
1494
1495         switch (CMD_ARGC) {
1496         case 0:
1497                 apsel = dap->apsel;
1498                 break;
1499         case 1:
1500                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1501                 break;
1502         default:
1503                 return ERROR_COMMAND_SYNTAX_ERROR;
1504         }
1505
1506         return dap_info_command(CMD_CTX, dap, apsel);
1507 }
1508
1509 COMMAND_HANDLER(dap_baseaddr_command)
1510 {
1511         struct target *target = get_current_target(CMD_CTX);
1512         struct arm *arm = target_to_arm(target);
1513         struct adiv5_dap *dap = arm->dap;
1514
1515         uint32_t apsel, baseaddr;
1516         int retval;
1517
1518         switch (CMD_ARGC) {
1519         case 0:
1520                 apsel = dap->apsel;
1521                 break;
1522         case 1:
1523                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1524                 /* AP address is in bits 31:24 of DP_SELECT */
1525                 if (apsel >= 256)
1526                         return ERROR_COMMAND_SYNTAX_ERROR;
1527                 break;
1528         default:
1529                 return ERROR_COMMAND_SYNTAX_ERROR;
1530         }
1531
1532         dap_ap_select(dap, apsel);
1533
1534         /* NOTE:  assumes we're talking to a MEM-AP, which
1535          * has a base address.  There are other kinds of AP,
1536          * though they're not common for now.  This should
1537          * use the ID register to verify it's a MEM-AP.
1538          */
1539         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1540         if (retval != ERROR_OK)
1541                 return retval;
1542         retval = dap_run(dap);
1543         if (retval != ERROR_OK)
1544                 return retval;
1545
1546         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1547
1548         return retval;
1549 }
1550
1551 COMMAND_HANDLER(dap_memaccess_command)
1552 {
1553         struct target *target = get_current_target(CMD_CTX);
1554         struct arm *arm = target_to_arm(target);
1555         struct adiv5_dap *dap = arm->dap;
1556
1557         uint32_t memaccess_tck;
1558
1559         switch (CMD_ARGC) {
1560         case 0:
1561                 memaccess_tck = dap->memaccess_tck;
1562                 break;
1563         case 1:
1564                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1565                 break;
1566         default:
1567                 return ERROR_COMMAND_SYNTAX_ERROR;
1568         }
1569         dap->memaccess_tck = memaccess_tck;
1570
1571         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1572                         dap->memaccess_tck);
1573
1574         return ERROR_OK;
1575 }
1576
1577 COMMAND_HANDLER(dap_apsel_command)
1578 {
1579         struct target *target = get_current_target(CMD_CTX);
1580         struct arm *arm = target_to_arm(target);
1581         struct adiv5_dap *dap = arm->dap;
1582
1583         uint32_t apsel, apid;
1584         int retval;
1585
1586         switch (CMD_ARGC) {
1587         case 0:
1588                 apsel = 0;
1589                 break;
1590         case 1:
1591                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1592                 /* AP address is in bits 31:24 of DP_SELECT */
1593                 if (apsel >= 256)
1594                         return ERROR_COMMAND_SYNTAX_ERROR;
1595                 break;
1596         default:
1597                 return ERROR_COMMAND_SYNTAX_ERROR;
1598         }
1599
1600         dap->apsel = apsel;
1601         dap_ap_select(dap, apsel);
1602
1603         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1604         if (retval != ERROR_OK)
1605                 return retval;
1606         retval = dap_run(dap);
1607         if (retval != ERROR_OK)
1608                 return retval;
1609
1610         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1611                         apsel, apid);
1612
1613         return retval;
1614 }
1615
1616 COMMAND_HANDLER(dap_apcsw_command)
1617 {
1618         struct target *target = get_current_target(CMD_CTX);
1619         struct arm *arm = target_to_arm(target);
1620         struct adiv5_dap *dap = arm->dap;
1621
1622         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1623
1624         switch (CMD_ARGC) {
1625         case 0:
1626                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1627                         (dap->apsel), apcsw);
1628                 break;
1629         case 1:
1630                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1631                 /* AP address is in bits 31:24 of DP_SELECT */
1632                 if (sprot > 1)
1633                         return ERROR_COMMAND_SYNTAX_ERROR;
1634                 if (sprot)
1635                         apcsw |= CSW_SPROT;
1636                 else
1637                         apcsw &= ~CSW_SPROT;
1638                 break;
1639         default:
1640                 return ERROR_COMMAND_SYNTAX_ERROR;
1641         }
1642         dap->apcsw[dap->apsel] = apcsw;
1643
1644         return 0;
1645 }
1646
1647
1648
1649 COMMAND_HANDLER(dap_apid_command)
1650 {
1651         struct target *target = get_current_target(CMD_CTX);
1652         struct arm *arm = target_to_arm(target);
1653         struct adiv5_dap *dap = arm->dap;
1654
1655         uint32_t apsel, apid;
1656         int retval;
1657
1658         switch (CMD_ARGC) {
1659         case 0:
1660                 apsel = dap->apsel;
1661                 break;
1662         case 1:
1663                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1664                 /* AP address is in bits 31:24 of DP_SELECT */
1665                 if (apsel >= 256)
1666                         return ERROR_COMMAND_SYNTAX_ERROR;
1667                 break;
1668         default:
1669                 return ERROR_COMMAND_SYNTAX_ERROR;
1670         }
1671
1672         dap_ap_select(dap, apsel);
1673
1674         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1675         if (retval != ERROR_OK)
1676                 return retval;
1677         retval = dap_run(dap);
1678         if (retval != ERROR_OK)
1679                 return retval;
1680
1681         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1682
1683         return retval;
1684 }
1685
1686 static const struct command_registration dap_commands[] = {
1687         {
1688                 .name = "info",
1689                 .handler = handle_dap_info_command,
1690                 .mode = COMMAND_EXEC,
1691                 .help = "display ROM table for MEM-AP "
1692                         "(default currently selected AP)",
1693                 .usage = "[ap_num]",
1694         },
1695         {
1696                 .name = "apsel",
1697                 .handler = dap_apsel_command,
1698                 .mode = COMMAND_EXEC,
1699                 .help = "Set the currently selected AP (default 0) "
1700                         "and display the result",
1701                 .usage = "[ap_num]",
1702         },
1703         {
1704                 .name = "apcsw",
1705                 .handler = dap_apcsw_command,
1706                 .mode = COMMAND_EXEC,
1707                 .help = "Set csw access bit ",
1708                 .usage = "[sprot]",
1709         },
1710
1711         {
1712                 .name = "apid",
1713                 .handler = dap_apid_command,
1714                 .mode = COMMAND_EXEC,
1715                 .help = "return ID register from AP "
1716                         "(default currently selected AP)",
1717                 .usage = "[ap_num]",
1718         },
1719         {
1720                 .name = "baseaddr",
1721                 .handler = dap_baseaddr_command,
1722                 .mode = COMMAND_EXEC,
1723                 .help = "return debug base address from MEM-AP "
1724                         "(default currently selected AP)",
1725                 .usage = "[ap_num]",
1726         },
1727         {
1728                 .name = "memaccess",
1729                 .handler = dap_memaccess_command,
1730                 .mode = COMMAND_EXEC,
1731                 .help = "set/get number of extra tck for MEM-AP memory "
1732                         "bus access [0-255]",
1733                 .usage = "[cycles]",
1734         },
1735         COMMAND_REGISTRATION_DONE
1736 };
1737
1738 const struct command_registration dap_command_handlers[] = {
1739         {
1740                 .name = "dap",
1741                 .mode = COMMAND_EXEC,
1742                 .help = "DAP command group",
1743                 .usage = "",
1744                 .chain = dap_commands,
1745         },
1746         COMMAND_REGISTRATION_DONE
1747 };