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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm920t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 0
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm920t_quit();
  52 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size);
  53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm920t_soft_reset_halt(struct target_s *target);
  56
  57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
  58
  59 target_type_t arm920t_target =
  60 {
  61         .name = "arm920t",
  62
  63         .poll = arm7_9_poll,
  64         .arch_state = arm920t_arch_state,
  65
  66         .halt = arm7_9_halt,
  67         .resume = arm7_9_resume,
  68         .step = arm7_9_step,
  69
  70         .assert_reset = arm7_9_assert_reset,
  71         .deassert_reset = arm7_9_deassert_reset,
  72         .soft_reset_halt = arm920t_soft_reset_halt,
  73         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  74
  75         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  76
  77         .read_memory = arm920t_read_memory,
  78         .write_memory = arm920t_write_memory,
  79         .bulk_write_memory = arm7_9_bulk_write_memory,
  80
  81         .run_algorithm = armv4_5_run_algorithm,
  82
  83         .add_breakpoint = arm7_9_add_breakpoint,
  84         .remove_breakpoint = arm7_9_remove_breakpoint,
  85         .add_watchpoint = arm7_9_add_watchpoint,
  86         .remove_watchpoint = arm7_9_remove_watchpoint,
  87
  88         .register_commands = arm920t_register_commands,
  89         .target_command = arm920t_target_command,
  90         .init_target = arm920t_init_target,
  91         .quit = arm920t_quit
  92 };
  93
  94 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
  95 {
  96         armv4_5_common_t *armv4_5 = target->arch_info;
  97         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  98         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
  99         scan_field_t fields[4];
 100         u8 access_type_buf = 1;
 101         u8 reg_addr_buf = reg_addr & 0x3f;
 102         u8 nr_w_buf = 0;
 103
 104         jtag_add_end_state(TAP_RTI);
 105         arm_jtag_scann(jtag_info, 0xf);
 106         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 107
 108         fields[0].device = jtag_info->chain_pos;
 109         fields[0].num_bits = 1;
 110         fields[0].out_value = &access_type_buf;
 111         fields[0].out_mask = NULL;
 112         fields[0].in_value = NULL;
 113         fields[0].in_check_value = NULL;
 114         fields[0].in_check_mask = NULL;
 115         fields[0].in_handler = NULL;
 116         fields[0].in_handler_priv = NULL;
 117
 118         fields[1].device = jtag_info->chain_pos;
 119         fields[1].num_bits = 32;
 120         fields[1].out_value = NULL;
 121         fields[1].out_mask = NULL;
 122         fields[1].in_value = NULL;
 123         fields[1].in_check_value = NULL;
 124         fields[1].in_check_mask = NULL;
 125         fields[1].in_handler = NULL;
 126         fields[1].in_handler_priv = NULL;
 127
 128         fields[2].device = jtag_info->chain_pos;
 129         fields[2].num_bits = 6;
 130         fields[2].out_value = &reg_addr_buf;
 131         fields[2].out_mask = NULL;
 132         fields[2].in_value = NULL;
 133         fields[2].in_check_value = NULL;
 134         fields[2].in_check_mask = NULL;
 135         fields[2].in_handler = NULL;
 136         fields[2].in_handler_priv = NULL;
 137
 138         fields[3].device = jtag_info->chain_pos;
 139         fields[3].num_bits = 1;
 140         fields[3].out_value = &nr_w_buf;
 141         fields[3].out_mask = NULL;
 142         fields[3].in_value = NULL;
 143         fields[3].in_check_value = NULL;
 144         fields[3].in_check_mask = NULL;
 145         fields[3].in_handler = NULL;
 146         fields[3].in_handler_priv = NULL;
 147
 148         jtag_add_dr_scan(4, fields, -1, NULL);
 149
 150         fields[1].in_handler_priv = value;
 151         fields[1].in_handler = arm_jtag_buf_to_u32;
 152
 153         jtag_add_dr_scan(4, fields, -1, NULL);
 154
 155 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 156         jtag_execute_queue();
 157         DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 158 #endif
 159
 160         return ERROR_OK;
 161 }
 162
 163 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 164 {
 165         armv4_5_common_t *armv4_5 = target->arch_info;
 166         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 167         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 168         scan_field_t fields[4];
 169         u8 access_type_buf = 1;
 170         u8 reg_addr_buf = reg_addr & 0x3f;
 171         u8 nr_w_buf = 1;
 172         u8 value_buf[4];
 173
 174         buf_set_u32(value_buf, 0, 32, value);
 175
 176         jtag_add_end_state(TAP_RTI);
 177         arm_jtag_scann(jtag_info, 0xf);
 178         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 179
 180         fields[0].device = jtag_info->chain_pos;
 181         fields[0].num_bits = 1;
 182         fields[0].out_value = &access_type_buf;
 183         fields[0].out_mask = NULL;
 184         fields[0].in_value = NULL;
 185         fields[0].in_check_value = NULL;
 186         fields[0].in_check_mask = NULL;
 187         fields[0].in_handler = NULL;
 188         fields[0].in_handler_priv = NULL;
 189
 190         fields[1].device = jtag_info->chain_pos;
 191         fields[1].num_bits = 32;
 192         fields[1].out_value = value_buf;
 193         fields[1].out_mask = NULL;
 194         fields[1].in_value = NULL;
 195         fields[1].in_check_value = NULL;
 196         fields[1].in_check_mask = NULL;
 197         fields[1].in_handler = NULL;
 198         fields[1].in_handler_priv = NULL;
 199
 200         fields[2].device = jtag_info->chain_pos;
 201         fields[2].num_bits = 6;
 202         fields[2].out_value = &reg_addr_buf;
 203         fields[2].out_mask = NULL;
 204         fields[2].in_value = NULL;
 205         fields[2].in_check_value = NULL;
 206         fields[2].in_check_mask = NULL;
 207         fields[2].in_handler = NULL;
 208         fields[2].in_handler_priv = NULL;
 209
 210         fields[3].device = jtag_info->chain_pos;
 211         fields[3].num_bits = 1;
 212         fields[3].out_value = &nr_w_buf;
 213         fields[3].out_mask = NULL;
 214         fields[3].in_value = NULL;
 215         fields[3].in_check_value = NULL;
 216         fields[3].in_check_mask = NULL;
 217         fields[3].in_handler = NULL;
 218         fields[3].in_handler_priv = NULL;
 219
 220         jtag_add_dr_scan(4, fields, -1, NULL);
 221
 222 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 223         DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
 224 #endif
 225
 226         return ERROR_OK;
 227 }
 228
 229 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 230 {
 231         armv4_5_common_t *armv4_5 = target->arch_info;
 232         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 233         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 234         scan_field_t fields[4];
 235         u8 access_type_buf = 0;         /* interpreted access */
 236         u8 reg_addr_buf = 0x0;
 237         u8 nr_w_buf = 0;
 238         u8 cp15_opcode_buf[4];
 239
 240         jtag_add_end_state(TAP_RTI);
 241         arm_jtag_scann(jtag_info, 0xf);
 242         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 243
 244         buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 245
 246         fields[0].device = jtag_info->chain_pos;
 247         fields[0].num_bits = 1;
 248         fields[0].out_value = &access_type_buf;
 249         fields[0].out_mask = NULL;
 250         fields[0].in_value = NULL;
 251         fields[0].in_check_value = NULL;
 252         fields[0].in_check_mask = NULL;
 253         fields[0].in_handler = NULL;
 254         fields[0].in_handler_priv = NULL;
 255
 256         fields[1].device = jtag_info->chain_pos;
 257         fields[1].num_bits = 32;
 258         fields[1].out_value = cp15_opcode_buf;
 259         fields[1].out_mask = NULL;
 260         fields[1].in_value = NULL;
 261         fields[1].in_check_value = NULL;
 262         fields[1].in_check_mask = NULL;
 263         fields[1].in_handler = NULL;
 264         fields[1].in_handler_priv = NULL;
 265
 266         fields[2].device = jtag_info->chain_pos;
 267         fields[2].num_bits = 6;
 268         fields[2].out_value = &reg_addr_buf;
 269         fields[2].out_mask = NULL;
 270         fields[2].in_value = NULL;
 271         fields[2].in_check_value = NULL;
 272         fields[2].in_check_mask = NULL;
 273         fields[2].in_handler = NULL;
 274         fields[2].in_handler_priv = NULL;
 275
 276         fields[3].device = jtag_info->chain_pos;
 277         fields[3].num_bits = 1;
 278         fields[3].out_value = &nr_w_buf;
 279         fields[3].out_mask = NULL;
 280         fields[3].in_value = NULL;
 281         fields[3].in_check_value = NULL;
 282         fields[3].in_check_mask = NULL;
 283         fields[3].in_handler = NULL;
 284         fields[3].in_handler_priv = NULL;
 285
 286         jtag_add_dr_scan(4, fields, -1, NULL);
 287
 288         arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 289         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 290         arm7_9_execute_sys_speed(target);
 291
 292         if (jtag_execute_queue() != ERROR_OK)
 293         {
 294                 ERROR("failed executing JTAG queue, exiting");
 295                 exit(-1);
 296         }
 297
 298         return ERROR_OK;
 299 }
 300
 301 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
 302 {
 303         armv4_5_common_t *armv4_5 = target->arch_info;
 304         u32* regs_p[1];
 305         u32 regs[2];
 306         u32 cp15c15 = 0x0;
 307
 308         /* load address into R1 */
 309         regs[1] = address;
 310         arm9tdmi_write_core_regs(target, 0x2, regs);
 311
 312         /* read-modify-write CP15 test state register
 313         * to enable interpreted access mode */
 314         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 315         jtag_execute_queue();
 316         cp15c15 |= 1;   /* set interpret mode */
 317         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 318
 319         /* execute CP15 instruction and ARM load (reading from coprocessor) */
 320         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 321
 322         /* disable interpreted access mode */
 323         cp15c15 &= ~1U; /* clear interpret mode */
 324         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 325
 326         /* retrieve value from R0 */
 327         regs_p[0] = value;
 328         arm9tdmi_read_core_regs(target, 0x1, regs_p);
 329         jtag_execute_queue();
 330
 331 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 332         DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 333 #endif
 334
 335         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 336         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 337
 338         return ERROR_OK;
 339 }
 340
 341 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
 342 {
 343         u32 cp15c15 = 0x0;
 344         armv4_5_common_t *armv4_5 = target->arch_info;
 345         u32 regs[2];
 346
 347         /* load value, address into R0, R1 */
 348         regs[0] = value;
 349         regs[1] = address;
 350         arm9tdmi_write_core_regs(target, 0x3, regs);
 351
 352         /* read-modify-write CP15 test state register
 353         * to enable interpreted access mode */
 354         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 355         jtag_execute_queue();
 356         cp15c15 |= 1;   /* set interpret mode */
 357         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 358
 359         /* execute CP15 instruction and ARM store (writing to coprocessor) */
 360         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 361
 362         /* disable interpreted access mode */
 363         cp15c15 &= ~1U; /* set interpret mode */
 364         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 365
 366 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 367         DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 368 #endif
 369
 370         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 371         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 372
 373         return ERROR_OK;
 374 }
 375
 376 u32 arm920t_get_ttb(target_t *target)
 377 {
 378         int retval;
 379         u32 ttb = 0x0;
 380
 381         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 382                 return retval;
 383
 384         return ttb;
 385 }
 386
 387 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 388 {
 389         u32 cp15_control;
 390
 391         /* read cp15 control register */
 392         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 393         jtag_execute_queue();
 394
 395         if (mmu)
 396                 cp15_control &= ~0x1U;
 397
 398         if (d_u_cache)
 399                 cp15_control &= ~0x4U;
 400
 401         if (i_cache)
 402                 cp15_control &= ~0x1000U;
 403
 404         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 405 }
 406
 407 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 408 {
 409         u32 cp15_control;
 410
 411         /* read cp15 control register */
 412         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 413         jtag_execute_queue();
 414
 415         if (mmu)
 416                 cp15_control |= 0x1U;
 417
 418         if (d_u_cache)
 419                 cp15_control |= 0x4U;
 420
 421         if (i_cache)
 422                 cp15_control |= 0x1000U;
 423
 424         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 425 }
 426
 427 void arm920t_post_debug_entry(target_t *target)
 428 {
 429         u32 cp15c15;
 430         armv4_5_common_t *armv4_5 = target->arch_info;
 431         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 432         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 433         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 434
 435         /* examine cp15 control reg */
 436         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 437         jtag_execute_queue();
 438         DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
 439
 440         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 441         {
 442                 u32 cache_type_reg;
 443                 /* identify caches */
 444                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 445                 jtag_execute_queue();
 446                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 447         }
 448
 449         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
 450         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 451         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 452
 453         /* save i/d fault status and address register */
 454         arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 455         arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 456         arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 457         arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 458
 459         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
 460                 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 461
 462         if (arm920t->preserve_cache)
 463         {
 464                 /* read-modify-write CP15 test state register
 465                  * to disable I/D-cache linefills */
 466                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 467                 jtag_execute_queue();
 468                 cp15c15 |= 0x600;
 469                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 470         }
 471 }
 472
 473 void arm920t_pre_restore_context(target_t *target)
 474 {
 475         u32 cp15c15;
 476         armv4_5_common_t *armv4_5 = target->arch_info;
 477         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 478         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 479         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 480
 481         /* restore i/d fault status and address register */
 482         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
 483         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
 484         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
 485         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
 486
 487         /* read-modify-write CP15 test state register
 488         * to reenable I/D-cache linefills */
 489         if (arm920t->preserve_cache)
 490         {
 491                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 492                 jtag_execute_queue();
 493                 cp15c15 &= ~0x600U;
 494                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 495         }
 496 }
 497
 498 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
 499 {
 500         armv4_5_common_t *armv4_5 = target->arch_info;
 501         arm7_9_common_t *arm7_9;
 502         arm9tdmi_common_t *arm9tdmi;
 503         arm920t_common_t *arm920t;
 504
 505         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 506         {
 507                 return -1;
 508         }
 509
 510         arm7_9 = armv4_5->arch_info;
 511         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 512         {
 513                 return -1;
 514         }
 515
 516         arm9tdmi = arm7_9->arch_info;
 517         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 518         {
 519                 return -1;
 520         }
 521
 522         arm920t = arm9tdmi->arch_info;
 523         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
 524         {
 525                 return -1;
 526         }
 527
 528         *armv4_5_p = armv4_5;
 529         *arm7_9_p = arm7_9;
 530         *arm9tdmi_p = arm9tdmi;
 531         *arm920t_p = arm920t;
 532
 533         return ERROR_OK;
 534 }
 535
 536 int arm920t_arch_state(struct target_s *target, char *buf, int buf_size)
 537 {
 538         armv4_5_common_t *armv4_5 = target->arch_info;
 539         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 540         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 541         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 542
 543         char *state[] =
 544         {
 545                 "disabled", "enabled"
 546         };
 547
 548         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 549         {
 550                 ERROR("BUG: called for a non-ARMv4/5 target");
 551                 exit(-1);
 552         }
 553
 554         snprintf(buf, buf_size,
 555                         "target halted in %s state due to %s, current mode: %s\n"
 556                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 557                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 558                          armv4_5_state_strings[armv4_5->core_state],
 559                          target_debug_reason_strings[target->debug_reason],
 560                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 561                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 562                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 563                          state[arm920t->armv4_5_mmu.mmu_enabled],
 564                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 565                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 566
 567         return ERROR_OK;
 568 }
 569
 570 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 571 {
 572         int retval;
 573
 574         retval = arm7_9_read_memory(target, address, size, count, buffer);
 575
 576         return retval;
 577 }
 578
 579 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 580 {
 581         int retval;
 582         armv4_5_common_t *armv4_5 = target->arch_info;
 583         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 584         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 585         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 586
 587         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 588                 return retval;
 589
 590         if (((size == 4) || (size == 2)) && (count == 1))
 591         {
 592                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 593                 {
 594                         DEBUG("D-Cache enabled, writing through to main memory");
 595                         u32 pa, cb, ap;
 596                         int type, domain;
 597
 598                         pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
 599                         if (type == -1)
 600                                 return ERROR_OK;
 601                         /* cacheable & bufferable means write-back region */
 602                         if (cb == 3)
 603                                 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
 604                 }
 605
 606                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 607                 {
 608                         DEBUG("I-Cache enabled, invalidating affected I-Cache line");
 609                         arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
 610                 }
 611         }
 612
 613         return retval;
 614 }
 615
 616 int arm920t_soft_reset_halt(struct target_s *target)
 617 {
 618         armv4_5_common_t *armv4_5 = target->arch_info;
 619         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 620         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 621         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 622         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 623
 624         if (target->state == TARGET_RUNNING)
 625         {
 626                 target->type->halt(target);
 627         }
 628
 629         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 630         {
 631                 embeddedice_read_reg(dbg_stat);
 632                 jtag_execute_queue();
 633         }
 634
 635         target->state = TARGET_HALTED;
 636
 637         /* SVC, ARM state, IRQ and FIQ disabled */
 638         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 639         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 640         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 641
 642         /* start fetching from 0x0 */
 643         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 644         armv4_5->core_cache->reg_list[15].dirty = 1;
 645         armv4_5->core_cache->reg_list[15].valid = 1;
 646
 647         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 648         armv4_5->core_state = ARMV4_5_STATE_ARM;
 649
 650         arm920t_disable_mmu_caches(target, 1, 1, 1);
 651         arm920t->armv4_5_mmu.mmu_enabled = 0;
 652         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 653         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 654
 655         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 656
 657         return ERROR_OK;
 658 }
 659
 660 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 661 {
 662         arm9tdmi_init_target(cmd_ctx, target);
 663
 664         return ERROR_OK;
 665
 666 }
 667
 668 int arm920t_quit()
 669 {
 670
 671         return ERROR_OK;
 672 }
 673
 674 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
 675 {
 676         arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 677         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 678
 679         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 680          */
 681         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 682
 683         arm9tdmi->arch_info = arm920t;
 684         arm920t->common_magic = ARM920T_COMMON_MAGIC;
 685
 686         arm7_9->post_debug_entry = arm920t_post_debug_entry;
 687         arm7_9->pre_restore_context = arm920t_pre_restore_context;
 688
 689         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 690         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
 691         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 692         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 693         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 694         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 695         arm920t->armv4_5_mmu.has_tiny_pages = 1;
 696         arm920t->armv4_5_mmu.mmu_enabled = 0;
 697
 698         /* disabling linefills leads to lockups, so keep them enabled for now
 699          * this doesn't affect correctness, but might affect timing issues, if
 700          * important data is evicted from the cache during the debug session
 701          * */
 702         arm920t->preserve_cache = 0;
 703
 704         /* override hw single-step capability from ARM9TDMI */
 705         arm7_9->has_single_step = 1;
 706
 707         return ERROR_OK;
 708 }
 709
 710 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 711 {
 712         int chain_pos;
 713         char *variant = NULL;
 714         arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
 715
 716         if (argc < 4)
 717         {
 718                 ERROR("'target arm920t' requires at least one additional argument");
 719                 exit(-1);
 720         }
 721
 722         chain_pos = strtoul(args[3], NULL, 0);
 723
 724         if (argc >= 5)
 725                 variant = args[4];
 726
 727         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 728
 729         arm920t_init_arch_info(target, arm920t, chain_pos, variant);
 730
 731         return ERROR_OK;
 732 }
 733
 734 int arm920t_register_commands(struct command_context_s *cmd_ctx)
 735 {
 736         int retval;
 737         command_t *arm920t_cmd;
 738
 739
 740         retval = arm9tdmi_register_commands(cmd_ctx);
 741
 742         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
 743
 744         register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 745         register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
 746         register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 747         register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 748
 749         register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 750         register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 751         register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 752
 753         register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 754         register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 755         register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 756
 757         register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
 758         register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
 759
 760         return ERROR_OK;
 761 }
 762
 763 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 764 {
 765         target_t *target = get_current_target(cmd_ctx);
 766         armv4_5_common_t *armv4_5;
 767         arm7_9_common_t *arm7_9;
 768         arm9tdmi_common_t *arm9tdmi;
 769         arm920t_common_t *arm920t;
 770         arm_jtag_t *jtag_info;
 771         u32 cp15c15;
 772         u32 cp15_ctrl, cp15_ctrl_saved;
 773         u32 regs[16];
 774         u32 *regs_p[16];
 775         u32 C15_C_D_Ind, C15_C_I_Ind;
 776         int i;
 777         FILE *output;
 778         arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
 779         int segment, index;
 780
 781         if (argc != 1)
 782         {
 783                 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
 784                 return ERROR_OK;
 785         }
 786
 787         if ((output = fopen(args[0], "w")) == NULL)
 788         {
 789                 DEBUG("error opening cache content file");
 790                 return ERROR_OK;
 791         }
 792
 793         for (i = 0; i < 16; i++)
 794                 regs_p[i] = &regs[i];
 795
 796         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 797         {
 798                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 799                 return ERROR_OK;
 800         }
 801
 802         jtag_info = &arm7_9->jtag_info;
 803
 804         /* disable MMU and Caches */
 805         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
 806         jtag_execute_queue();
 807         cp15_ctrl_saved = cp15_ctrl;
 808         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 809         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 810
 811         /* read CP15 test state register */
 812         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
 813         jtag_execute_queue();
 814
 815         /* read DCache content */
 816         fprintf(output, "DCache:\n");
 817
 818         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 819         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 820         {
 821                 fprintf(output, "\nsegment: %i\n----------", segment);
 822
 823                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 824                 regs[0] = 0x0 | (segment << 5);
 825                 arm9tdmi_write_core_regs(target, 0x1, regs);
 826
 827                 /* set interpret mode */
 828                 cp15c15 |= 0x1;
 829                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 830
 831                 /* D CAM Read, loads current victim into C15.C.D.Ind */
 832                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 833
 834                 /* read current victim */
 835                 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
 836
 837                 /* clear interpret mode */
 838                 cp15c15 &= ~0x1;
 839                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 840
 841                 for (index = 0; index < 64; index++)
 842                 {
 843                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 844                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 845                         arm9tdmi_write_core_regs(target, 0x1, regs);
 846
 847                         /* set interpret mode */
 848                         cp15c15 |= 0x1;
 849                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 850
 851                         /* Write DCache victim */
 852                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 853
 854                         /* Read D RAM */
 855                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 856
 857                         /* Read D CAM */
 858                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
 859
 860                         /* clear interpret mode */
 861                         cp15c15 &= ~0x1;
 862                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 863
 864                         /* read D RAM and CAM content */
 865                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 866                         jtag_execute_queue();
 867
 868                         d_cache[segment][index].cam = regs[9];
 869
 870                         /* mask LFSR[6] */
 871                         regs[9] &= 0xfffffffe;
 872                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 873
 874                         for (i = 1; i < 9; i++)
 875                         {
 876                                  d_cache[segment][index].data[i] = regs[i];
 877                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 878                         }
 879
 880                 }
 881
 882                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 883                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 884                 arm9tdmi_write_core_regs(target, 0x1, regs);
 885
 886                 /* set interpret mode */
 887                 cp15c15 |= 0x1;
 888                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 889
 890                 /* Write DCache victim */
 891                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 892
 893                 /* clear interpret mode */
 894                 cp15c15 &= ~0x1;
 895                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 896         }
 897
 898         /* read ICache content */
 899         fprintf(output, "ICache:\n");
 900
 901         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 902         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 903         {
 904                 fprintf(output, "segment: %i\n----------", segment);
 905
 906                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 907                 regs[0] = 0x0 | (segment << 5);
 908                 arm9tdmi_write_core_regs(target, 0x1, regs);
 909
 910                 /* set interpret mode */
 911                 cp15c15 |= 0x1;
 912                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 913
 914                 /* I CAM Read, loads current victim into C15.C.I.Ind */
 915                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 916
 917                 /* read current victim */
 918                 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
 919
 920                 /* clear interpret mode */
 921                 cp15c15 &= ~0x1;
 922                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 923
 924                 for (index = 0; index < 64; index++)
 925                 {
 926                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 927                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 928                         arm9tdmi_write_core_regs(target, 0x1, regs);
 929
 930                         /* set interpret mode */
 931                         cp15c15 |= 0x1;
 932                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 933
 934                         /* Write ICache victim */
 935                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 936
 937                         /* Read I RAM */
 938                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 939
 940                         /* Read I CAM */
 941                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
 942
 943                         /* clear interpret mode */
 944                         cp15c15 &= ~0x1;
 945                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 946
 947                         /* read I RAM and CAM content */
 948                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 949                         jtag_execute_queue();
 950
 951                         i_cache[segment][index].cam = regs[9];
 952
 953                         /* mask LFSR[6] */
 954                         regs[9] &= 0xfffffffe;
 955                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 956
 957                         for (i = 1; i < 9; i++)
 958                         {
 959                                  i_cache[segment][index].data[i] = regs[i];
 960                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 961                         }
 962
 963                 }
 964
 965
 966                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 967                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 968                 arm9tdmi_write_core_regs(target, 0x1, regs);
 969
 970                 /* set interpret mode */
 971                 cp15c15 |= 0x1;
 972                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 973
 974                 /* Write ICache victim */
 975                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 976
 977                 /* clear interpret mode */
 978                 cp15c15 &= ~0x1;
 979                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 980         }
 981
 982         /* restore CP15 MMU and Cache settings */
 983         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
 984
 985         command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
 986
 987         fclose(output);
 988
 989         /* mark registers dirty */
 990         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 991         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 992         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
 993         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
 994         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
 995         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
 996         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
 997         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
 998         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
 999         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
1000
1001         return ERROR_OK;
1002 }
1003
1004 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1005 {
1006         target_t *target = get_current_target(cmd_ctx);
1007         armv4_5_common_t *armv4_5;
1008         arm7_9_common_t *arm7_9;
1009         arm9tdmi_common_t *arm9tdmi;
1010         arm920t_common_t *arm920t;
1011         arm_jtag_t *jtag_info;
1012         u32 cp15c15;
1013         u32 cp15_ctrl, cp15_ctrl_saved;
1014         u32 regs[16];
1015         u32 *regs_p[16];
1016         int i;
1017         FILE *output;
1018         u32 Dlockdown, Ilockdown;
1019         arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1020         int victim;
1021
1022         if (argc != 1)
1023         {
1024                 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1025                 return ERROR_OK;
1026         }
1027
1028         if ((output = fopen(args[0], "w")) == NULL)
1029         {
1030                 DEBUG("error opening mmu content file");
1031                 return ERROR_OK;
1032         }
1033
1034         for (i = 0; i < 16; i++)
1035                 regs_p[i] = &regs[i];
1036
1037         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1038         {
1039                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1040                 return ERROR_OK;
1041         }
1042
1043         jtag_info = &arm7_9->jtag_info;
1044
1045         /* disable MMU and Caches */
1046         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1047         jtag_execute_queue();
1048         cp15_ctrl_saved = cp15_ctrl;
1049         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1050         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1051
1052         /* read CP15 test state register */
1053         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1054         jtag_execute_queue();
1055
1056         /* prepare reading D TLB content
1057          * */
1058
1059         /* set interpret mode */
1060         cp15c15 |= 0x1;
1061         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1062
1063         /* Read D TLB lockdown */
1064         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1065
1066         /* clear interpret mode */
1067         cp15c15 &= ~0x1;
1068         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1069
1070         /* read D TLB lockdown stored to r1 */
1071         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1072         jtag_execute_queue();
1073         Dlockdown = regs[1];
1074
1075         for (victim = 0; victim < 64; victim += 8)
1076         {
1077                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1078                  * base remains unchanged, victim goes through entries 0 to 63 */
1079                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1080                 arm9tdmi_write_core_regs(target, 0x2, regs);
1081
1082                 /* set interpret mode */
1083                 cp15c15 |= 0x1;
1084                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1085
1086                 /* Write D TLB lockdown */
1087                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1088
1089                 /* Read D TLB CAM */
1090                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1091
1092                 /* clear interpret mode */
1093                 cp15c15 &= ~0x1;
1094                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1095
1096                 /* read D TLB CAM content stored to r2-r9 */
1097                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1098                 jtag_execute_queue();
1099
1100                 for (i = 0; i < 8; i++)
1101                         d_tlb[victim + i].cam = regs[i + 2];
1102         }
1103
1104         for (victim = 0; victim < 64; victim++)
1105         {
1106                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1107                  * base remains unchanged, victim goes through entries 0 to 63 */
1108                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1109                 arm9tdmi_write_core_regs(target, 0x2, regs);
1110
1111                 /* set interpret mode */
1112                 cp15c15 |= 0x1;
1113                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1114
1115                 /* Write D TLB lockdown */
1116                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1117
1118                 /* Read D TLB RAM1 */
1119                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1120
1121                 /* Read D TLB RAM2 */
1122                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1123
1124                 /* clear interpret mode */
1125                 cp15c15 &= ~0x1;
1126                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1127
1128                 /* read D TLB RAM content stored to r2 and r3 */
1129                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1130                 jtag_execute_queue();
1131
1132                 d_tlb[victim].ram1 = regs[2];
1133                 d_tlb[victim].ram2 = regs[3];
1134         }
1135
1136         /* restore D TLB lockdown */
1137         regs[1] = Dlockdown;
1138         arm9tdmi_write_core_regs(target, 0x2, regs);
1139
1140         /* Write D TLB lockdown */
1141         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1142
1143         /* prepare reading I TLB content
1144          * */
1145
1146         /* set interpret mode */
1147         cp15c15 |= 0x1;
1148         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1149
1150         /* Read I TLB lockdown */
1151         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1152
1153         /* clear interpret mode */
1154         cp15c15 &= ~0x1;
1155         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1156
1157         /* read I TLB lockdown stored to r1 */
1158         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1159         jtag_execute_queue();
1160         Ilockdown = regs[1];
1161
1162         for (victim = 0; victim < 64; victim += 8)
1163         {
1164                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1165                  * base remains unchanged, victim goes through entries 0 to 63 */
1166                 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1167                 arm9tdmi_write_core_regs(target, 0x2, regs);
1168
1169                 /* set interpret mode */
1170                 cp15c15 |= 0x1;
1171                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1172
1173                 /* Write I TLB lockdown */
1174                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1175
1176                 /* Read I TLB CAM */
1177                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1178
1179                 /* clear interpret mode */
1180                 cp15c15 &= ~0x1;
1181                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1182
1183                 /* read I TLB CAM content stored to r2-r9 */
1184                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1185                 jtag_execute_queue();
1186
1187                 for (i = 0; i < 8; i++)
1188                         i_tlb[i + victim].cam = regs[i + 2];
1189         }
1190
1191         for (victim = 0; victim < 64; victim++)
1192         {
1193                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1194                  * base remains unchanged, victim goes through entries 0 to 63 */
1195                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1196                 arm9tdmi_write_core_regs(target, 0x2, regs);
1197
1198                 /* set interpret mode */
1199                 cp15c15 |= 0x1;
1200                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1201
1202                 /* Write I TLB lockdown */
1203                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1204
1205                 /* Read I TLB RAM1 */
1206                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1207
1208                 /* Read I TLB RAM2 */
1209                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1210
1211                 /* clear interpret mode */
1212                 cp15c15 &= ~0x1;
1213                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1214
1215                 /* read I TLB RAM content stored to r2 and r3 */
1216                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1217                 jtag_execute_queue();
1218
1219                 i_tlb[victim].ram1 = regs[2];
1220                 i_tlb[victim].ram2 = regs[3];
1221         }
1222
1223         /* restore I TLB lockdown */
1224         regs[1] = Ilockdown;
1225         arm9tdmi_write_core_regs(target, 0x2, regs);
1226
1227         /* Write I TLB lockdown */
1228         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1229
1230         /* restore CP15 MMU and Cache settings */
1231         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1232
1233         /* output data to file */
1234         fprintf(output, "D TLB content:\n");
1235         for (i = 0; i < 64; i++)
1236         {
1237                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1238         }
1239
1240         fprintf(output, "\n\nI TLB content:\n");
1241         for (i = 0; i < 64; i++)
1242         {
1243                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1244         }
1245
1246         command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1247
1248         fclose(output);
1249
1250         /* mark registers dirty */
1251         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
1252         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
1253         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = 1;
1254         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = 1;
1255         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = 1;
1256         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = 1;
1257         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = 1;
1258         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = 1;
1259         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = 1;
1260         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = 1;
1261
1262         return ERROR_OK;
1263 }
1264 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1265 {
1266         int retval;
1267         target_t *target = get_current_target(cmd_ctx);
1268         armv4_5_common_t *armv4_5;
1269         arm7_9_common_t *arm7_9;
1270         arm9tdmi_common_t *arm9tdmi;
1271         arm920t_common_t *arm920t;
1272         arm_jtag_t *jtag_info;
1273
1274         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1275         {
1276                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1277                 return ERROR_OK;
1278         }
1279
1280         jtag_info = &arm7_9->jtag_info;
1281
1282         if (target->state != TARGET_HALTED)
1283         {
1284                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1285                 return ERROR_OK;
1286         }
1287
1288         /* one or more argument, access a single register (write if second argument is given */
1289         if (argc >= 1)
1290         {
1291                 int address = strtoul(args[0], NULL, 0);
1292
1293                 if (argc == 1)
1294                 {
1295                         u32 value;
1296                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1297                         {
1298                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1299                                 return ERROR_OK;
1300                         }
1301                         jtag_execute_queue();
1302
1303                         command_print(cmd_ctx, "%i: %8.8x", address, value);
1304                 }
1305                 else if (argc == 2)
1306                 {
1307                         u32 value = strtoul(args[1], NULL, 0);
1308                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1309                         {
1310                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1311                                 return ERROR_OK;
1312                         }
1313                         command_print(cmd_ctx, "%i: %8.8x", address, value);
1314                 }
1315         }
1316
1317         return ERROR_OK;
1318 }
1319
1320 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1321 {
1322         int retval;
1323         target_t *target = get_current_target(cmd_ctx);
1324         armv4_5_common_t *armv4_5;
1325         arm7_9_common_t *arm7_9;
1326         arm9tdmi_common_t *arm9tdmi;
1327         arm920t_common_t *arm920t;
1328         arm_jtag_t *jtag_info;
1329
1330         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1331         {
1332                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1333                 return ERROR_OK;
1334         }
1335
1336         jtag_info = &arm7_9->jtag_info;
1337
1338         if (target->state != TARGET_HALTED)
1339         {
1340                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1341                 return ERROR_OK;
1342         }
1343
1344         /* one or more argument, access a single register (write if second argument is given */
1345         if (argc >= 1)
1346         {
1347                 u32 opcode = strtoul(args[0], NULL, 0);
1348
1349                 if (argc == 1)
1350                 {
1351                         u32 value;
1352                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1353                         {
1354                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1355                                 return ERROR_OK;
1356                         }
1357
1358                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1359                 }
1360                 else if (argc == 2)
1361                 {
1362                         u32 value = strtoul(args[1], NULL, 0);
1363                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1364                         {
1365                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1366                                 return ERROR_OK;
1367                         }
1368                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1369                 }
1370                 else if (argc == 3)
1371                 {
1372                         u32 value = strtoul(args[1], NULL, 0);
1373                         u32 address = strtoul(args[2], NULL, 0);
1374                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1375                         {
1376                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1377                                 return ERROR_OK;
1378                         }
1379                         command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1380                 }
1381         }
1382         else
1383         {
1384                 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1385         }
1386
1387         return ERROR_OK;
1388 }
1389
1390 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1391 {
1392         target_t *target = get_current_target(cmd_ctx);
1393         armv4_5_common_t *armv4_5;
1394         arm7_9_common_t *arm7_9;
1395         arm9tdmi_common_t *arm9tdmi;
1396         arm920t_common_t *arm920t;
1397
1398         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1399         {
1400                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1401                 return ERROR_OK;
1402         }
1403
1404         return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1405 }
1406
1407 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1408 {
1409         target_t *target = get_current_target(cmd_ctx);
1410         armv4_5_common_t *armv4_5;
1411         arm7_9_common_t *arm7_9;
1412         arm9tdmi_common_t *arm9tdmi;
1413         arm920t_common_t *arm920t;
1414         arm_jtag_t *jtag_info;
1415
1416         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1417         {
1418                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1419                 return ERROR_OK;
1420         }
1421
1422         jtag_info = &arm7_9->jtag_info;
1423
1424         if (target->state != TARGET_HALTED)
1425         {
1426                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1427                 return ERROR_OK;
1428         }
1429
1430         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1431 }
1432
1433 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1434 {
1435         target_t *target = get_current_target(cmd_ctx);
1436         armv4_5_common_t *armv4_5;
1437         arm7_9_common_t *arm7_9;
1438         arm9tdmi_common_t *arm9tdmi;
1439         arm920t_common_t *arm920t;
1440         arm_jtag_t *jtag_info;
1441
1442         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1443         {
1444                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1445                 return ERROR_OK;
1446         }
1447
1448         jtag_info = &arm7_9->jtag_info;
1449
1450         if (target->state != TARGET_HALTED)
1451         {
1452                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1453                 return ERROR_OK;
1454         }
1455
1456         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1457 }
1458
1459 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1460 {
1461         target_t *target = get_current_target(cmd_ctx);
1462         armv4_5_common_t *armv4_5;
1463         arm7_9_common_t *arm7_9;
1464         arm9tdmi_common_t *arm9tdmi;
1465         arm920t_common_t *arm920t;
1466         arm_jtag_t *jtag_info;
1467
1468         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1469         {
1470                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1471                 return ERROR_OK;
1472         }
1473
1474         jtag_info = &arm7_9->jtag_info;
1475
1476         if (target->state != TARGET_HALTED)
1477         {
1478                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1479                 return ERROR_OK;
1480         }
1481
1482         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1483 }