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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   6  *   oyvind.harboe@zylin.com                                               *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  20  ***************************************************************************/
  21
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "arm720t.h"
  27 #include <helper/time_support.h>
  28 #include "target_type.h"
  29 #include "register.h"
  30 #include "arm_opcodes.h"
  31
  32
  33 /*
  34  * ARM720 is an ARM7TDMI-S with MMU and ETM7.  For information, see
  35  * ARM DDI 0229C especially Chapter 9 about debug support.
  36  */
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 static int arm720t_scan_cp15(struct target *target,
  43                 uint32_t out, uint32_t *in, int instruction, int clock_arg)
  44 {
  45         int retval;
  46         struct arm720t_common *arm720t = target_to_arm720(target);
  47         struct arm_jtag *jtag_info;
  48         struct scan_field fields[2];
  49         uint8_t out_buf[4];
  50         uint8_t instruction_buf = instruction;
  51
  52         jtag_info = &arm720t->arm7_9_common.jtag_info;
  53
  54         buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
  55
  56         retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
  57         if (retval != ERROR_OK)
  58                 return retval;
  59         retval = arm_jtag_set_instr(jtag_info->tap, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
  60         if (retval != ERROR_OK)
  61                 return retval;
  62
  63         fields[0].num_bits = 1;
  64         fields[0].out_value = &instruction_buf;
  65         fields[0].in_value = NULL;
  66
  67         fields[1].num_bits = 32;
  68         fields[1].out_value = out_buf;
  69         fields[1].in_value = NULL;
  70
  71         if (in) {
  72                 fields[1].in_value = (uint8_t *)in;
  73                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  74                 jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
  75         } else
  76                 jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
  77
  78         if (clock_arg)
  79                 jtag_add_runtest(0, TAP_DRPAUSE);
  80
  81 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
  82         retval = jtag_execute_queue();
  83         if (retval != ERROR_OK)
  84                 return retval;
  85
  86         if (in)
  87                 LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
  88         else
  89                 LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock_arg);
  90 #else
  91                 LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock_arg);
  92 #endif
  93
  94         return ERROR_OK;
  95 }
  96
  97 static int arm720t_read_cp15(struct target *target, uint32_t opcode, uint32_t *value)
  98 {
  99         /* fetch CP15 opcode */
 100         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 101         /* "DECODE" stage */
 102         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 103         /* "EXECUTE" stage (1) */
 104         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 105         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 106         /* "EXECUTE" stage (2) */
 107         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 108         /* "EXECUTE" stage (3), CDATA is read */
 109         arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1);
 110
 111         return ERROR_OK;
 112 }
 113
 114 static int arm720t_write_cp15(struct target *target, uint32_t opcode, uint32_t value)
 115 {
 116         /* fetch CP15 opcode */
 117         arm720t_scan_cp15(target, opcode, NULL, 1, 1);
 118         /* "DECODE" stage */
 119         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 120         /* "EXECUTE" stage (1) */
 121         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 0);
 122         arm720t_scan_cp15(target, 0x0, NULL, 0, 1);
 123         /* "EXECUTE" stage (2) */
 124         arm720t_scan_cp15(target, value, NULL, 0, 1);
 125         arm720t_scan_cp15(target, ARMV4_5_NOP, NULL, 1, 1);
 126
 127         return ERROR_OK;
 128 }
 129
 130 static int arm720t_get_ttb(struct target *target, uint32_t *result)
 131 {
 132         uint32_t ttb = 0x0;
 133
 134         int retval;
 135
 136         retval = arm720t_read_cp15(target, 0xee120f10, &ttb);
 137         if (retval != ERROR_OK)
 138                 return retval;
 139         retval = jtag_execute_queue();
 140         if (retval != ERROR_OK)
 141                 return retval;
 142
 143         ttb &= 0xffffc000;
 144
 145         *result = ttb;
 146
 147         return ERROR_OK;
 148 }
 149
 150 static int arm720t_disable_mmu_caches(struct target *target,
 151                 int mmu, int d_u_cache, int i_cache)
 152 {
 153         uint32_t cp15_control;
 154         int retval;
 155
 156         /* read cp15 control register */
 157         retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 158         if (retval != ERROR_OK)
 159                 return retval;
 160         retval = jtag_execute_queue();
 161         if (retval != ERROR_OK)
 162                 return retval;
 163
 164         if (mmu)
 165                 cp15_control &= ~0x1U;
 166
 167         if (d_u_cache || i_cache)
 168                 cp15_control &= ~0x4U;
 169
 170         retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
 171         return retval;
 172 }
 173
 174 static int arm720t_enable_mmu_caches(struct target *target,
 175                 int mmu, int d_u_cache, int i_cache)
 176 {
 177         uint32_t cp15_control;
 178         int retval;
 179
 180         /* read cp15 control register */
 181         retval = arm720t_read_cp15(target, 0xee110f10, &cp15_control);
 182         if (retval != ERROR_OK)
 183                 return retval;
 184         retval = jtag_execute_queue();
 185         if (retval != ERROR_OK)
 186                 return retval;
 187
 188         if (mmu)
 189                 cp15_control |= 0x1U;
 190
 191         if (d_u_cache || i_cache)
 192                 cp15_control |= 0x4U;
 193
 194         retval = arm720t_write_cp15(target, 0xee010f10, cp15_control);
 195         return retval;
 196 }
 197
 198 static int arm720t_post_debug_entry(struct target *target)
 199 {
 200         struct arm720t_common *arm720t = target_to_arm720(target);
 201         int retval;
 202
 203         /* examine cp15 control reg */
 204         retval = arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 205         if (retval != ERROR_OK)
 206                 return retval;
 207         retval = jtag_execute_queue();
 208         if (retval != ERROR_OK)
 209                 return retval;
 210         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 211
 212         arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 213         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 214         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 215
 216         /* save i/d fault status and address register */
 217         retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
 218         if (retval != ERROR_OK)
 219                 return retval;
 220         retval = arm720t_read_cp15(target, 0xee160f10, &arm720t->far_reg);
 221         if (retval != ERROR_OK)
 222                 return retval;
 223         retval = jtag_execute_queue();
 224         return retval;
 225 }
 226
 227 static void arm720t_pre_restore_context(struct target *target)
 228 {
 229         struct arm720t_common *arm720t = target_to_arm720(target);
 230
 231         /* restore i/d fault status and address register */
 232         arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg);
 233         arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg);
 234 }
 235
 236 static int arm720t_arch_state(struct target *target)
 237 {
 238         struct arm720t_common *arm720t = target_to_arm720(target);
 239
 240         static const char *state[] = {
 241                 "disabled", "enabled"
 242         };
 243
 244         arm_arch_state(target);
 245         LOG_USER("MMU: %s, Cache: %s",
 246                          state[arm720t->armv4_5_mmu.mmu_enabled],
 247                          state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 248
 249         return ERROR_OK;
 250 }
 251
 252 static int arm720_mmu(struct target *target, int *enabled)
 253 {
 254         if (target->state != TARGET_HALTED) {
 255                 LOG_ERROR("%s: target not halted", __func__);
 256                 return ERROR_TARGET_INVALID;
 257         }
 258
 259         *enabled = target_to_arm720(target)->armv4_5_mmu.mmu_enabled;
 260         return ERROR_OK;
 261 }
 262
 263 static int arm720_virt2phys(struct target *target,
 264                 target_addr_t virtual, target_addr_t *physical)
 265 {
 266         uint32_t cb;
 267         struct arm720t_common *arm720t = target_to_arm720(target);
 268
 269         uint32_t ret;
 270         int retval = armv4_5_mmu_translate_va(target,
 271                         &arm720t->armv4_5_mmu, virtual, &cb, &ret);
 272         if (retval != ERROR_OK)
 273                 return retval;
 274         *physical = ret;
 275         return ERROR_OK;
 276 }
 277
 278 static int arm720t_read_memory(struct target *target,
 279                 target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 280 {
 281         int retval;
 282         struct arm720t_common *arm720t = target_to_arm720(target);
 283
 284         /* disable cache, but leave MMU enabled */
 285         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
 286                 retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
 287                 if (retval != ERROR_OK)
 288                         return retval;
 289         }
 290         retval = arm7_9_read_memory(target, address, size, count, buffer);
 291
 292         if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
 293                 retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
 294                 if (retval != ERROR_OK)
 295                         return retval;
 296         }
 297
 298         return retval;
 299 }
 300
 301 static int arm720t_read_phys_memory(struct target *target,
 302                 target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 303 {
 304         struct arm720t_common *arm720t = target_to_arm720(target);
 305
 306         return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 307 }
 308
 309 static int arm720t_write_phys_memory(struct target *target,
 310                 target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
 311 {
 312         struct arm720t_common *arm720t = target_to_arm720(target);
 313
 314         return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
 315 }
 316
 317 static int arm720t_soft_reset_halt(struct target *target)
 318 {
 319         int retval = ERROR_OK;
 320         struct arm720t_common *arm720t = target_to_arm720(target);
 321         struct reg *dbg_stat = &arm720t->arm7_9_common
 322                         .eice_cache->reg_list[EICE_DBG_STAT];
 323         struct arm *arm = &arm720t->arm7_9_common.arm;
 324
 325         retval = target_halt(target);
 326         if (retval != ERROR_OK)
 327                 return retval;
 328
 329         int64_t then = timeval_ms();
 330         int timeout;
 331         while (!(timeout = ((timeval_ms()-then) > 1000))) {
 332                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
 333                         embeddedice_read_reg(dbg_stat);
 334                         retval = jtag_execute_queue();
 335                         if (retval != ERROR_OK)
 336                                 return retval;
 337                 } else
 338                         break;
 339                 if (debug_level >= 3)
 340                         alive_sleep(100);
 341                 else
 342                         keep_alive();
 343         }
 344         if (timeout) {
 345                 LOG_ERROR("Failed to halt CPU after 1 sec");
 346                 return ERROR_TARGET_TIMEOUT;
 347         }
 348
 349         target->state = TARGET_HALTED;
 350
 351         /* SVC, ARM state, IRQ and FIQ disabled */
 352         uint32_t cpsr;
 353
 354         cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
 355         cpsr &= ~0xff;
 356         cpsr |= 0xd3;
 357         arm_set_cpsr(arm, cpsr);
 358         arm->cpsr->dirty = true;
 359
 360         /* start fetching from 0x0 */
 361         buf_set_u32(arm->pc->value, 0, 32, 0x0);
 362         arm->pc->dirty = true;
 363         arm->pc->valid = true;
 364
 365         retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
 366         if (retval != ERROR_OK)
 367                 return retval;
 368         arm720t->armv4_5_mmu.mmu_enabled = 0;
 369         arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 370         arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 371
 372         retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 373         if (retval != ERROR_OK)
 374                 return retval;
 375
 376         return ERROR_OK;
 377 }
 378
 379 static int arm720t_init_target(struct command_context *cmd_ctx, struct target *target)
 380 {
 381         return arm7tdmi_init_target(cmd_ctx, target);
 382 }
 383
 384 static void arm720t_deinit_target(struct target *target)
 385 {
 386         arm7tdmi_deinit_target(target);
 387 }
 388
 389 /* FIXME remove forward decls */
 390 static int arm720t_mrc(struct target *target, int cpnum,
 391                 uint32_t op1, uint32_t op2,
 392                 uint32_t crn, uint32_t crm,
 393                 uint32_t *value);
 394 static int arm720t_mcr(struct target *target, int cpnum,
 395                 uint32_t op1, uint32_t op2,
 396                 uint32_t crn, uint32_t crm,
 397                 uint32_t value);
 398
 399 static int arm720t_init_arch_info(struct target *target,
 400                 struct arm720t_common *arm720t, struct jtag_tap *tap)
 401 {
 402         struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common;
 403
 404         arm7_9->arm.mrc = arm720t_mrc;
 405         arm7_9->arm.mcr = arm720t_mcr;
 406
 407         arm7tdmi_init_arch_info(target, arm7_9, tap);
 408
 409         arm720t->common_magic = ARM720T_COMMON_MAGIC;
 410
 411         arm7_9->post_debug_entry = arm720t_post_debug_entry;
 412         arm7_9->pre_restore_context = arm720t_pre_restore_context;
 413
 414         arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 415         arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb;
 416         arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 417         arm720t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 418         arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 419         arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 420         arm720t->armv4_5_mmu.has_tiny_pages = 0;
 421         arm720t->armv4_5_mmu.mmu_enabled = 0;
 422
 423         return ERROR_OK;
 424 }
 425
 426 static int arm720t_target_create(struct target *target, Jim_Interp *interp)
 427 {
 428         struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t));
 429
 430         arm720t->arm7_9_common.arm.arch = ARM_ARCH_V4;
 431         return arm720t_init_arch_info(target, arm720t, target->tap);
 432 }
 433
 434 static int arm720t_mrc(struct target *target, int cpnum,
 435                 uint32_t op1, uint32_t op2,
 436                 uint32_t crn, uint32_t crm,
 437                 uint32_t *value)
 438 {
 439         if (cpnum != 15) {
 440                 LOG_ERROR("Only cp15 is supported");
 441                 return ERROR_FAIL;
 442         }
 443
 444         /* read "to" r0 */
 445         return arm720t_read_cp15(target,
 446                         ARMV4_5_MRC(cpnum, op1, 0, crn, crm, op2),
 447                         value);
 448
 449 }
 450
 451 static int arm720t_mcr(struct target *target, int cpnum,
 452                 uint32_t op1, uint32_t op2,
 453                 uint32_t crn, uint32_t crm,
 454                 uint32_t value)
 455 {
 456         if (cpnum != 15) {
 457                 LOG_ERROR("Only cp15 is supported");
 458                 return ERROR_FAIL;
 459         }
 460
 461         /* write "from" r0 */
 462         return arm720t_write_cp15(target,
 463                         ARMV4_5_MCR(cpnum, op1, 0, crn, crm, op2),
 464                         value);
 465 }
 466
 467 static const struct command_registration arm720t_command_handlers[] = {
 468         {
 469                 .chain = arm7_9_command_handlers,
 470         },
 471         COMMAND_REGISTRATION_DONE
 472 };
 473
 474 /** Holds methods for ARM720 targets. */
 475 struct target_type arm720t_target = {
 476         .name = "arm720t",
 477
 478         .poll = arm7_9_poll,
 479         .arch_state = arm720t_arch_state,
 480
 481         .halt = arm7_9_halt,
 482         .resume = arm7_9_resume,
 483         .step = arm7_9_step,
 484
 485         .assert_reset = arm7_9_assert_reset,
 486         .deassert_reset = arm7_9_deassert_reset,
 487         .soft_reset_halt = arm720t_soft_reset_halt,
 488
 489         .get_gdb_arch = arm_get_gdb_arch,
 490         .get_gdb_reg_list = arm_get_gdb_reg_list,
 491
 492         .read_memory = arm720t_read_memory,
 493         .write_memory = arm7_9_write_memory_opt,
 494         .read_phys_memory = arm720t_read_phys_memory,
 495         .write_phys_memory = arm720t_write_phys_memory,
 496         .mmu = arm720_mmu,
 497         .virt2phys = arm720_virt2phys,
 498
 499         .checksum_memory = arm_checksum_memory,
 500         .blank_check_memory = arm_blank_check_memory,
 501
 502         .run_algorithm = armv4_5_run_algorithm,
 503
 504         .add_breakpoint = arm7_9_add_breakpoint,
 505         .remove_breakpoint = arm7_9_remove_breakpoint,
 506         .add_watchpoint = arm7_9_add_watchpoint,
 507         .remove_watchpoint = arm7_9_remove_watchpoint,
 508
 509         .commands = arm720t_command_handlers,
 510         .target_create = arm720t_target_create,
 511         .init_target = arm720t_init_target,
 512         .deinit_target = arm720t_deinit_target,
 513         .examine = arm7_9_examine,
 514         .check_reset = arm7_9_check_reset,
 515 };